./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c8989412e094655bcf4508d76eb9764ed06d0b34 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 13:24:08,851 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 13:24:08,853 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 13:24:08,861 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 13:24:08,861 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 13:24:08,862 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 13:24:08,863 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 13:24:08,864 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 13:24:08,865 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 13:24:08,866 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 13:24:08,866 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 13:24:08,867 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 13:24:08,867 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 13:24:08,868 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 13:24:08,869 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 13:24:08,869 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 13:24:08,870 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 13:24:08,871 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 13:24:08,872 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 13:24:08,873 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 13:24:08,874 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 13:24:08,874 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 13:24:08,876 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 13:24:08,876 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 13:24:08,876 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 13:24:08,877 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 13:24:08,877 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 13:24:08,878 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 13:24:08,878 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 13:24:08,879 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 13:24:08,879 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 13:24:08,880 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 13:24:08,880 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 13:24:08,880 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 13:24:08,881 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 13:24:08,881 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 13:24:08,881 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-28 13:24:08,891 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 13:24:08,891 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 13:24:08,892 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-28 13:24:08,892 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-28 13:24:08,892 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 13:24:08,892 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 13:24:08,892 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 13:24:08,893 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 13:24:08,893 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 13:24:08,893 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 13:24:08,893 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 13:24:08,893 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 13:24:08,893 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-28 13:24:08,893 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-28 13:24:08,894 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-28 13:24:08,894 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 13:24:08,894 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-28 13:24:08,894 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 13:24:08,894 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-28 13:24:08,894 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 13:24:08,894 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 13:24:08,895 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-28 13:24:08,895 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-28 13:24:08,895 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 13:24:08,895 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 13:24:08,895 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-28 13:24:08,895 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-28 13:24:08,895 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 13:24:08,895 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-28 13:24:08,896 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-28 13:24:08,896 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c8989412e094655bcf4508d76eb9764ed06d0b34 [2018-11-28 13:24:08,919 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 13:24:08,929 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 13:24:08,932 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 13:24:08,933 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 13:24:08,933 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 13:24:08,934 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c [2018-11-28 13:24:08,979 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/data/5cb781f46/b1a6547c3a86449a804e56d192e44d2f/FLAG104a049f5 [2018-11-28 13:24:09,348 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 13:24:09,349 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c [2018-11-28 13:24:09,356 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/data/5cb781f46/b1a6547c3a86449a804e56d192e44d2f/FLAG104a049f5 [2018-11-28 13:24:09,364 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/data/5cb781f46/b1a6547c3a86449a804e56d192e44d2f [2018-11-28 13:24:09,365 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 13:24:09,366 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-28 13:24:09,367 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 13:24:09,367 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 13:24:09,369 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 13:24:09,369 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,371 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e0d5add and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09, skipping insertion in model container [2018-11-28 13:24:09,371 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,375 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 13:24:09,396 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 13:24:09,530 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 13:24:09,534 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 13:24:09,561 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 13:24:09,570 INFO L195 MainTranslator]: Completed translation [2018-11-28 13:24:09,570 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09 WrapperNode [2018-11-28 13:24:09,570 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 13:24:09,571 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-28 13:24:09,571 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-28 13:24:09,571 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-28 13:24:09,576 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,581 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,624 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-28 13:24:09,624 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 13:24:09,624 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 13:24:09,624 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 13:24:09,633 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,633 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,634 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,634 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,641 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,652 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,654 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... [2018-11-28 13:24:09,659 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 13:24:09,659 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 13:24:09,660 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 13:24:09,660 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 13:24:09,660 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-28 13:24:09,698 INFO L130 BoogieDeclarations]: Found specification of procedure read [2018-11-28 13:24:09,698 INFO L138 BoogieDeclarations]: Found implementation of procedure read [2018-11-28 13:24:09,698 INFO L130 BoogieDeclarations]: Found specification of procedure write_back [2018-11-28 13:24:09,699 INFO L138 BoogieDeclarations]: Found implementation of procedure write_back [2018-11-28 13:24:09,699 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-28 13:24:09,699 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-28 13:24:09,699 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-28 13:24:09,699 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-28 13:24:09,699 INFO L130 BoogieDeclarations]: Found specification of procedure compute2 [2018-11-28 13:24:09,699 INFO L138 BoogieDeclarations]: Found implementation of procedure compute2 [2018-11-28 13:24:09,699 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-28 13:24:09,699 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-28 13:24:09,699 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-28 13:24:09,700 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-28 13:24:09,700 INFO L130 BoogieDeclarations]: Found specification of procedure compute1 [2018-11-28 13:24:09,700 INFO L138 BoogieDeclarations]: Found implementation of procedure compute1 [2018-11-28 13:24:09,700 INFO L130 BoogieDeclarations]: Found specification of procedure write_loop [2018-11-28 13:24:09,700 INFO L138 BoogieDeclarations]: Found implementation of procedure write_loop [2018-11-28 13:24:09,700 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-28 13:24:09,700 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-28 13:24:09,700 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 13:24:09,700 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 13:24:10,133 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 13:24:10,133 INFO L280 CfgBuilder]: Removed 6 assue(true) statements. [2018-11-28 13:24:10,133 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:24:10 BoogieIcfgContainer [2018-11-28 13:24:10,133 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 13:24:10,134 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-28 13:24:10,134 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-28 13:24:10,136 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-28 13:24:10,137 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 01:24:09" (1/3) ... [2018-11-28 13:24:10,137 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5da2d08b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 01:24:10, skipping insertion in model container [2018-11-28 13:24:10,137 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 01:24:09" (2/3) ... [2018-11-28 13:24:10,138 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5da2d08b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 01:24:10, skipping insertion in model container [2018-11-28 13:24:10,138 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:24:10" (3/3) ... [2018-11-28 13:24:10,139 INFO L112 eAbstractionObserver]: Analyzing ICFG toy2_false-unreach-call_false-termination.cil.c [2018-11-28 13:24:10,146 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-28 13:24:10,152 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-28 13:24:10,164 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-28 13:24:10,184 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 13:24:10,185 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-28 13:24:10,185 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-28 13:24:10,185 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-28 13:24:10,185 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 13:24:10,185 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 13:24:10,185 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-28 13:24:10,185 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 13:24:10,186 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-28 13:24:10,202 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states. [2018-11-28 13:24:10,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:10,209 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:10,210 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:10,212 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:10,215 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:10,215 INFO L82 PathProgramCache]: Analyzing trace with hash 1787110337, now seen corresponding path program 1 times [2018-11-28 13:24:10,217 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:10,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:10,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:10,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:10,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:10,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:10,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:10,387 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:10,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 13:24:10,390 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:24:10,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:24:10,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:10,399 INFO L87 Difference]: Start difference. First operand 158 states. Second operand 3 states. [2018-11-28 13:24:10,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:10,439 INFO L93 Difference]: Finished difference Result 298 states and 509 transitions. [2018-11-28 13:24:10,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:24:10,440 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2018-11-28 13:24:10,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:10,448 INFO L225 Difference]: With dead ends: 298 [2018-11-28 13:24:10,448 INFO L226 Difference]: Without dead ends: 149 [2018-11-28 13:24:10,450 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:10,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-11-28 13:24:10,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-11-28 13:24:10,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-28 13:24:10,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 241 transitions. [2018-11-28 13:24:10,482 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 241 transitions. Word has length 46 [2018-11-28 13:24:10,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:10,483 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 241 transitions. [2018-11-28 13:24:10,483 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:24:10,483 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 241 transitions. [2018-11-28 13:24:10,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:10,484 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:10,484 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:10,484 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:10,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:10,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1714723779, now seen corresponding path program 1 times [2018-11-28 13:24:10,485 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:10,485 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:10,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:10,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:10,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:10,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:10,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:10,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:10,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 13:24:10,539 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:24:10,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:24:10,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:10,540 INFO L87 Difference]: Start difference. First operand 149 states and 241 transitions. Second operand 3 states. [2018-11-28 13:24:10,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:10,585 INFO L93 Difference]: Finished difference Result 281 states and 458 transitions. [2018-11-28 13:24:10,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:24:10,585 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2018-11-28 13:24:10,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:10,587 INFO L225 Difference]: With dead ends: 281 [2018-11-28 13:24:10,587 INFO L226 Difference]: Without dead ends: 149 [2018-11-28 13:24:10,588 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:10,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-11-28 13:24:10,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-11-28 13:24:10,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-28 13:24:10,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 233 transitions. [2018-11-28 13:24:10,597 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 233 transitions. Word has length 46 [2018-11-28 13:24:10,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:10,598 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 233 transitions. [2018-11-28 13:24:10,598 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:24:10,598 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 233 transitions. [2018-11-28 13:24:10,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:10,599 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:10,599 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:10,600 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:10,600 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:10,600 INFO L82 PathProgramCache]: Analyzing trace with hash 1171834943, now seen corresponding path program 1 times [2018-11-28 13:24:10,600 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:10,600 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:10,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:10,601 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:10,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:10,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:10,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:10,654 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:10,654 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:24:10,654 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:24:10,654 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:24:10,655 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:24:10,655 INFO L87 Difference]: Start difference. First operand 149 states and 233 transitions. Second operand 4 states. [2018-11-28 13:24:10,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:10,826 INFO L93 Difference]: Finished difference Result 383 states and 603 transitions. [2018-11-28 13:24:10,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:24:10,827 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-11-28 13:24:10,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:10,829 INFO L225 Difference]: With dead ends: 383 [2018-11-28 13:24:10,829 INFO L226 Difference]: Without dead ends: 252 [2018-11-28 13:24:10,830 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:10,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-11-28 13:24:10,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 149. [2018-11-28 13:24:10,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-28 13:24:10,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 231 transitions. [2018-11-28 13:24:10,848 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 231 transitions. Word has length 46 [2018-11-28 13:24:10,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:10,848 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 231 transitions. [2018-11-28 13:24:10,848 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:24:10,849 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 231 transitions. [2018-11-28 13:24:10,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:10,849 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:10,850 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:10,850 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:10,850 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:10,850 INFO L82 PathProgramCache]: Analyzing trace with hash 1873434817, now seen corresponding path program 1 times [2018-11-28 13:24:10,850 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:10,850 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:10,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:10,851 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:10,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:10,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:10,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:10,904 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:10,905 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:24:10,905 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:24:10,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:24:10,905 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:24:10,905 INFO L87 Difference]: Start difference. First operand 149 states and 231 transitions. Second operand 4 states. [2018-11-28 13:24:11,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:11,011 INFO L93 Difference]: Finished difference Result 418 states and 654 transitions. [2018-11-28 13:24:11,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:24:11,011 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-11-28 13:24:11,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:11,013 INFO L225 Difference]: With dead ends: 418 [2018-11-28 13:24:11,013 INFO L226 Difference]: Without dead ends: 289 [2018-11-28 13:24:11,014 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:11,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2018-11-28 13:24:11,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 165. [2018-11-28 13:24:11,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-11-28 13:24:11,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 253 transitions. [2018-11-28 13:24:11,028 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 253 transitions. Word has length 46 [2018-11-28 13:24:11,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:11,029 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 253 transitions. [2018-11-28 13:24:11,029 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:24:11,029 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 253 transitions. [2018-11-28 13:24:11,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:11,030 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:11,030 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:11,031 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:11,031 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:11,031 INFO L82 PathProgramCache]: Analyzing trace with hash -1035329085, now seen corresponding path program 1 times [2018-11-28 13:24:11,031 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:11,031 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:11,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:11,032 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:11,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:11,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:11,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:11,075 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:11,075 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:24:11,076 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:24:11,076 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:24:11,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:24:11,076 INFO L87 Difference]: Start difference. First operand 165 states and 253 transitions. Second operand 4 states. [2018-11-28 13:24:11,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:11,192 INFO L93 Difference]: Finished difference Result 503 states and 772 transitions. [2018-11-28 13:24:11,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:24:11,193 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-11-28 13:24:11,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:11,195 INFO L225 Difference]: With dead ends: 503 [2018-11-28 13:24:11,195 INFO L226 Difference]: Without dead ends: 369 [2018-11-28 13:24:11,196 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:11,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 369 states. [2018-11-28 13:24:11,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 352. [2018-11-28 13:24:11,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2018-11-28 13:24:11,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 540 transitions. [2018-11-28 13:24:11,220 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 540 transitions. Word has length 46 [2018-11-28 13:24:11,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:11,221 INFO L480 AbstractCegarLoop]: Abstraction has 352 states and 540 transitions. [2018-11-28 13:24:11,221 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:24:11,221 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 540 transitions. [2018-11-28 13:24:11,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:11,223 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:11,223 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:11,223 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:11,224 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:11,224 INFO L82 PathProgramCache]: Analyzing trace with hash -1544802175, now seen corresponding path program 1 times [2018-11-28 13:24:11,224 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:11,224 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:11,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:11,225 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:11,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:11,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:11,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:11,311 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:11,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 13:24:11,312 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:24:11,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:24:11,312 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:11,312 INFO L87 Difference]: Start difference. First operand 352 states and 540 transitions. Second operand 5 states. [2018-11-28 13:24:11,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:11,467 INFO L93 Difference]: Finished difference Result 974 states and 1524 transitions. [2018-11-28 13:24:11,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:24:11,468 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 46 [2018-11-28 13:24:11,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:11,471 INFO L225 Difference]: With dead ends: 974 [2018-11-28 13:24:11,471 INFO L226 Difference]: Without dead ends: 654 [2018-11-28 13:24:11,472 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:24:11,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-11-28 13:24:11,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 525. [2018-11-28 13:24:11,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 525 states. [2018-11-28 13:24:11,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 525 states to 525 states and 804 transitions. [2018-11-28 13:24:11,509 INFO L78 Accepts]: Start accepts. Automaton has 525 states and 804 transitions. Word has length 46 [2018-11-28 13:24:11,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:11,509 INFO L480 AbstractCegarLoop]: Abstraction has 525 states and 804 transitions. [2018-11-28 13:24:11,509 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:24:11,510 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 804 transitions. [2018-11-28 13:24:11,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:11,511 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:11,511 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:11,511 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:11,511 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:11,512 INFO L82 PathProgramCache]: Analyzing trace with hash -1914487912, now seen corresponding path program 1 times [2018-11-28 13:24:11,512 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:11,512 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:11,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:11,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:11,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:11,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:11,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:11,604 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:11,604 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 13:24:11,604 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:24:11,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:24:11,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:11,605 INFO L87 Difference]: Start difference. First operand 525 states and 804 transitions. Second operand 5 states. [2018-11-28 13:24:11,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:11,770 INFO L93 Difference]: Finished difference Result 2028 states and 3129 transitions. [2018-11-28 13:24:11,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:24:11,772 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 46 [2018-11-28 13:24:11,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:11,776 INFO L225 Difference]: With dead ends: 2028 [2018-11-28 13:24:11,776 INFO L226 Difference]: Without dead ends: 1544 [2018-11-28 13:24:11,778 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:24:11,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1544 states. [2018-11-28 13:24:11,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1544 to 587. [2018-11-28 13:24:11,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 587 states. [2018-11-28 13:24:11,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 901 transitions. [2018-11-28 13:24:11,816 INFO L78 Accepts]: Start accepts. Automaton has 587 states and 901 transitions. Word has length 46 [2018-11-28 13:24:11,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:11,816 INFO L480 AbstractCegarLoop]: Abstraction has 587 states and 901 transitions. [2018-11-28 13:24:11,816 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:24:11,816 INFO L276 IsEmpty]: Start isEmpty. Operand 587 states and 901 transitions. [2018-11-28 13:24:11,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:11,817 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:11,817 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:11,817 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:11,817 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:11,817 INFO L82 PathProgramCache]: Analyzing trace with hash 605189396, now seen corresponding path program 1 times [2018-11-28 13:24:11,817 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:11,817 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:11,818 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:11,818 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:11,818 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:11,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:11,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:11,862 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:11,862 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:24:11,862 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:24:11,862 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:24:11,862 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:24:11,863 INFO L87 Difference]: Start difference. First operand 587 states and 901 transitions. Second operand 4 states. [2018-11-28 13:24:11,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:11,990 INFO L93 Difference]: Finished difference Result 1686 states and 2621 transitions. [2018-11-28 13:24:11,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:24:11,990 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-11-28 13:24:11,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:11,993 INFO L225 Difference]: With dead ends: 1686 [2018-11-28 13:24:11,993 INFO L226 Difference]: Without dead ends: 1137 [2018-11-28 13:24:11,995 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:11,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1137 states. [2018-11-28 13:24:12,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1137 to 1121. [2018-11-28 13:24:12,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1121 states. [2018-11-28 13:24:12,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1731 transitions. [2018-11-28 13:24:12,050 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1731 transitions. Word has length 46 [2018-11-28 13:24:12,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:12,051 INFO L480 AbstractCegarLoop]: Abstraction has 1121 states and 1731 transitions. [2018-11-28 13:24:12,051 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:24:12,051 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1731 transitions. [2018-11-28 13:24:12,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:12,052 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:12,052 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:12,052 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:12,052 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:12,052 INFO L82 PathProgramCache]: Analyzing trace with hash 1027891222, now seen corresponding path program 1 times [2018-11-28 13:24:12,052 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:12,052 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:12,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:12,053 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:12,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:12,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:12,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:12,086 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:12,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:24:12,086 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:24:12,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:24:12,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:24:12,087 INFO L87 Difference]: Start difference. First operand 1121 states and 1731 transitions. Second operand 4 states. [2018-11-28 13:24:12,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:12,237 INFO L93 Difference]: Finished difference Result 2615 states and 4073 transitions. [2018-11-28 13:24:12,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:24:12,238 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 46 [2018-11-28 13:24:12,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:12,242 INFO L225 Difference]: With dead ends: 2615 [2018-11-28 13:24:12,242 INFO L226 Difference]: Without dead ends: 1597 [2018-11-28 13:24:12,244 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:12,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1597 states. [2018-11-28 13:24:12,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1597 to 1590. [2018-11-28 13:24:12,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1590 states. [2018-11-28 13:24:12,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1590 states to 1590 states and 2433 transitions. [2018-11-28 13:24:12,321 INFO L78 Accepts]: Start accepts. Automaton has 1590 states and 2433 transitions. Word has length 46 [2018-11-28 13:24:12,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:12,321 INFO L480 AbstractCegarLoop]: Abstraction has 1590 states and 2433 transitions. [2018-11-28 13:24:12,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:24:12,321 INFO L276 IsEmpty]: Start isEmpty. Operand 1590 states and 2433 transitions. [2018-11-28 13:24:12,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-28 13:24:12,322 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:12,322 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:12,322 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:12,323 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:12,323 INFO L82 PathProgramCache]: Analyzing trace with hash -560456680, now seen corresponding path program 1 times [2018-11-28 13:24:12,323 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:12,323 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:12,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:12,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:12,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:12,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:12,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:12,348 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:12,348 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 13:24:12,348 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:24:12,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:24:12,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:12,348 INFO L87 Difference]: Start difference. First operand 1590 states and 2433 transitions. Second operand 3 states. [2018-11-28 13:24:12,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:12,473 INFO L93 Difference]: Finished difference Result 3289 states and 5113 transitions. [2018-11-28 13:24:12,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:24:12,474 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2018-11-28 13:24:12,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:12,478 INFO L225 Difference]: With dead ends: 3289 [2018-11-28 13:24:12,479 INFO L226 Difference]: Without dead ends: 1749 [2018-11-28 13:24:12,483 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:12,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1749 states. [2018-11-28 13:24:12,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1749 to 1709. [2018-11-28 13:24:12,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1709 states. [2018-11-28 13:24:12,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1709 states to 1709 states and 2589 transitions. [2018-11-28 13:24:12,598 INFO L78 Accepts]: Start accepts. Automaton has 1709 states and 2589 transitions. Word has length 46 [2018-11-28 13:24:12,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:12,598 INFO L480 AbstractCegarLoop]: Abstraction has 1709 states and 2589 transitions. [2018-11-28 13:24:12,599 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:24:12,599 INFO L276 IsEmpty]: Start isEmpty. Operand 1709 states and 2589 transitions. [2018-11-28 13:24:12,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-28 13:24:12,601 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:12,601 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:12,601 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:12,601 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:12,601 INFO L82 PathProgramCache]: Analyzing trace with hash 1832125989, now seen corresponding path program 1 times [2018-11-28 13:24:12,602 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:12,602 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:12,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:12,602 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:12,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:12,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:12,647 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 19 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-28 13:24:12,647 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:12,647 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:12,669 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:12,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:12,741 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:12,770 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-28 13:24:12,786 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:24:12,787 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-11-28 13:24:12,787 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-28 13:24:12,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-28 13:24:12,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:24:12,787 INFO L87 Difference]: Start difference. First operand 1709 states and 2589 transitions. Second operand 8 states. [2018-11-28 13:24:13,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:13,725 INFO L93 Difference]: Finished difference Result 5664 states and 8960 transitions. [2018-11-28 13:24:13,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-28 13:24:13,726 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 80 [2018-11-28 13:24:13,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:13,735 INFO L225 Difference]: With dead ends: 5664 [2018-11-28 13:24:13,735 INFO L226 Difference]: Without dead ends: 1562 [2018-11-28 13:24:13,749 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=124, Invalid=338, Unknown=0, NotChecked=0, Total=462 [2018-11-28 13:24:13,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1562 states. [2018-11-28 13:24:13,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1562 to 1072. [2018-11-28 13:24:13,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1072 states. [2018-11-28 13:24:13,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1072 states to 1072 states and 1587 transitions. [2018-11-28 13:24:13,853 INFO L78 Accepts]: Start accepts. Automaton has 1072 states and 1587 transitions. Word has length 80 [2018-11-28 13:24:13,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:13,853 INFO L480 AbstractCegarLoop]: Abstraction has 1072 states and 1587 transitions. [2018-11-28 13:24:13,853 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-28 13:24:13,853 INFO L276 IsEmpty]: Start isEmpty. Operand 1072 states and 1587 transitions. [2018-11-28 13:24:13,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-11-28 13:24:13,857 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:13,857 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:13,857 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:13,857 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:13,858 INFO L82 PathProgramCache]: Analyzing trace with hash 527566372, now seen corresponding path program 1 times [2018-11-28 13:24:13,858 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:13,858 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:13,858 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:13,859 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:13,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:13,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:13,964 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-28 13:24:13,964 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:13,964 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-28 13:24:13,964 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 13:24:13,965 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 13:24:13,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:24:13,965 INFO L87 Difference]: Start difference. First operand 1072 states and 1587 transitions. Second operand 6 states. [2018-11-28 13:24:14,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:14,477 INFO L93 Difference]: Finished difference Result 3492 states and 5338 transitions. [2018-11-28 13:24:14,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 13:24:14,478 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 121 [2018-11-28 13:24:14,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:14,489 INFO L225 Difference]: With dead ends: 3492 [2018-11-28 13:24:14,489 INFO L226 Difference]: Without dead ends: 2497 [2018-11-28 13:24:14,493 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:24:14,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2497 states. [2018-11-28 13:24:14,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2497 to 2245. [2018-11-28 13:24:14,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2245 states. [2018-11-28 13:24:14,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2245 states to 2245 states and 3441 transitions. [2018-11-28 13:24:14,724 INFO L78 Accepts]: Start accepts. Automaton has 2245 states and 3441 transitions. Word has length 121 [2018-11-28 13:24:14,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:14,724 INFO L480 AbstractCegarLoop]: Abstraction has 2245 states and 3441 transitions. [2018-11-28 13:24:14,724 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 13:24:14,724 INFO L276 IsEmpty]: Start isEmpty. Operand 2245 states and 3441 transitions. [2018-11-28 13:24:14,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-11-28 13:24:14,730 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:14,730 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:14,731 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:14,731 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:14,731 INFO L82 PathProgramCache]: Analyzing trace with hash -1956157466, now seen corresponding path program 1 times [2018-11-28 13:24:14,731 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:14,731 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:14,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:14,732 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:14,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:14,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:14,849 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 6 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-28 13:24:14,849 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:14,849 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:14,861 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:14,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:14,951 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:14,993 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-28 13:24:15,018 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:24:15,018 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [9] total 11 [2018-11-28 13:24:15,019 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 13:24:15,019 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 13:24:15,019 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:24:15,019 INFO L87 Difference]: Start difference. First operand 2245 states and 3441 transitions. Second operand 11 states. [2018-11-28 13:24:15,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:15,844 INFO L93 Difference]: Finished difference Result 4305 states and 6737 transitions. [2018-11-28 13:24:15,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-28 13:24:15,845 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 121 [2018-11-28 13:24:15,845 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:15,858 INFO L225 Difference]: With dead ends: 4305 [2018-11-28 13:24:15,858 INFO L226 Difference]: Without dead ends: 2781 [2018-11-28 13:24:15,864 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 146 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=126, Invalid=294, Unknown=0, NotChecked=0, Total=420 [2018-11-28 13:24:15,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2781 states. [2018-11-28 13:24:16,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2781 to 1806. [2018-11-28 13:24:16,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1806 states. [2018-11-28 13:24:16,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1806 states to 1806 states and 2735 transitions. [2018-11-28 13:24:16,098 INFO L78 Accepts]: Start accepts. Automaton has 1806 states and 2735 transitions. Word has length 121 [2018-11-28 13:24:16,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:16,098 INFO L480 AbstractCegarLoop]: Abstraction has 1806 states and 2735 transitions. [2018-11-28 13:24:16,098 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 13:24:16,099 INFO L276 IsEmpty]: Start isEmpty. Operand 1806 states and 2735 transitions. [2018-11-28 13:24:16,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-11-28 13:24:16,103 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:16,104 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:16,104 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:16,104 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:16,104 INFO L82 PathProgramCache]: Analyzing trace with hash 512047654, now seen corresponding path program 1 times [2018-11-28 13:24:16,104 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:16,104 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:16,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:16,105 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:16,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:16,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:16,200 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 17 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 13:24:16,200 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:16,200 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:16,213 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:16,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:16,302 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:16,343 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 21 proven. 12 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-28 13:24:16,368 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-28 13:24:16,369 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 4] total 11 [2018-11-28 13:24:16,369 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-28 13:24:16,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-28 13:24:16,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:24:16,369 INFO L87 Difference]: Start difference. First operand 1806 states and 2735 transitions. Second operand 11 states. [2018-11-28 13:24:17,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:17,945 INFO L93 Difference]: Finished difference Result 4835 states and 7569 transitions. [2018-11-28 13:24:17,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-28 13:24:17,946 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 121 [2018-11-28 13:24:17,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:17,961 INFO L225 Difference]: With dead ends: 4835 [2018-11-28 13:24:17,962 INFO L226 Difference]: Without dead ends: 3103 [2018-11-28 13:24:17,974 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 130 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 171 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=209, Invalid=603, Unknown=0, NotChecked=0, Total=812 [2018-11-28 13:24:17,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3103 states. [2018-11-28 13:24:18,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3103 to 1869. [2018-11-28 13:24:18,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1869 states. [2018-11-28 13:24:18,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1869 states to 1869 states and 2685 transitions. [2018-11-28 13:24:18,147 INFO L78 Accepts]: Start accepts. Automaton has 1869 states and 2685 transitions. Word has length 121 [2018-11-28 13:24:18,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:18,147 INFO L480 AbstractCegarLoop]: Abstraction has 1869 states and 2685 transitions. [2018-11-28 13:24:18,147 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-28 13:24:18,147 INFO L276 IsEmpty]: Start isEmpty. Operand 1869 states and 2685 transitions. [2018-11-28 13:24:18,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-28 13:24:18,150 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:18,150 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:18,150 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:18,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:18,151 INFO L82 PathProgramCache]: Analyzing trace with hash -623475347, now seen corresponding path program 1 times [2018-11-28 13:24:18,151 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:18,151 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:18,151 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:18,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:18,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:18,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:18,191 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-28 13:24:18,191 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:18,192 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:24:18,192 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:24:18,192 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:24:18,192 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:24:18,192 INFO L87 Difference]: Start difference. First operand 1869 states and 2685 transitions. Second operand 4 states. [2018-11-28 13:24:18,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:18,559 INFO L93 Difference]: Finished difference Result 5051 states and 7352 transitions. [2018-11-28 13:24:18,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:24:18,560 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 123 [2018-11-28 13:24:18,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:18,571 INFO L225 Difference]: With dead ends: 5051 [2018-11-28 13:24:18,571 INFO L226 Difference]: Without dead ends: 3191 [2018-11-28 13:24:18,576 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:18,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3191 states. [2018-11-28 13:24:18,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3191 to 3055. [2018-11-28 13:24:18,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3055 states. [2018-11-28 13:24:18,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3055 states to 3055 states and 4487 transitions. [2018-11-28 13:24:18,927 INFO L78 Accepts]: Start accepts. Automaton has 3055 states and 4487 transitions. Word has length 123 [2018-11-28 13:24:18,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:18,927 INFO L480 AbstractCegarLoop]: Abstraction has 3055 states and 4487 transitions. [2018-11-28 13:24:18,927 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:24:18,927 INFO L276 IsEmpty]: Start isEmpty. Operand 3055 states and 4487 transitions. [2018-11-28 13:24:18,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-11-28 13:24:18,933 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:18,934 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:18,934 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:18,934 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:18,934 INFO L82 PathProgramCache]: Analyzing trace with hash -1945310007, now seen corresponding path program 1 times [2018-11-28 13:24:18,934 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:18,934 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:18,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:18,935 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:18,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:18,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:19,008 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-28 13:24:19,010 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:19,010 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:19,020 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:19,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:19,109 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:19,144 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-28 13:24:19,169 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:24:19,169 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-28 13:24:19,170 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 13:24:19,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 13:24:19,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:24:19,170 INFO L87 Difference]: Start difference. First operand 3055 states and 4487 transitions. Second operand 6 states. [2018-11-28 13:24:19,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:19,648 INFO L93 Difference]: Finished difference Result 6953 states and 10794 transitions. [2018-11-28 13:24:19,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 13:24:19,648 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 132 [2018-11-28 13:24:19,648 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:19,658 INFO L225 Difference]: With dead ends: 6953 [2018-11-28 13:24:19,659 INFO L226 Difference]: Without dead ends: 3924 [2018-11-28 13:24:19,665 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 142 GetRequests, 136 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:24:19,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3924 states. [2018-11-28 13:24:19,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3924 to 3836. [2018-11-28 13:24:19,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3836 states. [2018-11-28 13:24:19,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3836 states to 3836 states and 5620 transitions. [2018-11-28 13:24:19,907 INFO L78 Accepts]: Start accepts. Automaton has 3836 states and 5620 transitions. Word has length 132 [2018-11-28 13:24:19,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:19,907 INFO L480 AbstractCegarLoop]: Abstraction has 3836 states and 5620 transitions. [2018-11-28 13:24:19,907 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 13:24:19,907 INFO L276 IsEmpty]: Start isEmpty. Operand 3836 states and 5620 transitions. [2018-11-28 13:24:19,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-11-28 13:24:19,913 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:19,913 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:19,913 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:19,913 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:19,913 INFO L82 PathProgramCache]: Analyzing trace with hash 1263456783, now seen corresponding path program 1 times [2018-11-28 13:24:19,913 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:19,914 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:19,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:19,914 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:19,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:19,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:19,960 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-28 13:24:19,960 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:19,960 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 13:24:19,961 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:24:19,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:24:19,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:19,961 INFO L87 Difference]: Start difference. First operand 3836 states and 5620 transitions. Second operand 3 states. [2018-11-28 13:24:20,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:20,277 INFO L93 Difference]: Finished difference Result 8319 states and 12195 transitions. [2018-11-28 13:24:20,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:24:20,278 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 148 [2018-11-28 13:24:20,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:20,291 INFO L225 Difference]: With dead ends: 8319 [2018-11-28 13:24:20,291 INFO L226 Difference]: Without dead ends: 4519 [2018-11-28 13:24:20,298 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:20,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4519 states. [2018-11-28 13:24:20,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4519 to 4516. [2018-11-28 13:24:20,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4516 states. [2018-11-28 13:24:20,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4516 states to 4516 states and 6334 transitions. [2018-11-28 13:24:20,617 INFO L78 Accepts]: Start accepts. Automaton has 4516 states and 6334 transitions. Word has length 148 [2018-11-28 13:24:20,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:20,617 INFO L480 AbstractCegarLoop]: Abstraction has 4516 states and 6334 transitions. [2018-11-28 13:24:20,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:24:20,617 INFO L276 IsEmpty]: Start isEmpty. Operand 4516 states and 6334 transitions. [2018-11-28 13:24:20,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-11-28 13:24:20,623 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:20,623 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:20,623 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:20,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:20,623 INFO L82 PathProgramCache]: Analyzing trace with hash 282732019, now seen corresponding path program 1 times [2018-11-28 13:24:20,623 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:20,624 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:20,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:20,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:20,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:20,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:20,666 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-11-28 13:24:20,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:20,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:24:20,666 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:24:20,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:24:20,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:24:20,667 INFO L87 Difference]: Start difference. First operand 4516 states and 6334 transitions. Second operand 4 states. [2018-11-28 13:24:20,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:20,958 INFO L93 Difference]: Finished difference Result 8459 states and 11888 transitions. [2018-11-28 13:24:20,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:24:20,959 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 148 [2018-11-28 13:24:20,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:20,968 INFO L225 Difference]: With dead ends: 8459 [2018-11-28 13:24:20,968 INFO L226 Difference]: Without dead ends: 4491 [2018-11-28 13:24:20,975 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:20,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4491 states. [2018-11-28 13:24:21,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4491 to 4491. [2018-11-28 13:24:21,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4491 states. [2018-11-28 13:24:21,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4491 states to 4491 states and 6298 transitions. [2018-11-28 13:24:21,308 INFO L78 Accepts]: Start accepts. Automaton has 4491 states and 6298 transitions. Word has length 148 [2018-11-28 13:24:21,308 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:21,308 INFO L480 AbstractCegarLoop]: Abstraction has 4491 states and 6298 transitions. [2018-11-28 13:24:21,308 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:24:21,308 INFO L276 IsEmpty]: Start isEmpty. Operand 4491 states and 6298 transitions. [2018-11-28 13:24:21,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-11-28 13:24:21,341 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:21,341 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:21,341 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:21,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:21,341 INFO L82 PathProgramCache]: Analyzing trace with hash -1876352075, now seen corresponding path program 1 times [2018-11-28 13:24:21,341 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:21,342 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:21,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:21,342 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:21,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:21,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:21,414 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 48 proven. 2 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-28 13:24:21,415 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:21,415 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:21,433 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:21,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:21,529 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:21,547 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-28 13:24:21,572 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:24:21,572 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-28 13:24:21,573 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:24:21,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:24:21,573 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:21,573 INFO L87 Difference]: Start difference. First operand 4491 states and 6298 transitions. Second operand 5 states. [2018-11-28 13:24:22,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:22,130 INFO L93 Difference]: Finished difference Result 11612 states and 16526 transitions. [2018-11-28 13:24:22,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-28 13:24:22,130 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 148 [2018-11-28 13:24:22,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:22,144 INFO L225 Difference]: With dead ends: 11612 [2018-11-28 13:24:22,145 INFO L226 Difference]: Without dead ends: 6478 [2018-11-28 13:24:22,158 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 151 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:24:22,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6478 states. [2018-11-28 13:24:22,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6478 to 6455. [2018-11-28 13:24:22,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6455 states. [2018-11-28 13:24:22,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6455 states to 6455 states and 9026 transitions. [2018-11-28 13:24:22,616 INFO L78 Accepts]: Start accepts. Automaton has 6455 states and 9026 transitions. Word has length 148 [2018-11-28 13:24:22,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:22,616 INFO L480 AbstractCegarLoop]: Abstraction has 6455 states and 9026 transitions. [2018-11-28 13:24:22,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:24:22,617 INFO L276 IsEmpty]: Start isEmpty. Operand 6455 states and 9026 transitions. [2018-11-28 13:24:22,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2018-11-28 13:24:22,624 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:22,624 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:22,624 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:22,624 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:22,624 INFO L82 PathProgramCache]: Analyzing trace with hash -2030522642, now seen corresponding path program 1 times [2018-11-28 13:24:22,625 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:22,625 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:22,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:22,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:22,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:22,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:22,730 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 47 proven. 4 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-28 13:24:22,731 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:22,731 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:22,740 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:22,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:22,835 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:22,872 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 53 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-28 13:24:22,887 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:24:22,887 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-28 13:24:22,887 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-28 13:24:22,888 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 13:24:22,888 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:22,888 INFO L87 Difference]: Start difference. First operand 6455 states and 9026 transitions. Second operand 5 states. [2018-11-28 13:24:23,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:23,721 INFO L93 Difference]: Finished difference Result 17188 states and 24192 transitions. [2018-11-28 13:24:23,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 13:24:23,721 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 160 [2018-11-28 13:24:23,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:23,740 INFO L225 Difference]: With dead ends: 17188 [2018-11-28 13:24:23,740 INFO L226 Difference]: Without dead ends: 9653 [2018-11-28 13:24:23,752 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-28 13:24:23,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9653 states. [2018-11-28 13:24:24,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9653 to 8991. [2018-11-28 13:24:24,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8991 states. [2018-11-28 13:24:24,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8991 states to 8991 states and 11608 transitions. [2018-11-28 13:24:24,349 INFO L78 Accepts]: Start accepts. Automaton has 8991 states and 11608 transitions. Word has length 160 [2018-11-28 13:24:24,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:24,349 INFO L480 AbstractCegarLoop]: Abstraction has 8991 states and 11608 transitions. [2018-11-28 13:24:24,349 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-28 13:24:24,350 INFO L276 IsEmpty]: Start isEmpty. Operand 8991 states and 11608 transitions. [2018-11-28 13:24:24,355 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-11-28 13:24:24,355 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:24,355 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:24,356 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:24,356 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:24,356 INFO L82 PathProgramCache]: Analyzing trace with hash -2111688602, now seen corresponding path program 1 times [2018-11-28 13:24:24,356 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:24,356 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:24,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:24,356 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:24,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:24,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:24,403 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-28 13:24:24,403 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:24,403 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-28 13:24:24,404 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-28 13:24:24,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-28 13:24:24,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-28 13:24:24,406 INFO L87 Difference]: Start difference. First operand 8991 states and 11608 transitions. Second operand 4 states. [2018-11-28 13:24:25,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:25,061 INFO L93 Difference]: Finished difference Result 16484 states and 21234 transitions. [2018-11-28 13:24:25,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-28 13:24:25,061 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 161 [2018-11-28 13:24:25,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:25,076 INFO L225 Difference]: With dead ends: 16484 [2018-11-28 13:24:25,076 INFO L226 Difference]: Without dead ends: 8956 [2018-11-28 13:24:25,086 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-28 13:24:25,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8956 states. [2018-11-28 13:24:25,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8956 to 8956. [2018-11-28 13:24:25,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8956 states. [2018-11-28 13:24:25,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 11558 transitions. [2018-11-28 13:24:25,741 INFO L78 Accepts]: Start accepts. Automaton has 8956 states and 11558 transitions. Word has length 161 [2018-11-28 13:24:25,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:25,741 INFO L480 AbstractCegarLoop]: Abstraction has 8956 states and 11558 transitions. [2018-11-28 13:24:25,741 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-28 13:24:25,741 INFO L276 IsEmpty]: Start isEmpty. Operand 8956 states and 11558 transitions. [2018-11-28 13:24:25,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-11-28 13:24:25,750 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:25,750 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:25,751 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:25,751 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:25,751 INFO L82 PathProgramCache]: Analyzing trace with hash -1188521176, now seen corresponding path program 1 times [2018-11-28 13:24:25,751 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:25,751 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:25,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:25,752 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:25,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:25,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:25,810 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 37 proven. 10 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-28 13:24:25,810 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:25,810 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:25,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:25,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:25,892 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:25,917 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 53 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-28 13:24:25,933 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:24:25,934 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-28 13:24:25,934 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 13:24:25,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 13:24:25,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:24:25,934 INFO L87 Difference]: Start difference. First operand 8956 states and 11558 transitions. Second operand 6 states. [2018-11-28 13:24:26,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:26,783 INFO L93 Difference]: Finished difference Result 18394 states and 23923 transitions. [2018-11-28 13:24:26,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 13:24:26,784 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 161 [2018-11-28 13:24:26,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:26,806 INFO L225 Difference]: With dead ends: 18394 [2018-11-28 13:24:26,806 INFO L226 Difference]: Without dead ends: 9460 [2018-11-28 13:24:26,822 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-28 13:24:26,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9460 states. [2018-11-28 13:24:27,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9460 to 9435. [2018-11-28 13:24:27,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9435 states. [2018-11-28 13:24:27,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9435 states to 9435 states and 11734 transitions. [2018-11-28 13:24:27,496 INFO L78 Accepts]: Start accepts. Automaton has 9435 states and 11734 transitions. Word has length 161 [2018-11-28 13:24:27,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:27,496 INFO L480 AbstractCegarLoop]: Abstraction has 9435 states and 11734 transitions. [2018-11-28 13:24:27,496 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 13:24:27,496 INFO L276 IsEmpty]: Start isEmpty. Operand 9435 states and 11734 transitions. [2018-11-28 13:24:27,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 164 [2018-11-28 13:24:27,501 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:27,501 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:27,501 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:27,502 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:27,502 INFO L82 PathProgramCache]: Analyzing trace with hash -1709184774, now seen corresponding path program 1 times [2018-11-28 13:24:27,502 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:27,502 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:27,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:27,502 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:27,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:27,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:27,553 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 39 proven. 8 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-11-28 13:24:27,553 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:27,554 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:27,569 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:27,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:27,651 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:27,665 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-11-28 13:24:27,680 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:24:27,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-28 13:24:27,681 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-28 13:24:27,681 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-28 13:24:27,681 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-28 13:24:27,681 INFO L87 Difference]: Start difference. First operand 9435 states and 11734 transitions. Second operand 6 states. [2018-11-28 13:24:28,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:28,332 INFO L93 Difference]: Finished difference Result 14489 states and 18048 transitions. [2018-11-28 13:24:28,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-28 13:24:28,333 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 163 [2018-11-28 13:24:28,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:28,342 INFO L225 Difference]: With dead ends: 14489 [2018-11-28 13:24:28,342 INFO L226 Difference]: Without dead ends: 6111 [2018-11-28 13:24:28,350 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 170 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-28 13:24:28,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6111 states. [2018-11-28 13:24:28,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6111 to 5933. [2018-11-28 13:24:28,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5933 states. [2018-11-28 13:24:28,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5933 states to 5933 states and 7172 transitions. [2018-11-28 13:24:28,870 INFO L78 Accepts]: Start accepts. Automaton has 5933 states and 7172 transitions. Word has length 163 [2018-11-28 13:24:28,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:28,870 INFO L480 AbstractCegarLoop]: Abstraction has 5933 states and 7172 transitions. [2018-11-28 13:24:28,870 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-28 13:24:28,870 INFO L276 IsEmpty]: Start isEmpty. Operand 5933 states and 7172 transitions. [2018-11-28 13:24:28,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 212 [2018-11-28 13:24:28,872 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:28,872 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:28,872 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:28,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:28,872 INFO L82 PathProgramCache]: Analyzing trace with hash 1248070982, now seen corresponding path program 1 times [2018-11-28 13:24:28,872 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:28,873 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:28,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:28,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:28,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:28,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:29,106 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 43 proven. 65 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-28 13:24:29,106 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-28 13:24:29,106 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-28 13:24:29,112 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:29,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:29,182 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-28 13:24:29,285 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 71 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-11-28 13:24:29,300 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-28 13:24:29,301 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [16] total 20 [2018-11-28 13:24:29,301 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-28 13:24:29,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-28 13:24:29,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=340, Unknown=0, NotChecked=0, Total=380 [2018-11-28 13:24:29,301 INFO L87 Difference]: Start difference. First operand 5933 states and 7172 transitions. Second operand 20 states. [2018-11-28 13:24:38,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:38,666 INFO L93 Difference]: Finished difference Result 18970 states and 23388 transitions. [2018-11-28 13:24:38,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 189 states. [2018-11-28 13:24:38,666 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 211 [2018-11-28 13:24:38,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:38,688 INFO L225 Difference]: With dead ends: 18970 [2018-11-28 13:24:38,689 INFO L226 Difference]: Without dead ends: 14467 [2018-11-28 13:24:38,700 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 307 SyntacticMatches, 0 SemanticMatches, 204 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17331 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=3050, Invalid=39180, Unknown=0, NotChecked=0, Total=42230 [2018-11-28 13:24:38,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14467 states. [2018-11-28 13:24:39,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14467 to 11923. [2018-11-28 13:24:39,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11923 states. [2018-11-28 13:24:39,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11923 states to 11923 states and 14398 transitions. [2018-11-28 13:24:39,606 INFO L78 Accepts]: Start accepts. Automaton has 11923 states and 14398 transitions. Word has length 211 [2018-11-28 13:24:39,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:39,606 INFO L480 AbstractCegarLoop]: Abstraction has 11923 states and 14398 transitions. [2018-11-28 13:24:39,607 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-28 13:24:39,607 INFO L276 IsEmpty]: Start isEmpty. Operand 11923 states and 14398 transitions. [2018-11-28 13:24:39,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-11-28 13:24:39,609 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:39,609 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:39,609 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:39,610 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:39,610 INFO L82 PathProgramCache]: Analyzing trace with hash -557378392, now seen corresponding path program 1 times [2018-11-28 13:24:39,610 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:39,610 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:39,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:39,611 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:39,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:39,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 13:24:39,689 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 85 proven. 0 refuted. 0 times theorem prover too weak. 47 trivial. 0 not checked. [2018-11-28 13:24:39,689 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 13:24:39,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 13:24:39,690 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-28 13:24:39,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 13:24:39,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:39,691 INFO L87 Difference]: Start difference. First operand 11923 states and 14398 transitions. Second operand 3 states. [2018-11-28 13:24:40,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 13:24:40,573 INFO L93 Difference]: Finished difference Result 20264 states and 24874 transitions. [2018-11-28 13:24:40,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 13:24:40,573 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 233 [2018-11-28 13:24:40,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-28 13:24:40,589 INFO L225 Difference]: With dead ends: 20264 [2018-11-28 13:24:40,590 INFO L226 Difference]: Without dead ends: 10642 [2018-11-28 13:24:40,601 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 13:24:40,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10642 states. [2018-11-28 13:24:41,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10642 to 10536. [2018-11-28 13:24:41,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10536 states. [2018-11-28 13:24:41,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10536 states to 10536 states and 12572 transitions. [2018-11-28 13:24:41,375 INFO L78 Accepts]: Start accepts. Automaton has 10536 states and 12572 transitions. Word has length 233 [2018-11-28 13:24:41,375 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-28 13:24:41,375 INFO L480 AbstractCegarLoop]: Abstraction has 10536 states and 12572 transitions. [2018-11-28 13:24:41,375 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-28 13:24:41,375 INFO L276 IsEmpty]: Start isEmpty. Operand 10536 states and 12572 transitions. [2018-11-28 13:24:41,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-11-28 13:24:41,377 INFO L394 BasicCegarLoop]: Found error trace [2018-11-28 13:24:41,377 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 13:24:41,377 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-28 13:24:41,377 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 13:24:41,377 INFO L82 PathProgramCache]: Analyzing trace with hash 1383203622, now seen corresponding path program 1 times [2018-11-28 13:24:41,377 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 13:24:41,377 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 13:24:41,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:41,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 13:24:41,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 13:24:41,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 13:24:41,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 13:24:41,503 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-11-28 13:24:41,650 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 01:24:41 BoogieIcfgContainer [2018-11-28 13:24:41,650 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-28 13:24:41,651 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 13:24:41,651 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 13:24:41,651 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 13:24:41,651 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 01:24:10" (3/4) ... [2018-11-28 13:24:41,653 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-28 13:24:41,804 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_702b9e1a-051a-4aa3-bf2e-8d6e442c6d59/bin-2019/uautomizer/witness.graphml [2018-11-28 13:24:41,804 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 13:24:41,805 INFO L168 Benchmark]: Toolchain (without parser) took 32439.29 ms. Allocated memory was 1.0 GB in the beginning and 3.0 GB in the end (delta: 2.0 GB). Free memory was 959.8 MB in the beginning and 1.5 GB in the end (delta: -503.3 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2018-11-28 13:24:41,806 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 13:24:41,806 INFO L168 Benchmark]: CACSL2BoogieTranslator took 203.77 ms. Allocated memory is still 1.0 GB. Free memory was 959.8 MB in the beginning and 943.7 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-28 13:24:41,806 INFO L168 Benchmark]: Boogie Procedure Inliner took 53.21 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 133.7 MB). Free memory was 943.7 MB in the beginning and 1.1 GB in the end (delta: -191.9 MB). Peak memory consumption was 13.3 MB. Max. memory is 11.5 GB. [2018-11-28 13:24:41,807 INFO L168 Benchmark]: Boogie Preprocessor took 35.05 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. [2018-11-28 13:24:41,807 INFO L168 Benchmark]: RCFGBuilder took 473.86 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 46.1 MB). Peak memory consumption was 46.1 MB. Max. memory is 11.5 GB. [2018-11-28 13:24:41,807 INFO L168 Benchmark]: TraceAbstraction took 31516.41 ms. Allocated memory was 1.2 GB in the beginning and 3.0 GB in the end (delta: 1.8 GB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -427.8 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-11-28 13:24:41,807 INFO L168 Benchmark]: Witness Printer took 153.83 ms. Allocated memory is still 3.0 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 40.7 MB). Peak memory consumption was 40.7 MB. Max. memory is 11.5 GB. [2018-11-28 13:24:41,809 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 203.77 ms. Allocated memory is still 1.0 GB. Free memory was 959.8 MB in the beginning and 943.7 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 53.21 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 133.7 MB). Free memory was 943.7 MB in the beginning and 1.1 GB in the end (delta: -191.9 MB). Peak memory consumption was 13.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 35.05 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 473.86 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 46.1 MB). Peak memory consumption was 46.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 31516.41 ms. Allocated memory was 1.2 GB in the beginning and 3.0 GB in the end (delta: 1.8 GB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -427.8 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. * Witness Printer took 153.83 ms. Allocated memory is still 3.0 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 40.7 MB). Peak memory consumption was 40.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [\old(c)=17, \old(c1_i)=4, \old(c1_pc)=29, \old(c1_st)=24, \old(c2_i)=14, \old(c2_pc)=28, \old(c2_st)=25, \old(c_req_up)=30, \old(c_t)=20, \old(d)=23, \old(data)=18, \old(e_c)=11, \old(e_e)=31, \old(e_f)=21, \old(e_g)=10, \old(e_p_in)=8, \old(e_wl)=13, \old(p_in)=15, \old(p_out)=9, \old(processed)=16, \old(r_i)=26, \old(r_st)=7, \old(t_b)=12, \old(wb_i)=5, \old(wb_pc)=19, \old(wb_st)=3, \old(wl_i)=27, \old(wl_pc)=22, \old(wl_st)=6, c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L679] int __retres1 ; [L683] e_wl = 2 [L684] e_c = e_wl [L685] e_g = e_c [L686] e_f = e_g [L687] e_e = e_f [L688] wl_pc = 0 [L689] c1_pc = 0 [L690] c2_pc = 0 [L691] wb_pc = 0 [L692] wb_i = 1 [L693] c2_i = wb_i [L694] c1_i = c2_i [L695] wl_i = c1_i [L696] r_i = 0 [L697] c_req_up = 0 [L698] d = 0 [L699] c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=0, \old(e_e)=0, \old(e_f)=0, \old(e_g)=0, \old(e_wl)=0, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L700] CALL start_simulation() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L390] int kernel_st ; [L393] kernel_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L394] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L405] COND TRUE (int )wl_i == 1 [L406] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L410] COND TRUE (int )c1_i == 1 [L411] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )c2_i == 1 [L416] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )wb_i == 1 [L421] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND FALSE !((int )r_i == 1) [L428] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L463] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )c1_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L482] COND FALSE !((int )c2_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L491] COND FALSE !((int )wb_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L500] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L505] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L314] RET write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L329] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L127] COND TRUE (int )c1_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L138] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L329] RET compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L344] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L172] COND TRUE (int )c2_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L183] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L344] RET compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L359] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L217] COND TRUE (int )wb_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L228] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L359] RET write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L535] RET eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L537] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L538] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L565] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L570] COND TRUE (int )e_wl == 0 [L571] e_wl = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L575] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L576] COND TRUE (int )e_wl == 1 [L577] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L593] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L594] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L602] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L603] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L611] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L612] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L620] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L625] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L630] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L635] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L640] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L645] COND TRUE (int )e_wl == 1 [L646] e_wl = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L650] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L314] RET write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L329] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L127] COND FALSE !((int )c1_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L130] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L145] COND TRUE ! processed [L146] data += 1 [L147] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L148] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L149] COND TRUE (int )e_g == 1 [L150] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L157] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L138] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L329] RET compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L344] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L172] COND FALSE !((int )c2_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L175] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L190] COND TRUE ! processed [L191] data += 1 [L192] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L193] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L194] COND TRUE (int )e_g == 1 [L195] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L183] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L344] RET compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L359] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L217] COND FALSE !((int )wb_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L220] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L235] c_t = data [L236] c_req_up = 1 [L237] processed = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L228] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L359] RET write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L535] RET eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L537] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L538] COND TRUE (int )c_req_up == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L539] COND TRUE c != c_t [L540] c = c_t [L541] e_c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L545] c_req_up = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L565] COND TRUE (int )e_c == 0 [L566] e_c = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L570] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L575] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L583] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L584] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L593] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L594] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L602] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L603] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L611] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L612] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L620] COND TRUE (int )e_c == 1 [L621] r_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L625] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L630] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L635] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L640] COND TRUE (int )e_c == 1 [L641] e_c = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L645] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L650] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L653] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L656] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L659] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L337] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L352] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND TRUE (int )r_st == 0 [L369] tmp___3 = __VERIFIER_nondet_int() [L371] COND TRUE \read(tmp___3) [L373] r_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L374] CALL read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L249] d = c [L250] e_e = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L251] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L259] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L260] COND TRUE (int )e_e == 1 [L261] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L269] e_e = 2 [L270] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L374] RET read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L113] CALL error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 11 procedures, 158 locations, 1 error locations. UNSAFE Result, 31.4s OverallTime, 26 OverallIterations, 6 TraceHistogramMax, 20.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 7639 SDtfs, 21773 SDslu, 17957 SDs, 0 SdLazy, 15874 SolverSat, 3731 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 7.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1843 GetRequests, 1491 SyntacticMatches, 7 SemanticMatches, 345 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17678 ImplicationChecksByTransitivity, 4.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=11923occurred in iteration=24, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 6.9s AutomataMinimizationTime, 25 MinimizatonAttempts, 8109 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 4221 NumberOfCodeBlocks, 4221 NumberOfCodeBlocksAsserted, 35 NumberOfCheckSat, 3954 ConstructedInterpolants, 0 QuantifiedInterpolants, 1068559 SizeOfPredicates, 9 NumberOfNonLiveVariables, 8878 ConjunctsInSsa, 43 ConjunctsInUnsatCore, 34 InterpolantComputations, 24 PerfectInterpolantSequences, 1338/1474 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...