./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.13_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.13_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 8e2d25fbf8d8cd713a9c00bd03f1267ceae00265 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis No suitable file found in config dir /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: OutOfMemoryError: Java heap space --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 12:50:42,233 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 12:50:42,234 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 12:50:42,242 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 12:50:42,242 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 12:50:42,243 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 12:50:42,244 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 12:50:42,245 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 12:50:42,247 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 12:50:42,247 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 12:50:42,248 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 12:50:42,248 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 12:50:42,249 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 12:50:42,250 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 12:50:42,250 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 12:50:42,251 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 12:50:42,251 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 12:50:42,253 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 12:50:42,254 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 12:50:42,255 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 12:50:42,256 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 12:50:42,257 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 12:50:42,259 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 12:50:42,259 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 12:50:42,260 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 12:50:42,260 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 12:50:42,261 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 12:50:42,262 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 12:50:42,262 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 12:50:42,263 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 12:50:42,263 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 12:50:42,263 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 12:50:42,263 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 12:50:42,264 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 12:50:42,264 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 12:50:42,265 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 12:50:42,265 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-28 12:50:42,273 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 12:50:42,273 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 12:50:42,274 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 12:50:42,274 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 12:50:42,274 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 12:50:42,274 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-28 12:50:42,275 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-28 12:50:42,275 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-28 12:50:42,275 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-28 12:50:42,275 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-28 12:50:42,275 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-28 12:50:42,276 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 12:50:42,276 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 12:50:42,276 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 12:50:42,276 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 12:50:42,276 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 12:50:42,276 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 12:50:42,277 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-28 12:50:42,277 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-28 12:50:42,277 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-28 12:50:42,277 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 12:50:42,277 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-28 12:50:42,279 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-28 12:50:42,279 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 12:50:42,280 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-28 12:50:42,280 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 12:50:42,280 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 12:50:42,280 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-28 12:50:42,280 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 12:50:42,280 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 12:50:42,281 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-28 12:50:42,281 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-28 12:50:42,282 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8e2d25fbf8d8cd713a9c00bd03f1267ceae00265 [2018-11-28 12:50:42,309 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 12:50:42,319 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 12:50:42,321 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 12:50:42,323 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 12:50:42,323 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 12:50:42,324 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.13_false-unreach-call_false-termination.cil.c [2018-11-28 12:50:42,373 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/data/23e2f507d/93b0614069454c92a5498a175dc2718d/FLAGf98254774 [2018-11-28 12:50:42,773 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 12:50:42,773 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/sv-benchmarks/c/systemc/token_ring.13_false-unreach-call_false-termination.cil.c [2018-11-28 12:50:42,784 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/data/23e2f507d/93b0614069454c92a5498a175dc2718d/FLAGf98254774 [2018-11-28 12:50:43,136 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/data/23e2f507d/93b0614069454c92a5498a175dc2718d [2018-11-28 12:50:43,139 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 12:50:43,140 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-28 12:50:43,141 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 12:50:43,141 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 12:50:43,144 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 12:50:43,144 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,146 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ccccc15 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43, skipping insertion in model container [2018-11-28 12:50:43,146 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,152 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 12:50:43,188 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 12:50:43,410 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 12:50:43,417 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 12:50:43,546 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 12:50:43,561 INFO L195 MainTranslator]: Completed translation [2018-11-28 12:50:43,562 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43 WrapperNode [2018-11-28 12:50:43,562 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 12:50:43,562 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-28 12:50:43,562 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-28 12:50:43,563 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-28 12:50:43,568 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,577 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,652 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-28 12:50:43,653 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 12:50:43,653 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 12:50:43,653 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 12:50:43,660 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,660 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,669 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,669 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,700 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,727 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,734 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... [2018-11-28 12:50:43,742 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 12:50:43,742 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 12:50:43,742 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 12:50:43,743 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 12:50:43,743 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a9e1743-2373-48f5-8686-cf60c60d0557/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-28 12:50:43,793 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 12:50:43,794 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 12:50:45,789 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 12:50:45,790 INFO L280 CfgBuilder]: Removed 622 assue(true) statements. [2018-11-28 12:50:45,790 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:50:45 BoogieIcfgContainer [2018-11-28 12:50:45,790 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 12:50:45,791 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-28 12:50:45,791 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-28 12:50:45,793 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-28 12:50:45,794 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-28 12:50:45,794 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 12:50:43" (1/3) ... [2018-11-28 12:50:45,795 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@47fb0378 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 12:50:45, skipping insertion in model container [2018-11-28 12:50:45,795 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-28 12:50:45,795 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:50:43" (2/3) ... [2018-11-28 12:50:45,796 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@47fb0378 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 12:50:45, skipping insertion in model container [2018-11-28 12:50:45,796 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-28 12:50:45,796 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:50:45" (3/3) ... [2018-11-28 12:50:45,798 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.13_false-unreach-call_false-termination.cil.c [2018-11-28 12:50:45,842 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 12:50:45,843 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-28 12:50:45,843 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-28 12:50:45,843 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-28 12:50:45,843 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 12:50:45,843 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 12:50:45,843 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-28 12:50:45,844 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 12:50:45,844 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-28 12:50:45,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1994 states. [2018-11-28 12:50:45,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1819 [2018-11-28 12:50:45,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:45,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:45,948 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:45,948 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:45,948 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-28 12:50:45,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1994 states. [2018-11-28 12:50:45,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1819 [2018-11-28 12:50:45,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:45,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:45,966 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:45,966 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:45,973 INFO L794 eck$LassoCheckResult]: Stem: 375#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1179#L-1true havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1242#L1893true havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1547#L897true assume !(1 == ~m_i~0);~m_st~0 := 2; 161#L904-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 912#L909-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 772#L914-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 581#L919-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1241#L924-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 949#L929-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1771#L934-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1654#L939-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 488#L944-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 242#L949-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 853#L954-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 628#L959-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1305#L964-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 1202#L969-1true assume !(0 == ~M_E~0); 965#L1281-1true assume !(0 == ~T1_E~0); 1803#L1286-1true assume !(0 == ~T2_E~0); 1674#L1291-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 497#L1296-1true assume !(0 == ~T4_E~0); 258#L1301-1true assume !(0 == ~T5_E~0); 859#L1306-1true assume !(0 == ~T6_E~0); 643#L1311-1true assume !(0 == ~T7_E~0); 544#L1316-1true assume !(0 == ~T8_E~0); 1214#L1321-1true assume !(0 == ~T9_E~0); 1017#L1326-1true assume !(0 == ~T10_E~0); 1731#L1331-1true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1457#L1336-1true assume !(0 == ~T12_E~0); 346#L1341-1true assume !(0 == ~T13_E~0); 211#L1346-1true assume !(0 == ~E_M~0); 934#L1351-1true assume !(0 == ~E_1~0); 606#L1356-1true assume !(0 == ~E_2~0); 1281#L1361-1true assume !(0 == ~E_3~0); 1090#L1366-1true assume !(0 == ~E_4~0); 1004#L1371-1true assume 0 == ~E_5~0;~E_5~0 := 1; 1821#L1376-1true assume !(0 == ~E_6~0); 1562#L1381-1true assume !(0 == ~E_7~0); 277#L1386-1true assume !(0 == ~E_8~0); 22#L1391-1true assume !(0 == ~E_9~0); 752#L1396-1true assume !(0 == ~E_10~0); 703#L1401-1true assume !(0 == ~E_11~0); 1367#L1406-1true assume !(0 == ~E_12~0); 1033#L1411-1true assume 0 == ~E_13~0;~E_13~0 := 1; 1834#L1416-1true havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1700#L630true assume 1 == ~m_pc~0; 1491#L631true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 235#L641true is_master_triggered_#res := is_master_triggered_~__retres1~0; 48#L642true activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1960#L1593true assume !(0 != activate_threads_~tmp~1); 1967#L1593-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 816#L649true assume !(1 == ~t1_pc~0); 823#L649-2true is_transmit1_triggered_~__retres1~1 := 0; 1231#L660true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1199#L661true activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1423#L1601true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1428#L1601-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1987#L668true assume 1 == ~t2_pc~0; 1884#L669true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 506#L679true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 473#L680true activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 152#L1609true assume !(0 != activate_threads_~tmp___1~0); 154#L1609-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15#L687true assume !(1 == ~t3_pc~0); 5#L687-2true is_transmit3_triggered_~__retres1~3 := 0; 516#L698true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 577#L699true activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 743#L1617true assume !(0 != activate_threads_~tmp___2~0); 746#L1617-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1054#L706true assume 1 == ~t4_pc~0; 1153#L707true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1620#L717true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1694#L718true activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1284#L1625true assume !(0 != activate_threads_~tmp___3~0); 1288#L1625-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 324#L725true assume !(1 == ~t5_pc~0); 308#L725-2true is_transmit5_triggered_~__retres1~5 := 0; 748#L736true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 840#L737true activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 986#L1633true assume !(0 != activate_threads_~tmp___4~0); 991#L1633-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1298#L744true assume 1 == ~t6_pc~0; 1402#L745true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1845#L755true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1981#L756true activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1648#L1641true assume !(0 != activate_threads_~tmp___5~0); 1649#L1641-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1507#L763true assume 1 == ~t7_pc~0; 1431#L764true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 57#L774true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12#L775true activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 477#L1649true assume !(0 != activate_threads_~tmp___6~0); 483#L1649-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 755#L782true assume !(1 == ~t8_pc~0); 760#L782-2true is_transmit8_triggered_~__retres1~8 := 0; 1191#L793true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1061#L794true activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 94#L1657true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 99#L1657-2true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1910#L801true assume 1 == ~t9_pc~0; 1756#L802true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 484#L812true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 319#L813true activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 712#L1665true assume !(0 != activate_threads_~tmp___8~0); 713#L1665-2true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 108#L820true assume !(1 == ~t10_pc~0); 110#L820-2true is_transmit10_triggered_~__retres1~10 := 0; 582#L831true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1306#L832true activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1232#L1673true assume !(0 != activate_threads_~tmp___9~0); 1234#L1673-2true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1165#L839true assume 1 == ~t11_pc~0; 994#L840true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 1706#L850true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1502#L851true activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1988#L1681true assume !(0 != activate_threads_~tmp___10~0); 1994#L1681-2true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 432#L858true assume !(1 == ~t12_pc~0); 416#L858-2true is_transmit12_triggered_~__retres1~12 := 0; 850#L869true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 774#L870true activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1416#L1689true assume !(0 != activate_threads_~tmp___11~0); 1420#L1689-2true havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1245#L877true assume 1 == ~t13_pc~0; 1330#L878true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 1825#L888true is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1902#L889true activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 159#L1697true assume !(0 != activate_threads_~tmp___12~0); 160#L1697-2true assume !(1 == ~M_E~0); 337#L1429-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 202#L1434-1true assume !(1 == ~T2_E~0); 930#L1439-1true assume !(1 == ~T3_E~0); 599#L1444-1true assume !(1 == ~T4_E~0); 1273#L1449-1true assume !(1 == ~T5_E~0); 1081#L1454-1true assume !(1 == ~T6_E~0); 1001#L1459-1true assume !(1 == ~T7_E~0); 1819#L1464-1true assume !(1 == ~T8_E~0); 1586#L1469-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 294#L1474-1true assume !(1 == ~T10_E~0); 40#L1479-1true assume !(1 == ~T11_E~0); 924#L1484-1true assume !(1 == ~T12_E~0); 711#L1489-1true assume !(1 == ~T13_E~0); 1396#L1494-1true assume !(1 == ~E_M~0); 1050#L1499-1true assume !(1 == ~E_1~0); 1843#L1504-1true assume !(1 == ~E_2~0); 1642#L1509-1true assume 1 == ~E_3~0;~E_3~0 := 2; 1517#L1514-1true assume !(1 == ~E_4~0); 390#L1519-1true assume !(1 == ~E_5~0); 135#L1524-1true assume !(1 == ~E_6~0); 734#L1529-1true assume !(1 == ~E_7~0); 531#L1534-1true assume !(1 == ~E_8~0); 1314#L1539-1true assume !(1 == ~E_9~0); 1142#L1544-1true assume !(1 == ~E_10~0); 1971#L1549-1true assume 1 == ~E_11~0;~E_11~0 := 2; 1611#L1554-1true assume !(1 == ~E_12~0); 441#L1559-1true assume !(1 == ~E_13~0); 541#L1930-1true [2018-11-28 12:50:45,976 INFO L796 eck$LassoCheckResult]: Loop: 541#L1930-1true assume !false; 520#L1931true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 163#L1256true assume false; 585#L1271true start_simulation_~kernel_st~0 := 2; 1549#L897-1true start_simulation_~kernel_st~0 := 3; 967#L1281-2true assume 0 == ~M_E~0;~M_E~0 := 1; 952#L1281-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1773#L1286-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1659#L1291-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 490#L1296-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 262#L1301-3true assume !(0 == ~T5_E~0); 862#L1306-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 650#L1311-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 547#L1316-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1218#L1321-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1020#L1326-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1734#L1331-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1462#L1336-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 351#L1341-3true assume !(0 == ~T13_E~0); 216#L1346-3true assume 0 == ~E_M~0;~E_M~0 := 1; 927#L1351-3true assume 0 == ~E_1~0;~E_1~0 := 1; 714#L1356-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1262#L1361-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1070#L1366-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1000#L1371-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1817#L1376-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1569#L1381-3true assume !(0 == ~E_7~0); 282#L1386-3true assume 0 == ~E_8~0;~E_8~0 := 1; 27#L1391-3true assume 0 == ~E_9~0;~E_9~0 := 1; 753#L1396-3true assume 0 == ~E_10~0;~E_10~0 := 1; 705#L1401-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1374#L1406-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1039#L1411-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1837#L1416-3true havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1442#L630-45true assume 1 == ~m_pc~0; 1444#L631-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 195#L641-15true is_master_triggered_#res := is_master_triggered_~__retres1~0; 17#L642-15true activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1784#L1593-45true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1788#L1593-47true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 648#L649-45true assume 1 == ~t1_pc~0; 651#L650-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1220#L660-15true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1075#L661-15true activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 448#L1601-45true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 451#L1601-47true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1812#L668-45true assume !(1 == ~t2_pc~0); 1776#L668-47true is_transmit2_triggered_~__retres1~2 := 0; 491#L679-15true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 329#L680-15true activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 198#L1609-45true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 201#L1609-47true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66#L687-45true assume 1 == ~t3_pc~0; 69#L688-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 587#L698-15true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 548#L699-15true activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 777#L1617-45true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 782#L1617-47true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1136#L706-45true assume 1 == ~t4_pc~0; 1116#L707-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1717#L717-15true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1675#L718-15true activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1357#L1625-45true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1361#L1625-47true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 377#L725-45true assume 1 == ~t5_pc~0; 379#L726-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 727#L736-15true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 793#L737-15true activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1012#L1633-45true assume !(0 != activate_threads_~tmp___4~0); 1013#L1633-47true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1376#L744-45true assume 1 == ~t6_pc~0; 1380#L745-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1829#L755-15true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1959#L756-15true activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1720#L1641-45true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1722#L1641-47true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1564#L763-45true assume 1 == ~t7_pc~0; 1568#L764-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 26#L774-15true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 130#L775-15true activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 269#L1649-45true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 271#L1649-47true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 605#L782-45true assume !(1 == ~t8_pc~0); 608#L782-47true is_transmit8_triggered_~__retres1~8 := 0; 1095#L793-15true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1038#L794-15true activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 864#L1657-45true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 866#L1657-47true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1725#L801-45true assume 1 == ~t9_pc~0; 1728#L802-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 342#L812-15true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 279#L813-15true activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 521#L1665-45true assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 522#L1665-47true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 875#L820-45true assume 1 == ~t10_pc~0; 876#L821-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 560#L831-15true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1278#L832-15true activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1074#L1673-45true assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1077#L1673-47true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 979#L839-45true assume 1 == ~t11_pc~0; 958#L840-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 1666#L850-15true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1451#L851-15true activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1772#L1681-45true assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1780#L1681-47true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 168#L858-45true assume 1 == ~t12_pc~0; 169#L859-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 811#L869-15true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 664#L870-15true activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1514#L1689-45true assume !(0 != activate_threads_~tmp___11~0); 1516#L1689-47true havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1318#L877-45true assume !(1 == ~t13_pc~0); 1184#L877-47true is_transmit13_triggered_~__retres1~13 := 0; 1945#L888-15true is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1874#L889-15true activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 191#L1697-45true assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 196#L1697-47true assume 1 == ~M_E~0;~M_E~0 := 2; 343#L1429-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 208#L1434-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 933#L1439-3true assume !(1 == ~T3_E~0); 603#L1444-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1279#L1449-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1087#L1454-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1003#L1459-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1820#L1464-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1595#L1469-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 302#L1474-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 21#L1479-3true assume !(1 == ~T11_E~0); 751#L1484-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 702#L1489-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1366#L1494-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1031#L1499-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1833#L1504-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1645#L1509-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1521#L1514-3true assume 1 == ~E_4~0;~E_4~0 := 2; 396#L1519-3true assume !(1 == ~E_5~0); 140#L1524-3true assume 1 == ~E_6~0;~E_6~0 := 2; 739#L1529-3true assume 1 == ~E_7~0;~E_7~0 := 2; 534#L1534-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1319#L1539-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1149#L1544-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1980#L1549-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1618#L1554-3true assume 1 == ~E_12~0;~E_12~0 := 2; 438#L1559-3true assume !(1 == ~E_13~0); 164#L1564-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1715#L982-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1341#L1054-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1181#L1055-1true start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 1814#L1949true assume !(0 == start_simulation_~tmp~3); 1815#L1949-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1705#L982-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1346#L1054-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1182#L1055-2true stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 1824#L1904true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 446#L1911true stop_simulation_#res := stop_simulation_~__retres2~0; 434#L1912true start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 256#L1962true assume !(0 != start_simulation_~tmp___0~1); 541#L1930-1true [2018-11-28 12:50:45,991 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:45,991 INFO L82 PathProgramCache]: Analyzing trace with hash -1425010847, now seen corresponding path program 1 times [2018-11-28 12:50:45,993 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:45,994 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:46,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,030 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:46,030 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:46,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:46,152 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:46,152 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:46,156 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:46,156 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:46,156 INFO L82 PathProgramCache]: Analyzing trace with hash -100715658, now seen corresponding path program 1 times [2018-11-28 12:50:46,156 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:46,156 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:46,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,157 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:46,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:46,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:46,187 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:46,187 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:46,188 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:46,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:46,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:46,200 INFO L87 Difference]: Start difference. First operand 1994 states. Second operand 3 states. [2018-11-28 12:50:46,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:46,259 INFO L93 Difference]: Finished difference Result 1994 states and 2966 transitions. [2018-11-28 12:50:46,259 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:46,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1994 states and 2966 transitions. [2018-11-28 12:50:46,269 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:46,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1994 states to 1988 states and 2960 transitions. [2018-11-28 12:50:46,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:46,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:46,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2960 transitions. [2018-11-28 12:50:46,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:46,290 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2960 transitions. [2018-11-28 12:50:46,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2960 transitions. [2018-11-28 12:50:46,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:46,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:46,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2960 transitions. [2018-11-28 12:50:46,383 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2960 transitions. [2018-11-28 12:50:46,383 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2960 transitions. [2018-11-28 12:50:46,383 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-28 12:50:46,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2960 transitions. [2018-11-28 12:50:46,389 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:46,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:46,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:46,392 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:46,392 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:46,393 INFO L794 eck$LassoCheckResult]: Stem: 4558#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4559#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5407#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5445#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 4254#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4255#L909-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5012#L914-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4791#L919-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4792#L924-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5142#L929-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5143#L934-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5828#L939-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4666#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4371#L949-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4372#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4851#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4852#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5428#L969-1 assume !(0 == ~M_E~0); 5162#L1281-1 assume !(0 == ~T1_E~0); 5163#L1286-1 assume !(0 == ~T2_E~0); 5833#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4675#L1296-1 assume !(0 == ~T4_E~0); 4392#L1301-1 assume !(0 == ~T5_E~0); 4393#L1306-1 assume !(0 == ~T6_E~0); 4870#L1311-1 assume !(0 == ~T7_E~0); 4729#L1316-1 assume !(0 == ~T8_E~0); 4730#L1321-1 assume !(0 == ~T9_E~0); 5248#L1326-1 assume !(0 == ~T10_E~0); 5249#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5650#L1336-1 assume !(0 == ~T12_E~0); 4518#L1341-1 assume !(0 == ~T13_E~0); 4335#L1346-1 assume !(0 == ~E_M~0); 4336#L1351-1 assume !(0 == ~E_1~0); 4815#L1356-1 assume !(0 == ~E_2~0); 4816#L1361-1 assume !(0 == ~E_3~0); 5333#L1366-1 assume !(0 == ~E_4~0); 5229#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5230#L1376-1 assume !(0 == ~E_6~0); 5752#L1381-1 assume !(0 == ~E_7~0); 4417#L1386-1 assume !(0 == ~E_8~0); 4035#L1391-1 assume !(0 == ~E_9~0); 4036#L1396-1 assume !(0 == ~E_10~0); 4947#L1401-1 assume !(0 == ~E_11~0); 4948#L1406-1 assume !(0 == ~E_12~0); 5268#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 5269#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5836#L630 assume 1 == ~m_pc~0; 5688#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4365#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4086#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4087#L1593 assume !(0 != activate_threads_~tmp~1); 5982#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5046#L649 assume !(1 == ~t1_pc~0); 5006#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 5005#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5424#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5425#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5608#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5614#L668 assume 1 == ~t2_pc~0; 5954#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4684#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4652#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4242#L1609 assume !(0 != activate_threads_~tmp___1~0); 4243#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4021#L687 assume !(1 == ~t3_pc~0); 4001#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 4002#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4696#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4787#L1617 assume !(0 != activate_threads_~tmp___2~0); 4983#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4986#L706 assume 1 == ~t4_pc~0; 5295#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5299#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5801#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5490#L1625 assume !(0 != activate_threads_~tmp___3~0); 5491#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4493#L725 assume !(1 == ~t5_pc~0); 4468#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 4469#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4988#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5060#L1633 assume !(0 != activate_threads_~tmp___4~0); 5196#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5204#L744 assume 1 == ~t6_pc~0; 5499#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5501#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5925#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5825#L1641 assume !(0 != activate_threads_~tmp___5~0); 5826#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5708#L763 assume 1 == ~t7_pc~0; 5619#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4100#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4015#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4016#L1649 assume !(0 != activate_threads_~tmp___6~0); 4656#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4661#L782 assume !(1 == ~t8_pc~0); 4857#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 4856#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5303#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4169#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4170#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4181#L801 assume 1 == ~t9_pc~0; 5874#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 4662#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4486#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4487#L1665 assume !(0 != activate_threads_~tmp___8~0); 4955#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4196#L820 assume !(1 == ~t10_pc~0); 4197#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 4200#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 4793#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5442#L1673 assume !(0 != activate_threads_~tmp___9~0); 5443#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 5404#L839 assume 1 == ~t11_pc~0; 5209#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 5210#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 5701#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 5702#L1681 assume !(0 != activate_threads_~tmp___10~0); 5984#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 4606#L858 assume !(1 == ~t12_pc~0); 4543#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 4544#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 5014#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 5015#L1689 assume !(0 != activate_threads_~tmp___11~0); 5597#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 5450#L877 assume 1 == ~t13_pc~0; 5451#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 5457#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 5909#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4251#L1697 assume !(0 != activate_threads_~tmp___12~0); 4252#L1697-2 assume !(1 == ~M_E~0); 4253#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4321#L1434-1 assume !(1 == ~T2_E~0); 4322#L1439-1 assume !(1 == ~T3_E~0); 4802#L1444-1 assume !(1 == ~T4_E~0); 4803#L1449-1 assume !(1 == ~T5_E~0); 5323#L1454-1 assume !(1 == ~T6_E~0); 5224#L1459-1 assume !(1 == ~T7_E~0); 5225#L1464-1 assume !(1 == ~T8_E~0); 5770#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4447#L1474-1 assume !(1 == ~T10_E~0); 4071#L1479-1 assume !(1 == ~T11_E~0); 4072#L1484-1 assume !(1 == ~T12_E~0); 4953#L1489-1 assume !(1 == ~T13_E~0); 4954#L1494-1 assume !(1 == ~E_M~0); 5290#L1499-1 assume !(1 == ~E_1~0); 5291#L1504-1 assume !(1 == ~E_2~0); 5819#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5719#L1514-1 assume !(1 == ~E_4~0); 4576#L1519-1 assume !(1 == ~E_5~0); 4220#L1524-1 assume !(1 == ~E_6~0); 4221#L1529-1 assume !(1 == ~E_7~0); 4717#L1534-1 assume !(1 == ~E_8~0); 4718#L1539-1 assume !(1 == ~E_9~0); 5387#L1544-1 assume !(1 == ~E_10~0); 5388#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 5791#L1554-1 assume !(1 == ~E_12~0); 4617#L1559-1 assume !(1 == ~E_13~0); 4390#L1930-1 [2018-11-28 12:50:46,396 INFO L796 eck$LassoCheckResult]: Loop: 4390#L1930-1 assume !false; 4703#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 4049#L1256 assume !false; 4258#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5842#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4296#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5412#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5413#L1069 assume !(0 != eval_~tmp~0); 4794#L1271 start_simulation_~kernel_st~0 := 2; 4795#L897-1 start_simulation_~kernel_st~0 := 3; 5164#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5147#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5148#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5831#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4668#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4396#L1301-3 assume !(0 == ~T5_E~0); 4397#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4880#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4735#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4736#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5253#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5254#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5656#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4522#L1341-3 assume !(0 == ~T13_E~0); 4340#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4341#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4956#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4957#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5310#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5222#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5223#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5761#L1381-3 assume !(0 == ~E_7~0); 4427#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4045#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4046#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4950#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4951#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5277#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5278#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5635#L630-45 assume !(1 == ~m_pc~0); 5636#L630-47 is_master_triggered_~__retres1~0 := 0; 4313#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4025#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4026#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5890#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4877#L649-45 assume 1 == ~t1_pc~0; 4878#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4881#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5318#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4625#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4626#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4630#L668-45 assume 1 == ~t2_pc~0; 5884#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4669#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4501#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4317#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4318#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4117#L687-45 assume 1 == ~t3_pc~0; 4118#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4126#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4737#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4738#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5018#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5021#L706-45 assume 1 == ~t4_pc~0; 5355#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5356#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5834#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5564#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5565#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4561#L725-45 assume !(1 == ~t5_pc~0); 4562#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 4565#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4971#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5031#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 5242#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5243#L744-45 assume !(1 == ~t6_pc~0); 5556#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 5557#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5913#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5844#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5845#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5755#L763-45 assume !(1 == ~t7_pc~0); 5756#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 4043#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4044#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4216#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4405#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4409#L782-45 assume 1 == ~t8_pc~0; 4813#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4817#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5276#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5073#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 5074#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5077#L801-45 assume !(1 == ~t9_pc~0); 5849#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 4515#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4421#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4422#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 4704#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4705#L820-45 assume 1 == ~t10_pc~0; 5090#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 4761#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 4762#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5316#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 5317#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 5183#L839-45 assume 1 == ~t11_pc~0; 5153#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 5154#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 5641#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 5642#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 5883#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 4267#L858-45 assume !(1 == ~t12_pc~0); 4268#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 4270#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4896#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 4897#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 5717#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 5521#L877-45 assume 1 == ~t13_pc~0; 5522#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 5415#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 5948#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4307#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 4308#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 4314#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4330#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4331#L1439-3 assume !(1 == ~T3_E~0); 4811#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4812#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5330#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5227#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5228#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5773#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4460#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4033#L1479-3 assume !(1 == ~T11_E~0); 4034#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4945#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4946#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5264#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5265#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5823#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5724#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4584#L1519-3 assume !(1 == ~E_5~0); 4225#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4226#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4721#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4722#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5396#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5397#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5798#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4613#L1559-3 assume !(1 == ~E_13~0); 4259#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4260#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4299#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5408#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 5409#L1949 assume !(0 == start_simulation_~tmp~3); 5908#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5837#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4302#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5410#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 5411#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4622#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 4608#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 4389#L1962 assume !(0 != start_simulation_~tmp___0~1); 4390#L1930-1 [2018-11-28 12:50:46,397 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:46,398 INFO L82 PathProgramCache]: Analyzing trace with hash -813741789, now seen corresponding path program 1 times [2018-11-28 12:50:46,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:46,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:46,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:46,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:46,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:46,464 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:46,465 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:46,465 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:46,465 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:46,465 INFO L82 PathProgramCache]: Analyzing trace with hash -65346558, now seen corresponding path program 1 times [2018-11-28 12:50:46,465 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:46,466 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:46,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:46,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:46,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:46,569 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:46,570 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:46,570 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:46,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:46,570 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:46,571 INFO L87 Difference]: Start difference. First operand 1988 states and 2960 transitions. cyclomatic complexity: 973 Second operand 3 states. [2018-11-28 12:50:46,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:46,609 INFO L93 Difference]: Finished difference Result 1988 states and 2959 transitions. [2018-11-28 12:50:46,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:46,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2959 transitions. [2018-11-28 12:50:46,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:46,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2959 transitions. [2018-11-28 12:50:46,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:46,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:46,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2959 transitions. [2018-11-28 12:50:46,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:46,637 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2959 transitions. [2018-11-28 12:50:46,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2959 transitions. [2018-11-28 12:50:46,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:46,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:46,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2959 transitions. [2018-11-28 12:50:46,663 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2959 transitions. [2018-11-28 12:50:46,663 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2959 transitions. [2018-11-28 12:50:46,663 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-28 12:50:46,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2959 transitions. [2018-11-28 12:50:46,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:46,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:46,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:46,674 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:46,674 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:46,675 INFO L794 eck$LassoCheckResult]: Stem: 8541#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8542#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9390#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9428#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 8237#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8238#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8995#L914-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8774#L919-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8775#L924-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9125#L929-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9126#L934-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9811#L939-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8649#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8354#L949-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8355#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8834#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8835#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9411#L969-1 assume !(0 == ~M_E~0); 9145#L1281-1 assume !(0 == ~T1_E~0); 9146#L1286-1 assume !(0 == ~T2_E~0); 9816#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8658#L1296-1 assume !(0 == ~T4_E~0); 8375#L1301-1 assume !(0 == ~T5_E~0); 8376#L1306-1 assume !(0 == ~T6_E~0); 8853#L1311-1 assume !(0 == ~T7_E~0); 8712#L1316-1 assume !(0 == ~T8_E~0); 8713#L1321-1 assume !(0 == ~T9_E~0); 9231#L1326-1 assume !(0 == ~T10_E~0); 9232#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9633#L1336-1 assume !(0 == ~T12_E~0); 8501#L1341-1 assume !(0 == ~T13_E~0); 8318#L1346-1 assume !(0 == ~E_M~0); 8319#L1351-1 assume !(0 == ~E_1~0); 8798#L1356-1 assume !(0 == ~E_2~0); 8799#L1361-1 assume !(0 == ~E_3~0); 9316#L1366-1 assume !(0 == ~E_4~0); 9212#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 9213#L1376-1 assume !(0 == ~E_6~0); 9735#L1381-1 assume !(0 == ~E_7~0); 8400#L1386-1 assume !(0 == ~E_8~0); 8018#L1391-1 assume !(0 == ~E_9~0); 8019#L1396-1 assume !(0 == ~E_10~0); 8930#L1401-1 assume !(0 == ~E_11~0); 8931#L1406-1 assume !(0 == ~E_12~0); 9251#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 9252#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9819#L630 assume 1 == ~m_pc~0; 9671#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8348#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8069#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8070#L1593 assume !(0 != activate_threads_~tmp~1); 9965#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9029#L649 assume !(1 == ~t1_pc~0); 8989#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 8988#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9407#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9408#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9591#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9597#L668 assume 1 == ~t2_pc~0; 9937#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8667#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8635#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8225#L1609 assume !(0 != activate_threads_~tmp___1~0); 8226#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8004#L687 assume !(1 == ~t3_pc~0); 7984#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 7985#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8679#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8770#L1617 assume !(0 != activate_threads_~tmp___2~0); 8966#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8969#L706 assume 1 == ~t4_pc~0; 9278#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9282#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9784#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9473#L1625 assume !(0 != activate_threads_~tmp___3~0); 9474#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8476#L725 assume !(1 == ~t5_pc~0); 8451#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 8452#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8971#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 9043#L1633 assume !(0 != activate_threads_~tmp___4~0); 9179#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9187#L744 assume 1 == ~t6_pc~0; 9482#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9484#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9908#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 9808#L1641 assume !(0 != activate_threads_~tmp___5~0); 9809#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9691#L763 assume 1 == ~t7_pc~0; 9602#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8083#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7998#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7999#L1649 assume !(0 != activate_threads_~tmp___6~0); 8639#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8644#L782 assume !(1 == ~t8_pc~0); 8840#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 8839#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9286#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8152#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 8153#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 8164#L801 assume 1 == ~t9_pc~0; 9857#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 8645#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 8469#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 8470#L1665 assume !(0 != activate_threads_~tmp___8~0); 8938#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 8179#L820 assume !(1 == ~t10_pc~0); 8180#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 8183#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 8776#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9425#L1673 assume !(0 != activate_threads_~tmp___9~0); 9426#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 9387#L839 assume 1 == ~t11_pc~0; 9192#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 9193#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 9684#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 9685#L1681 assume !(0 != activate_threads_~tmp___10~0); 9967#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 8589#L858 assume !(1 == ~t12_pc~0); 8526#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 8527#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 8997#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8998#L1689 assume !(0 != activate_threads_~tmp___11~0); 9580#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 9433#L877 assume 1 == ~t13_pc~0; 9434#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 9440#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 9892#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8234#L1697 assume !(0 != activate_threads_~tmp___12~0); 8235#L1697-2 assume !(1 == ~M_E~0); 8236#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8304#L1434-1 assume !(1 == ~T2_E~0); 8305#L1439-1 assume !(1 == ~T3_E~0); 8785#L1444-1 assume !(1 == ~T4_E~0); 8786#L1449-1 assume !(1 == ~T5_E~0); 9306#L1454-1 assume !(1 == ~T6_E~0); 9207#L1459-1 assume !(1 == ~T7_E~0); 9208#L1464-1 assume !(1 == ~T8_E~0); 9753#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8430#L1474-1 assume !(1 == ~T10_E~0); 8054#L1479-1 assume !(1 == ~T11_E~0); 8055#L1484-1 assume !(1 == ~T12_E~0); 8936#L1489-1 assume !(1 == ~T13_E~0); 8937#L1494-1 assume !(1 == ~E_M~0); 9273#L1499-1 assume !(1 == ~E_1~0); 9274#L1504-1 assume !(1 == ~E_2~0); 9802#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9702#L1514-1 assume !(1 == ~E_4~0); 8559#L1519-1 assume !(1 == ~E_5~0); 8203#L1524-1 assume !(1 == ~E_6~0); 8204#L1529-1 assume !(1 == ~E_7~0); 8700#L1534-1 assume !(1 == ~E_8~0); 8701#L1539-1 assume !(1 == ~E_9~0); 9370#L1544-1 assume !(1 == ~E_10~0); 9371#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 9774#L1554-1 assume !(1 == ~E_12~0); 8600#L1559-1 assume !(1 == ~E_13~0); 8373#L1930-1 [2018-11-28 12:50:46,675 INFO L796 eck$LassoCheckResult]: Loop: 8373#L1930-1 assume !false; 8686#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 8032#L1256 assume !false; 8241#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 9825#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8279#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 9395#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9396#L1069 assume !(0 != eval_~tmp~0); 8777#L1271 start_simulation_~kernel_st~0 := 2; 8778#L897-1 start_simulation_~kernel_st~0 := 3; 9147#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9130#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9131#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9814#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8651#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8379#L1301-3 assume !(0 == ~T5_E~0); 8380#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8863#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8718#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8719#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9236#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9237#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9639#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8505#L1341-3 assume !(0 == ~T13_E~0); 8323#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8324#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8939#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8940#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9293#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9205#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9206#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9744#L1381-3 assume !(0 == ~E_7~0); 8410#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8028#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8029#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8933#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8934#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9260#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9261#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9618#L630-45 assume !(1 == ~m_pc~0); 9619#L630-47 is_master_triggered_~__retres1~0 := 0; 8296#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8008#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8009#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9873#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8860#L649-45 assume 1 == ~t1_pc~0; 8861#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8864#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9301#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8608#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8609#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8613#L668-45 assume 1 == ~t2_pc~0; 9867#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8652#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8484#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8300#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8301#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8100#L687-45 assume 1 == ~t3_pc~0; 8101#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8109#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8720#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8721#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9001#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9004#L706-45 assume 1 == ~t4_pc~0; 9338#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9339#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9817#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9547#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9548#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8544#L725-45 assume !(1 == ~t5_pc~0); 8545#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 8548#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8954#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 9014#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 9225#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9226#L744-45 assume !(1 == ~t6_pc~0); 9539#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 9540#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9896#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 9827#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9828#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9738#L763-45 assume !(1 == ~t7_pc~0); 9739#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 8026#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8027#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8199#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8388#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8392#L782-45 assume 1 == ~t8_pc~0; 8796#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8800#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9259#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9056#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9057#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9060#L801-45 assume !(1 == ~t9_pc~0); 9832#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 8498#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 8404#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 8405#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 8687#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 8688#L820-45 assume 1 == ~t10_pc~0; 9073#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 8744#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 8745#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9299#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 9300#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 9166#L839-45 assume 1 == ~t11_pc~0; 9136#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 9137#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 9624#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 9625#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 9866#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 8250#L858-45 assume !(1 == ~t12_pc~0); 8251#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 8253#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 8879#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8880#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 9700#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 9504#L877-45 assume 1 == ~t13_pc~0; 9505#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 9398#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 9931#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8290#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 8291#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 8297#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8313#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8314#L1439-3 assume !(1 == ~T3_E~0); 8794#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8795#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9313#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9210#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9211#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9756#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8443#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8016#L1479-3 assume !(1 == ~T11_E~0); 8017#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8928#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8929#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9247#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9248#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9806#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9707#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8567#L1519-3 assume !(1 == ~E_5~0); 8208#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8209#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8704#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8705#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9379#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9380#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9781#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8596#L1559-3 assume !(1 == ~E_13~0); 8242#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 8243#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8282#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 9391#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 9392#L1949 assume !(0 == start_simulation_~tmp~3); 9891#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 9820#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8285#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 9393#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 9394#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 8605#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 8591#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 8372#L1962 assume !(0 != start_simulation_~tmp___0~1); 8373#L1930-1 [2018-11-28 12:50:46,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:46,675 INFO L82 PathProgramCache]: Analyzing trace with hash 1586891621, now seen corresponding path program 1 times [2018-11-28 12:50:46,676 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:46,676 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:46,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,677 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:46,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:46,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:46,719 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:46,719 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:46,720 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:46,720 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:46,720 INFO L82 PathProgramCache]: Analyzing trace with hash -65346558, now seen corresponding path program 2 times [2018-11-28 12:50:46,720 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:46,720 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:46,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:46,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:46,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:46,795 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:46,795 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:46,796 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:46,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:46,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:46,796 INFO L87 Difference]: Start difference. First operand 1988 states and 2959 transitions. cyclomatic complexity: 972 Second operand 3 states. [2018-11-28 12:50:46,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:46,819 INFO L93 Difference]: Finished difference Result 1988 states and 2958 transitions. [2018-11-28 12:50:46,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:46,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2958 transitions. [2018-11-28 12:50:46,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:46,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2958 transitions. [2018-11-28 12:50:46,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:46,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:46,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2958 transitions. [2018-11-28 12:50:46,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:46,840 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2958 transitions. [2018-11-28 12:50:46,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2958 transitions. [2018-11-28 12:50:46,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:46,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:46,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2958 transitions. [2018-11-28 12:50:46,867 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2958 transitions. [2018-11-28 12:50:46,867 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2958 transitions. [2018-11-28 12:50:46,868 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-28 12:50:46,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2958 transitions. [2018-11-28 12:50:46,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:46,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:46,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:46,878 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:46,878 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:46,878 INFO L794 eck$LassoCheckResult]: Stem: 12524#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12525#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13373#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13411#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 12220#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12221#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12978#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12757#L919-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12758#L924-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13108#L929-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13109#L934-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13794#L939-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12632#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12337#L949-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12338#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12817#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12818#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13394#L969-1 assume !(0 == ~M_E~0); 13128#L1281-1 assume !(0 == ~T1_E~0); 13129#L1286-1 assume !(0 == ~T2_E~0); 13799#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12641#L1296-1 assume !(0 == ~T4_E~0); 12358#L1301-1 assume !(0 == ~T5_E~0); 12359#L1306-1 assume !(0 == ~T6_E~0); 12836#L1311-1 assume !(0 == ~T7_E~0); 12695#L1316-1 assume !(0 == ~T8_E~0); 12696#L1321-1 assume !(0 == ~T9_E~0); 13214#L1326-1 assume !(0 == ~T10_E~0); 13215#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13616#L1336-1 assume !(0 == ~T12_E~0); 12484#L1341-1 assume !(0 == ~T13_E~0); 12301#L1346-1 assume !(0 == ~E_M~0); 12302#L1351-1 assume !(0 == ~E_1~0); 12781#L1356-1 assume !(0 == ~E_2~0); 12782#L1361-1 assume !(0 == ~E_3~0); 13299#L1366-1 assume !(0 == ~E_4~0); 13195#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13196#L1376-1 assume !(0 == ~E_6~0); 13718#L1381-1 assume !(0 == ~E_7~0); 12383#L1386-1 assume !(0 == ~E_8~0); 12001#L1391-1 assume !(0 == ~E_9~0); 12002#L1396-1 assume !(0 == ~E_10~0); 12913#L1401-1 assume !(0 == ~E_11~0); 12914#L1406-1 assume !(0 == ~E_12~0); 13234#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 13235#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13802#L630 assume 1 == ~m_pc~0; 13654#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12331#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12052#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12053#L1593 assume !(0 != activate_threads_~tmp~1); 13948#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13012#L649 assume !(1 == ~t1_pc~0); 12972#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 12971#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13390#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13391#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13574#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13580#L668 assume 1 == ~t2_pc~0; 13920#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12650#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12618#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12208#L1609 assume !(0 != activate_threads_~tmp___1~0); 12209#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11987#L687 assume !(1 == ~t3_pc~0); 11967#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 11968#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12662#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12753#L1617 assume !(0 != activate_threads_~tmp___2~0); 12949#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12952#L706 assume 1 == ~t4_pc~0; 13261#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13265#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13767#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 13456#L1625 assume !(0 != activate_threads_~tmp___3~0); 13457#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12459#L725 assume !(1 == ~t5_pc~0); 12434#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 12435#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12954#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 13026#L1633 assume !(0 != activate_threads_~tmp___4~0); 13162#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13170#L744 assume 1 == ~t6_pc~0; 13465#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13467#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13891#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 13791#L1641 assume !(0 != activate_threads_~tmp___5~0); 13792#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13674#L763 assume 1 == ~t7_pc~0; 13585#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12066#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11981#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11982#L1649 assume !(0 != activate_threads_~tmp___6~0); 12622#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12627#L782 assume !(1 == ~t8_pc~0); 12823#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 12822#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 13269#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12135#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 12136#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12147#L801 assume 1 == ~t9_pc~0; 13840#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 12628#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12452#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12453#L1665 assume !(0 != activate_threads_~tmp___8~0); 12921#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12162#L820 assume !(1 == ~t10_pc~0); 12163#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 12166#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 12759#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 13408#L1673 assume !(0 != activate_threads_~tmp___9~0); 13409#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 13370#L839 assume 1 == ~t11_pc~0; 13175#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 13176#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 13667#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 13668#L1681 assume !(0 != activate_threads_~tmp___10~0); 13950#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 12572#L858 assume !(1 == ~t12_pc~0); 12509#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 12510#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 12980#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 12981#L1689 assume !(0 != activate_threads_~tmp___11~0); 13563#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 13416#L877 assume 1 == ~t13_pc~0; 13417#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 13423#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 13875#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12217#L1697 assume !(0 != activate_threads_~tmp___12~0); 12218#L1697-2 assume !(1 == ~M_E~0); 12219#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12287#L1434-1 assume !(1 == ~T2_E~0); 12288#L1439-1 assume !(1 == ~T3_E~0); 12768#L1444-1 assume !(1 == ~T4_E~0); 12769#L1449-1 assume !(1 == ~T5_E~0); 13289#L1454-1 assume !(1 == ~T6_E~0); 13190#L1459-1 assume !(1 == ~T7_E~0); 13191#L1464-1 assume !(1 == ~T8_E~0); 13736#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12413#L1474-1 assume !(1 == ~T10_E~0); 12037#L1479-1 assume !(1 == ~T11_E~0); 12038#L1484-1 assume !(1 == ~T12_E~0); 12919#L1489-1 assume !(1 == ~T13_E~0); 12920#L1494-1 assume !(1 == ~E_M~0); 13256#L1499-1 assume !(1 == ~E_1~0); 13257#L1504-1 assume !(1 == ~E_2~0); 13785#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 13685#L1514-1 assume !(1 == ~E_4~0); 12542#L1519-1 assume !(1 == ~E_5~0); 12186#L1524-1 assume !(1 == ~E_6~0); 12187#L1529-1 assume !(1 == ~E_7~0); 12683#L1534-1 assume !(1 == ~E_8~0); 12684#L1539-1 assume !(1 == ~E_9~0); 13353#L1544-1 assume !(1 == ~E_10~0); 13354#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 13757#L1554-1 assume !(1 == ~E_12~0); 12583#L1559-1 assume !(1 == ~E_13~0); 12356#L1930-1 [2018-11-28 12:50:46,879 INFO L796 eck$LassoCheckResult]: Loop: 12356#L1930-1 assume !false; 12669#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 12015#L1256 assume !false; 12224#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 13808#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12262#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 13378#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 13379#L1069 assume !(0 != eval_~tmp~0); 12760#L1271 start_simulation_~kernel_st~0 := 2; 12761#L897-1 start_simulation_~kernel_st~0 := 3; 13130#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13113#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13114#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13797#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12634#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12362#L1301-3 assume !(0 == ~T5_E~0); 12363#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12846#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12701#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12702#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13219#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13220#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13622#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12488#L1341-3 assume !(0 == ~T13_E~0); 12306#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12307#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12922#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12923#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13276#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13188#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13189#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13727#L1381-3 assume !(0 == ~E_7~0); 12393#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12011#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12012#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12916#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12917#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 13243#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13244#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13601#L630-45 assume !(1 == ~m_pc~0); 13602#L630-47 is_master_triggered_~__retres1~0 := 0; 12279#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11991#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11992#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13856#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12843#L649-45 assume 1 == ~t1_pc~0; 12844#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12847#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13284#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12591#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12592#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12596#L668-45 assume 1 == ~t2_pc~0; 13850#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12635#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12467#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12283#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12284#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12083#L687-45 assume 1 == ~t3_pc~0; 12084#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12092#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12703#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12704#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12984#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12987#L706-45 assume 1 == ~t4_pc~0; 13321#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13322#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13800#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 13530#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13531#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12527#L725-45 assume !(1 == ~t5_pc~0); 12528#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 12531#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12937#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12997#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 13208#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13209#L744-45 assume !(1 == ~t6_pc~0); 13522#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 13523#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13879#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 13810#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 13811#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13721#L763-45 assume !(1 == ~t7_pc~0); 13722#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 12009#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12010#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12182#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12371#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12375#L782-45 assume 1 == ~t8_pc~0; 12779#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12783#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 13242#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 13039#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13040#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 13043#L801-45 assume !(1 == ~t9_pc~0); 13815#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 12481#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12387#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12388#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 12670#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12671#L820-45 assume 1 == ~t10_pc~0; 13056#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 12727#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 12728#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 13282#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 13283#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 13149#L839-45 assume !(1 == ~t11_pc~0); 13121#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 13120#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 13607#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 13608#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 13849#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 12233#L858-45 assume !(1 == ~t12_pc~0); 12234#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 12236#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 12862#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 12863#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 13683#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 13487#L877-45 assume 1 == ~t13_pc~0; 13488#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 13381#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 13914#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12273#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 12274#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 12280#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12296#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12297#L1439-3 assume !(1 == ~T3_E~0); 12777#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12778#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13296#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13193#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13194#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13739#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12426#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11999#L1479-3 assume !(1 == ~T11_E~0); 12000#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12911#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12912#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13230#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13231#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13789#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13690#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12550#L1519-3 assume !(1 == ~E_5~0); 12191#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12192#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12687#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12688#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13362#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13363#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13764#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12579#L1559-3 assume !(1 == ~E_13~0); 12225#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 12226#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12265#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 13374#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 13375#L1949 assume !(0 == start_simulation_~tmp~3); 13874#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 13803#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12268#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 13376#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 13377#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 12588#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 12574#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 12355#L1962 assume !(0 != start_simulation_~tmp___0~1); 12356#L1930-1 [2018-11-28 12:50:46,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:46,879 INFO L82 PathProgramCache]: Analyzing trace with hash 140310755, now seen corresponding path program 1 times [2018-11-28 12:50:46,879 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:46,879 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:46,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,880 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:50:46,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:46,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:46,938 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:46,938 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:46,939 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:46,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:46,939 INFO L82 PathProgramCache]: Analyzing trace with hash -1206993951, now seen corresponding path program 1 times [2018-11-28 12:50:46,939 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:46,939 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:46,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,940 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:46,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:46,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,021 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,021 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,022 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:47,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:47,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:47,022 INFO L87 Difference]: Start difference. First operand 1988 states and 2958 transitions. cyclomatic complexity: 971 Second operand 3 states. [2018-11-28 12:50:47,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:47,047 INFO L93 Difference]: Finished difference Result 1988 states and 2957 transitions. [2018-11-28 12:50:47,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:47,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2957 transitions. [2018-11-28 12:50:47,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2957 transitions. [2018-11-28 12:50:47,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:47,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:47,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2957 transitions. [2018-11-28 12:50:47,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:47,071 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2957 transitions. [2018-11-28 12:50:47,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2957 transitions. [2018-11-28 12:50:47,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:47,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:47,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2957 transitions. [2018-11-28 12:50:47,142 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2957 transitions. [2018-11-28 12:50:47,142 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2957 transitions. [2018-11-28 12:50:47,142 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-28 12:50:47,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2957 transitions. [2018-11-28 12:50:47,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:47,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:47,151 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,151 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,152 INFO L794 eck$LassoCheckResult]: Stem: 16507#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16508#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17356#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17394#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 16203#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16204#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16961#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16740#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16741#L924-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17091#L929-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17092#L934-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17777#L939-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16615#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16320#L949-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16321#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16800#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16801#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17377#L969-1 assume !(0 == ~M_E~0); 17111#L1281-1 assume !(0 == ~T1_E~0); 17112#L1286-1 assume !(0 == ~T2_E~0); 17782#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16624#L1296-1 assume !(0 == ~T4_E~0); 16341#L1301-1 assume !(0 == ~T5_E~0); 16342#L1306-1 assume !(0 == ~T6_E~0); 16819#L1311-1 assume !(0 == ~T7_E~0); 16678#L1316-1 assume !(0 == ~T8_E~0); 16679#L1321-1 assume !(0 == ~T9_E~0); 17197#L1326-1 assume !(0 == ~T10_E~0); 17198#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17599#L1336-1 assume !(0 == ~T12_E~0); 16467#L1341-1 assume !(0 == ~T13_E~0); 16284#L1346-1 assume !(0 == ~E_M~0); 16285#L1351-1 assume !(0 == ~E_1~0); 16764#L1356-1 assume !(0 == ~E_2~0); 16765#L1361-1 assume !(0 == ~E_3~0); 17282#L1366-1 assume !(0 == ~E_4~0); 17178#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17179#L1376-1 assume !(0 == ~E_6~0); 17701#L1381-1 assume !(0 == ~E_7~0); 16366#L1386-1 assume !(0 == ~E_8~0); 15984#L1391-1 assume !(0 == ~E_9~0); 15985#L1396-1 assume !(0 == ~E_10~0); 16896#L1401-1 assume !(0 == ~E_11~0); 16897#L1406-1 assume !(0 == ~E_12~0); 17217#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 17218#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17785#L630 assume 1 == ~m_pc~0; 17637#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 16314#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16035#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16036#L1593 assume !(0 != activate_threads_~tmp~1); 17931#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16995#L649 assume !(1 == ~t1_pc~0); 16955#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 16954#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17373#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 17374#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17557#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17563#L668 assume 1 == ~t2_pc~0; 17903#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16633#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16601#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16191#L1609 assume !(0 != activate_threads_~tmp___1~0); 16192#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15970#L687 assume !(1 == ~t3_pc~0); 15950#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 15951#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16645#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16736#L1617 assume !(0 != activate_threads_~tmp___2~0); 16932#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16935#L706 assume 1 == ~t4_pc~0; 17244#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17248#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17750#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 17439#L1625 assume !(0 != activate_threads_~tmp___3~0); 17440#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16442#L725 assume !(1 == ~t5_pc~0); 16417#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 16418#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16937#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 17009#L1633 assume !(0 != activate_threads_~tmp___4~0); 17145#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17153#L744 assume 1 == ~t6_pc~0; 17448#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17450#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17874#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 17774#L1641 assume !(0 != activate_threads_~tmp___5~0); 17775#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17657#L763 assume 1 == ~t7_pc~0; 17568#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16049#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15964#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 15965#L1649 assume !(0 != activate_threads_~tmp___6~0); 16605#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16610#L782 assume !(1 == ~t8_pc~0); 16806#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 16805#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 17252#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16118#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 16119#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 16130#L801 assume 1 == ~t9_pc~0; 17823#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 16611#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16435#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16436#L1665 assume !(0 != activate_threads_~tmp___8~0); 16904#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 16145#L820 assume !(1 == ~t10_pc~0); 16146#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 16149#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 16742#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 17391#L1673 assume !(0 != activate_threads_~tmp___9~0); 17392#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 17353#L839 assume 1 == ~t11_pc~0; 17158#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 17159#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 17650#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 17651#L1681 assume !(0 != activate_threads_~tmp___10~0); 17933#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 16555#L858 assume !(1 == ~t12_pc~0); 16492#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 16493#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 16963#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 16964#L1689 assume !(0 != activate_threads_~tmp___11~0); 17546#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 17399#L877 assume 1 == ~t13_pc~0; 17400#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 17406#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 17858#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 16200#L1697 assume !(0 != activate_threads_~tmp___12~0); 16201#L1697-2 assume !(1 == ~M_E~0); 16202#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16270#L1434-1 assume !(1 == ~T2_E~0); 16271#L1439-1 assume !(1 == ~T3_E~0); 16751#L1444-1 assume !(1 == ~T4_E~0); 16752#L1449-1 assume !(1 == ~T5_E~0); 17272#L1454-1 assume !(1 == ~T6_E~0); 17173#L1459-1 assume !(1 == ~T7_E~0); 17174#L1464-1 assume !(1 == ~T8_E~0); 17719#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16396#L1474-1 assume !(1 == ~T10_E~0); 16020#L1479-1 assume !(1 == ~T11_E~0); 16021#L1484-1 assume !(1 == ~T12_E~0); 16902#L1489-1 assume !(1 == ~T13_E~0); 16903#L1494-1 assume !(1 == ~E_M~0); 17239#L1499-1 assume !(1 == ~E_1~0); 17240#L1504-1 assume !(1 == ~E_2~0); 17768#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 17668#L1514-1 assume !(1 == ~E_4~0); 16525#L1519-1 assume !(1 == ~E_5~0); 16169#L1524-1 assume !(1 == ~E_6~0); 16170#L1529-1 assume !(1 == ~E_7~0); 16666#L1534-1 assume !(1 == ~E_8~0); 16667#L1539-1 assume !(1 == ~E_9~0); 17336#L1544-1 assume !(1 == ~E_10~0); 17337#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 17740#L1554-1 assume !(1 == ~E_12~0); 16566#L1559-1 assume !(1 == ~E_13~0); 16339#L1930-1 [2018-11-28 12:50:47,152 INFO L796 eck$LassoCheckResult]: Loop: 16339#L1930-1 assume !false; 16652#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 15998#L1256 assume !false; 16207#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 17791#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16245#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 17361#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 17362#L1069 assume !(0 != eval_~tmp~0); 16743#L1271 start_simulation_~kernel_st~0 := 2; 16744#L897-1 start_simulation_~kernel_st~0 := 3; 17113#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17096#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17097#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17780#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16617#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16345#L1301-3 assume !(0 == ~T5_E~0); 16346#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16829#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16684#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16685#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17202#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17203#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17605#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16471#L1341-3 assume !(0 == ~T13_E~0); 16289#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16290#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16905#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16906#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17259#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17171#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17172#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17710#L1381-3 assume !(0 == ~E_7~0); 16376#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15994#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15995#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16899#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16900#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 17226#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17227#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17584#L630-45 assume !(1 == ~m_pc~0); 17585#L630-47 is_master_triggered_~__retres1~0 := 0; 16262#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15974#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15975#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17839#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16826#L649-45 assume 1 == ~t1_pc~0; 16827#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16830#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17267#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16574#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16575#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16579#L668-45 assume 1 == ~t2_pc~0; 17833#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16618#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16450#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16266#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16267#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16066#L687-45 assume 1 == ~t3_pc~0; 16067#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16075#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16686#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16687#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16967#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16970#L706-45 assume 1 == ~t4_pc~0; 17304#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17305#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17783#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 17513#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17514#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16510#L725-45 assume 1 == ~t5_pc~0; 16512#L726-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16514#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16920#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16980#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 17191#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17192#L744-45 assume !(1 == ~t6_pc~0); 17505#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 17506#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17862#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 17793#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 17794#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17704#L763-45 assume !(1 == ~t7_pc~0); 17705#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 15992#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15993#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16165#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 16354#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16358#L782-45 assume 1 == ~t8_pc~0; 16762#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 16766#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 17225#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 17022#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 17023#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 17026#L801-45 assume !(1 == ~t9_pc~0); 17798#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 16464#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16370#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16371#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 16653#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 16654#L820-45 assume !(1 == ~t10_pc~0); 17040#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 16710#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 16711#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 17265#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 17266#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 17132#L839-45 assume !(1 == ~t11_pc~0); 17104#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 17103#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 17590#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 17591#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 17832#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 16216#L858-45 assume !(1 == ~t12_pc~0); 16217#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 16219#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 16845#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 16846#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 17666#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 17470#L877-45 assume !(1 == ~t13_pc~0); 17363#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 17364#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 17897#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 16256#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 16257#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 16263#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16279#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16280#L1439-3 assume !(1 == ~T3_E~0); 16760#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16761#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17279#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17176#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17177#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17722#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16409#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15982#L1479-3 assume !(1 == ~T11_E~0); 15983#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16894#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16895#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17213#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17214#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17772#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17673#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16533#L1519-3 assume !(1 == ~E_5~0); 16174#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16175#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16670#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16671#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17345#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17346#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17747#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16562#L1559-3 assume !(1 == ~E_13~0); 16208#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 16209#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16248#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 17357#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 17358#L1949 assume !(0 == start_simulation_~tmp~3); 17857#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 17786#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16251#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 17359#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 17360#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 16571#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 16557#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 16338#L1962 assume !(0 != start_simulation_~tmp___0~1); 16339#L1930-1 [2018-11-28 12:50:47,152 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,153 INFO L82 PathProgramCache]: Analyzing trace with hash 1063478181, now seen corresponding path program 1 times [2018-11-28 12:50:47,153 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,153 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,154 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,209 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,209 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,209 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:47,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,209 INFO L82 PathProgramCache]: Analyzing trace with hash -2083075456, now seen corresponding path program 1 times [2018-11-28 12:50:47,210 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,210 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,210 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,283 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,283 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,283 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:47,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:47,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:47,284 INFO L87 Difference]: Start difference. First operand 1988 states and 2957 transitions. cyclomatic complexity: 970 Second operand 3 states. [2018-11-28 12:50:47,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:47,315 INFO L93 Difference]: Finished difference Result 1988 states and 2956 transitions. [2018-11-28 12:50:47,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:47,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2956 transitions. [2018-11-28 12:50:47,323 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2956 transitions. [2018-11-28 12:50:47,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:47,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:47,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2956 transitions. [2018-11-28 12:50:47,336 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:47,336 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2956 transitions. [2018-11-28 12:50:47,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2956 transitions. [2018-11-28 12:50:47,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:47,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:47,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2956 transitions. [2018-11-28 12:50:47,363 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2956 transitions. [2018-11-28 12:50:47,363 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2956 transitions. [2018-11-28 12:50:47,363 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-28 12:50:47,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2956 transitions. [2018-11-28 12:50:47,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:47,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:47,371 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,371 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,372 INFO L794 eck$LassoCheckResult]: Stem: 20490#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20491#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21339#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21377#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 20186#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20187#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20944#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20723#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20724#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21074#L929-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21075#L934-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21760#L939-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20598#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20303#L949-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20304#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20783#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20784#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21360#L969-1 assume !(0 == ~M_E~0); 21094#L1281-1 assume !(0 == ~T1_E~0); 21095#L1286-1 assume !(0 == ~T2_E~0); 21765#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20607#L1296-1 assume !(0 == ~T4_E~0); 20324#L1301-1 assume !(0 == ~T5_E~0); 20325#L1306-1 assume !(0 == ~T6_E~0); 20802#L1311-1 assume !(0 == ~T7_E~0); 20661#L1316-1 assume !(0 == ~T8_E~0); 20662#L1321-1 assume !(0 == ~T9_E~0); 21180#L1326-1 assume !(0 == ~T10_E~0); 21181#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21582#L1336-1 assume !(0 == ~T12_E~0); 20450#L1341-1 assume !(0 == ~T13_E~0); 20267#L1346-1 assume !(0 == ~E_M~0); 20268#L1351-1 assume !(0 == ~E_1~0); 20747#L1356-1 assume !(0 == ~E_2~0); 20748#L1361-1 assume !(0 == ~E_3~0); 21265#L1366-1 assume !(0 == ~E_4~0); 21161#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 21162#L1376-1 assume !(0 == ~E_6~0); 21684#L1381-1 assume !(0 == ~E_7~0); 20349#L1386-1 assume !(0 == ~E_8~0); 19967#L1391-1 assume !(0 == ~E_9~0); 19968#L1396-1 assume !(0 == ~E_10~0); 20879#L1401-1 assume !(0 == ~E_11~0); 20880#L1406-1 assume !(0 == ~E_12~0); 21200#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 21201#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21768#L630 assume 1 == ~m_pc~0; 21620#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 20297#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20018#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20019#L1593 assume !(0 != activate_threads_~tmp~1); 21914#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20978#L649 assume !(1 == ~t1_pc~0); 20938#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 20937#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21356#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21357#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21540#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21546#L668 assume 1 == ~t2_pc~0; 21886#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 20616#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20584#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20174#L1609 assume !(0 != activate_threads_~tmp___1~0); 20175#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19953#L687 assume !(1 == ~t3_pc~0); 19933#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 19934#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20628#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 20719#L1617 assume !(0 != activate_threads_~tmp___2~0); 20915#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20918#L706 assume 1 == ~t4_pc~0; 21227#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 21231#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21733#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21422#L1625 assume !(0 != activate_threads_~tmp___3~0); 21423#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20425#L725 assume !(1 == ~t5_pc~0); 20400#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 20401#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20920#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 20992#L1633 assume !(0 != activate_threads_~tmp___4~0); 21128#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21136#L744 assume 1 == ~t6_pc~0; 21431#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 21433#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21857#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21757#L1641 assume !(0 != activate_threads_~tmp___5~0); 21758#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21640#L763 assume 1 == ~t7_pc~0; 21551#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 20032#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19947#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 19948#L1649 assume !(0 != activate_threads_~tmp___6~0); 20588#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 20593#L782 assume !(1 == ~t8_pc~0); 20789#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 20788#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21235#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 20101#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 20102#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 20113#L801 assume 1 == ~t9_pc~0; 21806#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 20594#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 20418#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 20419#L1665 assume !(0 != activate_threads_~tmp___8~0); 20887#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 20128#L820 assume !(1 == ~t10_pc~0); 20129#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 20132#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 20725#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21374#L1673 assume !(0 != activate_threads_~tmp___9~0); 21375#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 21336#L839 assume 1 == ~t11_pc~0; 21141#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 21142#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 21633#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 21634#L1681 assume !(0 != activate_threads_~tmp___10~0); 21916#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 20538#L858 assume !(1 == ~t12_pc~0); 20475#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 20476#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 20946#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 20947#L1689 assume !(0 != activate_threads_~tmp___11~0); 21529#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 21382#L877 assume 1 == ~t13_pc~0; 21383#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 21389#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 21841#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 20183#L1697 assume !(0 != activate_threads_~tmp___12~0); 20184#L1697-2 assume !(1 == ~M_E~0); 20185#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20253#L1434-1 assume !(1 == ~T2_E~0); 20254#L1439-1 assume !(1 == ~T3_E~0); 20734#L1444-1 assume !(1 == ~T4_E~0); 20735#L1449-1 assume !(1 == ~T5_E~0); 21255#L1454-1 assume !(1 == ~T6_E~0); 21156#L1459-1 assume !(1 == ~T7_E~0); 21157#L1464-1 assume !(1 == ~T8_E~0); 21702#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 20379#L1474-1 assume !(1 == ~T10_E~0); 20003#L1479-1 assume !(1 == ~T11_E~0); 20004#L1484-1 assume !(1 == ~T12_E~0); 20885#L1489-1 assume !(1 == ~T13_E~0); 20886#L1494-1 assume !(1 == ~E_M~0); 21222#L1499-1 assume !(1 == ~E_1~0); 21223#L1504-1 assume !(1 == ~E_2~0); 21751#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 21651#L1514-1 assume !(1 == ~E_4~0); 20508#L1519-1 assume !(1 == ~E_5~0); 20152#L1524-1 assume !(1 == ~E_6~0); 20153#L1529-1 assume !(1 == ~E_7~0); 20649#L1534-1 assume !(1 == ~E_8~0); 20650#L1539-1 assume !(1 == ~E_9~0); 21319#L1544-1 assume !(1 == ~E_10~0); 21320#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 21723#L1554-1 assume !(1 == ~E_12~0); 20549#L1559-1 assume !(1 == ~E_13~0); 20322#L1930-1 [2018-11-28 12:50:47,372 INFO L796 eck$LassoCheckResult]: Loop: 20322#L1930-1 assume !false; 20635#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 19981#L1256 assume !false; 20190#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 21774#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20228#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 21344#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 21345#L1069 assume !(0 != eval_~tmp~0); 20726#L1271 start_simulation_~kernel_st~0 := 2; 20727#L897-1 start_simulation_~kernel_st~0 := 3; 21096#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 21079#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21080#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21763#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20600#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20328#L1301-3 assume !(0 == ~T5_E~0); 20329#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20812#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20667#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20668#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21185#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21186#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21588#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20454#L1341-3 assume !(0 == ~T13_E~0); 20272#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20273#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20888#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20889#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21242#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21154#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21155#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21693#L1381-3 assume !(0 == ~E_7~0); 20359#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19977#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19978#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20882#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20883#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21209#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21210#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21567#L630-45 assume !(1 == ~m_pc~0); 21568#L630-47 is_master_triggered_~__retres1~0 := 0; 20245#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19957#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 19958#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21822#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20809#L649-45 assume 1 == ~t1_pc~0; 20810#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 20813#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21250#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20557#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20558#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20562#L668-45 assume 1 == ~t2_pc~0; 21816#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 20601#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20433#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20249#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20250#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20049#L687-45 assume 1 == ~t3_pc~0; 20050#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20058#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20669#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 20670#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20950#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20953#L706-45 assume 1 == ~t4_pc~0; 21287#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 21288#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21766#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21496#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21497#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20493#L725-45 assume !(1 == ~t5_pc~0); 20494#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 20497#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20903#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 20963#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 21174#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21175#L744-45 assume !(1 == ~t6_pc~0); 21488#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 21489#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21845#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21776#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 21777#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21687#L763-45 assume !(1 == ~t7_pc~0); 21688#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 19975#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19976#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 20148#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 20337#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 20341#L782-45 assume 1 == ~t8_pc~0; 20745#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 20749#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21208#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 21005#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21006#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21009#L801-45 assume !(1 == ~t9_pc~0); 21781#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 20447#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 20353#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 20354#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 20636#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 20637#L820-45 assume 1 == ~t10_pc~0; 21022#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 20693#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 20694#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21248#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 21249#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 21115#L839-45 assume 1 == ~t11_pc~0; 21085#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 21086#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 21573#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 21574#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 21815#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 20199#L858-45 assume !(1 == ~t12_pc~0); 20200#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 20202#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 20828#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 20829#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 21649#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 21453#L877-45 assume !(1 == ~t13_pc~0); 21346#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 21347#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 21880#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 20239#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 20240#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 20246#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20262#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20263#L1439-3 assume !(1 == ~T3_E~0); 20743#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20744#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21262#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21159#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21160#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21705#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 20392#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19965#L1479-3 assume !(1 == ~T11_E~0); 19966#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20877#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 20878#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21196#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21197#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21755#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21656#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20516#L1519-3 assume !(1 == ~E_5~0); 20157#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20158#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20653#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20654#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21328#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21329#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21730#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20545#L1559-3 assume !(1 == ~E_13~0); 20191#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 20192#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20231#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 21340#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 21341#L1949 assume !(0 == start_simulation_~tmp~3); 21840#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 21769#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20234#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 21342#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 21343#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 20554#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 20540#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 20321#L1962 assume !(0 != start_simulation_~tmp___0~1); 20322#L1930-1 [2018-11-28 12:50:47,372 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,372 INFO L82 PathProgramCache]: Analyzing trace with hash 677615779, now seen corresponding path program 1 times [2018-11-28 12:50:47,373 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,373 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,373 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,417 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,417 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,417 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:47,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,419 INFO L82 PathProgramCache]: Analyzing trace with hash -1373351327, now seen corresponding path program 1 times [2018-11-28 12:50:47,419 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,419 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,422 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,482 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,482 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,482 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:47,482 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:47,482 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:47,482 INFO L87 Difference]: Start difference. First operand 1988 states and 2956 transitions. cyclomatic complexity: 969 Second operand 3 states. [2018-11-28 12:50:47,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:47,503 INFO L93 Difference]: Finished difference Result 1988 states and 2955 transitions. [2018-11-28 12:50:47,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:47,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2955 transitions. [2018-11-28 12:50:47,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2955 transitions. [2018-11-28 12:50:47,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:47,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:47,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2955 transitions. [2018-11-28 12:50:47,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:47,523 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2955 transitions. [2018-11-28 12:50:47,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2955 transitions. [2018-11-28 12:50:47,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:47,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:47,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2955 transitions. [2018-11-28 12:50:47,551 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2955 transitions. [2018-11-28 12:50:47,551 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2955 transitions. [2018-11-28 12:50:47,551 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-28 12:50:47,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2955 transitions. [2018-11-28 12:50:47,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:47,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:47,559 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,559 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,559 INFO L794 eck$LassoCheckResult]: Stem: 24473#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24474#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25322#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25360#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 24169#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24170#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24927#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24706#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24707#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25057#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25058#L934-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25743#L939-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24581#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24286#L949-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24287#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24766#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24767#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25343#L969-1 assume !(0 == ~M_E~0); 25077#L1281-1 assume !(0 == ~T1_E~0); 25078#L1286-1 assume !(0 == ~T2_E~0); 25748#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24590#L1296-1 assume !(0 == ~T4_E~0); 24307#L1301-1 assume !(0 == ~T5_E~0); 24308#L1306-1 assume !(0 == ~T6_E~0); 24785#L1311-1 assume !(0 == ~T7_E~0); 24644#L1316-1 assume !(0 == ~T8_E~0); 24645#L1321-1 assume !(0 == ~T9_E~0); 25163#L1326-1 assume !(0 == ~T10_E~0); 25164#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25565#L1336-1 assume !(0 == ~T12_E~0); 24433#L1341-1 assume !(0 == ~T13_E~0); 24250#L1346-1 assume !(0 == ~E_M~0); 24251#L1351-1 assume !(0 == ~E_1~0); 24730#L1356-1 assume !(0 == ~E_2~0); 24731#L1361-1 assume !(0 == ~E_3~0); 25248#L1366-1 assume !(0 == ~E_4~0); 25144#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 25145#L1376-1 assume !(0 == ~E_6~0); 25667#L1381-1 assume !(0 == ~E_7~0); 24332#L1386-1 assume !(0 == ~E_8~0); 23950#L1391-1 assume !(0 == ~E_9~0); 23951#L1396-1 assume !(0 == ~E_10~0); 24862#L1401-1 assume !(0 == ~E_11~0); 24863#L1406-1 assume !(0 == ~E_12~0); 25183#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 25184#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25751#L630 assume 1 == ~m_pc~0; 25603#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 24280#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24001#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 24002#L1593 assume !(0 != activate_threads_~tmp~1); 25897#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24961#L649 assume !(1 == ~t1_pc~0); 24921#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 24920#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25339#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 25340#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25523#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25529#L668 assume 1 == ~t2_pc~0; 25869#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 24599#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24567#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 24157#L1609 assume !(0 != activate_threads_~tmp___1~0); 24158#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23936#L687 assume !(1 == ~t3_pc~0); 23916#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 23917#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24611#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 24702#L1617 assume !(0 != activate_threads_~tmp___2~0); 24898#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 24901#L706 assume 1 == ~t4_pc~0; 25210#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 25214#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25716#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 25405#L1625 assume !(0 != activate_threads_~tmp___3~0); 25406#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 24408#L725 assume !(1 == ~t5_pc~0); 24383#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 24384#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24903#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 24975#L1633 assume !(0 != activate_threads_~tmp___4~0); 25111#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25119#L744 assume 1 == ~t6_pc~0; 25414#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 25416#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 25840#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 25740#L1641 assume !(0 != activate_threads_~tmp___5~0); 25741#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25623#L763 assume 1 == ~t7_pc~0; 25534#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 24015#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 23930#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 23931#L1649 assume !(0 != activate_threads_~tmp___6~0); 24571#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 24576#L782 assume !(1 == ~t8_pc~0); 24772#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 24771#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 25218#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 24084#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 24085#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 24096#L801 assume 1 == ~t9_pc~0; 25789#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 24577#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 24401#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 24402#L1665 assume !(0 != activate_threads_~tmp___8~0); 24870#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 24111#L820 assume !(1 == ~t10_pc~0); 24112#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 24115#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 24708#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 25357#L1673 assume !(0 != activate_threads_~tmp___9~0); 25358#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 25319#L839 assume 1 == ~t11_pc~0; 25124#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 25125#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 25616#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 25617#L1681 assume !(0 != activate_threads_~tmp___10~0); 25899#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 24521#L858 assume !(1 == ~t12_pc~0); 24458#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 24459#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 24929#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 24930#L1689 assume !(0 != activate_threads_~tmp___11~0); 25512#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 25365#L877 assume 1 == ~t13_pc~0; 25366#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 25372#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 25824#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 24166#L1697 assume !(0 != activate_threads_~tmp___12~0); 24167#L1697-2 assume !(1 == ~M_E~0); 24168#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24236#L1434-1 assume !(1 == ~T2_E~0); 24237#L1439-1 assume !(1 == ~T3_E~0); 24717#L1444-1 assume !(1 == ~T4_E~0); 24718#L1449-1 assume !(1 == ~T5_E~0); 25238#L1454-1 assume !(1 == ~T6_E~0); 25139#L1459-1 assume !(1 == ~T7_E~0); 25140#L1464-1 assume !(1 == ~T8_E~0); 25685#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24362#L1474-1 assume !(1 == ~T10_E~0); 23986#L1479-1 assume !(1 == ~T11_E~0); 23987#L1484-1 assume !(1 == ~T12_E~0); 24868#L1489-1 assume !(1 == ~T13_E~0); 24869#L1494-1 assume !(1 == ~E_M~0); 25205#L1499-1 assume !(1 == ~E_1~0); 25206#L1504-1 assume !(1 == ~E_2~0); 25734#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 25634#L1514-1 assume !(1 == ~E_4~0); 24491#L1519-1 assume !(1 == ~E_5~0); 24135#L1524-1 assume !(1 == ~E_6~0); 24136#L1529-1 assume !(1 == ~E_7~0); 24632#L1534-1 assume !(1 == ~E_8~0); 24633#L1539-1 assume !(1 == ~E_9~0); 25302#L1544-1 assume !(1 == ~E_10~0); 25303#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 25706#L1554-1 assume !(1 == ~E_12~0); 24532#L1559-1 assume !(1 == ~E_13~0); 24305#L1930-1 [2018-11-28 12:50:47,559 INFO L796 eck$LassoCheckResult]: Loop: 24305#L1930-1 assume !false; 24618#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 23964#L1256 assume !false; 24173#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 25757#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24211#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 25327#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 25328#L1069 assume !(0 != eval_~tmp~0); 24709#L1271 start_simulation_~kernel_st~0 := 2; 24710#L897-1 start_simulation_~kernel_st~0 := 3; 25079#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25062#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25063#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25746#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24583#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24311#L1301-3 assume !(0 == ~T5_E~0); 24312#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24795#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24650#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24651#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25168#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25169#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25571#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24437#L1341-3 assume !(0 == ~T13_E~0); 24255#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24256#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24871#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24872#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25225#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25137#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25138#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25676#L1381-3 assume !(0 == ~E_7~0); 24342#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23960#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23961#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24865#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24866#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25192#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25193#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25550#L630-45 assume 1 == ~m_pc~0; 25552#L631-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 24228#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23940#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23941#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25805#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24792#L649-45 assume 1 == ~t1_pc~0; 24793#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 24796#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25233#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 24540#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 24541#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24545#L668-45 assume 1 == ~t2_pc~0; 25799#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 24584#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24416#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 24232#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 24233#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24032#L687-45 assume 1 == ~t3_pc~0; 24033#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 24041#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24652#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 24653#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 24933#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 24936#L706-45 assume 1 == ~t4_pc~0; 25270#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 25271#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25749#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 25479#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 25480#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 24476#L725-45 assume !(1 == ~t5_pc~0); 24477#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 24480#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24886#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 24946#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 25157#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25158#L744-45 assume 1 == ~t6_pc~0; 25498#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 25472#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 25828#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 25759#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 25760#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25670#L763-45 assume !(1 == ~t7_pc~0); 25671#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 23958#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 23959#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 24131#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 24320#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 24324#L782-45 assume 1 == ~t8_pc~0; 24728#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 24732#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 25191#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 24988#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 24989#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 24992#L801-45 assume !(1 == ~t9_pc~0); 25764#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 24430#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 24336#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 24337#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 24619#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 24620#L820-45 assume 1 == ~t10_pc~0; 25005#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 24676#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 24677#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 25231#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 25232#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 25098#L839-45 assume 1 == ~t11_pc~0; 25068#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 25069#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 25556#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 25557#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 25798#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 24182#L858-45 assume !(1 == ~t12_pc~0); 24183#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 24185#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 24811#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 24812#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 25632#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 25436#L877-45 assume !(1 == ~t13_pc~0); 25329#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 25330#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 25863#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 24222#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 24223#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 24229#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24245#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24246#L1439-3 assume !(1 == ~T3_E~0); 24726#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24727#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25245#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25142#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25143#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25688#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24375#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23948#L1479-3 assume !(1 == ~T11_E~0); 23949#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24860#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 24861#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25179#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25180#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25738#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25639#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24499#L1519-3 assume !(1 == ~E_5~0); 24140#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24141#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24636#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24637#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25311#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25312#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25713#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24528#L1559-3 assume !(1 == ~E_13~0); 24174#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 24175#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24214#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 25323#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 25324#L1949 assume !(0 == start_simulation_~tmp~3); 25823#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 25752#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24217#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 25325#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 25326#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 24537#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 24523#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 24304#L1962 assume !(0 != start_simulation_~tmp___0~1); 24305#L1930-1 [2018-11-28 12:50:47,560 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,560 INFO L82 PathProgramCache]: Analyzing trace with hash 942263269, now seen corresponding path program 1 times [2018-11-28 12:50:47,560 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,560 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,595 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,595 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,596 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:47,596 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,596 INFO L82 PathProgramCache]: Analyzing trace with hash 114255523, now seen corresponding path program 1 times [2018-11-28 12:50:47,596 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,596 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,597 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,647 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,647 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,648 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:47,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:47,648 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:47,648 INFO L87 Difference]: Start difference. First operand 1988 states and 2955 transitions. cyclomatic complexity: 968 Second operand 3 states. [2018-11-28 12:50:47,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:47,671 INFO L93 Difference]: Finished difference Result 1988 states and 2954 transitions. [2018-11-28 12:50:47,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:47,672 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2954 transitions. [2018-11-28 12:50:47,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2954 transitions. [2018-11-28 12:50:47,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:47,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:47,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2954 transitions. [2018-11-28 12:50:47,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:47,693 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2954 transitions. [2018-11-28 12:50:47,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2954 transitions. [2018-11-28 12:50:47,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:47,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:47,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2954 transitions. [2018-11-28 12:50:47,719 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2954 transitions. [2018-11-28 12:50:47,719 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2954 transitions. [2018-11-28 12:50:47,719 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-28 12:50:47,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2954 transitions. [2018-11-28 12:50:47,724 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:47,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:47,755 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,756 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,756 INFO L794 eck$LassoCheckResult]: Stem: 28456#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28457#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29305#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29343#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 28152#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28153#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28910#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28689#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28690#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29040#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29041#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29726#L939-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28564#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28269#L949-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28270#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28749#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28750#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29326#L969-1 assume !(0 == ~M_E~0); 29060#L1281-1 assume !(0 == ~T1_E~0); 29061#L1286-1 assume !(0 == ~T2_E~0); 29731#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28573#L1296-1 assume !(0 == ~T4_E~0); 28290#L1301-1 assume !(0 == ~T5_E~0); 28291#L1306-1 assume !(0 == ~T6_E~0); 28768#L1311-1 assume !(0 == ~T7_E~0); 28627#L1316-1 assume !(0 == ~T8_E~0); 28628#L1321-1 assume !(0 == ~T9_E~0); 29146#L1326-1 assume !(0 == ~T10_E~0); 29147#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29548#L1336-1 assume !(0 == ~T12_E~0); 28416#L1341-1 assume !(0 == ~T13_E~0); 28233#L1346-1 assume !(0 == ~E_M~0); 28234#L1351-1 assume !(0 == ~E_1~0); 28713#L1356-1 assume !(0 == ~E_2~0); 28714#L1361-1 assume !(0 == ~E_3~0); 29231#L1366-1 assume !(0 == ~E_4~0); 29127#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 29128#L1376-1 assume !(0 == ~E_6~0); 29650#L1381-1 assume !(0 == ~E_7~0); 28315#L1386-1 assume !(0 == ~E_8~0); 27933#L1391-1 assume !(0 == ~E_9~0); 27934#L1396-1 assume !(0 == ~E_10~0); 28845#L1401-1 assume !(0 == ~E_11~0); 28846#L1406-1 assume !(0 == ~E_12~0); 29166#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 29167#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29734#L630 assume 1 == ~m_pc~0; 29586#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 28263#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27984#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27985#L1593 assume !(0 != activate_threads_~tmp~1); 29880#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28944#L649 assume !(1 == ~t1_pc~0); 28904#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 28903#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29322#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 29323#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 29506#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29512#L668 assume 1 == ~t2_pc~0; 29852#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 28582#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28550#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 28140#L1609 assume !(0 != activate_threads_~tmp___1~0); 28141#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27919#L687 assume !(1 == ~t3_pc~0); 27899#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 27900#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28594#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 28685#L1617 assume !(0 != activate_threads_~tmp___2~0); 28881#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28884#L706 assume 1 == ~t4_pc~0; 29193#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 29197#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29699#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 29388#L1625 assume !(0 != activate_threads_~tmp___3~0); 29389#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28391#L725 assume !(1 == ~t5_pc~0); 28366#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 28367#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28886#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 28958#L1633 assume !(0 != activate_threads_~tmp___4~0); 29094#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 29102#L744 assume 1 == ~t6_pc~0; 29397#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 29399#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 29823#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 29723#L1641 assume !(0 != activate_threads_~tmp___5~0); 29724#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 29606#L763 assume 1 == ~t7_pc~0; 29517#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 27998#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 27913#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 27914#L1649 assume !(0 != activate_threads_~tmp___6~0); 28554#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28559#L782 assume !(1 == ~t8_pc~0); 28755#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 28754#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 29201#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 28067#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 28068#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 28079#L801 assume 1 == ~t9_pc~0; 29772#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 28560#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 28384#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28385#L1665 assume !(0 != activate_threads_~tmp___8~0); 28853#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 28094#L820 assume !(1 == ~t10_pc~0); 28095#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 28098#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 28691#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 29340#L1673 assume !(0 != activate_threads_~tmp___9~0); 29341#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 29302#L839 assume 1 == ~t11_pc~0; 29107#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 29108#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 29599#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 29600#L1681 assume !(0 != activate_threads_~tmp___10~0); 29882#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 28504#L858 assume !(1 == ~t12_pc~0); 28441#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 28442#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 28912#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 28913#L1689 assume !(0 != activate_threads_~tmp___11~0); 29495#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 29348#L877 assume 1 == ~t13_pc~0; 29349#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 29355#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 29807#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 28149#L1697 assume !(0 != activate_threads_~tmp___12~0); 28150#L1697-2 assume !(1 == ~M_E~0); 28151#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28219#L1434-1 assume !(1 == ~T2_E~0); 28220#L1439-1 assume !(1 == ~T3_E~0); 28700#L1444-1 assume !(1 == ~T4_E~0); 28701#L1449-1 assume !(1 == ~T5_E~0); 29221#L1454-1 assume !(1 == ~T6_E~0); 29122#L1459-1 assume !(1 == ~T7_E~0); 29123#L1464-1 assume !(1 == ~T8_E~0); 29668#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28345#L1474-1 assume !(1 == ~T10_E~0); 27969#L1479-1 assume !(1 == ~T11_E~0); 27970#L1484-1 assume !(1 == ~T12_E~0); 28851#L1489-1 assume !(1 == ~T13_E~0); 28852#L1494-1 assume !(1 == ~E_M~0); 29188#L1499-1 assume !(1 == ~E_1~0); 29189#L1504-1 assume !(1 == ~E_2~0); 29717#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 29617#L1514-1 assume !(1 == ~E_4~0); 28474#L1519-1 assume !(1 == ~E_5~0); 28118#L1524-1 assume !(1 == ~E_6~0); 28119#L1529-1 assume !(1 == ~E_7~0); 28615#L1534-1 assume !(1 == ~E_8~0); 28616#L1539-1 assume !(1 == ~E_9~0); 29285#L1544-1 assume !(1 == ~E_10~0); 29286#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 29689#L1554-1 assume !(1 == ~E_12~0); 28515#L1559-1 assume !(1 == ~E_13~0); 28288#L1930-1 [2018-11-28 12:50:47,756 INFO L796 eck$LassoCheckResult]: Loop: 28288#L1930-1 assume !false; 28601#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 27947#L1256 assume !false; 28156#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 29740#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28194#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 29310#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 29311#L1069 assume !(0 != eval_~tmp~0); 28692#L1271 start_simulation_~kernel_st~0 := 2; 28693#L897-1 start_simulation_~kernel_st~0 := 3; 29062#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 29045#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29046#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29729#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28566#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28294#L1301-3 assume !(0 == ~T5_E~0); 28295#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28778#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28633#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28634#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29151#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29152#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29554#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28420#L1341-3 assume !(0 == ~T13_E~0); 28238#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28239#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28854#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28855#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29208#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29120#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29121#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29659#L1381-3 assume !(0 == ~E_7~0); 28325#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27943#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27944#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28848#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28849#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29175#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29176#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29533#L630-45 assume !(1 == ~m_pc~0); 29534#L630-47 is_master_triggered_~__retres1~0 := 0; 28211#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27923#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27924#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 29788#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28775#L649-45 assume 1 == ~t1_pc~0; 28776#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 28779#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29216#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 28523#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 28524#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28528#L668-45 assume 1 == ~t2_pc~0; 29782#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 28567#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28399#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 28215#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28216#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28015#L687-45 assume 1 == ~t3_pc~0; 28016#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 28024#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28635#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 28636#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28916#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28919#L706-45 assume 1 == ~t4_pc~0; 29253#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 29254#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29732#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 29462#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 29463#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28459#L725-45 assume !(1 == ~t5_pc~0); 28460#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 28463#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28869#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 28929#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 29140#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 29141#L744-45 assume 1 == ~t6_pc~0; 29481#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 29455#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 29811#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 29742#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 29743#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 29653#L763-45 assume !(1 == ~t7_pc~0); 29654#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 27941#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 27942#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 28114#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 28303#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28307#L782-45 assume 1 == ~t8_pc~0; 28711#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 28715#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 29174#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 28971#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 28972#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 28975#L801-45 assume !(1 == ~t9_pc~0); 29747#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 28413#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 28319#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28320#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 28602#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 28603#L820-45 assume 1 == ~t10_pc~0; 28988#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 28659#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 28660#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 29214#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 29215#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 29081#L839-45 assume 1 == ~t11_pc~0; 29051#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 29052#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 29539#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 29540#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 29781#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 28165#L858-45 assume !(1 == ~t12_pc~0); 28166#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 28168#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 28794#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 28795#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 29615#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 29419#L877-45 assume !(1 == ~t13_pc~0); 29312#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 29313#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 29846#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 28205#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 28206#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 28212#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28228#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28229#L1439-3 assume !(1 == ~T3_E~0); 28709#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28710#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29228#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29125#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29126#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29671#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28358#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27931#L1479-3 assume !(1 == ~T11_E~0); 27932#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28843#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 28844#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29162#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29163#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29721#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29622#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28482#L1519-3 assume !(1 == ~E_5~0); 28123#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28124#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28619#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28620#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29294#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29295#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29696#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28511#L1559-3 assume !(1 == ~E_13~0); 28157#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 28158#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28197#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 29306#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 29307#L1949 assume !(0 == start_simulation_~tmp~3); 29806#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 29735#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28200#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 29308#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 29309#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 28520#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 28506#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 28287#L1962 assume !(0 != start_simulation_~tmp___0~1); 28288#L1930-1 [2018-11-28 12:50:47,756 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,757 INFO L82 PathProgramCache]: Analyzing trace with hash -988862365, now seen corresponding path program 1 times [2018-11-28 12:50:47,757 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,757 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,758 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,795 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,795 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,795 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:47,795 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,796 INFO L82 PathProgramCache]: Analyzing trace with hash 1719421634, now seen corresponding path program 1 times [2018-11-28 12:50:47,796 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,796 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,846 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:47,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:47,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:47,847 INFO L87 Difference]: Start difference. First operand 1988 states and 2954 transitions. cyclomatic complexity: 967 Second operand 3 states. [2018-11-28 12:50:47,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:47,871 INFO L93 Difference]: Finished difference Result 1988 states and 2953 transitions. [2018-11-28 12:50:47,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:47,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2953 transitions. [2018-11-28 12:50:47,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2953 transitions. [2018-11-28 12:50:47,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:47,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:47,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2953 transitions. [2018-11-28 12:50:47,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:47,891 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2953 transitions. [2018-11-28 12:50:47,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2953 transitions. [2018-11-28 12:50:47,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:47,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:47,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2953 transitions. [2018-11-28 12:50:47,919 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2953 transitions. [2018-11-28 12:50:47,919 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2953 transitions. [2018-11-28 12:50:47,919 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-28 12:50:47,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2953 transitions. [2018-11-28 12:50:47,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:47,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:47,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:47,926 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,927 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:47,927 INFO L794 eck$LassoCheckResult]: Stem: 32439#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32440#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33288#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33326#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 32135#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32136#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32893#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32672#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32673#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33023#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33024#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33709#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32547#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32252#L949-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32253#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32732#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32733#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33309#L969-1 assume !(0 == ~M_E~0); 33043#L1281-1 assume !(0 == ~T1_E~0); 33044#L1286-1 assume !(0 == ~T2_E~0); 33714#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32556#L1296-1 assume !(0 == ~T4_E~0); 32273#L1301-1 assume !(0 == ~T5_E~0); 32274#L1306-1 assume !(0 == ~T6_E~0); 32751#L1311-1 assume !(0 == ~T7_E~0); 32610#L1316-1 assume !(0 == ~T8_E~0); 32611#L1321-1 assume !(0 == ~T9_E~0); 33129#L1326-1 assume !(0 == ~T10_E~0); 33130#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33531#L1336-1 assume !(0 == ~T12_E~0); 32399#L1341-1 assume !(0 == ~T13_E~0); 32216#L1346-1 assume !(0 == ~E_M~0); 32217#L1351-1 assume !(0 == ~E_1~0); 32696#L1356-1 assume !(0 == ~E_2~0); 32697#L1361-1 assume !(0 == ~E_3~0); 33214#L1366-1 assume !(0 == ~E_4~0); 33110#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 33111#L1376-1 assume !(0 == ~E_6~0); 33633#L1381-1 assume !(0 == ~E_7~0); 32298#L1386-1 assume !(0 == ~E_8~0); 31916#L1391-1 assume !(0 == ~E_9~0); 31917#L1396-1 assume !(0 == ~E_10~0); 32828#L1401-1 assume !(0 == ~E_11~0); 32829#L1406-1 assume !(0 == ~E_12~0); 33149#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 33150#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33717#L630 assume 1 == ~m_pc~0; 33569#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 32246#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31967#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 31968#L1593 assume !(0 != activate_threads_~tmp~1); 33863#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32927#L649 assume !(1 == ~t1_pc~0); 32887#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 32886#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33305#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 33306#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 33489#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33495#L668 assume 1 == ~t2_pc~0; 33835#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 32565#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32533#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32123#L1609 assume !(0 != activate_threads_~tmp___1~0); 32124#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31902#L687 assume !(1 == ~t3_pc~0); 31882#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 31883#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32577#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32668#L1617 assume !(0 != activate_threads_~tmp___2~0); 32864#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32867#L706 assume 1 == ~t4_pc~0; 33176#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 33180#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33682#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 33371#L1625 assume !(0 != activate_threads_~tmp___3~0); 33372#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32374#L725 assume !(1 == ~t5_pc~0); 32349#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 32350#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32869#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32941#L1633 assume !(0 != activate_threads_~tmp___4~0); 33077#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 33085#L744 assume 1 == ~t6_pc~0; 33380#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 33382#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 33806#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 33706#L1641 assume !(0 != activate_threads_~tmp___5~0); 33707#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 33589#L763 assume 1 == ~t7_pc~0; 33500#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 31981#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 31896#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 31897#L1649 assume !(0 != activate_threads_~tmp___6~0); 32537#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32542#L782 assume !(1 == ~t8_pc~0); 32738#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 32737#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 33184#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32050#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 32051#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 32062#L801 assume 1 == ~t9_pc~0; 33755#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 32543#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32367#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32368#L1665 assume !(0 != activate_threads_~tmp___8~0); 32836#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 32077#L820 assume !(1 == ~t10_pc~0); 32078#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 32081#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 32674#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 33323#L1673 assume !(0 != activate_threads_~tmp___9~0); 33324#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 33285#L839 assume 1 == ~t11_pc~0; 33090#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 33091#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 33582#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 33583#L1681 assume !(0 != activate_threads_~tmp___10~0); 33865#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 32487#L858 assume !(1 == ~t12_pc~0); 32424#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 32425#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 32895#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 32896#L1689 assume !(0 != activate_threads_~tmp___11~0); 33478#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 33331#L877 assume 1 == ~t13_pc~0; 33332#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 33338#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 33790#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 32132#L1697 assume !(0 != activate_threads_~tmp___12~0); 32133#L1697-2 assume !(1 == ~M_E~0); 32134#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32202#L1434-1 assume !(1 == ~T2_E~0); 32203#L1439-1 assume !(1 == ~T3_E~0); 32683#L1444-1 assume !(1 == ~T4_E~0); 32684#L1449-1 assume !(1 == ~T5_E~0); 33204#L1454-1 assume !(1 == ~T6_E~0); 33105#L1459-1 assume !(1 == ~T7_E~0); 33106#L1464-1 assume !(1 == ~T8_E~0); 33651#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32328#L1474-1 assume !(1 == ~T10_E~0); 31952#L1479-1 assume !(1 == ~T11_E~0); 31953#L1484-1 assume !(1 == ~T12_E~0); 32834#L1489-1 assume !(1 == ~T13_E~0); 32835#L1494-1 assume !(1 == ~E_M~0); 33171#L1499-1 assume !(1 == ~E_1~0); 33172#L1504-1 assume !(1 == ~E_2~0); 33700#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 33600#L1514-1 assume !(1 == ~E_4~0); 32457#L1519-1 assume !(1 == ~E_5~0); 32101#L1524-1 assume !(1 == ~E_6~0); 32102#L1529-1 assume !(1 == ~E_7~0); 32598#L1534-1 assume !(1 == ~E_8~0); 32599#L1539-1 assume !(1 == ~E_9~0); 33268#L1544-1 assume !(1 == ~E_10~0); 33269#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 33672#L1554-1 assume !(1 == ~E_12~0); 32498#L1559-1 assume !(1 == ~E_13~0); 32271#L1930-1 [2018-11-28 12:50:47,927 INFO L796 eck$LassoCheckResult]: Loop: 32271#L1930-1 assume !false; 32584#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 31930#L1256 assume !false; 32139#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 33723#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32177#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 33293#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 33294#L1069 assume !(0 != eval_~tmp~0); 32675#L1271 start_simulation_~kernel_st~0 := 2; 32676#L897-1 start_simulation_~kernel_st~0 := 3; 33045#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 33028#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33029#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33712#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32549#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32277#L1301-3 assume !(0 == ~T5_E~0); 32278#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32761#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32616#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32617#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33134#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33135#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33537#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32403#L1341-3 assume !(0 == ~T13_E~0); 32221#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32222#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32837#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32838#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33191#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33103#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33104#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33642#L1381-3 assume !(0 == ~E_7~0); 32308#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31926#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31927#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32831#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32832#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33158#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33159#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33516#L630-45 assume !(1 == ~m_pc~0); 33517#L630-47 is_master_triggered_~__retres1~0 := 0; 32194#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31906#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 31907#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 33771#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32758#L649-45 assume 1 == ~t1_pc~0; 32759#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 32762#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33199#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 32506#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32507#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32511#L668-45 assume 1 == ~t2_pc~0; 33765#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 32550#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32382#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32198#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32199#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31998#L687-45 assume !(1 == ~t3_pc~0); 32000#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 32007#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32618#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32619#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32899#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32902#L706-45 assume 1 == ~t4_pc~0; 33236#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 33237#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33715#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 33445#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 33446#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32442#L725-45 assume !(1 == ~t5_pc~0); 32443#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 32446#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32852#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32912#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 33123#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 33124#L744-45 assume 1 == ~t6_pc~0; 33464#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 33438#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 33794#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 33725#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 33726#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 33636#L763-45 assume !(1 == ~t7_pc~0); 33637#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 31924#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 31925#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 32097#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32286#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32290#L782-45 assume 1 == ~t8_pc~0; 32694#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32698#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 33157#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32954#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 32955#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 32958#L801-45 assume !(1 == ~t9_pc~0); 33730#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 32396#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32302#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32303#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 32585#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 32586#L820-45 assume 1 == ~t10_pc~0; 32971#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 32642#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 32643#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 33197#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 33198#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 33064#L839-45 assume 1 == ~t11_pc~0; 33034#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 33035#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 33522#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 33523#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 33764#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 32148#L858-45 assume !(1 == ~t12_pc~0); 32149#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 32151#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 32777#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 32778#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 33598#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 33402#L877-45 assume 1 == ~t13_pc~0; 33403#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 33296#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 33829#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 32188#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 32189#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 32195#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32211#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32212#L1439-3 assume !(1 == ~T3_E~0); 32692#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32693#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33211#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33108#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33109#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33654#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32341#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31914#L1479-3 assume !(1 == ~T11_E~0); 31915#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32826#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 32827#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33145#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33146#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33704#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33605#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32465#L1519-3 assume !(1 == ~E_5~0); 32106#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32107#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32602#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32603#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33277#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33278#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33679#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32494#L1559-3 assume !(1 == ~E_13~0); 32140#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 32141#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32180#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 33289#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 33290#L1949 assume !(0 == start_simulation_~tmp~3); 33789#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 33718#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32183#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 33291#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 33292#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 32503#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 32489#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 32270#L1962 assume !(0 != start_simulation_~tmp___0~1); 32271#L1930-1 [2018-11-28 12:50:47,928 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,928 INFO L82 PathProgramCache]: Analyzing trace with hash 334316581, now seen corresponding path program 1 times [2018-11-28 12:50:47,928 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,928 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,929 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:47,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:47,977 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:47,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:47,978 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:47,978 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:47,978 INFO L82 PathProgramCache]: Analyzing trace with hash -946218430, now seen corresponding path program 1 times [2018-11-28 12:50:47,978 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:47,978 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:47,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,979 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:47,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:47,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,038 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,038 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:48,039 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:48,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:48,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:48,042 INFO L87 Difference]: Start difference. First operand 1988 states and 2953 transitions. cyclomatic complexity: 966 Second operand 3 states. [2018-11-28 12:50:48,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:48,062 INFO L93 Difference]: Finished difference Result 1988 states and 2952 transitions. [2018-11-28 12:50:48,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:48,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2952 transitions. [2018-11-28 12:50:48,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2952 transitions. [2018-11-28 12:50:48,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:48,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:48,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2952 transitions. [2018-11-28 12:50:48,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:48,080 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2952 transitions. [2018-11-28 12:50:48,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2952 transitions. [2018-11-28 12:50:48,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:48,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:48,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2952 transitions. [2018-11-28 12:50:48,106 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2952 transitions. [2018-11-28 12:50:48,106 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2952 transitions. [2018-11-28 12:50:48,106 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-28 12:50:48,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2952 transitions. [2018-11-28 12:50:48,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:48,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:48,114 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,114 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,114 INFO L794 eck$LassoCheckResult]: Stem: 36422#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 36423#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37271#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 37309#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 36118#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36119#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36876#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36655#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36656#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37006#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37007#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37692#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36530#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36235#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36236#L954-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36715#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36716#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37292#L969-1 assume !(0 == ~M_E~0); 37026#L1281-1 assume !(0 == ~T1_E~0); 37027#L1286-1 assume !(0 == ~T2_E~0); 37697#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36539#L1296-1 assume !(0 == ~T4_E~0); 36256#L1301-1 assume !(0 == ~T5_E~0); 36257#L1306-1 assume !(0 == ~T6_E~0); 36734#L1311-1 assume !(0 == ~T7_E~0); 36593#L1316-1 assume !(0 == ~T8_E~0); 36594#L1321-1 assume !(0 == ~T9_E~0); 37112#L1326-1 assume !(0 == ~T10_E~0); 37113#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37514#L1336-1 assume !(0 == ~T12_E~0); 36382#L1341-1 assume !(0 == ~T13_E~0); 36199#L1346-1 assume !(0 == ~E_M~0); 36200#L1351-1 assume !(0 == ~E_1~0); 36679#L1356-1 assume !(0 == ~E_2~0); 36680#L1361-1 assume !(0 == ~E_3~0); 37197#L1366-1 assume !(0 == ~E_4~0); 37093#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37094#L1376-1 assume !(0 == ~E_6~0); 37616#L1381-1 assume !(0 == ~E_7~0); 36281#L1386-1 assume !(0 == ~E_8~0); 35899#L1391-1 assume !(0 == ~E_9~0); 35900#L1396-1 assume !(0 == ~E_10~0); 36811#L1401-1 assume !(0 == ~E_11~0); 36812#L1406-1 assume !(0 == ~E_12~0); 37132#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 37133#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37700#L630 assume 1 == ~m_pc~0; 37552#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 36229#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35950#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 35951#L1593 assume !(0 != activate_threads_~tmp~1); 37846#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36910#L649 assume !(1 == ~t1_pc~0); 36870#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 36869#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37288#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 37289#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 37472#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37478#L668 assume 1 == ~t2_pc~0; 37818#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 36548#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36516#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36106#L1609 assume !(0 != activate_threads_~tmp___1~0); 36107#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35885#L687 assume !(1 == ~t3_pc~0); 35865#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 35866#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36560#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36651#L1617 assume !(0 != activate_threads_~tmp___2~0); 36847#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36850#L706 assume 1 == ~t4_pc~0; 37159#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 37163#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37665#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 37354#L1625 assume !(0 != activate_threads_~tmp___3~0); 37355#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36357#L725 assume !(1 == ~t5_pc~0); 36332#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 36333#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36852#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 36924#L1633 assume !(0 != activate_threads_~tmp___4~0); 37060#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 37068#L744 assume 1 == ~t6_pc~0; 37363#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 37365#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 37789#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 37689#L1641 assume !(0 != activate_threads_~tmp___5~0); 37690#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 37572#L763 assume 1 == ~t7_pc~0; 37483#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 35964#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 35879#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 35880#L1649 assume !(0 != activate_threads_~tmp___6~0); 36520#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 36525#L782 assume !(1 == ~t8_pc~0); 36721#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 36720#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 37167#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 36033#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 36034#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 36045#L801 assume 1 == ~t9_pc~0; 37738#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 36526#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 36350#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 36351#L1665 assume !(0 != activate_threads_~tmp___8~0); 36819#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 36060#L820 assume !(1 == ~t10_pc~0); 36061#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 36064#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 36657#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 37306#L1673 assume !(0 != activate_threads_~tmp___9~0); 37307#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 37268#L839 assume 1 == ~t11_pc~0; 37073#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 37074#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 37565#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 37566#L1681 assume !(0 != activate_threads_~tmp___10~0); 37848#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 36470#L858 assume !(1 == ~t12_pc~0); 36407#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 36408#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 36878#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 36879#L1689 assume !(0 != activate_threads_~tmp___11~0); 37461#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 37314#L877 assume 1 == ~t13_pc~0; 37315#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 37321#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 37773#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 36115#L1697 assume !(0 != activate_threads_~tmp___12~0); 36116#L1697-2 assume !(1 == ~M_E~0); 36117#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36185#L1434-1 assume !(1 == ~T2_E~0); 36186#L1439-1 assume !(1 == ~T3_E~0); 36666#L1444-1 assume !(1 == ~T4_E~0); 36667#L1449-1 assume !(1 == ~T5_E~0); 37187#L1454-1 assume !(1 == ~T6_E~0); 37088#L1459-1 assume !(1 == ~T7_E~0); 37089#L1464-1 assume !(1 == ~T8_E~0); 37634#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36311#L1474-1 assume !(1 == ~T10_E~0); 35935#L1479-1 assume !(1 == ~T11_E~0); 35936#L1484-1 assume !(1 == ~T12_E~0); 36817#L1489-1 assume !(1 == ~T13_E~0); 36818#L1494-1 assume !(1 == ~E_M~0); 37154#L1499-1 assume !(1 == ~E_1~0); 37155#L1504-1 assume !(1 == ~E_2~0); 37683#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 37583#L1514-1 assume !(1 == ~E_4~0); 36440#L1519-1 assume !(1 == ~E_5~0); 36084#L1524-1 assume !(1 == ~E_6~0); 36085#L1529-1 assume !(1 == ~E_7~0); 36581#L1534-1 assume !(1 == ~E_8~0); 36582#L1539-1 assume !(1 == ~E_9~0); 37251#L1544-1 assume !(1 == ~E_10~0); 37252#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 37655#L1554-1 assume !(1 == ~E_12~0); 36481#L1559-1 assume !(1 == ~E_13~0); 36254#L1930-1 [2018-11-28 12:50:48,114 INFO L796 eck$LassoCheckResult]: Loop: 36254#L1930-1 assume !false; 36567#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 35913#L1256 assume !false; 36122#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 37706#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36160#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 37276#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 37277#L1069 assume !(0 != eval_~tmp~0); 36658#L1271 start_simulation_~kernel_st~0 := 2; 36659#L897-1 start_simulation_~kernel_st~0 := 3; 37028#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 37011#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37012#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37695#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36532#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36260#L1301-3 assume !(0 == ~T5_E~0); 36261#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36744#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36599#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36600#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37117#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37118#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37520#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36386#L1341-3 assume !(0 == ~T13_E~0); 36204#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36205#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36820#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36821#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37174#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37086#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37087#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37625#L1381-3 assume !(0 == ~E_7~0); 36291#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35909#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35910#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36814#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36815#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 37141#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37142#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37499#L630-45 assume !(1 == ~m_pc~0); 37500#L630-47 is_master_triggered_~__retres1~0 := 0; 36177#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35889#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 35890#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 37754#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36741#L649-45 assume 1 == ~t1_pc~0; 36742#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 36745#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37182#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36489#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 36490#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36494#L668-45 assume 1 == ~t2_pc~0; 37748#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 36533#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36365#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36181#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 36182#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35981#L687-45 assume 1 == ~t3_pc~0; 35982#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 35990#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36601#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36602#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36882#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36885#L706-45 assume 1 == ~t4_pc~0; 37219#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 37220#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37698#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 37428#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 37429#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36425#L725-45 assume !(1 == ~t5_pc~0); 36426#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 36429#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36835#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 36895#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 37106#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 37107#L744-45 assume 1 == ~t6_pc~0; 37447#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 37421#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 37777#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 37708#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 37709#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 37619#L763-45 assume !(1 == ~t7_pc~0); 37620#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 35907#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 35908#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 36080#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 36269#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 36273#L782-45 assume 1 == ~t8_pc~0; 36677#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 36681#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 37140#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 36937#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 36938#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 36941#L801-45 assume !(1 == ~t9_pc~0); 37713#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 36379#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 36285#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 36286#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 36568#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 36569#L820-45 assume 1 == ~t10_pc~0; 36954#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 36625#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 36626#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 37180#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 37181#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 37047#L839-45 assume 1 == ~t11_pc~0; 37017#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 37018#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 37505#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 37506#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 37747#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 36131#L858-45 assume !(1 == ~t12_pc~0); 36132#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 36134#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 36760#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 36761#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 37581#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 37385#L877-45 assume 1 == ~t13_pc~0; 37386#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 37279#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 37812#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 36171#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 36172#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 36178#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36194#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36195#L1439-3 assume !(1 == ~T3_E~0); 36675#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36676#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37194#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37091#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37092#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37637#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36324#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35897#L1479-3 assume !(1 == ~T11_E~0); 35898#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36809#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 36810#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37128#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37129#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37687#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37588#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36448#L1519-3 assume !(1 == ~E_5~0); 36089#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36090#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36585#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36586#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37260#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37261#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37662#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 36477#L1559-3 assume !(1 == ~E_13~0); 36123#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 36124#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36163#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 37272#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 37273#L1949 assume !(0 == start_simulation_~tmp~3); 37772#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 37701#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36166#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 37274#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 37275#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 36486#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 36472#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 36253#L1962 assume !(0 != start_simulation_~tmp___0~1); 36254#L1930-1 [2018-11-28 12:50:48,115 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,115 INFO L82 PathProgramCache]: Analyzing trace with hash -3970969, now seen corresponding path program 1 times [2018-11-28 12:50:48,115 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,115 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,116 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:48,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,158 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:48,160 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:48,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,160 INFO L82 PathProgramCache]: Analyzing trace with hash -1267540893, now seen corresponding path program 1 times [2018-11-28 12:50:48,160 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,160 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,161 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:48,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,220 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,220 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:48,220 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:48,221 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:48,221 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:48,221 INFO L87 Difference]: Start difference. First operand 1988 states and 2952 transitions. cyclomatic complexity: 965 Second operand 3 states. [2018-11-28 12:50:48,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:48,243 INFO L93 Difference]: Finished difference Result 1988 states and 2951 transitions. [2018-11-28 12:50:48,245 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:48,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2951 transitions. [2018-11-28 12:50:48,251 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2951 transitions. [2018-11-28 12:50:48,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:48,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:48,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2951 transitions. [2018-11-28 12:50:48,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:48,263 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2951 transitions. [2018-11-28 12:50:48,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2951 transitions. [2018-11-28 12:50:48,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:48,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:48,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2951 transitions. [2018-11-28 12:50:48,288 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2951 transitions. [2018-11-28 12:50:48,288 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2951 transitions. [2018-11-28 12:50:48,288 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-28 12:50:48,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2951 transitions. [2018-11-28 12:50:48,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:48,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:48,295 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,295 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,295 INFO L794 eck$LassoCheckResult]: Stem: 40405#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 40406#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 41254#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41292#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 40101#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40102#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40859#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40638#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40639#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40989#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40990#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41675#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40513#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40218#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40219#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40698#L959-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40699#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41275#L969-1 assume !(0 == ~M_E~0); 41009#L1281-1 assume !(0 == ~T1_E~0); 41010#L1286-1 assume !(0 == ~T2_E~0); 41680#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40522#L1296-1 assume !(0 == ~T4_E~0); 40239#L1301-1 assume !(0 == ~T5_E~0); 40240#L1306-1 assume !(0 == ~T6_E~0); 40717#L1311-1 assume !(0 == ~T7_E~0); 40576#L1316-1 assume !(0 == ~T8_E~0); 40577#L1321-1 assume !(0 == ~T9_E~0); 41095#L1326-1 assume !(0 == ~T10_E~0); 41096#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41497#L1336-1 assume !(0 == ~T12_E~0); 40365#L1341-1 assume !(0 == ~T13_E~0); 40182#L1346-1 assume !(0 == ~E_M~0); 40183#L1351-1 assume !(0 == ~E_1~0); 40662#L1356-1 assume !(0 == ~E_2~0); 40663#L1361-1 assume !(0 == ~E_3~0); 41180#L1366-1 assume !(0 == ~E_4~0); 41076#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 41077#L1376-1 assume !(0 == ~E_6~0); 41599#L1381-1 assume !(0 == ~E_7~0); 40264#L1386-1 assume !(0 == ~E_8~0); 39882#L1391-1 assume !(0 == ~E_9~0); 39883#L1396-1 assume !(0 == ~E_10~0); 40794#L1401-1 assume !(0 == ~E_11~0); 40795#L1406-1 assume !(0 == ~E_12~0); 41115#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 41116#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41683#L630 assume 1 == ~m_pc~0; 41535#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 40212#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39933#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 39934#L1593 assume !(0 != activate_threads_~tmp~1); 41829#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40893#L649 assume !(1 == ~t1_pc~0); 40853#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 40852#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41271#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 41272#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 41455#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41461#L668 assume 1 == ~t2_pc~0; 41801#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 40531#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40499#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 40089#L1609 assume !(0 != activate_threads_~tmp___1~0); 40090#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39868#L687 assume !(1 == ~t3_pc~0); 39848#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 39849#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40543#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 40634#L1617 assume !(0 != activate_threads_~tmp___2~0); 40830#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40833#L706 assume 1 == ~t4_pc~0; 41142#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 41146#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41648#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 41337#L1625 assume !(0 != activate_threads_~tmp___3~0); 41338#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40340#L725 assume !(1 == ~t5_pc~0); 40315#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 40316#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40835#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 40907#L1633 assume !(0 != activate_threads_~tmp___4~0); 41043#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 41051#L744 assume 1 == ~t6_pc~0; 41346#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 41348#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 41772#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 41672#L1641 assume !(0 != activate_threads_~tmp___5~0); 41673#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 41555#L763 assume 1 == ~t7_pc~0; 41466#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 39947#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 39862#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 39863#L1649 assume !(0 != activate_threads_~tmp___6~0); 40503#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 40508#L782 assume !(1 == ~t8_pc~0); 40704#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 40703#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 41150#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 40016#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 40017#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 40028#L801 assume 1 == ~t9_pc~0; 41721#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 40509#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 40333#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 40334#L1665 assume !(0 != activate_threads_~tmp___8~0); 40802#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 40043#L820 assume !(1 == ~t10_pc~0); 40044#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 40047#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 40640#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 41289#L1673 assume !(0 != activate_threads_~tmp___9~0); 41290#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 41251#L839 assume 1 == ~t11_pc~0; 41056#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 41057#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 41548#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 41549#L1681 assume !(0 != activate_threads_~tmp___10~0); 41831#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 40453#L858 assume !(1 == ~t12_pc~0); 40390#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 40391#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 40861#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 40862#L1689 assume !(0 != activate_threads_~tmp___11~0); 41444#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 41297#L877 assume 1 == ~t13_pc~0; 41298#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 41304#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 41756#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 40098#L1697 assume !(0 != activate_threads_~tmp___12~0); 40099#L1697-2 assume !(1 == ~M_E~0); 40100#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40168#L1434-1 assume !(1 == ~T2_E~0); 40169#L1439-1 assume !(1 == ~T3_E~0); 40649#L1444-1 assume !(1 == ~T4_E~0); 40650#L1449-1 assume !(1 == ~T5_E~0); 41170#L1454-1 assume !(1 == ~T6_E~0); 41071#L1459-1 assume !(1 == ~T7_E~0); 41072#L1464-1 assume !(1 == ~T8_E~0); 41617#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40294#L1474-1 assume !(1 == ~T10_E~0); 39918#L1479-1 assume !(1 == ~T11_E~0); 39919#L1484-1 assume !(1 == ~T12_E~0); 40800#L1489-1 assume !(1 == ~T13_E~0); 40801#L1494-1 assume !(1 == ~E_M~0); 41137#L1499-1 assume !(1 == ~E_1~0); 41138#L1504-1 assume !(1 == ~E_2~0); 41666#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 41566#L1514-1 assume !(1 == ~E_4~0); 40423#L1519-1 assume !(1 == ~E_5~0); 40067#L1524-1 assume !(1 == ~E_6~0); 40068#L1529-1 assume !(1 == ~E_7~0); 40564#L1534-1 assume !(1 == ~E_8~0); 40565#L1539-1 assume !(1 == ~E_9~0); 41234#L1544-1 assume !(1 == ~E_10~0); 41235#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 41638#L1554-1 assume !(1 == ~E_12~0); 40464#L1559-1 assume !(1 == ~E_13~0); 40237#L1930-1 [2018-11-28 12:50:48,296 INFO L796 eck$LassoCheckResult]: Loop: 40237#L1930-1 assume !false; 40550#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 39896#L1256 assume !false; 40105#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 41689#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40143#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 41259#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 41260#L1069 assume !(0 != eval_~tmp~0); 40641#L1271 start_simulation_~kernel_st~0 := 2; 40642#L897-1 start_simulation_~kernel_st~0 := 3; 41011#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 40994#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40995#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41678#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40515#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40243#L1301-3 assume !(0 == ~T5_E~0); 40244#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40727#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40582#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40583#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41100#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41101#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41503#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40369#L1341-3 assume !(0 == ~T13_E~0); 40187#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40188#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40803#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40804#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41157#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41069#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41070#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41608#L1381-3 assume !(0 == ~E_7~0); 40274#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39892#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39893#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40797#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40798#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 41124#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41125#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41482#L630-45 assume !(1 == ~m_pc~0); 41483#L630-47 is_master_triggered_~__retres1~0 := 0; 40160#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39872#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 39873#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 41737#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40724#L649-45 assume 1 == ~t1_pc~0; 40725#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 40728#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41165#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 40472#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40473#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40477#L668-45 assume 1 == ~t2_pc~0; 41731#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 40516#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40348#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 40164#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 40165#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39964#L687-45 assume 1 == ~t3_pc~0; 39965#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 39973#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40584#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 40585#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 40865#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40868#L706-45 assume 1 == ~t4_pc~0; 41202#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 41203#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41681#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 41411#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 41412#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40408#L725-45 assume !(1 == ~t5_pc~0); 40409#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 40412#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40818#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 40878#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 41089#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 41090#L744-45 assume 1 == ~t6_pc~0; 41430#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 41404#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 41760#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 41691#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 41692#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 41602#L763-45 assume !(1 == ~t7_pc~0); 41603#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 39890#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 39891#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 40063#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 40252#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 40256#L782-45 assume 1 == ~t8_pc~0; 40660#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 40664#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 41123#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 40920#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 40921#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 40924#L801-45 assume !(1 == ~t9_pc~0); 41696#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 40362#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 40268#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 40269#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 40551#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 40552#L820-45 assume 1 == ~t10_pc~0; 40937#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 40608#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 40609#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 41163#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 41164#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 41030#L839-45 assume 1 == ~t11_pc~0; 41000#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 41001#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 41488#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 41489#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 41730#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 40114#L858-45 assume !(1 == ~t12_pc~0); 40115#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 40117#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 40743#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 40744#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 41564#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 41368#L877-45 assume 1 == ~t13_pc~0; 41369#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 41262#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 41795#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 40154#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 40155#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 40161#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40177#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40178#L1439-3 assume !(1 == ~T3_E~0); 40658#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40659#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41177#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41074#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41075#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41620#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40307#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39880#L1479-3 assume !(1 == ~T11_E~0); 39881#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40792#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 40793#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41111#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41112#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41670#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41571#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40431#L1519-3 assume !(1 == ~E_5~0); 40072#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40073#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40568#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40569#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41243#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41244#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41645#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40460#L1559-3 assume !(1 == ~E_13~0); 40106#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 40107#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40146#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 41255#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 41256#L1949 assume !(0 == start_simulation_~tmp~3); 41755#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 41684#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40149#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 41257#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 41258#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 40469#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 40455#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 40236#L1962 assume !(0 != start_simulation_~tmp___0~1); 40237#L1930-1 [2018-11-28 12:50:48,296 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,296 INFO L82 PathProgramCache]: Analyzing trace with hash -430525467, now seen corresponding path program 1 times [2018-11-28 12:50:48,296 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,296 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,297 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,297 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:48,297 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,337 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,338 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:48,338 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:48,338 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,338 INFO L82 PathProgramCache]: Analyzing trace with hash -1267540893, now seen corresponding path program 2 times [2018-11-28 12:50:48,338 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,338 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,339 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:48,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,390 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:48,391 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:48,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:48,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:48,391 INFO L87 Difference]: Start difference. First operand 1988 states and 2951 transitions. cyclomatic complexity: 964 Second operand 3 states. [2018-11-28 12:50:48,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:48,422 INFO L93 Difference]: Finished difference Result 1988 states and 2950 transitions. [2018-11-28 12:50:48,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:48,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2950 transitions. [2018-11-28 12:50:48,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2950 transitions. [2018-11-28 12:50:48,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:48,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:48,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2950 transitions. [2018-11-28 12:50:48,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:48,444 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2950 transitions. [2018-11-28 12:50:48,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2950 transitions. [2018-11-28 12:50:48,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:48,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:48,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2950 transitions. [2018-11-28 12:50:48,473 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2950 transitions. [2018-11-28 12:50:48,473 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2950 transitions. [2018-11-28 12:50:48,473 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-28 12:50:48,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2950 transitions. [2018-11-28 12:50:48,479 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:48,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:48,482 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,482 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,482 INFO L794 eck$LassoCheckResult]: Stem: 44388#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 44389#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45237#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 45275#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 44084#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44085#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44842#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44621#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44622#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44972#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44973#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45658#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44496#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44201#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44202#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44681#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44682#L964-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45258#L969-1 assume !(0 == ~M_E~0); 44992#L1281-1 assume !(0 == ~T1_E~0); 44993#L1286-1 assume !(0 == ~T2_E~0); 45663#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44505#L1296-1 assume !(0 == ~T4_E~0); 44222#L1301-1 assume !(0 == ~T5_E~0); 44223#L1306-1 assume !(0 == ~T6_E~0); 44700#L1311-1 assume !(0 == ~T7_E~0); 44559#L1316-1 assume !(0 == ~T8_E~0); 44560#L1321-1 assume !(0 == ~T9_E~0); 45078#L1326-1 assume !(0 == ~T10_E~0); 45079#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45480#L1336-1 assume !(0 == ~T12_E~0); 44348#L1341-1 assume !(0 == ~T13_E~0); 44165#L1346-1 assume !(0 == ~E_M~0); 44166#L1351-1 assume !(0 == ~E_1~0); 44645#L1356-1 assume !(0 == ~E_2~0); 44646#L1361-1 assume !(0 == ~E_3~0); 45163#L1366-1 assume !(0 == ~E_4~0); 45059#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 45060#L1376-1 assume !(0 == ~E_6~0); 45582#L1381-1 assume !(0 == ~E_7~0); 44247#L1386-1 assume !(0 == ~E_8~0); 43865#L1391-1 assume !(0 == ~E_9~0); 43866#L1396-1 assume !(0 == ~E_10~0); 44777#L1401-1 assume !(0 == ~E_11~0); 44778#L1406-1 assume !(0 == ~E_12~0); 45098#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 45099#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45666#L630 assume 1 == ~m_pc~0; 45518#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 44195#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43916#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 43917#L1593 assume !(0 != activate_threads_~tmp~1); 45812#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44876#L649 assume !(1 == ~t1_pc~0); 44836#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 44835#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45254#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 45255#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 45438#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45444#L668 assume 1 == ~t2_pc~0; 45784#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 44514#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44482#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 44072#L1609 assume !(0 != activate_threads_~tmp___1~0); 44073#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43851#L687 assume !(1 == ~t3_pc~0); 43831#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 43832#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44526#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 44617#L1617 assume !(0 != activate_threads_~tmp___2~0); 44813#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44816#L706 assume 1 == ~t4_pc~0; 45125#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 45129#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45631#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 45320#L1625 assume !(0 != activate_threads_~tmp___3~0); 45321#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44323#L725 assume !(1 == ~t5_pc~0); 44298#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 44299#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44818#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 44890#L1633 assume !(0 != activate_threads_~tmp___4~0); 45026#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 45034#L744 assume 1 == ~t6_pc~0; 45329#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 45331#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 45755#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 45655#L1641 assume !(0 != activate_threads_~tmp___5~0); 45656#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 45538#L763 assume 1 == ~t7_pc~0; 45449#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 43930#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 43845#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 43846#L1649 assume !(0 != activate_threads_~tmp___6~0); 44486#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 44491#L782 assume !(1 == ~t8_pc~0); 44687#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 44686#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 45133#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 43999#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 44000#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 44011#L801 assume 1 == ~t9_pc~0; 45704#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 44492#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 44316#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 44317#L1665 assume !(0 != activate_threads_~tmp___8~0); 44785#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 44026#L820 assume !(1 == ~t10_pc~0); 44027#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 44030#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 44623#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 45272#L1673 assume !(0 != activate_threads_~tmp___9~0); 45273#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 45234#L839 assume 1 == ~t11_pc~0; 45039#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 45040#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 45531#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 45532#L1681 assume !(0 != activate_threads_~tmp___10~0); 45814#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 44436#L858 assume !(1 == ~t12_pc~0); 44373#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 44374#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 44844#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 44845#L1689 assume !(0 != activate_threads_~tmp___11~0); 45427#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 45280#L877 assume 1 == ~t13_pc~0; 45281#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 45287#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 45739#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 44081#L1697 assume !(0 != activate_threads_~tmp___12~0); 44082#L1697-2 assume !(1 == ~M_E~0); 44083#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44151#L1434-1 assume !(1 == ~T2_E~0); 44152#L1439-1 assume !(1 == ~T3_E~0); 44632#L1444-1 assume !(1 == ~T4_E~0); 44633#L1449-1 assume !(1 == ~T5_E~0); 45153#L1454-1 assume !(1 == ~T6_E~0); 45054#L1459-1 assume !(1 == ~T7_E~0); 45055#L1464-1 assume !(1 == ~T8_E~0); 45600#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44277#L1474-1 assume !(1 == ~T10_E~0); 43901#L1479-1 assume !(1 == ~T11_E~0); 43902#L1484-1 assume !(1 == ~T12_E~0); 44783#L1489-1 assume !(1 == ~T13_E~0); 44784#L1494-1 assume !(1 == ~E_M~0); 45120#L1499-1 assume !(1 == ~E_1~0); 45121#L1504-1 assume !(1 == ~E_2~0); 45649#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 45549#L1514-1 assume !(1 == ~E_4~0); 44406#L1519-1 assume !(1 == ~E_5~0); 44050#L1524-1 assume !(1 == ~E_6~0); 44051#L1529-1 assume !(1 == ~E_7~0); 44547#L1534-1 assume !(1 == ~E_8~0); 44548#L1539-1 assume !(1 == ~E_9~0); 45217#L1544-1 assume !(1 == ~E_10~0); 45218#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 45621#L1554-1 assume !(1 == ~E_12~0); 44447#L1559-1 assume !(1 == ~E_13~0); 44220#L1930-1 [2018-11-28 12:50:48,483 INFO L796 eck$LassoCheckResult]: Loop: 44220#L1930-1 assume !false; 44533#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 43879#L1256 assume !false; 44088#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 45672#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44126#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 45242#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 45243#L1069 assume !(0 != eval_~tmp~0); 44624#L1271 start_simulation_~kernel_st~0 := 2; 44625#L897-1 start_simulation_~kernel_st~0 := 3; 44994#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 44977#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44978#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45661#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44498#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44226#L1301-3 assume !(0 == ~T5_E~0); 44227#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44710#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44565#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44566#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45083#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45084#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45486#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44352#L1341-3 assume !(0 == ~T13_E~0); 44170#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44171#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44786#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44787#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45140#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 45052#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45053#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45591#L1381-3 assume !(0 == ~E_7~0); 44257#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43875#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43876#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44780#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44781#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 45107#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45108#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45465#L630-45 assume !(1 == ~m_pc~0); 45466#L630-47 is_master_triggered_~__retres1~0 := 0; 44143#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43855#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 43856#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45720#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44707#L649-45 assume 1 == ~t1_pc~0; 44708#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 44711#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45148#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 44455#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 44456#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44460#L668-45 assume 1 == ~t2_pc~0; 45714#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 44499#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44331#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 44147#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 44148#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43947#L687-45 assume 1 == ~t3_pc~0; 43948#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 43956#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44567#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 44568#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 44848#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44851#L706-45 assume 1 == ~t4_pc~0; 45185#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 45186#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45664#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 45394#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 45395#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44391#L725-45 assume !(1 == ~t5_pc~0); 44392#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 44395#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44801#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 44861#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 45072#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 45073#L744-45 assume 1 == ~t6_pc~0; 45413#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 45387#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 45743#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 45674#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 45675#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 45585#L763-45 assume !(1 == ~t7_pc~0); 45586#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 43873#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 43874#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 44046#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 44235#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 44239#L782-45 assume 1 == ~t8_pc~0; 44643#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 44647#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 45106#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 44903#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 44904#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 44907#L801-45 assume 1 == ~t9_pc~0; 45680#L802-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 44345#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 44251#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 44252#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 44534#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 44535#L820-45 assume 1 == ~t10_pc~0; 44920#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 44591#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 44592#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 45146#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 45147#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 45013#L839-45 assume 1 == ~t11_pc~0; 44983#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 44984#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 45471#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 45472#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 45713#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 44097#L858-45 assume !(1 == ~t12_pc~0); 44098#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 44100#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 44726#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 44727#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 45547#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 45351#L877-45 assume 1 == ~t13_pc~0; 45352#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 45245#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 45778#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 44137#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 44138#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 44144#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44160#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44161#L1439-3 assume !(1 == ~T3_E~0); 44641#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44642#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45160#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45057#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45058#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45603#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44290#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43863#L1479-3 assume !(1 == ~T11_E~0); 43864#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44775#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 44776#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45094#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45095#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45653#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45554#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44414#L1519-3 assume !(1 == ~E_5~0); 44055#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44056#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44551#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44552#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45226#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45227#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45628#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44443#L1559-3 assume !(1 == ~E_13~0); 44089#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 44090#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44129#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 45238#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 45239#L1949 assume !(0 == start_simulation_~tmp~3); 45738#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 45667#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44132#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 45240#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 45241#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 44452#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 44438#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 44219#L1962 assume !(0 != start_simulation_~tmp___0~1); 44220#L1930-1 [2018-11-28 12:50:48,483 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,483 INFO L82 PathProgramCache]: Analyzing trace with hash 109904039, now seen corresponding path program 1 times [2018-11-28 12:50:48,483 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,483 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,484 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,484 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:50:48,484 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,548 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,549 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:48,549 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:48,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,549 INFO L82 PathProgramCache]: Analyzing trace with hash 2120669956, now seen corresponding path program 1 times [2018-11-28 12:50:48,549 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,550 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,550 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:48,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,670 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,670 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:48,670 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:48,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:48,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:48,671 INFO L87 Difference]: Start difference. First operand 1988 states and 2950 transitions. cyclomatic complexity: 963 Second operand 3 states. [2018-11-28 12:50:48,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:48,686 INFO L93 Difference]: Finished difference Result 1988 states and 2949 transitions. [2018-11-28 12:50:48,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:48,686 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2949 transitions. [2018-11-28 12:50:48,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2949 transitions. [2018-11-28 12:50:48,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:48,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:48,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2949 transitions. [2018-11-28 12:50:48,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:48,699 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2949 transitions. [2018-11-28 12:50:48,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2949 transitions. [2018-11-28 12:50:48,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:48,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:48,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2949 transitions. [2018-11-28 12:50:48,718 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2949 transitions. [2018-11-28 12:50:48,718 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2949 transitions. [2018-11-28 12:50:48,718 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-28 12:50:48,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2949 transitions. [2018-11-28 12:50:48,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:48,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:48,726 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,726 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,726 INFO L794 eck$LassoCheckResult]: Stem: 48371#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 48372#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 49220#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49258#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 48067#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48068#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48825#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48604#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48605#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48955#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48956#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49641#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48479#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48184#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48185#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48664#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48665#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 49241#L969-1 assume !(0 == ~M_E~0); 48975#L1281-1 assume !(0 == ~T1_E~0); 48976#L1286-1 assume !(0 == ~T2_E~0); 49646#L1291-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48488#L1296-1 assume !(0 == ~T4_E~0); 48205#L1301-1 assume !(0 == ~T5_E~0); 48206#L1306-1 assume !(0 == ~T6_E~0); 48683#L1311-1 assume !(0 == ~T7_E~0); 48542#L1316-1 assume !(0 == ~T8_E~0); 48543#L1321-1 assume !(0 == ~T9_E~0); 49061#L1326-1 assume !(0 == ~T10_E~0); 49062#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49463#L1336-1 assume !(0 == ~T12_E~0); 48331#L1341-1 assume !(0 == ~T13_E~0); 48148#L1346-1 assume !(0 == ~E_M~0); 48149#L1351-1 assume !(0 == ~E_1~0); 48628#L1356-1 assume !(0 == ~E_2~0); 48629#L1361-1 assume !(0 == ~E_3~0); 49146#L1366-1 assume !(0 == ~E_4~0); 49042#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 49043#L1376-1 assume !(0 == ~E_6~0); 49565#L1381-1 assume !(0 == ~E_7~0); 48230#L1386-1 assume !(0 == ~E_8~0); 47848#L1391-1 assume !(0 == ~E_9~0); 47849#L1396-1 assume !(0 == ~E_10~0); 48760#L1401-1 assume !(0 == ~E_11~0); 48761#L1406-1 assume !(0 == ~E_12~0); 49081#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 49082#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 49649#L630 assume 1 == ~m_pc~0; 49501#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 48178#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47899#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 47900#L1593 assume !(0 != activate_threads_~tmp~1); 49795#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48859#L649 assume !(1 == ~t1_pc~0); 48819#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 48818#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49237#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 49238#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 49421#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49427#L668 assume 1 == ~t2_pc~0; 49767#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 48497#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48465#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 48055#L1609 assume !(0 != activate_threads_~tmp___1~0); 48056#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47834#L687 assume !(1 == ~t3_pc~0); 47814#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 47815#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48509#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 48600#L1617 assume !(0 != activate_threads_~tmp___2~0); 48796#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48799#L706 assume 1 == ~t4_pc~0; 49108#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 49112#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49614#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 49303#L1625 assume !(0 != activate_threads_~tmp___3~0); 49304#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48306#L725 assume !(1 == ~t5_pc~0); 48281#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 48282#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48801#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 48873#L1633 assume !(0 != activate_threads_~tmp___4~0); 49009#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49017#L744 assume 1 == ~t6_pc~0; 49312#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 49314#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49738#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 49638#L1641 assume !(0 != activate_threads_~tmp___5~0); 49639#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 49521#L763 assume 1 == ~t7_pc~0; 49432#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 47913#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 47828#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 47829#L1649 assume !(0 != activate_threads_~tmp___6~0); 48469#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 48474#L782 assume !(1 == ~t8_pc~0); 48670#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 48669#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 49116#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 47982#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 47983#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 47994#L801 assume 1 == ~t9_pc~0; 49687#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 48475#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 48299#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 48300#L1665 assume !(0 != activate_threads_~tmp___8~0); 48768#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 48009#L820 assume !(1 == ~t10_pc~0); 48010#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 48013#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 48606#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 49255#L1673 assume !(0 != activate_threads_~tmp___9~0); 49256#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 49217#L839 assume 1 == ~t11_pc~0; 49022#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 49023#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 49514#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 49515#L1681 assume !(0 != activate_threads_~tmp___10~0); 49797#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 48419#L858 assume !(1 == ~t12_pc~0); 48356#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 48357#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 48827#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 48828#L1689 assume !(0 != activate_threads_~tmp___11~0); 49410#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 49263#L877 assume 1 == ~t13_pc~0; 49264#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 49270#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 49722#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 48064#L1697 assume !(0 != activate_threads_~tmp___12~0); 48065#L1697-2 assume !(1 == ~M_E~0); 48066#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48134#L1434-1 assume !(1 == ~T2_E~0); 48135#L1439-1 assume !(1 == ~T3_E~0); 48615#L1444-1 assume !(1 == ~T4_E~0); 48616#L1449-1 assume !(1 == ~T5_E~0); 49136#L1454-1 assume !(1 == ~T6_E~0); 49037#L1459-1 assume !(1 == ~T7_E~0); 49038#L1464-1 assume !(1 == ~T8_E~0); 49583#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48260#L1474-1 assume !(1 == ~T10_E~0); 47884#L1479-1 assume !(1 == ~T11_E~0); 47885#L1484-1 assume !(1 == ~T12_E~0); 48766#L1489-1 assume !(1 == ~T13_E~0); 48767#L1494-1 assume !(1 == ~E_M~0); 49103#L1499-1 assume !(1 == ~E_1~0); 49104#L1504-1 assume !(1 == ~E_2~0); 49632#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 49532#L1514-1 assume !(1 == ~E_4~0); 48389#L1519-1 assume !(1 == ~E_5~0); 48033#L1524-1 assume !(1 == ~E_6~0); 48034#L1529-1 assume !(1 == ~E_7~0); 48530#L1534-1 assume !(1 == ~E_8~0); 48531#L1539-1 assume !(1 == ~E_9~0); 49200#L1544-1 assume !(1 == ~E_10~0); 49201#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 49604#L1554-1 assume !(1 == ~E_12~0); 48430#L1559-1 assume !(1 == ~E_13~0); 48203#L1930-1 [2018-11-28 12:50:48,726 INFO L796 eck$LassoCheckResult]: Loop: 48203#L1930-1 assume !false; 48516#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 47862#L1256 assume !false; 48071#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 49655#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48109#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 49225#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 49226#L1069 assume !(0 != eval_~tmp~0); 48607#L1271 start_simulation_~kernel_st~0 := 2; 48608#L897-1 start_simulation_~kernel_st~0 := 3; 48977#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 48960#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48961#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49644#L1291-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48481#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48209#L1301-3 assume !(0 == ~T5_E~0); 48210#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48693#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48548#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48549#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49066#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49067#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49469#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 48335#L1341-3 assume !(0 == ~T13_E~0); 48153#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48154#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48769#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48770#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49123#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49035#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49036#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49574#L1381-3 assume !(0 == ~E_7~0); 48240#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47858#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47859#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48763#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48764#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 49090#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49091#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 49448#L630-45 assume !(1 == ~m_pc~0); 49449#L630-47 is_master_triggered_~__retres1~0 := 0; 48126#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47838#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 47839#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 49703#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48690#L649-45 assume 1 == ~t1_pc~0; 48691#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 48694#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49131#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 48438#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 48439#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48443#L668-45 assume 1 == ~t2_pc~0; 49697#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 48482#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48314#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 48130#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 48131#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47930#L687-45 assume 1 == ~t3_pc~0; 47931#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 47939#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48550#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 48551#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 48831#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48834#L706-45 assume 1 == ~t4_pc~0; 49168#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 49169#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49647#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 49377#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 49378#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48374#L725-45 assume !(1 == ~t5_pc~0); 48375#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 48378#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48784#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 48844#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 49055#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49056#L744-45 assume 1 == ~t6_pc~0; 49396#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 49370#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49726#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 49657#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 49658#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 49568#L763-45 assume !(1 == ~t7_pc~0); 49569#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 47856#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 47857#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 48029#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 48218#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 48222#L782-45 assume 1 == ~t8_pc~0; 48626#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 48630#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 49089#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 48886#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 48887#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 48890#L801-45 assume !(1 == ~t9_pc~0); 49662#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 48328#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 48234#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 48235#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 48517#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 48518#L820-45 assume 1 == ~t10_pc~0; 48903#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 48574#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 48575#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 49129#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 49130#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 48996#L839-45 assume 1 == ~t11_pc~0; 48966#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 48967#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 49454#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 49455#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 49696#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 48080#L858-45 assume !(1 == ~t12_pc~0); 48081#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 48083#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 48709#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 48710#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 49530#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 49334#L877-45 assume 1 == ~t13_pc~0; 49335#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 49228#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 49761#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 48120#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 48121#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 48127#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48143#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48144#L1439-3 assume !(1 == ~T3_E~0); 48624#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48625#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49143#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49040#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49041#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49586#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48273#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47846#L1479-3 assume !(1 == ~T11_E~0); 47847#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48758#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 48759#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49077#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49078#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49636#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49537#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48397#L1519-3 assume !(1 == ~E_5~0); 48038#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48039#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48534#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48535#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49209#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49210#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49611#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48426#L1559-3 assume !(1 == ~E_13~0); 48072#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 48073#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48112#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 49221#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 49222#L1949 assume !(0 == start_simulation_~tmp~3); 49721#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 49650#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48115#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 49223#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 49224#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 48435#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 48421#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 48202#L1962 assume !(0 != start_simulation_~tmp___0~1); 48203#L1930-1 [2018-11-28 12:50:48,727 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,727 INFO L82 PathProgramCache]: Analyzing trace with hash 265884581, now seen corresponding path program 1 times [2018-11-28 12:50:48,727 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,727 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,728 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:48,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,774 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,774 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:48,774 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:48,775 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,775 INFO L82 PathProgramCache]: Analyzing trace with hash -1267540893, now seen corresponding path program 3 times [2018-11-28 12:50:48,775 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,775 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,776 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,776 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:48,776 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,820 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,821 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:48,821 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:48,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:48,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:48,822 INFO L87 Difference]: Start difference. First operand 1988 states and 2949 transitions. cyclomatic complexity: 962 Second operand 3 states. [2018-11-28 12:50:48,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:48,855 INFO L93 Difference]: Finished difference Result 1988 states and 2944 transitions. [2018-11-28 12:50:48,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:48,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2944 transitions. [2018-11-28 12:50:48,860 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2944 transitions. [2018-11-28 12:50:48,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:48,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:48,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2944 transitions. [2018-11-28 12:50:48,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:48,870 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2944 transitions. [2018-11-28 12:50:48,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2944 transitions. [2018-11-28 12:50:48,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:48,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:48,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2944 transitions. [2018-11-28 12:50:48,897 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2944 transitions. [2018-11-28 12:50:48,897 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2944 transitions. [2018-11-28 12:50:48,897 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-28 12:50:48,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2944 transitions. [2018-11-28 12:50:48,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:48,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:48,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:48,905 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,905 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:48,905 INFO L794 eck$LassoCheckResult]: Stem: 52354#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 52355#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53203#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53241#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 52050#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52051#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52808#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52587#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52588#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52938#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52939#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53624#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52462#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52167#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52168#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52647#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52648#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53224#L969-1 assume !(0 == ~M_E~0); 52958#L1281-1 assume !(0 == ~T1_E~0); 52959#L1286-1 assume !(0 == ~T2_E~0); 53629#L1291-1 assume !(0 == ~T3_E~0); 52471#L1296-1 assume !(0 == ~T4_E~0); 52188#L1301-1 assume !(0 == ~T5_E~0); 52189#L1306-1 assume !(0 == ~T6_E~0); 52666#L1311-1 assume !(0 == ~T7_E~0); 52525#L1316-1 assume !(0 == ~T8_E~0); 52526#L1321-1 assume !(0 == ~T9_E~0); 53044#L1326-1 assume !(0 == ~T10_E~0); 53045#L1331-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53446#L1336-1 assume !(0 == ~T12_E~0); 52314#L1341-1 assume !(0 == ~T13_E~0); 52131#L1346-1 assume !(0 == ~E_M~0); 52132#L1351-1 assume !(0 == ~E_1~0); 52611#L1356-1 assume !(0 == ~E_2~0); 52612#L1361-1 assume !(0 == ~E_3~0); 53129#L1366-1 assume !(0 == ~E_4~0); 53025#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 53026#L1376-1 assume !(0 == ~E_6~0); 53548#L1381-1 assume !(0 == ~E_7~0); 52213#L1386-1 assume !(0 == ~E_8~0); 51831#L1391-1 assume !(0 == ~E_9~0); 51832#L1396-1 assume !(0 == ~E_10~0); 52743#L1401-1 assume !(0 == ~E_11~0); 52744#L1406-1 assume !(0 == ~E_12~0); 53064#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 53065#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53632#L630 assume 1 == ~m_pc~0; 53484#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 52161#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51882#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 51883#L1593 assume !(0 != activate_threads_~tmp~1); 53778#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52842#L649 assume !(1 == ~t1_pc~0); 52802#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 52801#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53220#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 53221#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 53404#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53410#L668 assume 1 == ~t2_pc~0; 53750#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 52480#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52448#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 52038#L1609 assume !(0 != activate_threads_~tmp___1~0); 52039#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51817#L687 assume !(1 == ~t3_pc~0); 51797#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 51798#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52492#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 52583#L1617 assume !(0 != activate_threads_~tmp___2~0); 52779#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 52782#L706 assume 1 == ~t4_pc~0; 53091#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 53095#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53597#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 53286#L1625 assume !(0 != activate_threads_~tmp___3~0); 53287#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 52289#L725 assume !(1 == ~t5_pc~0); 52264#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 52265#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52784#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 52856#L1633 assume !(0 != activate_threads_~tmp___4~0); 52992#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 53000#L744 assume 1 == ~t6_pc~0; 53295#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 53297#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53721#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 53621#L1641 assume !(0 != activate_threads_~tmp___5~0); 53622#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 53504#L763 assume 1 == ~t7_pc~0; 53415#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 51896#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 51811#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 51812#L1649 assume !(0 != activate_threads_~tmp___6~0); 52452#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 52457#L782 assume !(1 == ~t8_pc~0); 52653#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 52652#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 53099#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 51965#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 51966#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 51977#L801 assume 1 == ~t9_pc~0; 53670#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 52458#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 52282#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 52283#L1665 assume !(0 != activate_threads_~tmp___8~0); 52751#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 51992#L820 assume !(1 == ~t10_pc~0); 51993#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 51996#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 52589#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 53238#L1673 assume !(0 != activate_threads_~tmp___9~0); 53239#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 53200#L839 assume 1 == ~t11_pc~0; 53005#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 53006#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 53497#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 53498#L1681 assume !(0 != activate_threads_~tmp___10~0); 53780#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 52402#L858 assume !(1 == ~t12_pc~0); 52339#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 52340#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 52810#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 52811#L1689 assume !(0 != activate_threads_~tmp___11~0); 53393#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 53246#L877 assume 1 == ~t13_pc~0; 53247#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 53253#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 53705#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 52047#L1697 assume !(0 != activate_threads_~tmp___12~0); 52048#L1697-2 assume !(1 == ~M_E~0); 52049#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52117#L1434-1 assume !(1 == ~T2_E~0); 52118#L1439-1 assume !(1 == ~T3_E~0); 52598#L1444-1 assume !(1 == ~T4_E~0); 52599#L1449-1 assume !(1 == ~T5_E~0); 53119#L1454-1 assume !(1 == ~T6_E~0); 53020#L1459-1 assume !(1 == ~T7_E~0); 53021#L1464-1 assume !(1 == ~T8_E~0); 53566#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52243#L1474-1 assume !(1 == ~T10_E~0); 51867#L1479-1 assume !(1 == ~T11_E~0); 51868#L1484-1 assume !(1 == ~T12_E~0); 52749#L1489-1 assume !(1 == ~T13_E~0); 52750#L1494-1 assume !(1 == ~E_M~0); 53086#L1499-1 assume !(1 == ~E_1~0); 53087#L1504-1 assume !(1 == ~E_2~0); 53615#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 53515#L1514-1 assume !(1 == ~E_4~0); 52372#L1519-1 assume !(1 == ~E_5~0); 52016#L1524-1 assume !(1 == ~E_6~0); 52017#L1529-1 assume !(1 == ~E_7~0); 52513#L1534-1 assume !(1 == ~E_8~0); 52514#L1539-1 assume !(1 == ~E_9~0); 53183#L1544-1 assume !(1 == ~E_10~0); 53184#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 53587#L1554-1 assume !(1 == ~E_12~0); 52413#L1559-1 assume !(1 == ~E_13~0); 52186#L1930-1 [2018-11-28 12:50:48,906 INFO L796 eck$LassoCheckResult]: Loop: 52186#L1930-1 assume !false; 52499#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 51845#L1256 assume !false; 52054#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 53638#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 52092#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 53208#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 53209#L1069 assume !(0 != eval_~tmp~0); 52590#L1271 start_simulation_~kernel_st~0 := 2; 52591#L897-1 start_simulation_~kernel_st~0 := 3; 52960#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 52943#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52944#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53627#L1291-3 assume !(0 == ~T3_E~0); 52464#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52192#L1301-3 assume !(0 == ~T5_E~0); 52193#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52676#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52531#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52532#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53049#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53050#L1331-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53452#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52318#L1341-3 assume !(0 == ~T13_E~0); 52136#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52137#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52752#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52753#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53106#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53018#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53019#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53557#L1381-3 assume !(0 == ~E_7~0); 52223#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51841#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51842#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52746#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52747#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 53073#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53074#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53431#L630-45 assume !(1 == ~m_pc~0); 53432#L630-47 is_master_triggered_~__retres1~0 := 0; 52109#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51821#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 51822#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 53686#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52673#L649-45 assume 1 == ~t1_pc~0; 52674#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 52677#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53114#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 52421#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 52422#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52426#L668-45 assume 1 == ~t2_pc~0; 53680#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 52465#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52297#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 52113#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 52114#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51913#L687-45 assume 1 == ~t3_pc~0; 51914#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 51922#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52533#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 52534#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 52814#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 52817#L706-45 assume !(1 == ~t4_pc~0); 53153#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 53152#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53630#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 53360#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 53361#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 52357#L725-45 assume !(1 == ~t5_pc~0); 52358#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 52361#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52767#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 52827#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 53038#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 53039#L744-45 assume 1 == ~t6_pc~0; 53379#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 53353#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53709#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 53640#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 53641#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 53551#L763-45 assume !(1 == ~t7_pc~0); 53552#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 51839#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 51840#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 52012#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 52201#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 52205#L782-45 assume 1 == ~t8_pc~0; 52609#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 52613#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 53072#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 52869#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 52870#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 52873#L801-45 assume !(1 == ~t9_pc~0); 53645#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 52311#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 52217#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 52218#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 52500#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 52501#L820-45 assume 1 == ~t10_pc~0; 52886#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 52557#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 52558#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 53112#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 53113#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 52979#L839-45 assume 1 == ~t11_pc~0; 52949#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 52950#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 53437#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 53438#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 53679#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 52063#L858-45 assume !(1 == ~t12_pc~0); 52064#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 52066#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 52692#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 52693#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 53513#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 53317#L877-45 assume 1 == ~t13_pc~0; 53318#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 53211#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 53744#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 52103#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 52104#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 52110#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52126#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52127#L1439-3 assume !(1 == ~T3_E~0); 52607#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52608#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53126#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53023#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53024#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53569#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52256#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51829#L1479-3 assume !(1 == ~T11_E~0); 51830#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52741#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 52742#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53060#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53061#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53619#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53520#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52380#L1519-3 assume !(1 == ~E_5~0); 52021#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52022#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52517#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52518#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53192#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53193#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53594#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 52409#L1559-3 assume !(1 == ~E_13~0); 52055#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 52056#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 52095#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 53204#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 53205#L1949 assume !(0 == start_simulation_~tmp~3); 53704#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 53633#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 52098#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 53206#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 53207#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 52418#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 52404#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 52185#L1962 assume !(0 != start_simulation_~tmp___0~1); 52186#L1930-1 [2018-11-28 12:50:48,906 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,906 INFO L82 PathProgramCache]: Analyzing trace with hash 335532455, now seen corresponding path program 1 times [2018-11-28 12:50:48,906 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,906 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,907 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:50:48,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:48,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:48,955 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:48,955 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:48,956 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:48,956 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:48,956 INFO L82 PathProgramCache]: Analyzing trace with hash 1101202112, now seen corresponding path program 1 times [2018-11-28 12:50:48,956 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:48,956 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:48,957 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,957 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:48,957 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:48,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:49,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:49,022 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:49,022 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:49,022 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:49,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:49,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:49,023 INFO L87 Difference]: Start difference. First operand 1988 states and 2944 transitions. cyclomatic complexity: 957 Second operand 3 states. [2018-11-28 12:50:49,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:49,052 INFO L93 Difference]: Finished difference Result 1988 states and 2939 transitions. [2018-11-28 12:50:49,053 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:49,053 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2939 transitions. [2018-11-28 12:50:49,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:49,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2939 transitions. [2018-11-28 12:50:49,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:49,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:49,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2939 transitions. [2018-11-28 12:50:49,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:49,071 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2939 transitions. [2018-11-28 12:50:49,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2939 transitions. [2018-11-28 12:50:49,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:49,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:49,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2939 transitions. [2018-11-28 12:50:49,097 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2939 transitions. [2018-11-28 12:50:49,097 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2939 transitions. [2018-11-28 12:50:49,097 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-28 12:50:49,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2939 transitions. [2018-11-28 12:50:49,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:49,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:49,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:49,104 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:49,104 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:49,105 INFO L794 eck$LassoCheckResult]: Stem: 56337#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 56338#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 57186#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 57224#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 56033#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56034#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56791#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56570#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56571#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56921#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56922#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57607#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 56445#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56150#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56151#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56630#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56631#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 57207#L969-1 assume !(0 == ~M_E~0); 56941#L1281-1 assume !(0 == ~T1_E~0); 56942#L1286-1 assume !(0 == ~T2_E~0); 57612#L1291-1 assume !(0 == ~T3_E~0); 56454#L1296-1 assume !(0 == ~T4_E~0); 56171#L1301-1 assume !(0 == ~T5_E~0); 56172#L1306-1 assume !(0 == ~T6_E~0); 56649#L1311-1 assume !(0 == ~T7_E~0); 56508#L1316-1 assume !(0 == ~T8_E~0); 56509#L1321-1 assume !(0 == ~T9_E~0); 57027#L1326-1 assume !(0 == ~T10_E~0); 57028#L1331-1 assume !(0 == ~T11_E~0); 57429#L1336-1 assume !(0 == ~T12_E~0); 56297#L1341-1 assume !(0 == ~T13_E~0); 56114#L1346-1 assume !(0 == ~E_M~0); 56115#L1351-1 assume !(0 == ~E_1~0); 56594#L1356-1 assume !(0 == ~E_2~0); 56595#L1361-1 assume !(0 == ~E_3~0); 57112#L1366-1 assume !(0 == ~E_4~0); 57008#L1371-1 assume 0 == ~E_5~0;~E_5~0 := 1; 57009#L1376-1 assume !(0 == ~E_6~0); 57531#L1381-1 assume !(0 == ~E_7~0); 56196#L1386-1 assume !(0 == ~E_8~0); 55814#L1391-1 assume !(0 == ~E_9~0); 55815#L1396-1 assume !(0 == ~E_10~0); 56726#L1401-1 assume !(0 == ~E_11~0); 56727#L1406-1 assume !(0 == ~E_12~0); 57047#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 57048#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57615#L630 assume 1 == ~m_pc~0; 57467#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 56144#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55865#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55866#L1593 assume !(0 != activate_threads_~tmp~1); 57761#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56825#L649 assume !(1 == ~t1_pc~0); 56785#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 56784#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57203#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 57204#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 57387#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 57393#L668 assume 1 == ~t2_pc~0; 57733#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 56463#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56431#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56021#L1609 assume !(0 != activate_threads_~tmp___1~0); 56022#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55800#L687 assume !(1 == ~t3_pc~0); 55780#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 55781#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56475#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 56566#L1617 assume !(0 != activate_threads_~tmp___2~0); 56762#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56765#L706 assume 1 == ~t4_pc~0; 57074#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 57078#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57580#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 57269#L1625 assume !(0 != activate_threads_~tmp___3~0); 57270#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56272#L725 assume !(1 == ~t5_pc~0); 56247#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 56248#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56767#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 56839#L1633 assume !(0 != activate_threads_~tmp___4~0); 56975#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 56983#L744 assume 1 == ~t6_pc~0; 57278#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 57280#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 57704#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 57604#L1641 assume !(0 != activate_threads_~tmp___5~0); 57605#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 57487#L763 assume 1 == ~t7_pc~0; 57398#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 55879#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 55794#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 55795#L1649 assume !(0 != activate_threads_~tmp___6~0); 56435#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 56440#L782 assume !(1 == ~t8_pc~0); 56636#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 56635#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 57082#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 55948#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 55949#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 55960#L801 assume 1 == ~t9_pc~0; 57653#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 56441#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 56265#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 56266#L1665 assume !(0 != activate_threads_~tmp___8~0); 56734#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 55975#L820 assume !(1 == ~t10_pc~0); 55976#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 55979#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 56572#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 57221#L1673 assume !(0 != activate_threads_~tmp___9~0); 57222#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 57183#L839 assume 1 == ~t11_pc~0; 56988#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 56989#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 57480#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 57481#L1681 assume !(0 != activate_threads_~tmp___10~0); 57763#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 56385#L858 assume !(1 == ~t12_pc~0); 56322#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 56323#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 56793#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 56794#L1689 assume !(0 != activate_threads_~tmp___11~0); 57376#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 57229#L877 assume 1 == ~t13_pc~0; 57230#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 57236#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 57688#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 56030#L1697 assume !(0 != activate_threads_~tmp___12~0); 56031#L1697-2 assume !(1 == ~M_E~0); 56032#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56100#L1434-1 assume !(1 == ~T2_E~0); 56101#L1439-1 assume !(1 == ~T3_E~0); 56581#L1444-1 assume !(1 == ~T4_E~0); 56582#L1449-1 assume !(1 == ~T5_E~0); 57102#L1454-1 assume !(1 == ~T6_E~0); 57003#L1459-1 assume !(1 == ~T7_E~0); 57004#L1464-1 assume !(1 == ~T8_E~0); 57549#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56226#L1474-1 assume !(1 == ~T10_E~0); 55850#L1479-1 assume !(1 == ~T11_E~0); 55851#L1484-1 assume !(1 == ~T12_E~0); 56732#L1489-1 assume !(1 == ~T13_E~0); 56733#L1494-1 assume !(1 == ~E_M~0); 57069#L1499-1 assume !(1 == ~E_1~0); 57070#L1504-1 assume !(1 == ~E_2~0); 57598#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 57498#L1514-1 assume !(1 == ~E_4~0); 56355#L1519-1 assume !(1 == ~E_5~0); 55999#L1524-1 assume !(1 == ~E_6~0); 56000#L1529-1 assume !(1 == ~E_7~0); 56496#L1534-1 assume !(1 == ~E_8~0); 56497#L1539-1 assume !(1 == ~E_9~0); 57166#L1544-1 assume !(1 == ~E_10~0); 57167#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 57570#L1554-1 assume !(1 == ~E_12~0); 56396#L1559-1 assume !(1 == ~E_13~0); 56169#L1930-1 [2018-11-28 12:50:49,105 INFO L796 eck$LassoCheckResult]: Loop: 56169#L1930-1 assume !false; 56482#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 55828#L1256 assume !false; 56037#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 57621#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 56075#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57191#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 57192#L1069 assume !(0 != eval_~tmp~0); 56573#L1271 start_simulation_~kernel_st~0 := 2; 56574#L897-1 start_simulation_~kernel_st~0 := 3; 56943#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 56926#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56927#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57610#L1291-3 assume !(0 == ~T3_E~0); 56447#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56175#L1301-3 assume !(0 == ~T5_E~0); 56176#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56659#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56514#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 56515#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 57032#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57033#L1331-3 assume !(0 == ~T11_E~0); 57435#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56301#L1341-3 assume !(0 == ~T13_E~0); 56119#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56120#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 56735#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56736#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57089#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57001#L1371-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57002#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57540#L1381-3 assume !(0 == ~E_7~0); 56206#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 55824#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55825#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 56729#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56730#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 57056#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 57057#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57414#L630-45 assume !(1 == ~m_pc~0); 57415#L630-47 is_master_triggered_~__retres1~0 := 0; 56092#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55804#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55805#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 57669#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56656#L649-45 assume 1 == ~t1_pc~0; 56657#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 56660#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57097#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56404#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56405#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56409#L668-45 assume !(1 == ~t2_pc~0); 57664#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 56448#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56280#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56096#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 56097#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55896#L687-45 assume 1 == ~t3_pc~0; 55897#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 55905#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56516#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 56517#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 56797#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56800#L706-45 assume !(1 == ~t4_pc~0); 57136#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 57135#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57613#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 57343#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 57344#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56340#L725-45 assume !(1 == ~t5_pc~0); 56341#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 56344#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56750#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 56810#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 57021#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 57022#L744-45 assume 1 == ~t6_pc~0; 57362#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 57336#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 57692#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 57623#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 57624#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 57534#L763-45 assume 1 == ~t7_pc~0; 57536#L764-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 55822#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 55823#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 55995#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 56184#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 56188#L782-45 assume 1 == ~t8_pc~0; 56592#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 56596#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 57055#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 56852#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 56853#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 56856#L801-45 assume !(1 == ~t9_pc~0); 57628#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 56294#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 56200#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 56201#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 56483#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 56484#L820-45 assume 1 == ~t10_pc~0; 56869#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 56540#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 56541#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 57095#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 57096#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 56962#L839-45 assume 1 == ~t11_pc~0; 56932#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 56933#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 57420#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 57421#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 57662#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 56046#L858-45 assume 1 == ~t12_pc~0; 56048#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 56049#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 56675#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 56676#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 57496#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 57300#L877-45 assume 1 == ~t13_pc~0; 57301#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 57194#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 57727#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 56086#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 56087#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 56093#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56109#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56110#L1439-3 assume !(1 == ~T3_E~0); 56590#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56591#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57109#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57006#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57007#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57552#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56239#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 55812#L1479-3 assume !(1 == ~T11_E~0); 55813#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56724#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 56725#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57043#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57044#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57602#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57503#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56363#L1519-3 assume !(1 == ~E_5~0); 56004#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56005#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56500#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56501#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57175#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57176#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 57577#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 56392#L1559-3 assume !(1 == ~E_13~0); 56038#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 56039#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 56078#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57187#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 57188#L1949 assume !(0 == start_simulation_~tmp~3); 57687#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 57616#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 56081#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57189#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 57190#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 56401#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 56387#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 56168#L1962 assume !(0 != start_simulation_~tmp___0~1); 56169#L1930-1 [2018-11-28 12:50:49,105 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:49,105 INFO L82 PathProgramCache]: Analyzing trace with hash -612519511, now seen corresponding path program 1 times [2018-11-28 12:50:49,106 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:49,106 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:49,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,106 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:49,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:49,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:49,166 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:49,166 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:49,166 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:49,166 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:49,166 INFO L82 PathProgramCache]: Analyzing trace with hash -45172065, now seen corresponding path program 1 times [2018-11-28 12:50:49,166 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:49,166 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:49,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,167 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:49,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:49,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:49,223 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:49,223 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:49,223 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:49,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:49,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:49,224 INFO L87 Difference]: Start difference. First operand 1988 states and 2939 transitions. cyclomatic complexity: 952 Second operand 3 states. [2018-11-28 12:50:49,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:49,325 INFO L93 Difference]: Finished difference Result 1988 states and 2918 transitions. [2018-11-28 12:50:49,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:49,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2918 transitions. [2018-11-28 12:50:49,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:49,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2918 transitions. [2018-11-28 12:50:49,337 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:49,340 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:49,341 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2918 transitions. [2018-11-28 12:50:49,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:49,343 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2918 transitions. [2018-11-28 12:50:49,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2918 transitions. [2018-11-28 12:50:49,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:49,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:49,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2918 transitions. [2018-11-28 12:50:49,373 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2918 transitions. [2018-11-28 12:50:49,373 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2918 transitions. [2018-11-28 12:50:49,373 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-28 12:50:49,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2918 transitions. [2018-11-28 12:50:49,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:49,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:49,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:49,380 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:49,380 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:49,380 INFO L794 eck$LassoCheckResult]: Stem: 60319#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 60320#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 61169#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 61207#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 60016#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60017#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60774#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60553#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60554#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60904#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60905#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61590#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60428#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60133#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60134#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 60613#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60614#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 61190#L969-1 assume !(0 == ~M_E~0); 60924#L1281-1 assume !(0 == ~T1_E~0); 60925#L1286-1 assume !(0 == ~T2_E~0); 61595#L1291-1 assume !(0 == ~T3_E~0); 60437#L1296-1 assume !(0 == ~T4_E~0); 60154#L1301-1 assume !(0 == ~T5_E~0); 60155#L1306-1 assume !(0 == ~T6_E~0); 60632#L1311-1 assume !(0 == ~T7_E~0); 60491#L1316-1 assume !(0 == ~T8_E~0); 60492#L1321-1 assume !(0 == ~T9_E~0); 61010#L1326-1 assume !(0 == ~T10_E~0); 61011#L1331-1 assume !(0 == ~T11_E~0); 61412#L1336-1 assume !(0 == ~T12_E~0); 60280#L1341-1 assume !(0 == ~T13_E~0); 60097#L1346-1 assume !(0 == ~E_M~0); 60098#L1351-1 assume !(0 == ~E_1~0); 60577#L1356-1 assume !(0 == ~E_2~0); 60578#L1361-1 assume !(0 == ~E_3~0); 61095#L1366-1 assume !(0 == ~E_4~0); 60991#L1371-1 assume !(0 == ~E_5~0); 60992#L1376-1 assume !(0 == ~E_6~0); 61514#L1381-1 assume !(0 == ~E_7~0); 60179#L1386-1 assume !(0 == ~E_8~0); 59797#L1391-1 assume !(0 == ~E_9~0); 59798#L1396-1 assume !(0 == ~E_10~0); 60709#L1401-1 assume !(0 == ~E_11~0); 60710#L1406-1 assume !(0 == ~E_12~0); 61030#L1411-1 assume 0 == ~E_13~0;~E_13~0 := 1; 61031#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 61598#L630 assume 1 == ~m_pc~0; 61450#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 60127#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59848#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 59849#L1593 assume !(0 != activate_threads_~tmp~1); 61744#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60808#L649 assume !(1 == ~t1_pc~0); 60768#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 60767#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 61186#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 61187#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 61370#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 61376#L668 assume 1 == ~t2_pc~0; 61716#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 60446#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60414#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 60004#L1609 assume !(0 != activate_threads_~tmp___1~0); 60005#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59783#L687 assume !(1 == ~t3_pc~0); 59763#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 59764#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60458#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 60549#L1617 assume !(0 != activate_threads_~tmp___2~0); 60745#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60748#L706 assume 1 == ~t4_pc~0; 61057#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 61061#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 61563#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 61252#L1625 assume !(0 != activate_threads_~tmp___3~0); 61253#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60255#L725 assume !(1 == ~t5_pc~0); 60230#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 60231#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 60750#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 60822#L1633 assume !(0 != activate_threads_~tmp___4~0); 60958#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 60966#L744 assume 1 == ~t6_pc~0; 61261#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 61263#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 61687#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 61587#L1641 assume !(0 != activate_threads_~tmp___5~0); 61588#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 61470#L763 assume 1 == ~t7_pc~0; 61381#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 59862#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 59777#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 59778#L1649 assume !(0 != activate_threads_~tmp___6~0); 60418#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 60423#L782 assume !(1 == ~t8_pc~0); 60619#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 60618#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 61065#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 59931#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 59932#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 59943#L801 assume 1 == ~t9_pc~0; 61636#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 60424#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 60248#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 60249#L1665 assume !(0 != activate_threads_~tmp___8~0); 60717#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 59958#L820 assume !(1 == ~t10_pc~0); 59959#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 59962#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 60555#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 61204#L1673 assume !(0 != activate_threads_~tmp___9~0); 61205#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 61166#L839 assume 1 == ~t11_pc~0; 60971#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 60972#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 61463#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 61464#L1681 assume !(0 != activate_threads_~tmp___10~0); 61746#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 60368#L858 assume !(1 == ~t12_pc~0); 60305#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 60306#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 60776#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 60777#L1689 assume !(0 != activate_threads_~tmp___11~0); 61359#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 61212#L877 assume 1 == ~t13_pc~0; 61213#L878 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 61219#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 61671#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 60013#L1697 assume !(0 != activate_threads_~tmp___12~0); 60014#L1697-2 assume !(1 == ~M_E~0); 60015#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60083#L1434-1 assume !(1 == ~T2_E~0); 60084#L1439-1 assume !(1 == ~T3_E~0); 60564#L1444-1 assume !(1 == ~T4_E~0); 60565#L1449-1 assume !(1 == ~T5_E~0); 61085#L1454-1 assume !(1 == ~T6_E~0); 60986#L1459-1 assume !(1 == ~T7_E~0); 60987#L1464-1 assume !(1 == ~T8_E~0); 61532#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60209#L1474-1 assume !(1 == ~T10_E~0); 59833#L1479-1 assume !(1 == ~T11_E~0); 59834#L1484-1 assume !(1 == ~T12_E~0); 60715#L1489-1 assume !(1 == ~T13_E~0); 60716#L1494-1 assume !(1 == ~E_M~0); 61052#L1499-1 assume !(1 == ~E_1~0); 61053#L1504-1 assume !(1 == ~E_2~0); 61581#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 61481#L1514-1 assume !(1 == ~E_4~0); 60336#L1519-1 assume !(1 == ~E_5~0); 59982#L1524-1 assume !(1 == ~E_6~0); 59983#L1529-1 assume !(1 == ~E_7~0); 60479#L1534-1 assume !(1 == ~E_8~0); 60480#L1539-1 assume !(1 == ~E_9~0); 61149#L1544-1 assume !(1 == ~E_10~0); 61150#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 61553#L1554-1 assume !(1 == ~E_12~0); 60379#L1559-1 assume !(1 == ~E_13~0); 60152#L1930-1 [2018-11-28 12:50:49,381 INFO L796 eck$LassoCheckResult]: Loop: 60152#L1930-1 assume !false; 60465#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 59811#L1256 assume !false; 60020#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 61604#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 60058#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 61174#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 61175#L1069 assume !(0 != eval_~tmp~0); 60556#L1271 start_simulation_~kernel_st~0 := 2; 60557#L897-1 start_simulation_~kernel_st~0 := 3; 60926#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 60909#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60910#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61593#L1291-3 assume !(0 == ~T3_E~0); 60430#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60158#L1301-3 assume !(0 == ~T5_E~0); 60159#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60642#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60497#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60498#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 61015#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 61016#L1331-3 assume !(0 == ~T11_E~0); 61418#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60284#L1341-3 assume !(0 == ~T13_E~0); 60102#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60103#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60718#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60719#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61072#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60984#L1371-3 assume !(0 == ~E_5~0); 60985#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61523#L1381-3 assume !(0 == ~E_7~0); 60189#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59807#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59808#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 60712#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60713#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 61039#L1411-3 assume 0 == ~E_13~0;~E_13~0 := 1; 61040#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 61397#L630-45 assume !(1 == ~m_pc~0); 61398#L630-47 is_master_triggered_~__retres1~0 := 0; 60075#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59787#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 59788#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 61652#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60639#L649-45 assume 1 == ~t1_pc~0; 60640#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 60643#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 61080#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 60387#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 60388#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60392#L668-45 assume 1 == ~t2_pc~0; 61646#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 60431#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60263#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 60079#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 60080#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59879#L687-45 assume 1 == ~t3_pc~0; 59880#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 59888#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60499#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 60500#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 60780#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60783#L706-45 assume 1 == ~t4_pc~0; 61117#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 61118#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 61596#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 61326#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 61327#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60322#L725-45 assume !(1 == ~t5_pc~0); 60323#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 60326#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 60733#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 60793#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 61004#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 61005#L744-45 assume 1 == ~t6_pc~0; 61345#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 61319#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 61675#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 61606#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 61607#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 61517#L763-45 assume !(1 == ~t7_pc~0); 61518#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 59805#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 59806#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 59978#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 60167#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 60171#L782-45 assume !(1 == ~t8_pc~0); 60576#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 60579#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 61038#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 60835#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 60836#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 60839#L801-45 assume !(1 == ~t9_pc~0); 61611#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 60277#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 60183#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 60184#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 60466#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 60467#L820-45 assume 1 == ~t10_pc~0; 60852#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 60523#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 60524#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 61078#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 61079#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 60945#L839-45 assume 1 == ~t11_pc~0; 60915#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 60916#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 61403#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 61404#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 61645#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 60029#L858-45 assume !(1 == ~t12_pc~0); 60030#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 60032#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 60658#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 60659#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 61479#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 61283#L877-45 assume 1 == ~t13_pc~0; 61284#L878-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 61177#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 61710#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 60069#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 60070#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 60076#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60092#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60093#L1439-3 assume !(1 == ~T3_E~0); 60573#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60574#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 61092#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60989#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60990#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 61535#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60222#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59795#L1479-3 assume !(1 == ~T11_E~0); 59796#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60707#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 60708#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 61026#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61027#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61585#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61486#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60343#L1519-3 assume !(1 == ~E_5~0); 59987#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59988#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60483#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60484#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 61158#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 61159#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61560#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60375#L1559-3 assume !(1 == ~E_13~0); 60021#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 60022#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 60061#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 61170#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 61171#L1949 assume !(0 == start_simulation_~tmp~3); 61670#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 61599#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 60064#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 61172#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 61173#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 60384#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 60370#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 60151#L1962 assume !(0 != start_simulation_~tmp___0~1); 60152#L1930-1 [2018-11-28 12:50:49,381 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:49,381 INFO L82 PathProgramCache]: Analyzing trace with hash -124472405, now seen corresponding path program 1 times [2018-11-28 12:50:49,381 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:49,381 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:49,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,382 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:49,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:49,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:49,427 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:49,427 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:49,427 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:49,427 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:49,428 INFO L82 PathProgramCache]: Analyzing trace with hash 25506876, now seen corresponding path program 1 times [2018-11-28 12:50:49,428 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:49,428 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:49,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,436 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:49,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:49,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:49,519 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:49,519 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:50:49,519 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:49,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:49,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:49,519 INFO L87 Difference]: Start difference. First operand 1988 states and 2918 transitions. cyclomatic complexity: 931 Second operand 3 states. [2018-11-28 12:50:49,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:49,646 INFO L93 Difference]: Finished difference Result 1988 states and 2897 transitions. [2018-11-28 12:50:49,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:49,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1988 states and 2897 transitions. [2018-11-28 12:50:49,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:49,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1988 states to 1988 states and 2897 transitions. [2018-11-28 12:50:49,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1988 [2018-11-28 12:50:49,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1988 [2018-11-28 12:50:49,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1988 states and 2897 transitions. [2018-11-28 12:50:49,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:49,664 INFO L705 BuchiCegarLoop]: Abstraction has 1988 states and 2897 transitions. [2018-11-28 12:50:49,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states and 2897 transitions. [2018-11-28 12:50:49,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1988. [2018-11-28 12:50:49,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1988 states. [2018-11-28 12:50:49,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2897 transitions. [2018-11-28 12:50:49,690 INFO L728 BuchiCegarLoop]: Abstraction has 1988 states and 2897 transitions. [2018-11-28 12:50:49,690 INFO L608 BuchiCegarLoop]: Abstraction has 1988 states and 2897 transitions. [2018-11-28 12:50:49,690 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-28 12:50:49,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2897 transitions. [2018-11-28 12:50:49,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2018-11-28 12:50:49,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:49,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:49,701 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:49,701 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:49,702 INFO L794 eck$LassoCheckResult]: Stem: 64302#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 64303#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 65152#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65190#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 63999#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64000#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64757#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64536#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64537#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64887#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64888#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65573#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64411#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64116#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64117#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64596#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64597#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 65173#L969-1 assume !(0 == ~M_E~0); 64907#L1281-1 assume !(0 == ~T1_E~0); 64908#L1286-1 assume !(0 == ~T2_E~0); 65578#L1291-1 assume !(0 == ~T3_E~0); 64420#L1296-1 assume !(0 == ~T4_E~0); 64137#L1301-1 assume !(0 == ~T5_E~0); 64138#L1306-1 assume !(0 == ~T6_E~0); 64615#L1311-1 assume !(0 == ~T7_E~0); 64474#L1316-1 assume !(0 == ~T8_E~0); 64475#L1321-1 assume !(0 == ~T9_E~0); 64993#L1326-1 assume !(0 == ~T10_E~0); 64994#L1331-1 assume !(0 == ~T11_E~0); 65395#L1336-1 assume !(0 == ~T12_E~0); 64263#L1341-1 assume !(0 == ~T13_E~0); 64080#L1346-1 assume !(0 == ~E_M~0); 64081#L1351-1 assume !(0 == ~E_1~0); 64560#L1356-1 assume !(0 == ~E_2~0); 64561#L1361-1 assume !(0 == ~E_3~0); 65078#L1366-1 assume !(0 == ~E_4~0); 64974#L1371-1 assume !(0 == ~E_5~0); 64975#L1376-1 assume !(0 == ~E_6~0); 65497#L1381-1 assume !(0 == ~E_7~0); 64162#L1386-1 assume !(0 == ~E_8~0); 63780#L1391-1 assume !(0 == ~E_9~0); 63781#L1396-1 assume !(0 == ~E_10~0); 64692#L1401-1 assume !(0 == ~E_11~0); 64693#L1406-1 assume !(0 == ~E_12~0); 65013#L1411-1 assume !(0 == ~E_13~0); 65014#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65581#L630 assume 1 == ~m_pc~0; 65433#L631 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 64110#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 63831#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 63832#L1593 assume !(0 != activate_threads_~tmp~1); 65727#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64791#L649 assume !(1 == ~t1_pc~0); 64751#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 64750#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65169#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 65170#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 65353#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65359#L668 assume 1 == ~t2_pc~0; 65699#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 64429#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64397#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 63987#L1609 assume !(0 != activate_threads_~tmp___1~0); 63988#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 63766#L687 assume !(1 == ~t3_pc~0); 63746#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 63747#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64441#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 64532#L1617 assume !(0 != activate_threads_~tmp___2~0); 64728#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64731#L706 assume 1 == ~t4_pc~0; 65040#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 65044#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65546#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 65235#L1625 assume !(0 != activate_threads_~tmp___3~0); 65236#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 64238#L725 assume !(1 == ~t5_pc~0); 64213#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 64214#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 64733#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 64805#L1633 assume !(0 != activate_threads_~tmp___4~0); 64941#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 64949#L744 assume 1 == ~t6_pc~0; 65244#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 65246#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 65670#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 65570#L1641 assume !(0 != activate_threads_~tmp___5~0); 65571#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 65453#L763 assume 1 == ~t7_pc~0; 65364#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 63845#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 63760#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 63761#L1649 assume !(0 != activate_threads_~tmp___6~0); 64401#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 64406#L782 assume !(1 == ~t8_pc~0); 64602#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 64601#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 65048#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 63914#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 63915#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 63926#L801 assume 1 == ~t9_pc~0; 65619#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 64407#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 64231#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 64232#L1665 assume !(0 != activate_threads_~tmp___8~0); 64700#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 63941#L820 assume !(1 == ~t10_pc~0); 63942#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 63945#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 64538#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 65187#L1673 assume !(0 != activate_threads_~tmp___9~0); 65188#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 65149#L839 assume 1 == ~t11_pc~0; 64954#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 64955#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 65446#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 65447#L1681 assume !(0 != activate_threads_~tmp___10~0); 65729#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 64351#L858 assume !(1 == ~t12_pc~0); 64288#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 64289#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 64759#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 64760#L1689 assume !(0 != activate_threads_~tmp___11~0); 65342#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 65195#L877 assume !(1 == ~t13_pc~0); 65197#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 65202#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 65654#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 63996#L1697 assume !(0 != activate_threads_~tmp___12~0); 63997#L1697-2 assume !(1 == ~M_E~0); 63998#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64066#L1434-1 assume !(1 == ~T2_E~0); 64067#L1439-1 assume !(1 == ~T3_E~0); 64547#L1444-1 assume !(1 == ~T4_E~0); 64548#L1449-1 assume !(1 == ~T5_E~0); 65068#L1454-1 assume !(1 == ~T6_E~0); 64969#L1459-1 assume !(1 == ~T7_E~0); 64970#L1464-1 assume !(1 == ~T8_E~0); 65515#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64192#L1474-1 assume !(1 == ~T10_E~0); 63816#L1479-1 assume !(1 == ~T11_E~0); 63817#L1484-1 assume !(1 == ~T12_E~0); 64698#L1489-1 assume !(1 == ~T13_E~0); 64699#L1494-1 assume !(1 == ~E_M~0); 65035#L1499-1 assume !(1 == ~E_1~0); 65036#L1504-1 assume !(1 == ~E_2~0); 65564#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 65464#L1514-1 assume !(1 == ~E_4~0); 64319#L1519-1 assume !(1 == ~E_5~0); 63965#L1524-1 assume !(1 == ~E_6~0); 63966#L1529-1 assume !(1 == ~E_7~0); 64462#L1534-1 assume !(1 == ~E_8~0); 64463#L1539-1 assume !(1 == ~E_9~0); 65132#L1544-1 assume !(1 == ~E_10~0); 65133#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 65536#L1554-1 assume !(1 == ~E_12~0); 64362#L1559-1 assume !(1 == ~E_13~0); 64135#L1930-1 [2018-11-28 12:50:49,702 INFO L796 eck$LassoCheckResult]: Loop: 64135#L1930-1 assume !false; 64448#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 63794#L1256 assume !false; 64003#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 65587#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 64041#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 65157#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 65158#L1069 assume !(0 != eval_~tmp~0); 64539#L1271 start_simulation_~kernel_st~0 := 2; 64540#L897-1 start_simulation_~kernel_st~0 := 3; 64909#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 64892#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64893#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65576#L1291-3 assume !(0 == ~T3_E~0); 64413#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64141#L1301-3 assume !(0 == ~T5_E~0); 64142#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64625#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64480#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64481#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64998#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 64999#L1331-3 assume !(0 == ~T11_E~0); 65401#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 64267#L1341-3 assume !(0 == ~T13_E~0); 64085#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64086#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64701#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64702#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65055#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 64967#L1371-3 assume !(0 == ~E_5~0); 64968#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65506#L1381-3 assume !(0 == ~E_7~0); 64172#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63790#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 63791#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64695#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 64696#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 65022#L1411-3 assume !(0 == ~E_13~0); 65023#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65380#L630-45 assume !(1 == ~m_pc~0); 65381#L630-47 is_master_triggered_~__retres1~0 := 0; 64058#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 63770#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 63771#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 65635#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64622#L649-45 assume !(1 == ~t1_pc~0); 64624#L649-47 is_transmit1_triggered_~__retres1~1 := 0; 64626#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65063#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 64370#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 64371#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64375#L668-45 assume 1 == ~t2_pc~0; 65629#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 64414#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64246#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 64062#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 64063#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 63862#L687-45 assume 1 == ~t3_pc~0; 63863#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 63871#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64482#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 64483#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 64763#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64766#L706-45 assume 1 == ~t4_pc~0; 65100#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 65101#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65579#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 65303#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 65304#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 64305#L725-45 assume !(1 == ~t5_pc~0); 64306#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 64309#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 64716#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 64776#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 64987#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 64988#L744-45 assume 1 == ~t6_pc~0; 65324#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 65295#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 65658#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 65589#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 65590#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 65500#L763-45 assume !(1 == ~t7_pc~0); 65501#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 63788#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 63789#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 63961#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 64150#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 64154#L782-45 assume 1 == ~t8_pc~0; 64558#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 64562#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 65021#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 64818#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 64819#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 64822#L801-45 assume 1 == ~t9_pc~0; 65595#L802-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 64260#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 64166#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 64167#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 64449#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 64450#L820-45 assume 1 == ~t10_pc~0; 64835#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 64506#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 64507#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 65061#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 65062#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 64928#L839-45 assume 1 == ~t11_pc~0; 64898#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 64899#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 65386#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 65387#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 65628#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 64012#L858-45 assume !(1 == ~t12_pc~0); 64013#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 64015#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 64641#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 64642#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 65462#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 65263#L877-45 assume !(1 == ~t13_pc~0); 65159#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 65160#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 65693#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 64052#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 64053#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 64059#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64075#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64076#L1439-3 assume !(1 == ~T3_E~0); 64556#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64557#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65075#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64972#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64973#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65518#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64205#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63778#L1479-3 assume !(1 == ~T11_E~0); 63779#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64690#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 64691#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65009#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65010#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65568#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65469#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64326#L1519-3 assume !(1 == ~E_5~0); 63970#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63971#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64466#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64467#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65141#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65142#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65543#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 64358#L1559-3 assume !(1 == ~E_13~0); 64004#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 64005#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 64044#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 65153#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 65154#L1949 assume !(0 == start_simulation_~tmp~3); 65653#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 65582#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 64047#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 65155#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 65156#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 64367#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 64353#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 64134#L1962 assume !(0 != start_simulation_~tmp___0~1); 64135#L1930-1 [2018-11-28 12:50:49,702 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:49,702 INFO L82 PathProgramCache]: Analyzing trace with hash 26114798, now seen corresponding path program 1 times [2018-11-28 12:50:49,702 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:49,702 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:49,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:49,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:49,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:49,763 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:49,763 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:49,764 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:49,764 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:49,764 INFO L82 PathProgramCache]: Analyzing trace with hash 719681978, now seen corresponding path program 1 times [2018-11-28 12:50:49,764 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:49,764 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:49,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,765 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:49,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:49,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:49,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:49,810 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:49,810 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:50:49,811 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:49,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:49,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:49,811 INFO L87 Difference]: Start difference. First operand 1988 states and 2897 transitions. cyclomatic complexity: 910 Second operand 3 states. [2018-11-28 12:50:49,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:49,974 INFO L93 Difference]: Finished difference Result 3782 states and 5471 transitions. [2018-11-28 12:50:49,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:49,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3782 states and 5471 transitions. [2018-11-28 12:50:49,987 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3610 [2018-11-28 12:50:49,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3782 states to 3782 states and 5471 transitions. [2018-11-28 12:50:49,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3782 [2018-11-28 12:50:50,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3782 [2018-11-28 12:50:50,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3782 states and 5471 transitions. [2018-11-28 12:50:50,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:50,004 INFO L705 BuchiCegarLoop]: Abstraction has 3782 states and 5471 transitions. [2018-11-28 12:50:50,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3782 states and 5471 transitions. [2018-11-28 12:50:50,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3782 to 3686. [2018-11-28 12:50:50,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3686 states. [2018-11-28 12:50:50,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3686 states to 3686 states and 5337 transitions. [2018-11-28 12:50:50,052 INFO L728 BuchiCegarLoop]: Abstraction has 3686 states and 5337 transitions. [2018-11-28 12:50:50,052 INFO L608 BuchiCegarLoop]: Abstraction has 3686 states and 5337 transitions. [2018-11-28 12:50:50,052 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-28 12:50:50,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3686 states and 5337 transitions. [2018-11-28 12:50:50,062 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3514 [2018-11-28 12:50:50,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:50,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:50,064 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:50,064 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:50,064 INFO L794 eck$LassoCheckResult]: Stem: 70085#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 70086#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 70952#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 70991#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 69780#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69781#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70548#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70322#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70323#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70682#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 70683#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 71401#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70197#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69897#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69898#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 70382#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 70383#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 70973#L969-1 assume !(0 == ~M_E~0); 70702#L1281-1 assume !(0 == ~T1_E~0); 70703#L1286-1 assume !(0 == ~T2_E~0); 71410#L1291-1 assume !(0 == ~T3_E~0); 70206#L1296-1 assume !(0 == ~T4_E~0); 69919#L1301-1 assume !(0 == ~T5_E~0); 69920#L1306-1 assume !(0 == ~T6_E~0); 70403#L1311-1 assume !(0 == ~T7_E~0); 70260#L1316-1 assume !(0 == ~T8_E~0); 70261#L1321-1 assume !(0 == ~T9_E~0); 70788#L1326-1 assume !(0 == ~T10_E~0); 70789#L1331-1 assume !(0 == ~T11_E~0); 71204#L1336-1 assume !(0 == ~T12_E~0); 70046#L1341-1 assume !(0 == ~T13_E~0); 69861#L1346-1 assume !(0 == ~E_M~0); 69862#L1351-1 assume !(0 == ~E_1~0); 70346#L1356-1 assume !(0 == ~E_2~0); 70347#L1361-1 assume !(0 == ~E_3~0); 70873#L1366-1 assume !(0 == ~E_4~0); 70769#L1371-1 assume !(0 == ~E_5~0); 70770#L1376-1 assume !(0 == ~E_6~0); 71320#L1381-1 assume !(0 == ~E_7~0); 69944#L1386-1 assume !(0 == ~E_8~0); 69559#L1391-1 assume !(0 == ~E_9~0); 69560#L1396-1 assume !(0 == ~E_10~0); 70483#L1401-1 assume !(0 == ~E_11~0); 70484#L1406-1 assume !(0 == ~E_12~0); 70808#L1411-1 assume !(0 == ~E_13~0); 70809#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 71415#L630 assume !(1 == ~m_pc~0); 71412#L630-2 is_master_triggered_~__retres1~0 := 0; 69891#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69610#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 69611#L1593 assume !(0 != activate_threads_~tmp~1); 71570#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70584#L649 assume !(1 == ~t1_pc~0); 70542#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 70541#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70969#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70970#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 71156#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 71162#L668 assume 1 == ~t2_pc~0; 71541#L669 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 70215#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70182#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 69768#L1609 assume !(0 != activate_threads_~tmp___1~0); 69769#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69545#L687 assume !(1 == ~t3_pc~0); 69525#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 69526#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70227#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 70318#L1617 assume !(0 != activate_threads_~tmp___2~0); 70519#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 70522#L706 assume 1 == ~t4_pc~0; 70835#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 70839#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 71371#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 71038#L1625 assume !(0 != activate_threads_~tmp___3~0); 71039#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 70020#L725 assume !(1 == ~t5_pc~0); 69995#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 69996#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 70524#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 70598#L1633 assume !(0 != activate_threads_~tmp___4~0); 70736#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 70744#L744 assume 1 == ~t6_pc~0; 71047#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 71049#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 71511#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 71395#L1641 assume !(0 != activate_threads_~tmp___5~0); 71396#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 71276#L763 assume 1 == ~t7_pc~0; 71167#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 69624#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 69539#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 69540#L1649 assume !(0 != activate_threads_~tmp___6~0); 70187#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 70192#L782 assume !(1 == ~t8_pc~0); 70390#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 70389#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 70843#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 69693#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 69694#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 69705#L801 assume 1 == ~t9_pc~0; 71454#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 70193#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 70013#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 70014#L1665 assume !(0 != activate_threads_~tmp___8~0); 70491#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 69720#L820 assume !(1 == ~t10_pc~0); 69721#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 69724#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 70324#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 70988#L1673 assume !(0 != activate_threads_~tmp___9~0); 70989#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 70947#L839 assume 1 == ~t11_pc~0; 70749#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 70750#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 71269#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 71270#L1681 assume !(0 != activate_threads_~tmp___10~0); 71572#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 70136#L858 assume !(1 == ~t12_pc~0); 70071#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 70072#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 70550#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 70551#L1689 assume !(0 != activate_threads_~tmp___11~0); 71145#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 70996#L877 assume !(1 == ~t13_pc~0); 70998#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 71003#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 71495#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 69777#L1697 assume !(0 != activate_threads_~tmp___12~0); 69778#L1697-2 assume !(1 == ~M_E~0); 69779#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69847#L1434-1 assume !(1 == ~T2_E~0); 69848#L1439-1 assume !(1 == ~T3_E~0); 70333#L1444-1 assume !(1 == ~T4_E~0); 70334#L1449-1 assume !(1 == ~T5_E~0); 70863#L1454-1 assume !(1 == ~T6_E~0); 70764#L1459-1 assume !(1 == ~T7_E~0); 70765#L1464-1 assume !(1 == ~T8_E~0); 71338#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69974#L1474-1 assume !(1 == ~T10_E~0); 69595#L1479-1 assume !(1 == ~T11_E~0); 69596#L1484-1 assume !(1 == ~T12_E~0); 70489#L1489-1 assume !(1 == ~T13_E~0); 70490#L1494-1 assume !(1 == ~E_M~0); 70830#L1499-1 assume !(1 == ~E_1~0); 70831#L1504-1 assume !(1 == ~E_2~0); 71389#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 71287#L1514-1 assume !(1 == ~E_4~0); 70103#L1519-1 assume !(1 == ~E_5~0); 69746#L1524-1 assume !(1 == ~E_6~0); 69747#L1529-1 assume !(1 == ~E_7~0); 70248#L1534-1 assume !(1 == ~E_8~0); 70249#L1539-1 assume !(1 == ~E_9~0); 70930#L1544-1 assume !(1 == ~E_10~0); 70931#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 71359#L1554-1 assume !(1 == ~E_12~0); 70147#L1559-1 assume !(1 == ~E_13~0); 69917#L1930-1 [2018-11-28 12:50:50,065 INFO L796 eck$LassoCheckResult]: Loop: 69917#L1930-1 assume !false; 70234#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 69573#L1256 assume !false; 69784#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 71421#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 69822#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 70957#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 70958#L1069 assume !(0 != eval_~tmp~0); 70325#L1271 start_simulation_~kernel_st~0 := 2; 70326#L897-1 start_simulation_~kernel_st~0 := 3; 70704#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 70687#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70688#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 71405#L1291-3 assume !(0 == ~T3_E~0); 70199#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69923#L1301-3 assume !(0 == ~T5_E~0); 69924#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70413#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70266#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70267#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70793#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 70794#L1331-3 assume !(0 == ~T11_E~0); 71213#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 70050#L1341-3 assume !(0 == ~T13_E~0); 69866#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69867#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 70492#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70493#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70850#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70762#L1371-3 assume !(0 == ~E_5~0); 70763#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 71329#L1381-3 assume !(0 == ~E_7~0); 69954#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69569#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 69570#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 70486#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70487#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 70817#L1411-3 assume !(0 == ~E_13~0); 70818#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 71181#L630-45 assume !(1 == ~m_pc~0); 71182#L630-47 is_master_triggered_~__retres1~0 := 0; 69839#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69549#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 69550#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 71473#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70410#L649-45 assume 1 == ~t1_pc~0; 70411#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 70414#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70858#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70155#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 70156#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70160#L668-45 assume 1 == ~t2_pc~0; 71467#L669-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 70200#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70028#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 69843#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 69844#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69641#L687-45 assume !(1 == ~t3_pc~0); 69643#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 69650#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70268#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 70269#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 70554#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 70557#L706-45 assume 1 == ~t4_pc~0; 70898#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 70899#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 71411#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 71106#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 71107#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 70088#L725-45 assume !(1 == ~t5_pc~0); 70089#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 70092#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 70507#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 70567#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 70782#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 70783#L744-45 assume 1 == ~t6_pc~0; 71127#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 71098#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 71499#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 71424#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 71425#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 71323#L763-45 assume 1 == ~t7_pc~0; 71325#L764-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 69567#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 69568#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 69740#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 69932#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 69936#L782-45 assume !(1 == ~t8_pc~0); 70345#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 70348#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 70816#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 70611#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 70612#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 70615#L801-45 assume !(1 == ~t9_pc~0); 71429#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 70043#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 69948#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 69949#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 70235#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 70236#L820-45 assume !(1 == ~t10_pc~0); 70629#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 70292#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 70293#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 70856#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 70857#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 70723#L839-45 assume 1 == ~t11_pc~0; 70693#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 70694#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 71193#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 71194#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 73088#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 73087#L858-45 assume 1 == ~t12_pc~0; 73085#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 73084#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 73083#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 73082#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 73081#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 73080#L877-45 assume !(1 == ~t13_pc~0); 73078#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 73077#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 73076#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 69833#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 69834#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 69840#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69856#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69857#L1439-3 assume !(1 == ~T3_E~0); 70342#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70343#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70870#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70767#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70768#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 71341#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69987#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69557#L1479-3 assume !(1 == ~T11_E~0); 69558#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70481#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 70482#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70804#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70805#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 71393#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 71292#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70110#L1519-3 assume !(1 == ~E_5~0); 69751#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69752#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70252#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70253#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70939#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 70940#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 71367#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 71368#L1559-3 assume !(1 == ~E_13~0); 72227#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 71422#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 69825#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 70953#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 70954#L1949 assume !(0 == start_simulation_~tmp~3); 71494#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 71416#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 69828#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 70955#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 70956#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 70152#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 70138#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 69916#L1962 assume !(0 != start_simulation_~tmp___0~1); 69917#L1930-1 [2018-11-28 12:50:50,065 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:50,065 INFO L82 PathProgramCache]: Analyzing trace with hash 751194223, now seen corresponding path program 1 times [2018-11-28 12:50:50,065 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:50,065 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:50,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:50,066 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:50,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:50,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:50,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:50,129 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:50,129 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:50,129 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:50,130 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:50,130 INFO L82 PathProgramCache]: Analyzing trace with hash 2000481881, now seen corresponding path program 1 times [2018-11-28 12:50:50,130 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:50,130 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:50,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:50,131 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:50,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:50,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:50,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:50,186 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:50,186 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:50:50,186 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:50,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:50,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:50,187 INFO L87 Difference]: Start difference. First operand 3686 states and 5337 transitions. cyclomatic complexity: 1653 Second operand 3 states. [2018-11-28 12:50:50,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:50,355 INFO L93 Difference]: Finished difference Result 6975 states and 10049 transitions. [2018-11-28 12:50:50,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:50,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6975 states and 10049 transitions. [2018-11-28 12:50:50,379 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6798 [2018-11-28 12:50:50,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6975 states to 6975 states and 10049 transitions. [2018-11-28 12:50:50,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6975 [2018-11-28 12:50:50,404 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6975 [2018-11-28 12:50:50,404 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6975 states and 10049 transitions. [2018-11-28 12:50:50,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:50,411 INFO L705 BuchiCegarLoop]: Abstraction has 6975 states and 10049 transitions. [2018-11-28 12:50:50,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6975 states and 10049 transitions. [2018-11-28 12:50:50,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6975 to 6971. [2018-11-28 12:50:50,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6971 states. [2018-11-28 12:50:50,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6971 states to 6971 states and 10045 transitions. [2018-11-28 12:50:50,493 INFO L728 BuchiCegarLoop]: Abstraction has 6971 states and 10045 transitions. [2018-11-28 12:50:50,493 INFO L608 BuchiCegarLoop]: Abstraction has 6971 states and 10045 transitions. [2018-11-28 12:50:50,493 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-28 12:50:50,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6971 states and 10045 transitions. [2018-11-28 12:50:50,511 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6794 [2018-11-28 12:50:50,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:50,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:50,513 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:50,513 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:50,513 INFO L794 eck$LassoCheckResult]: Stem: 80755#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 80756#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 81638#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81679#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 80449#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80450#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81227#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80999#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81000#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81363#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81364#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82097#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 80869#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 80567#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 80568#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 81060#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 81061#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 81660#L969-1 assume !(0 == ~M_E~0); 81385#L1281-1 assume !(0 == ~T1_E~0); 81386#L1286-1 assume !(0 == ~T2_E~0); 82108#L1291-1 assume !(0 == ~T3_E~0); 80879#L1296-1 assume !(0 == ~T4_E~0); 80588#L1301-1 assume !(0 == ~T5_E~0); 80589#L1306-1 assume !(0 == ~T6_E~0); 81079#L1311-1 assume !(0 == ~T7_E~0); 80935#L1316-1 assume !(0 == ~T8_E~0); 80936#L1321-1 assume !(0 == ~T9_E~0); 81471#L1326-1 assume !(0 == ~T10_E~0); 81472#L1331-1 assume !(0 == ~T11_E~0); 81897#L1336-1 assume !(0 == ~T12_E~0); 80716#L1341-1 assume !(0 == ~T13_E~0); 80530#L1346-1 assume !(0 == ~E_M~0); 80531#L1351-1 assume !(0 == ~E_1~0); 81024#L1356-1 assume !(0 == ~E_2~0); 81025#L1361-1 assume !(0 == ~E_3~0); 81558#L1366-1 assume !(0 == ~E_4~0); 81452#L1371-1 assume !(0 == ~E_5~0); 81453#L1376-1 assume !(0 == ~E_6~0); 82013#L1381-1 assume !(0 == ~E_7~0); 80614#L1386-1 assume !(0 == ~E_8~0); 80229#L1391-1 assume !(0 == ~E_9~0); 80230#L1396-1 assume !(0 == ~E_10~0); 81160#L1401-1 assume !(0 == ~E_11~0); 81161#L1406-1 assume !(0 == ~E_12~0); 81492#L1411-1 assume !(0 == ~E_13~0); 81493#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 82114#L630 assume !(1 == ~m_pc~0); 82110#L630-2 is_master_triggered_~__retres1~0 := 0; 80560#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 80280#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 80281#L1593 assume !(0 != activate_threads_~tmp~1); 82287#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81263#L649 assume !(1 == ~t1_pc~0); 81221#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 81220#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81656#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81657#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 81849#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81855#L668 assume !(1 == ~t2_pc~0); 82292#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 80889#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 80854#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 80437#L1609 assume !(0 != activate_threads_~tmp___1~0); 80438#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 80215#L687 assume !(1 == ~t3_pc~0); 80195#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 80196#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 80902#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 80995#L1617 assume !(0 != activate_threads_~tmp___2~0); 81197#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81200#L706 assume 1 == ~t4_pc~0; 81520#L707 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 81524#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 82065#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 81728#L1625 assume !(0 != activate_threads_~tmp___3~0); 81729#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 80689#L725 assume !(1 == ~t5_pc~0); 80664#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 80665#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81202#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 81278#L1633 assume !(0 != activate_threads_~tmp___4~0); 81419#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 81427#L744 assume 1 == ~t6_pc~0; 81737#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 81739#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 82217#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 82092#L1641 assume !(0 != activate_threads_~tmp___5~0); 82093#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 81969#L763 assume 1 == ~t7_pc~0; 81860#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 80294#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 80209#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 80210#L1649 assume !(0 != activate_threads_~tmp___6~0); 80859#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 80864#L782 assume !(1 == ~t8_pc~0); 81066#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 81065#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 81528#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 80363#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 80364#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 80375#L801 assume 1 == ~t9_pc~0; 82153#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 80865#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 80682#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 80683#L1665 assume !(0 != activate_threads_~tmp___8~0); 81168#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 80390#L820 assume !(1 == ~t10_pc~0); 80391#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 80394#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 81001#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 81676#L1673 assume !(0 != activate_threads_~tmp___9~0); 81677#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 81633#L839 assume 1 == ~t11_pc~0; 81432#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 81433#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 81962#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 81963#L1681 assume !(0 != activate_threads_~tmp___10~0); 82293#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 80806#L858 assume !(1 == ~t12_pc~0); 80741#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 80742#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 81229#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 81230#L1689 assume !(0 != activate_threads_~tmp___11~0); 81838#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 81684#L877 assume !(1 == ~t13_pc~0); 81686#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 81691#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 82200#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 80446#L1697 assume !(0 != activate_threads_~tmp___12~0); 80447#L1697-2 assume !(1 == ~M_E~0); 80448#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80516#L1434-1 assume !(1 == ~T2_E~0); 80517#L1439-1 assume !(1 == ~T3_E~0); 81011#L1444-1 assume !(1 == ~T4_E~0); 81012#L1449-1 assume !(1 == ~T5_E~0); 81548#L1454-1 assume !(1 == ~T6_E~0); 81447#L1459-1 assume !(1 == ~T7_E~0); 81448#L1464-1 assume !(1 == ~T8_E~0); 82032#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 80643#L1474-1 assume !(1 == ~T10_E~0); 80265#L1479-1 assume !(1 == ~T11_E~0); 80266#L1484-1 assume !(1 == ~T12_E~0); 81166#L1489-1 assume !(1 == ~T13_E~0); 81167#L1494-1 assume !(1 == ~E_M~0); 81515#L1499-1 assume !(1 == ~E_1~0); 81516#L1504-1 assume !(1 == ~E_2~0); 82086#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 81980#L1514-1 assume !(1 == ~E_4~0); 80773#L1519-1 assume !(1 == ~E_5~0); 80414#L1524-1 assume !(1 == ~E_6~0); 80415#L1529-1 assume !(1 == ~E_7~0); 80923#L1534-1 assume !(1 == ~E_8~0); 80924#L1539-1 assume !(1 == ~E_9~0); 81615#L1544-1 assume !(1 == ~E_10~0); 81616#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 82055#L1554-1 assume !(1 == ~E_12~0); 80818#L1559-1 assume !(1 == ~E_13~0); 80586#L1930-1 [2018-11-28 12:50:50,513 INFO L796 eck$LassoCheckResult]: Loop: 80586#L1930-1 assume !false; 80909#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 80243#L1256 assume !false; 80453#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 82121#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 80491#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 81643#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 81644#L1069 assume !(0 != eval_~tmp~0); 81002#L1271 start_simulation_~kernel_st~0 := 2; 81003#L897-1 start_simulation_~kernel_st~0 := 3; 81387#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 81368#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 81369#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82101#L1291-3 assume !(0 == ~T3_E~0); 80871#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 80593#L1301-3 assume !(0 == ~T5_E~0); 80594#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81092#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 80941#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 80942#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 81476#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 81477#L1331-3 assume !(0 == ~T11_E~0); 81906#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 80720#L1341-3 assume !(0 == ~T13_E~0); 80535#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 80536#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 81169#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 81170#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81535#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81445#L1371-3 assume !(0 == ~E_5~0); 81446#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 82022#L1381-3 assume !(0 == ~E_7~0); 80624#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 80239#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 80240#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 81163#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 81164#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 81502#L1411-3 assume !(0 == ~E_13~0); 81503#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81874#L630-45 assume !(1 == ~m_pc~0); 81875#L630-47 is_master_triggered_~__retres1~0 := 0; 80508#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 80219#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 80220#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 82170#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81086#L649-45 assume !(1 == ~t1_pc~0); 81088#L649-47 is_transmit1_triggered_~__retres1~1 := 0; 81093#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81543#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 80826#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 80827#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 80831#L668-45 assume !(1 == ~t2_pc~0); 82195#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 80872#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 80873#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 86870#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 86869#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86868#L687-45 assume !(1 == ~t3_pc~0); 86867#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 86865#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86864#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 85983#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 81237#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81238#L706-45 assume 1 == ~t4_pc~0; 81581#L707-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 81582#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 82109#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 81796#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 81797#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 80758#L725-45 assume !(1 == ~t5_pc~0); 80759#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 80762#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81184#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 81248#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 81465#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 81466#L744-45 assume 1 == ~t6_pc~0; 81817#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 81788#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 82204#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 82123#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 82124#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 82016#L763-45 assume !(1 == ~t7_pc~0); 82017#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 80237#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 80238#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 80410#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 80602#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 80606#L782-45 assume !(1 == ~t8_pc~0); 81023#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 81026#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 81501#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 81292#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 81293#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 81296#L801-45 assume 1 == ~t9_pc~0; 82129#L802-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 80712#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 80618#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 80619#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 80910#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 80911#L820-45 assume 1 == ~t10_pc~0; 81309#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 80967#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 80968#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 81541#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 81542#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 81406#L839-45 assume 1 == ~t11_pc~0; 81376#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 81377#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 81887#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 81888#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 82162#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 80462#L858-45 assume 1 == ~t12_pc~0; 80464#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 80465#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 81108#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 81109#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 81978#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 81756#L877-45 assume !(1 == ~t13_pc~0); 81645#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 81646#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 82242#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 80502#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 80503#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 80509#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80525#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80526#L1439-3 assume !(1 == ~T3_E~0); 81020#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81021#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81724#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86877#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86875#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86873#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 80656#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 80227#L1479-3 assume !(1 == ~T11_E~0); 80228#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81158#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 81159#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81488#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81489#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82090#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81985#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80780#L1519-3 assume !(1 == ~E_5~0); 80419#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 80420#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 80927#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 80928#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 81624#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 81625#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 82062#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 80814#L1559-3 assume !(1 == ~E_13~0); 80454#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 80455#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 80494#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 81639#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 81640#L1949 assume !(0 == start_simulation_~tmp~3); 82198#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 82116#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 80497#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 81641#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 81642#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 80823#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 80808#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 80585#L1962 assume !(0 != start_simulation_~tmp___0~1); 80586#L1930-1 [2018-11-28 12:50:50,514 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:50,514 INFO L82 PathProgramCache]: Analyzing trace with hash -1359372432, now seen corresponding path program 1 times [2018-11-28 12:50:50,514 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:50,514 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:50,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:50,515 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:50,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:50,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:50,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:50,584 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:50,585 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:50,585 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:50,585 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:50,585 INFO L82 PathProgramCache]: Analyzing trace with hash -1470651080, now seen corresponding path program 1 times [2018-11-28 12:50:50,585 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:50,585 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:50,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:50,586 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:50,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:50,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:50,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:50,654 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:50,654 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:50:50,654 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:50,655 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:50,655 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:50,655 INFO L87 Difference]: Start difference. First operand 6971 states and 10045 transitions. cyclomatic complexity: 3078 Second operand 3 states. [2018-11-28 12:50:50,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:50,891 INFO L93 Difference]: Finished difference Result 13324 states and 19112 transitions. [2018-11-28 12:50:50,891 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:50,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13324 states and 19112 transitions. [2018-11-28 12:50:50,939 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13132 [2018-11-28 12:50:50,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13324 states to 13324 states and 19112 transitions. [2018-11-28 12:50:50,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13324 [2018-11-28 12:50:50,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13324 [2018-11-28 12:50:50,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13324 states and 19112 transitions. [2018-11-28 12:50:50,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:50,999 INFO L705 BuchiCegarLoop]: Abstraction has 13324 states and 19112 transitions. [2018-11-28 12:50:51,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13324 states and 19112 transitions. [2018-11-28 12:50:51,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13324 to 13316. [2018-11-28 12:50:51,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13316 states. [2018-11-28 12:50:51,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13316 states to 13316 states and 19104 transitions. [2018-11-28 12:50:51,172 INFO L728 BuchiCegarLoop]: Abstraction has 13316 states and 19104 transitions. [2018-11-28 12:50:51,172 INFO L608 BuchiCegarLoop]: Abstraction has 13316 states and 19104 transitions. [2018-11-28 12:50:51,172 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-28 12:50:51,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13316 states and 19104 transitions. [2018-11-28 12:50:51,212 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13124 [2018-11-28 12:50:51,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:51,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:51,214 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:51,215 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:51,215 INFO L794 eck$LassoCheckResult]: Stem: 101062#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 101063#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 101964#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 102002#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 100753#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100754#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101529#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101302#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101303#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 101667#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 101668#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 102421#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 101176#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 100875#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 100876#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 101365#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 101366#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 101985#L969-1 assume !(0 == ~M_E~0); 101687#L1281-1 assume !(0 == ~T1_E~0); 101688#L1286-1 assume !(0 == ~T2_E~0); 102430#L1291-1 assume !(0 == ~T3_E~0); 101185#L1296-1 assume !(0 == ~T4_E~0); 100895#L1301-1 assume !(0 == ~T5_E~0); 100896#L1306-1 assume !(0 == ~T6_E~0); 101384#L1311-1 assume !(0 == ~T7_E~0); 101240#L1316-1 assume !(0 == ~T8_E~0); 101241#L1321-1 assume !(0 == ~T9_E~0); 101774#L1326-1 assume !(0 == ~T10_E~0); 101775#L1331-1 assume !(0 == ~T11_E~0); 102218#L1336-1 assume !(0 == ~T12_E~0); 101023#L1341-1 assume !(0 == ~T13_E~0); 100834#L1346-1 assume !(0 == ~E_M~0); 100835#L1351-1 assume !(0 == ~E_1~0); 101328#L1356-1 assume !(0 == ~E_2~0); 101329#L1361-1 assume !(0 == ~E_3~0); 101859#L1366-1 assume !(0 == ~E_4~0); 101755#L1371-1 assume !(0 == ~E_5~0); 101756#L1376-1 assume !(0 == ~E_6~0); 102336#L1381-1 assume !(0 == ~E_7~0); 100921#L1386-1 assume !(0 == ~E_8~0); 100533#L1391-1 assume !(0 == ~E_9~0); 100534#L1396-1 assume !(0 == ~E_10~0); 101462#L1401-1 assume !(0 == ~E_11~0); 101463#L1406-1 assume !(0 == ~E_12~0); 101793#L1411-1 assume !(0 == ~E_13~0); 101794#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 102438#L630 assume !(1 == ~m_pc~0); 102432#L630-2 is_master_triggered_~__retres1~0 := 0; 100866#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 100584#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 100585#L1593 assume !(0 != activate_threads_~tmp~1); 102613#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 101564#L649 assume !(1 == ~t1_pc~0); 101523#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 101522#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 101981#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 101982#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 102171#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 102177#L668 assume !(1 == ~t2_pc~0); 102622#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 101194#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 101163#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 100740#L1609 assume !(0 != activate_threads_~tmp___1~0); 100741#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 100519#L687 assume !(1 == ~t3_pc~0); 100499#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 100500#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 101206#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 101299#L1617 assume !(0 != activate_threads_~tmp___2~0); 101499#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 101502#L706 assume !(1 == ~t4_pc~0); 101820#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 101823#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 102388#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 102048#L1625 assume !(0 != activate_threads_~tmp___3~0); 102049#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 100996#L725 assume !(1 == ~t5_pc~0); 100971#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 100972#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 101504#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 101581#L1633 assume !(0 != activate_threads_~tmp___4~0); 101721#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 101729#L744 assume 1 == ~t6_pc~0; 102059#L745 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 102061#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 102541#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 102416#L1641 assume !(0 != activate_threads_~tmp___5~0); 102417#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 102290#L763 assume 1 == ~t7_pc~0; 102182#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 100598#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 100513#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 100514#L1649 assume !(0 != activate_threads_~tmp___6~0); 101166#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 101171#L782 assume !(1 == ~t8_pc~0); 101371#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 101370#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 101826#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 100667#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 100668#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 100679#L801 assume 1 == ~t9_pc~0; 102479#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 101172#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 100989#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 100990#L1665 assume !(0 != activate_threads_~tmp___8~0); 101469#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 100694#L820 assume !(1 == ~t10_pc~0); 100695#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 100698#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 101304#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 101999#L1673 assume !(0 != activate_threads_~tmp___9~0); 102000#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 101954#L839 assume 1 == ~t11_pc~0; 101734#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 101735#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 102283#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 102284#L1681 assume !(0 != activate_threads_~tmp___10~0); 102623#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 101115#L858 assume !(1 == ~t12_pc~0); 101048#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 101049#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 101531#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 101532#L1689 assume !(0 != activate_threads_~tmp___11~0); 102160#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 102007#L877 assume !(1 == ~t13_pc~0); 102009#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 102014#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 102524#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 100750#L1697 assume !(0 != activate_threads_~tmp___12~0); 100751#L1697-2 assume !(1 == ~M_E~0); 100752#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100820#L1434-1 assume !(1 == ~T2_E~0); 100821#L1439-1 assume !(1 == ~T3_E~0); 101315#L1444-1 assume !(1 == ~T4_E~0); 101316#L1449-1 assume !(1 == ~T5_E~0); 101849#L1454-1 assume !(1 == ~T6_E~0); 101749#L1459-1 assume !(1 == ~T7_E~0); 101750#L1464-1 assume !(1 == ~T8_E~0); 102355#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100950#L1474-1 assume !(1 == ~T10_E~0); 100569#L1479-1 assume !(1 == ~T11_E~0); 100570#L1484-1 assume !(1 == ~T12_E~0); 101467#L1489-1 assume !(1 == ~T13_E~0); 101468#L1494-1 assume !(1 == ~E_M~0); 101814#L1499-1 assume !(1 == ~E_1~0); 101815#L1504-1 assume !(1 == ~E_2~0); 102408#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 102302#L1514-1 assume !(1 == ~E_4~0); 101080#L1519-1 assume !(1 == ~E_5~0); 100718#L1524-1 assume !(1 == ~E_6~0); 100719#L1529-1 assume !(1 == ~E_7~0); 101227#L1534-1 assume !(1 == ~E_8~0); 101228#L1539-1 assume !(1 == ~E_9~0); 101922#L1544-1 assume !(1 == ~E_10~0); 101923#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 102376#L1554-1 assume !(1 == ~E_12~0); 101126#L1559-1 assume !(1 == ~E_13~0); 100893#L1930-1 [2018-11-28 12:50:51,216 INFO L796 eck$LassoCheckResult]: Loop: 100893#L1930-1 assume !false; 101213#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 100549#L1256 assume !false; 100757#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 102444#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 100795#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 101969#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 101970#L1069 assume !(0 != eval_~tmp~0); 102399#L1271 start_simulation_~kernel_st~0 := 2; 113460#L897-1 start_simulation_~kernel_st~0 := 3; 113458#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 113456#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 113454#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 113452#L1291-3 assume !(0 == ~T3_E~0); 113450#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 113448#L1301-3 assume !(0 == ~T5_E~0); 113446#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 113444#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 113442#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 113440#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 113438#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 113436#L1331-3 assume !(0 == ~T11_E~0); 113434#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 113432#L1341-3 assume !(0 == ~T13_E~0); 113430#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 113428#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 113426#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 113424#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 113422#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 113420#L1371-3 assume !(0 == ~E_5~0); 113418#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 113416#L1381-3 assume !(0 == ~E_7~0); 113414#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 113412#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 113410#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 113408#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 113406#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 113404#L1411-3 assume !(0 == ~E_13~0); 113402#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 113400#L630-45 assume !(1 == ~m_pc~0); 113398#L630-47 is_master_triggered_~__retres1~0 := 0; 113395#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 113393#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 113391#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 113390#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 113389#L649-45 assume 1 == ~t1_pc~0; 113387#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 113386#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 113385#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 113384#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 101139#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 101140#L668-45 assume !(1 == ~t2_pc~0); 102496#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 101179#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 101004#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 100817#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 100818#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 100615#L687-45 assume !(1 == ~t3_pc~0); 100617#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 100624#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 101307#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 113468#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 113467#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 101913#L706-45 assume !(1 == ~t4_pc~0); 101887#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 101888#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 102431#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 102119#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 102120#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 101065#L725-45 assume !(1 == ~t5_pc~0); 101066#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 101070#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 101486#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 101548#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 101768#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 101769#L744-45 assume 1 == ~t6_pc~0; 102140#L745-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 102111#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 102528#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 102446#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 102447#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 102337#L763-45 assume 1 == ~t7_pc~0; 102339#L764-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 100539#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 100540#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 100714#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 100908#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 100912#L782-45 assume !(1 == ~t8_pc~0); 101327#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 101330#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 101800#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 101801#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 112408#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 112409#L801-45 assume !(1 == ~t9_pc~0); 112403#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 112402#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 112401#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 112400#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 112399#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 112398#L820-45 assume !(1 == ~t10_pc~0); 112397#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 112395#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 112394#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 112393#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 101845#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 101708#L839-45 assume !(1 == ~t11_pc~0); 101680#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 101679#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 102207#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 102208#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 102488#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 100766#L858-45 assume 1 == ~t12_pc~0; 100768#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 100769#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 101410#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 101411#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 102300#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 102078#L877-45 assume !(1 == ~t13_pc~0); 102080#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 102608#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 102570#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 100806#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 100807#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 100813#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100829#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100830#L1439-3 assume !(1 == ~T3_E~0); 101324#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101325#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101856#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101751#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101752#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 102358#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100962#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100527#L1479-3 assume !(1 == ~T11_E~0); 100528#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 101459#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 101460#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101788#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101789#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 102412#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 102307#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101088#L1519-3 assume !(1 == ~E_5~0); 100722#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100723#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101230#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101231#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 101931#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 101932#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 102385#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 101122#L1559-3 assume !(1 == ~E_13~0); 100758#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 100759#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 100798#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 101965#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 101966#L1949 assume !(0 == start_simulation_~tmp~3); 102522#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 102439#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 100801#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 101967#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 101968#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 101131#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 101117#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 100892#L1962 assume !(0 != start_simulation_~tmp___0~1); 100893#L1930-1 [2018-11-28 12:50:51,216 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:51,216 INFO L82 PathProgramCache]: Analyzing trace with hash 1450354673, now seen corresponding path program 1 times [2018-11-28 12:50:51,216 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:51,216 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:51,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:51,217 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:51,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:51,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:51,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:51,289 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:51,290 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:51,290 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:51,290 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:51,290 INFO L82 PathProgramCache]: Analyzing trace with hash 858403318, now seen corresponding path program 1 times [2018-11-28 12:50:51,290 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:51,291 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:51,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:51,291 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:51,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:51,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:51,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:51,366 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:51,366 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:50:51,367 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:51,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:51,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:51,367 INFO L87 Difference]: Start difference. First operand 13316 states and 19104 transitions. cyclomatic complexity: 5796 Second operand 3 states. [2018-11-28 12:50:51,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:51,607 INFO L93 Difference]: Finished difference Result 25575 states and 36545 transitions. [2018-11-28 12:50:51,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:51,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25575 states and 36545 transitions. [2018-11-28 12:50:51,781 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25344 [2018-11-28 12:50:51,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25575 states to 25575 states and 36545 transitions. [2018-11-28 12:50:51,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25575 [2018-11-28 12:50:51,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25575 [2018-11-28 12:50:51,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25575 states and 36545 transitions. [2018-11-28 12:50:51,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:51,871 INFO L705 BuchiCegarLoop]: Abstraction has 25575 states and 36545 transitions. [2018-11-28 12:50:51,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25575 states and 36545 transitions. [2018-11-28 12:50:52,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25575 to 25559. [2018-11-28 12:50:52,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25559 states. [2018-11-28 12:50:52,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25559 states to 25559 states and 36529 transitions. [2018-11-28 12:50:52,118 INFO L728 BuchiCegarLoop]: Abstraction has 25559 states and 36529 transitions. [2018-11-28 12:50:52,118 INFO L608 BuchiCegarLoop]: Abstraction has 25559 states and 36529 transitions. [2018-11-28 12:50:52,118 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-28 12:50:52,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25559 states and 36529 transitions. [2018-11-28 12:50:52,184 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25328 [2018-11-28 12:50:52,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:52,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:52,185 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:52,185 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:52,186 INFO L794 eck$LassoCheckResult]: Stem: 139979#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 139980#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 140919#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 140962#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 139660#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 139661#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 140470#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 140229#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 140230#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 140622#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 140623#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 141438#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 140099#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 139787#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 139788#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 140292#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 140293#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 140943#L969-1 assume !(0 == ~M_E~0); 140643#L1281-1 assume !(0 == ~T1_E~0); 140644#L1286-1 assume !(0 == ~T2_E~0); 141448#L1291-1 assume !(0 == ~T3_E~0); 140108#L1296-1 assume !(0 == ~T4_E~0); 139808#L1301-1 assume !(0 == ~T5_E~0); 139809#L1306-1 assume !(0 == ~T6_E~0); 140312#L1311-1 assume !(0 == ~T7_E~0); 140163#L1316-1 assume !(0 == ~T8_E~0); 140164#L1321-1 assume !(0 == ~T9_E~0); 140737#L1326-1 assume !(0 == ~T10_E~0); 140738#L1331-1 assume !(0 == ~T11_E~0); 141221#L1336-1 assume !(0 == ~T12_E~0); 139939#L1341-1 assume !(0 == ~T13_E~0); 139743#L1346-1 assume !(0 == ~E_M~0); 139744#L1351-1 assume !(0 == ~E_1~0); 140256#L1356-1 assume !(0 == ~E_2~0); 140257#L1361-1 assume !(0 == ~E_3~0); 140827#L1366-1 assume !(0 == ~E_4~0); 140717#L1371-1 assume !(0 == ~E_5~0); 140718#L1376-1 assume !(0 == ~E_6~0); 141343#L1381-1 assume !(0 == ~E_7~0); 139835#L1386-1 assume !(0 == ~E_8~0); 139433#L1391-1 assume !(0 == ~E_9~0); 139434#L1396-1 assume !(0 == ~E_10~0); 140399#L1401-1 assume !(0 == ~E_11~0); 140400#L1406-1 assume !(0 == ~E_12~0); 140758#L1411-1 assume !(0 == ~E_13~0); 140759#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 141458#L630 assume !(1 == ~m_pc~0); 141449#L630-2 is_master_triggered_~__retres1~0 := 0; 139777#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 139485#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 139486#L1593 assume !(0 != activate_threads_~tmp~1); 141638#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 140508#L649 assume !(1 == ~t1_pc~0); 140464#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 140463#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 140939#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 140940#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 141171#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 141178#L668 assume !(1 == ~t2_pc~0); 141647#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 140117#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 140085#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 139648#L1609 assume !(0 != activate_threads_~tmp___1~0); 139649#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 139419#L687 assume !(1 == ~t3_pc~0); 139399#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 139400#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 140129#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 140226#L1617 assume !(0 != activate_threads_~tmp___2~0); 140441#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 140444#L706 assume !(1 == ~t4_pc~0); 140787#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 140790#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 141403#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 141009#L1625 assume !(0 != activate_threads_~tmp___3~0); 141010#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 139912#L725 assume !(1 == ~t5_pc~0); 139886#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 139887#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 140445#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 140526#L1633 assume !(0 != activate_threads_~tmp___4~0); 140683#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 140691#L744 assume !(1 == ~t6_pc~0); 141019#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 141020#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 141572#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 141432#L1641 assume !(0 != activate_threads_~tmp___5~0); 141433#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 141287#L763 assume 1 == ~t7_pc~0; 141183#L764 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 139498#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 139413#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 139414#L1649 assume !(0 != activate_threads_~tmp___6~0); 140088#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 140094#L782 assume !(1 == ~t8_pc~0); 140298#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 140297#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 140794#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 139567#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 139568#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 139579#L801 assume 1 == ~t9_pc~0; 141505#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 140095#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 139905#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 139906#L1665 assume !(0 != activate_threads_~tmp___8~0); 140409#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 139596#L820 assume !(1 == ~t10_pc~0); 139597#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 139600#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 140231#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 140958#L1673 assume !(0 != activate_threads_~tmp___9~0); 140959#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 140910#L839 assume 1 == ~t11_pc~0; 140696#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 140697#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 141280#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 141281#L1681 assume !(0 != activate_threads_~tmp___10~0); 141648#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 140032#L858 assume !(1 == ~t12_pc~0); 139964#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 139965#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 140472#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 140473#L1689 assume !(0 != activate_threads_~tmp___11~0); 141159#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 140967#L877 assume !(1 == ~t13_pc~0); 140969#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 140974#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 141555#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 139657#L1697 assume !(0 != activate_threads_~tmp___12~0); 139658#L1697-2 assume !(1 == ~M_E~0); 139659#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 139729#L1434-1 assume !(1 == ~T2_E~0); 139730#L1439-1 assume !(1 == ~T3_E~0); 140243#L1444-1 assume !(1 == ~T4_E~0); 140244#L1449-1 assume !(1 == ~T5_E~0); 140814#L1454-1 assume !(1 == ~T6_E~0); 140711#L1459-1 assume !(1 == ~T7_E~0); 140712#L1464-1 assume !(1 == ~T8_E~0); 141367#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 139867#L1474-1 assume !(1 == ~T10_E~0); 139471#L1479-1 assume !(1 == ~T11_E~0); 139472#L1484-1 assume !(1 == ~T12_E~0); 140407#L1489-1 assume !(1 == ~T13_E~0); 140408#L1494-1 assume !(1 == ~E_M~0); 140783#L1499-1 assume !(1 == ~E_1~0); 140784#L1504-1 assume !(1 == ~E_2~0); 141424#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 141301#L1514-1 assume !(1 == ~E_4~0); 139998#L1519-1 assume !(1 == ~E_5~0); 139625#L1524-1 assume !(1 == ~E_6~0); 139626#L1529-1 assume !(1 == ~E_7~0); 140151#L1534-1 assume !(1 == ~E_8~0); 140152#L1539-1 assume !(1 == ~E_9~0); 140889#L1544-1 assume !(1 == ~E_10~0); 140890#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 141391#L1554-1 assume !(1 == ~E_12~0); 140043#L1559-1 assume !(1 == ~E_13~0); 140044#L1930-1 [2018-11-28 12:50:52,186 INFO L796 eck$LassoCheckResult]: Loop: 140044#L1930-1 assume !false; 152171#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 152166#L1256 assume !false; 152165#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 152156#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 152150#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 152149#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 152147#L1069 assume !(0 != eval_~tmp~0); 152148#L1271 start_simulation_~kernel_st~0 := 2; 152681#L897-1 start_simulation_~kernel_st~0 := 3; 152680#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 152679#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 152678#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 152677#L1291-3 assume !(0 == ~T3_E~0); 152676#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 152675#L1301-3 assume !(0 == ~T5_E~0); 152674#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 152673#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 152672#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 152671#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 152670#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 152669#L1331-3 assume !(0 == ~T11_E~0); 152668#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 152667#L1341-3 assume !(0 == ~T13_E~0); 152665#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 152663#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 152661#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 152659#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 152657#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 152655#L1371-3 assume !(0 == ~E_5~0); 152653#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 152650#L1381-3 assume !(0 == ~E_7~0); 152648#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 152646#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 152644#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 152642#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 152640#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 152638#L1411-3 assume !(0 == ~E_13~0); 152636#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 152634#L630-45 assume !(1 == ~m_pc~0); 152632#L630-47 is_master_triggered_~__retres1~0 := 0; 152630#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 152628#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 152625#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 152623#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 152621#L649-45 assume 1 == ~t1_pc~0; 152618#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 152616#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 152614#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 152612#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 152610#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 152608#L668-45 assume !(1 == ~t2_pc~0); 152606#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 152604#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 152601#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 152599#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 152597#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 152595#L687-45 assume 1 == ~t3_pc~0; 152592#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 152590#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 152588#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 152586#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 152584#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 152582#L706-45 assume !(1 == ~t4_pc~0); 152580#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 152578#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 152576#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 152573#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 152571#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 152569#L725-45 assume !(1 == ~t5_pc~0); 152566#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 152564#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 152562#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 152559#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 152557#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 152555#L744-45 assume !(1 == ~t6_pc~0); 152553#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 152551#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 152549#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 152546#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 152544#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 152542#L763-45 assume !(1 == ~t7_pc~0); 152539#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 152537#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 152535#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 152532#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 152530#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 152528#L782-45 assume !(1 == ~t8_pc~0); 152526#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 152523#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 152521#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 152518#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 152516#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 152514#L801-45 assume 1 == ~t9_pc~0; 152512#L802-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 152509#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 152507#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 152504#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 152502#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 152500#L820-45 assume !(1 == ~t10_pc~0); 152498#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 152495#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 152493#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 152490#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 152488#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 152486#L839-45 assume !(1 == ~t11_pc~0); 152483#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 152482#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 152478#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 152476#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 152471#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 152470#L858-45 assume 1 == ~t12_pc~0; 152468#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 152467#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 152466#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 152465#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 152464#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 152463#L877-45 assume !(1 == ~t13_pc~0); 152461#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 152460#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 152459#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 152458#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 152457#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 152456#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 152455#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152454#L1439-3 assume !(1 == ~T3_E~0); 152453#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 152452#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152451#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 152450#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 152449#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 152448#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 152447#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 152446#L1479-3 assume !(1 == ~T11_E~0); 152445#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 152444#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 152442#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 152440#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 152438#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 152436#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 152434#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 152432#L1519-3 assume !(1 == ~E_5~0); 152430#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 152427#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 152425#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 152423#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 152421#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 152419#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 152417#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 152415#L1559-3 assume !(1 == ~E_13~0); 152413#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 152403#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 152390#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 152388#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 152212#L1949 assume !(0 == start_simulation_~tmp~3); 152210#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 152198#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 152185#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 152183#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 152181#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 152179#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 152177#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 152173#L1962 assume !(0 != start_simulation_~tmp___0~1); 140044#L1930-1 [2018-11-28 12:50:52,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:52,186 INFO L82 PathProgramCache]: Analyzing trace with hash 1591454194, now seen corresponding path program 1 times [2018-11-28 12:50:52,187 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:52,187 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:52,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:52,187 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:52,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:52,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:52,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:52,248 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:52,248 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:52,249 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:52,249 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:52,249 INFO L82 PathProgramCache]: Analyzing trace with hash -1152309962, now seen corresponding path program 1 times [2018-11-28 12:50:52,249 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:52,249 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:52,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:52,250 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:52,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:52,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:52,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:52,316 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:52,316 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:50:52,317 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:52,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:52,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:52,317 INFO L87 Difference]: Start difference. First operand 25559 states and 36529 transitions. cyclomatic complexity: 10986 Second operand 3 states. [2018-11-28 12:50:52,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:52,533 INFO L93 Difference]: Finished difference Result 49190 states and 70038 transitions. [2018-11-28 12:50:52,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:52,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49190 states and 70038 transitions. [2018-11-28 12:50:52,659 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48864 [2018-11-28 12:50:52,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49190 states to 49190 states and 70038 transitions. [2018-11-28 12:50:52,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49190 [2018-11-28 12:50:52,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49190 [2018-11-28 12:50:52,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49190 states and 70038 transitions. [2018-11-28 12:50:52,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:52,809 INFO L705 BuchiCegarLoop]: Abstraction has 49190 states and 70038 transitions. [2018-11-28 12:50:52,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49190 states and 70038 transitions. [2018-11-28 12:50:53,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49190 to 49158. [2018-11-28 12:50:53,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49158 states. [2018-11-28 12:50:53,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49158 states to 49158 states and 70006 transitions. [2018-11-28 12:50:53,386 INFO L728 BuchiCegarLoop]: Abstraction has 49158 states and 70006 transitions. [2018-11-28 12:50:53,386 INFO L608 BuchiCegarLoop]: Abstraction has 49158 states and 70006 transitions. [2018-11-28 12:50:53,386 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-28 12:50:53,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49158 states and 70006 transitions. [2018-11-28 12:50:53,448 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48832 [2018-11-28 12:50:53,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:53,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:53,450 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:53,450 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:53,450 INFO L794 eck$LassoCheckResult]: Stem: 214735#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 214736#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 215659#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 215701#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 214415#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 214416#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 215211#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 214977#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 214978#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215360#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215361#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 216127#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 214849#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 214539#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 214540#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 215041#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 215042#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 215680#L969-1 assume !(0 == ~M_E~0); 215381#L1281-1 assume !(0 == ~T1_E~0); 215382#L1286-1 assume !(0 == ~T2_E~0); 216135#L1291-1 assume !(0 == ~T3_E~0); 214859#L1296-1 assume !(0 == ~T4_E~0); 214561#L1301-1 assume !(0 == ~T5_E~0); 214562#L1306-1 assume !(0 == ~T6_E~0); 215061#L1311-1 assume !(0 == ~T7_E~0); 214913#L1316-1 assume !(0 == ~T8_E~0); 214914#L1321-1 assume !(0 == ~T9_E~0); 215469#L1326-1 assume !(0 == ~T10_E~0); 215470#L1331-1 assume !(0 == ~T11_E~0); 215920#L1336-1 assume !(0 == ~T12_E~0); 214695#L1341-1 assume !(0 == ~T13_E~0); 214502#L1346-1 assume !(0 == ~E_M~0); 214503#L1351-1 assume !(0 == ~E_1~0); 215005#L1356-1 assume !(0 == ~E_2~0); 215006#L1361-1 assume !(0 == ~E_3~0); 215556#L1366-1 assume !(0 == ~E_4~0); 215450#L1371-1 assume !(0 == ~E_5~0); 215451#L1376-1 assume !(0 == ~E_6~0); 216042#L1381-1 assume !(0 == ~E_7~0); 214589#L1386-1 assume !(0 == ~E_8~0); 214191#L1391-1 assume !(0 == ~E_9~0); 214192#L1396-1 assume !(0 == ~E_10~0); 215141#L1401-1 assume !(0 == ~E_11~0); 215142#L1406-1 assume !(0 == ~E_12~0); 215489#L1411-1 assume !(0 == ~E_13~0); 215490#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 216141#L630 assume !(1 == ~m_pc~0); 216137#L630-2 is_master_triggered_~__retres1~0 := 0; 214532#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 214242#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 214243#L1593 assume !(0 != activate_threads_~tmp~1); 216318#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 215250#L649 assume !(1 == ~t1_pc~0); 215205#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 215204#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 215676#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 215677#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 215874#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 215880#L668 assume !(1 == ~t2_pc~0); 216323#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 214868#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 214835#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 214403#L1609 assume !(0 != activate_threads_~tmp___1~0); 214404#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 214177#L687 assume !(1 == ~t3_pc~0); 214157#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 214158#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 214880#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 214973#L1617 assume !(0 != activate_threads_~tmp___2~0); 215180#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 215184#L706 assume !(1 == ~t4_pc~0); 215517#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 215520#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 216095#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 215749#L1625 assume !(0 != activate_threads_~tmp___3~0); 215750#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 214664#L725 assume !(1 == ~t5_pc~0); 214639#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 214640#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 215186#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 215264#L1633 assume !(0 != activate_threads_~tmp___4~0); 215415#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 215423#L744 assume !(1 == ~t6_pc~0); 215758#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 215759#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 216246#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 216121#L1641 assume !(0 != activate_threads_~tmp___5~0); 216122#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 215992#L763 assume !(1 == ~t7_pc~0); 215962#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 214256#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 214171#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 214172#L1649 assume !(0 != activate_threads_~tmp___6~0); 214839#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 214844#L782 assume !(1 == ~t8_pc~0); 215047#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 215046#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 215525#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 214328#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 214329#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 214340#L801 assume 1 == ~t9_pc~0; 216182#L802 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 214845#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 214657#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 214658#L1665 assume !(0 != activate_threads_~tmp___8~0); 215150#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 214355#L820 assume !(1 == ~t10_pc~0); 214356#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 214359#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 214979#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 215696#L1673 assume !(0 != activate_threads_~tmp___9~0); 215697#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 215649#L839 assume 1 == ~t11_pc~0; 215428#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 215429#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 215985#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 215986#L1681 assume !(0 != activate_threads_~tmp___10~0); 216324#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 214786#L858 assume !(1 == ~t12_pc~0); 214721#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 214722#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 215213#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 215214#L1689 assume !(0 != activate_threads_~tmp___11~0); 215862#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 215706#L877 assume !(1 == ~t13_pc~0); 215708#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 215713#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 216229#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 214412#L1697 assume !(0 != activate_threads_~tmp___12~0); 214413#L1697-2 assume !(1 == ~M_E~0); 214414#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 214488#L1434-1 assume !(1 == ~T2_E~0); 214489#L1439-1 assume !(1 == ~T3_E~0); 214992#L1444-1 assume !(1 == ~T4_E~0); 214993#L1449-1 assume !(1 == ~T5_E~0); 215546#L1454-1 assume !(1 == ~T6_E~0); 215445#L1459-1 assume !(1 == ~T7_E~0); 215446#L1464-1 assume !(1 == ~T8_E~0); 216061#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 214618#L1474-1 assume !(1 == ~T10_E~0); 214227#L1479-1 assume !(1 == ~T11_E~0); 214228#L1484-1 assume !(1 == ~T12_E~0); 215148#L1489-1 assume !(1 == ~T13_E~0); 215149#L1494-1 assume !(1 == ~E_M~0); 215512#L1499-1 assume !(1 == ~E_1~0); 215513#L1504-1 assume !(1 == ~E_2~0); 216115#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 216004#L1514-1 assume !(1 == ~E_4~0); 214753#L1519-1 assume !(1 == ~E_5~0); 214381#L1524-1 assume !(1 == ~E_6~0); 214382#L1529-1 assume !(1 == ~E_7~0); 214900#L1534-1 assume !(1 == ~E_8~0); 214901#L1539-1 assume !(1 == ~E_9~0); 215619#L1544-1 assume !(1 == ~E_10~0); 215620#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 216085#L1554-1 assume !(1 == ~E_12~0); 214798#L1559-1 assume !(1 == ~E_13~0); 214799#L1930-1 [2018-11-28 12:50:53,451 INFO L796 eck$LassoCheckResult]: Loop: 214799#L1930-1 assume !false; 228389#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 228382#L1256 assume !false; 228377#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 228160#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 228153#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 228151#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 228148#L1069 assume !(0 != eval_~tmp~0); 228149#L1271 start_simulation_~kernel_st~0 := 2; 229006#L897-1 start_simulation_~kernel_st~0 := 3; 229003#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 229001#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 228999#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 228997#L1291-3 assume !(0 == ~T3_E~0); 228995#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 228993#L1301-3 assume !(0 == ~T5_E~0); 228990#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 228988#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 228986#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 228984#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 228982#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 228980#L1331-3 assume !(0 == ~T11_E~0); 228977#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 228975#L1341-3 assume !(0 == ~T13_E~0); 228973#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 228971#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 228969#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 228966#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 228964#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 228962#L1371-3 assume !(0 == ~E_5~0); 228960#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 228958#L1381-3 assume !(0 == ~E_7~0); 228957#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 228953#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 228951#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 228946#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 228942#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 228941#L1411-3 assume !(0 == ~E_13~0); 228940#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 228939#L630-45 assume !(1 == ~m_pc~0); 228938#L630-47 is_master_triggered_~__retres1~0 := 0; 228937#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 228936#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 228935#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 228934#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 228933#L649-45 assume 1 == ~t1_pc~0; 228931#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 228930#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 228929#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 228928#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 228927#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 228926#L668-45 assume !(1 == ~t2_pc~0); 228925#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 228924#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 228923#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 228922#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 228920#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 228918#L687-45 assume 1 == ~t3_pc~0; 228915#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 228913#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 228911#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 228909#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 228907#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 228904#L706-45 assume !(1 == ~t4_pc~0); 228902#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 228900#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 228898#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 228896#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 228894#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 228892#L725-45 assume !(1 == ~t5_pc~0); 228889#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 228887#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 228885#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 228883#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 228881#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 228878#L744-45 assume !(1 == ~t6_pc~0); 228876#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 228874#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 228872#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 228870#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 228868#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 228866#L763-45 assume !(1 == ~t7_pc~0); 228864#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 228862#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 228860#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 228858#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 228855#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 228853#L782-45 assume !(1 == ~t8_pc~0); 228851#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 228848#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 228846#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 228844#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 228842#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 228840#L801-45 assume 1 == ~t9_pc~0; 228838#L802-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 228835#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 228833#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 228831#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 228829#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 228827#L820-45 assume !(1 == ~t10_pc~0); 228825#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 228822#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 228820#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 228818#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 228816#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 228813#L839-45 assume 1 == ~t11_pc~0; 228811#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 228808#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 228806#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 228804#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 228802#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 228799#L858-45 assume !(1 == ~t12_pc~0); 228797#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 228794#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 228792#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 228790#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 228788#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 228785#L877-45 assume !(1 == ~t13_pc~0); 228782#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 228780#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 228778#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 228776#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 228774#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 228771#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 228769#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 228767#L1439-3 assume !(1 == ~T3_E~0); 228765#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 228763#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 228761#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 228760#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 228759#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 228758#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 228757#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 228756#L1479-3 assume !(1 == ~T11_E~0); 228755#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 228754#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 228753#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 228752#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 228751#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 228750#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 228749#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 228747#L1519-3 assume !(1 == ~E_5~0); 228745#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 228743#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 228741#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 228739#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 228737#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 228735#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 228732#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 228730#L1559-3 assume !(1 == ~E_13~0); 228728#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 228720#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 228707#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 228705#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 228453#L1949 assume !(0 == start_simulation_~tmp~3); 228451#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 228439#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 228427#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 228425#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 228423#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 228420#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 228418#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 228416#L1962 assume !(0 != start_simulation_~tmp___0~1); 214799#L1930-1 [2018-11-28 12:50:53,451 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:53,451 INFO L82 PathProgramCache]: Analyzing trace with hash -1565884237, now seen corresponding path program 1 times [2018-11-28 12:50:53,451 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:53,451 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:53,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:53,452 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:53,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:53,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:53,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:53,522 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:53,522 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:53,522 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:53,522 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:53,522 INFO L82 PathProgramCache]: Analyzing trace with hash -712230794, now seen corresponding path program 1 times [2018-11-28 12:50:53,522 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:53,523 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:53,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:53,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:53,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:53,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:53,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:53,590 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:53,591 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:50:53,591 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:53,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:53,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:53,591 INFO L87 Difference]: Start difference. First operand 49158 states and 70006 transitions. cyclomatic complexity: 20880 Second operand 3 states. [2018-11-28 12:50:53,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:53,872 INFO L93 Difference]: Finished difference Result 94661 states and 134323 transitions. [2018-11-28 12:50:53,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:53,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94661 states and 134323 transitions. [2018-11-28 12:50:54,100 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94112 [2018-11-28 12:50:54,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94661 states to 94661 states and 134323 transitions. [2018-11-28 12:50:54,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94661 [2018-11-28 12:50:54,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94661 [2018-11-28 12:50:54,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94661 states and 134323 transitions. [2018-11-28 12:50:54,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:54,391 INFO L705 BuchiCegarLoop]: Abstraction has 94661 states and 134323 transitions. [2018-11-28 12:50:54,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94661 states and 134323 transitions. [2018-11-28 12:50:54,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94661 to 94597. [2018-11-28 12:50:54,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94597 states. [2018-11-28 12:50:55,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94597 states to 94597 states and 134259 transitions. [2018-11-28 12:50:55,374 INFO L728 BuchiCegarLoop]: Abstraction has 94597 states and 134259 transitions. [2018-11-28 12:50:55,374 INFO L608 BuchiCegarLoop]: Abstraction has 94597 states and 134259 transitions. [2018-11-28 12:50:55,374 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-28 12:50:55,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94597 states and 134259 transitions. [2018-11-28 12:50:55,534 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94048 [2018-11-28 12:50:55,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:50:55,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:50:55,536 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:55,536 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:50:55,536 INFO L794 eck$LassoCheckResult]: Stem: 358547#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 358548#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 359463#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 359503#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 358240#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 358241#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 359024#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 358790#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 358791#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 359163#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 359164#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 359936#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 358663#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 358359#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 358360#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 358851#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 358852#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 359484#L969-1 assume !(0 == ~M_E~0); 359185#L1281-1 assume !(0 == ~T1_E~0); 359186#L1286-1 assume !(0 == ~T2_E~0); 359946#L1291-1 assume !(0 == ~T3_E~0); 358673#L1296-1 assume !(0 == ~T4_E~0); 358380#L1301-1 assume !(0 == ~T5_E~0); 358381#L1306-1 assume !(0 == ~T6_E~0); 358871#L1311-1 assume !(0 == ~T7_E~0); 358727#L1316-1 assume !(0 == ~T8_E~0); 358728#L1321-1 assume !(0 == ~T9_E~0); 359273#L1326-1 assume !(0 == ~T10_E~0); 359274#L1331-1 assume !(0 == ~T11_E~0); 359745#L1336-1 assume !(0 == ~T12_E~0); 358507#L1341-1 assume !(0 == ~T13_E~0); 358321#L1346-1 assume !(0 == ~E_M~0); 358322#L1351-1 assume !(0 == ~E_1~0); 358815#L1356-1 assume !(0 == ~E_2~0); 358816#L1361-1 assume !(0 == ~E_3~0); 359360#L1366-1 assume !(0 == ~E_4~0); 359254#L1371-1 assume !(0 == ~E_5~0); 359255#L1376-1 assume !(0 == ~E_6~0); 359857#L1381-1 assume !(0 == ~E_7~0); 358405#L1386-1 assume !(0 == ~E_8~0); 358019#L1391-1 assume !(0 == ~E_9~0); 358020#L1396-1 assume !(0 == ~E_10~0); 358948#L1401-1 assume !(0 == ~E_11~0); 358949#L1406-1 assume !(0 == ~E_12~0); 359293#L1411-1 assume !(0 == ~E_13~0); 359294#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 359952#L630 assume !(1 == ~m_pc~0); 359948#L630-2 is_master_triggered_~__retres1~0 := 0; 358352#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 358070#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 358071#L1593 assume !(0 != activate_threads_~tmp~1); 360116#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 359061#L649 assume !(1 == ~t1_pc~0); 359018#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 359017#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 359480#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 359481#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 359698#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 359705#L668 assume !(1 == ~t2_pc~0); 360121#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 358682#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 358649#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 358228#L1609 assume !(0 != activate_threads_~tmp___1~0); 358229#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 358005#L687 assume !(1 == ~t3_pc~0); 357985#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 357986#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 358694#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 358786#L1617 assume !(0 != activate_threads_~tmp___2~0); 358992#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 358995#L706 assume !(1 == ~t4_pc~0); 359321#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 359324#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 359907#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 359552#L1625 assume !(0 != activate_threads_~tmp___3~0); 359553#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 358481#L725 assume !(1 == ~t5_pc~0); 358456#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 358457#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 358997#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 359078#L1633 assume !(0 != activate_threads_~tmp___4~0); 359220#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 359228#L744 assume !(1 == ~t6_pc~0); 359561#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 359562#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 360053#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 359933#L1641 assume !(0 != activate_threads_~tmp___5~0); 359934#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 359808#L763 assume !(1 == ~t7_pc~0); 359781#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 358084#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 357999#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 358000#L1649 assume !(0 != activate_threads_~tmp___6~0); 358653#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 358658#L782 assume !(1 == ~t8_pc~0); 358858#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 358857#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 359328#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 358153#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 358154#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 358165#L801 assume !(1 == ~t9_pc~0); 360099#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 358659#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 358474#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 358475#L1665 assume !(0 != activate_threads_~tmp___8~0); 358959#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 358180#L820 assume !(1 == ~t10_pc~0); 358181#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 358184#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 358792#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 359498#L1673 assume !(0 != activate_threads_~tmp___9~0); 359499#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 359453#L839 assume 1 == ~t11_pc~0; 359233#L840 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 359234#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 359801#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 359802#L1681 assume !(0 != activate_threads_~tmp___10~0); 360122#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 358601#L858 assume !(1 == ~t12_pc~0); 358532#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 358533#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 359026#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 359027#L1689 assume !(0 != activate_threads_~tmp___11~0); 359685#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 359508#L877 assume !(1 == ~t13_pc~0); 359510#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 359515#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 360035#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 358237#L1697 assume !(0 != activate_threads_~tmp___12~0); 358238#L1697-2 assume !(1 == ~M_E~0); 358239#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 358307#L1434-1 assume !(1 == ~T2_E~0); 358308#L1439-1 assume !(1 == ~T3_E~0); 358802#L1444-1 assume !(1 == ~T4_E~0); 358803#L1449-1 assume !(1 == ~T5_E~0); 359350#L1454-1 assume !(1 == ~T6_E~0); 359248#L1459-1 assume !(1 == ~T7_E~0); 359249#L1464-1 assume !(1 == ~T8_E~0); 359877#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 358435#L1474-1 assume !(1 == ~T10_E~0); 358055#L1479-1 assume !(1 == ~T11_E~0); 358056#L1484-1 assume !(1 == ~T12_E~0); 358957#L1489-1 assume !(1 == ~T13_E~0); 358958#L1494-1 assume !(1 == ~E_M~0); 359316#L1499-1 assume !(1 == ~E_1~0); 359317#L1504-1 assume !(1 == ~E_2~0); 359927#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 359822#L1514-1 assume !(1 == ~E_4~0); 358566#L1519-1 assume !(1 == ~E_5~0); 358204#L1524-1 assume !(1 == ~E_6~0); 358205#L1529-1 assume !(1 == ~E_7~0); 358715#L1534-1 assume !(1 == ~E_8~0); 358716#L1539-1 assume !(1 == ~E_9~0); 359421#L1544-1 assume !(1 == ~E_10~0); 359422#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 359898#L1554-1 assume !(1 == ~E_12~0); 358613#L1559-1 assume !(1 == ~E_13~0); 358614#L1930-1 [2018-11-28 12:50:55,537 INFO L796 eck$LassoCheckResult]: Loop: 358614#L1930-1 assume !false; 368963#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 368885#L1256 assume !false; 368858#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 368540#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 368504#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 368162#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 368138#L1069 assume !(0 != eval_~tmp~0); 368139#L1271 start_simulation_~kernel_st~0 := 2; 369464#L897-1 start_simulation_~kernel_st~0 := 3; 369462#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 369460#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 369457#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 369455#L1291-3 assume !(0 == ~T3_E~0); 369453#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 369451#L1301-3 assume !(0 == ~T5_E~0); 369450#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 369449#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 369448#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 369447#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 369446#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 369445#L1331-3 assume !(0 == ~T11_E~0); 369444#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 369443#L1341-3 assume !(0 == ~T13_E~0); 369442#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 369441#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 369440#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 369439#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 369438#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 369437#L1371-3 assume !(0 == ~E_5~0); 369436#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 369435#L1381-3 assume !(0 == ~E_7~0); 369434#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 369433#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 369432#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 369430#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 369428#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 369426#L1411-3 assume !(0 == ~E_13~0); 369424#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 369422#L630-45 assume !(1 == ~m_pc~0); 369420#L630-47 is_master_triggered_~__retres1~0 := 0; 369418#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 369416#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 369414#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 369411#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 369409#L649-45 assume !(1 == ~t1_pc~0); 369407#L649-47 is_transmit1_triggered_~__retres1~1 := 0; 369404#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 369402#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 369400#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 369398#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 369396#L668-45 assume !(1 == ~t2_pc~0); 369394#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 369392#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 369390#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 369388#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 369385#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 369383#L687-45 assume !(1 == ~t3_pc~0); 369381#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 369378#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 369376#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 369374#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 369372#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 369370#L706-45 assume !(1 == ~t4_pc~0); 369368#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 369366#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 369364#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 369361#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 369359#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 369357#L725-45 assume !(1 == ~t5_pc~0); 369354#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 369352#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 369350#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 369348#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 369346#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 369344#L744-45 assume !(1 == ~t6_pc~0); 369342#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 369340#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 369338#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 369336#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 369333#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 369331#L763-45 assume !(1 == ~t7_pc~0); 369329#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 369327#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 369325#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 369323#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 369320#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 369318#L782-45 assume !(1 == ~t8_pc~0); 369316#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 369313#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 369311#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 369309#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 369307#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 369305#L801-45 assume !(1 == ~t9_pc~0); 369303#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 369301#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 369299#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 369297#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 369294#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 369292#L820-45 assume 1 == ~t10_pc~0; 369289#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 369287#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 369285#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 369283#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 369280#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 369278#L839-45 assume 1 == ~t11_pc~0; 369276#L840-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 369273#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 369271#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 369269#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 369268#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 369267#L858-45 assume 1 == ~t12_pc~0; 369265#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 369264#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 369263#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 369262#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 369261#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 369260#L877-45 assume !(1 == ~t13_pc~0); 369258#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 369257#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 369256#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 369255#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 369254#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 369253#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 369252#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 369250#L1439-3 assume !(1 == ~T3_E~0); 369248#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 369246#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 369244#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 369242#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 369240#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 369238#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 369235#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 369233#L1479-3 assume !(1 == ~T11_E~0); 369231#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 369229#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 369227#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 369225#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 369223#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 369221#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 369219#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 369217#L1519-3 assume !(1 == ~E_5~0); 369215#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 369213#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 369210#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 369208#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 369206#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 369204#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 369202#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 369200#L1559-3 assume !(1 == ~E_13~0); 369198#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 369189#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 369176#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 369174#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 369019#L1949 assume !(0 == start_simulation_~tmp~3); 369017#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 369005#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 368993#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 368990#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 368988#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 368986#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 368984#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 368983#L1962 assume !(0 != start_simulation_~tmp___0~1); 358614#L1930-1 [2018-11-28 12:50:55,537 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:55,537 INFO L82 PathProgramCache]: Analyzing trace with hash -1325616908, now seen corresponding path program 1 times [2018-11-28 12:50:55,537 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:55,537 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:55,538 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:55,538 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:55,538 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:55,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:55,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:55,607 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:55,607 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:50:55,607 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:50:55,607 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:50:55,608 INFO L82 PathProgramCache]: Analyzing trace with hash -364757163, now seen corresponding path program 1 times [2018-11-28 12:50:55,608 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:50:55,608 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:50:55,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:55,608 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:50:55,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:50:55,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:50:55,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:50:55,655 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:50:55,655 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:50:55,658 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:50:55,658 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:50:55,658 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:50:55,658 INFO L87 Difference]: Start difference. First operand 94597 states and 134259 transitions. cyclomatic complexity: 39726 Second operand 3 states. [2018-11-28 12:50:56,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:50:56,105 INFO L93 Difference]: Finished difference Result 182116 states and 257584 transitions. [2018-11-28 12:50:56,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:50:56,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 182116 states and 257584 transitions. [2018-11-28 12:50:56,559 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 181056 [2018-11-28 12:50:56,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 182116 states to 182116 states and 257584 transitions. [2018-11-28 12:50:56,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 182116 [2018-11-28 12:50:56,920 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 182116 [2018-11-28 12:50:56,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 182116 states and 257584 transitions. [2018-11-28 12:50:59,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:50:59,572 INFO L705 BuchiCegarLoop]: Abstraction has 182116 states and 257584 transitions. [2018-11-28 12:50:59,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182116 states and 257584 transitions. [2018-11-28 12:51:00,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182116 to 181988. [2018-11-28 12:51:00,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 181988 states. [2018-11-28 12:51:00,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181988 states to 181988 states and 257456 transitions. [2018-11-28 12:51:00,632 INFO L728 BuchiCegarLoop]: Abstraction has 181988 states and 257456 transitions. [2018-11-28 12:51:00,632 INFO L608 BuchiCegarLoop]: Abstraction has 181988 states and 257456 transitions. [2018-11-28 12:51:00,632 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-28 12:51:00,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 181988 states and 257456 transitions. [2018-11-28 12:51:00,974 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:00,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:00,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:00,975 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:00,975 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:00,975 INFO L794 eck$LassoCheckResult]: Stem: 635278#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 635279#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 636205#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 636247#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 634967#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 634968#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 635752#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 635523#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 635524#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 635885#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 635886#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 636696#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 635392#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 635093#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 635094#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 635584#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 635585#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 636228#L969-1 assume !(0 == ~M_E~0); 635910#L1281-1 assume !(0 == ~T1_E~0); 635911#L1286-1 assume !(0 == ~T2_E~0); 636705#L1291-1 assume !(0 == ~T3_E~0); 635403#L1296-1 assume !(0 == ~T4_E~0); 635112#L1301-1 assume !(0 == ~T5_E~0); 635113#L1306-1 assume !(0 == ~T6_E~0); 635603#L1311-1 assume !(0 == ~T7_E~0); 635459#L1316-1 assume !(0 == ~T8_E~0); 635460#L1321-1 assume !(0 == ~T9_E~0); 636002#L1326-1 assume !(0 == ~T10_E~0); 636003#L1331-1 assume !(0 == ~T11_E~0); 636485#L1336-1 assume !(0 == ~T12_E~0); 635239#L1341-1 assume !(0 == ~T13_E~0); 635050#L1346-1 assume !(0 == ~E_M~0); 635051#L1351-1 assume !(0 == ~E_1~0); 635548#L1356-1 assume !(0 == ~E_2~0); 635549#L1361-1 assume !(0 == ~E_3~0); 636092#L1366-1 assume !(0 == ~E_4~0); 635982#L1371-1 assume !(0 == ~E_5~0); 635983#L1376-1 assume !(0 == ~E_6~0); 636600#L1381-1 assume !(0 == ~E_7~0); 635137#L1386-1 assume !(0 == ~E_8~0); 634741#L1391-1 assume !(0 == ~E_9~0); 634742#L1396-1 assume !(0 == ~E_10~0); 635684#L1401-1 assume !(0 == ~E_11~0); 635685#L1406-1 assume !(0 == ~E_12~0); 636027#L1411-1 assume !(0 == ~E_13~0); 636028#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 636714#L630 assume !(1 == ~m_pc~0); 636706#L630-2 is_master_triggered_~__retres1~0 := 0; 635082#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 634793#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 634794#L1593 assume !(0 != activate_threads_~tmp~1); 636892#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 635788#L649 assume !(1 == ~t1_pc~0); 635745#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 635744#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 636224#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 636225#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 636439#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 636447#L668 assume !(1 == ~t2_pc~0); 636895#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 635411#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 635379#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 634954#L1609 assume !(0 != activate_threads_~tmp___1~0); 634955#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 634727#L687 assume !(1 == ~t3_pc~0); 634707#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 634708#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 635424#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 635518#L1617 assume !(0 != activate_threads_~tmp___2~0); 635722#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 635725#L706 assume !(1 == ~t4_pc~0); 636054#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 636057#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 636665#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 636295#L1625 assume !(0 != activate_threads_~tmp___3~0); 636296#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 635214#L725 assume !(1 == ~t5_pc~0); 635188#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 635189#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 635726#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 635800#L1633 assume !(0 != activate_threads_~tmp___4~0); 635948#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 635956#L744 assume !(1 == ~t6_pc~0); 636305#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 636306#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 636822#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 636691#L1641 assume !(0 != activate_threads_~tmp___5~0); 636692#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 636553#L763 assume !(1 == ~t7_pc~0); 636523#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 634806#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 634721#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 634722#L1649 assume !(0 != activate_threads_~tmp___6~0); 635382#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 635387#L782 assume !(1 == ~t8_pc~0); 635590#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 635589#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 636061#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 634875#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 634876#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 634887#L801 assume !(1 == ~t9_pc~0); 636871#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 635388#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 635206#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 635207#L1665 assume !(0 != activate_threads_~tmp___8~0); 635691#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 634903#L820 assume !(1 == ~t10_pc~0); 634904#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 634906#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 635525#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 636243#L1673 assume !(0 != activate_threads_~tmp___9~0); 636244#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 636193#L839 assume !(1 == ~t11_pc~0); 636194#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 636195#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 636545#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 636546#L1681 assume !(0 != activate_threads_~tmp___10~0); 636896#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 635330#L858 assume !(1 == ~t12_pc~0); 635264#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 635265#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 635753#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 635754#L1689 assume !(0 != activate_threads_~tmp___11~0); 636426#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 636254#L877 assume !(1 == ~t13_pc~0); 636256#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 636261#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 636805#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 634964#L1697 assume !(0 != activate_threads_~tmp___12~0); 634965#L1697-2 assume !(1 == ~M_E~0); 634966#L1429-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 635035#L1434-1 assume !(1 == ~T2_E~0); 635036#L1439-1 assume !(1 == ~T3_E~0); 635535#L1444-1 assume !(1 == ~T4_E~0); 635536#L1449-1 assume !(1 == ~T5_E~0); 636082#L1454-1 assume !(1 == ~T6_E~0); 635976#L1459-1 assume !(1 == ~T7_E~0); 635977#L1464-1 assume !(1 == ~T8_E~0); 636631#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 635171#L1474-1 assume !(1 == ~T10_E~0); 634781#L1479-1 assume !(1 == ~T11_E~0); 634782#L1484-1 assume !(1 == ~T12_E~0); 635689#L1489-1 assume !(1 == ~T13_E~0); 635690#L1494-1 assume !(1 == ~E_M~0); 636050#L1499-1 assume !(1 == ~E_1~0); 636051#L1504-1 assume !(1 == ~E_2~0); 636685#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 636564#L1514-1 assume !(1 == ~E_4~0); 635296#L1519-1 assume !(1 == ~E_5~0); 634930#L1524-1 assume !(1 == ~E_6~0); 634931#L1529-1 assume !(1 == ~E_7~0); 635446#L1534-1 assume !(1 == ~E_8~0); 635447#L1539-1 assume !(1 == ~E_9~0); 636166#L1544-1 assume !(1 == ~E_10~0); 636167#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 636655#L1554-1 assume !(1 == ~E_12~0); 635341#L1559-1 assume !(1 == ~E_13~0); 635342#L1930-1 [2018-11-28 12:51:00,975 INFO L796 eck$LassoCheckResult]: Loop: 635342#L1930-1 assume !false; 658512#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 658502#L1256 assume !false; 658496#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 658470#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 658463#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 658461#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 658458#L1069 assume !(0 != eval_~tmp~0); 658459#L1271 start_simulation_~kernel_st~0 := 2; 659958#L897-1 start_simulation_~kernel_st~0 := 3; 659957#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 659956#L1281-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 659955#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 659954#L1291-3 assume !(0 == ~T3_E~0); 659953#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 659952#L1301-3 assume !(0 == ~T5_E~0); 659951#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 659950#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 659949#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 659948#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 659947#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 659946#L1331-3 assume !(0 == ~T11_E~0); 659945#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 659944#L1341-3 assume !(0 == ~T13_E~0); 659943#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 659942#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 659941#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 659940#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 659939#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 659938#L1371-3 assume !(0 == ~E_5~0); 659937#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 659936#L1381-3 assume !(0 == ~E_7~0); 659935#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 659934#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 659933#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 659932#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 659931#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 659930#L1411-3 assume !(0 == ~E_13~0); 659929#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 659928#L630-45 assume !(1 == ~m_pc~0); 659927#L630-47 is_master_triggered_~__retres1~0 := 0; 659926#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 659925#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 659923#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 659921#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 659919#L649-45 assume 1 == ~t1_pc~0; 659916#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 659914#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 659912#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 659910#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 659907#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 659905#L668-45 assume !(1 == ~t2_pc~0); 659903#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 659901#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 659899#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 659897#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 659895#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 659893#L687-45 assume 1 == ~t3_pc~0; 659890#L688-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 659888#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 659886#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 659884#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 659881#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 659879#L706-45 assume !(1 == ~t4_pc~0); 659877#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 659875#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 659873#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 659871#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 659868#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 659865#L725-45 assume !(1 == ~t5_pc~0); 659861#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 659858#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 659855#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 659851#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 659848#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 659843#L744-45 assume !(1 == ~t6_pc~0); 659839#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 659835#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 659831#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 659827#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 659823#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 659819#L763-45 assume !(1 == ~t7_pc~0); 659814#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 659810#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 659805#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 659800#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 659795#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 659789#L782-45 assume !(1 == ~t8_pc~0); 659784#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 659778#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 659773#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 659767#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 659761#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 659756#L801-45 assume !(1 == ~t9_pc~0); 659750#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 659745#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 659740#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 659735#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 659729#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 659724#L820-45 assume 1 == ~t10_pc~0; 659718#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 659713#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 659708#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 659702#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 659696#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 659690#L839-45 assume !(1 == ~t11_pc~0); 659685#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 659680#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 659675#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 659670#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 659665#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 659660#L858-45 assume 1 == ~t12_pc~0; 659654#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 659649#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 659641#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 659634#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 659626#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 659618#L877-45 assume !(1 == ~t13_pc~0); 659610#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 659604#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 659598#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 659589#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 659583#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 659577#L1429-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 659570#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 659563#L1439-3 assume !(1 == ~T3_E~0); 659555#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 659548#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 659541#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 659533#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 659526#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 659519#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 659511#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 659502#L1479-3 assume !(1 == ~T11_E~0); 659495#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 659488#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 659480#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 659473#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 659466#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 659459#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 659453#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 659446#L1519-3 assume !(1 == ~E_5~0); 659440#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 659433#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 659424#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 659419#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 659414#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 659409#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 659403#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 659399#L1559-3 assume !(1 == ~E_13~0); 659397#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 659214#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 659198#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 659193#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 659187#L1949 assume !(0 == start_simulation_~tmp~3); 659185#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 658593#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 658546#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 658543#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 658541#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 658539#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 658537#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 658535#L1962 assume !(0 != start_simulation_~tmp___0~1); 635342#L1930-1 [2018-11-28 12:51:00,976 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:00,976 INFO L82 PathProgramCache]: Analyzing trace with hash 2095872693, now seen corresponding path program 1 times [2018-11-28 12:51:00,976 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:00,976 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:00,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:00,977 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:00,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:00,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:01,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:01,073 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:01,073 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:51:01,073 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:51:01,073 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:01,074 INFO L82 PathProgramCache]: Analyzing trace with hash -950472202, now seen corresponding path program 1 times [2018-11-28 12:51:01,074 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:01,074 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:01,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:01,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:01,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:01,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:01,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:01,162 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:01,162 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:01,163 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:01,163 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:51:01,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:51:01,163 INFO L87 Difference]: Start difference. First operand 181988 states and 257456 transitions. cyclomatic complexity: 75596 Second operand 3 states. [2018-11-28 12:51:01,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:01,845 INFO L93 Difference]: Finished difference Result 181988 states and 257070 transitions. [2018-11-28 12:51:01,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:51:01,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 181988 states and 257070 transitions. [2018-11-28 12:51:02,311 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:02,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 181988 states to 181988 states and 257070 transitions. [2018-11-28 12:51:02,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 181988 [2018-11-28 12:51:02,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 181988 [2018-11-28 12:51:02,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181988 states and 257070 transitions. [2018-11-28 12:51:02,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:02,757 INFO L705 BuchiCegarLoop]: Abstraction has 181988 states and 257070 transitions. [2018-11-28 12:51:02,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181988 states and 257070 transitions. [2018-11-28 12:51:04,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181988 to 181988. [2018-11-28 12:51:04,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 181988 states. [2018-11-28 12:51:04,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181988 states to 181988 states and 257070 transitions. [2018-11-28 12:51:04,404 INFO L728 BuchiCegarLoop]: Abstraction has 181988 states and 257070 transitions. [2018-11-28 12:51:04,404 INFO L608 BuchiCegarLoop]: Abstraction has 181988 states and 257070 transitions. [2018-11-28 12:51:04,404 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-28 12:51:04,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 181988 states and 257070 transitions. [2018-11-28 12:51:04,726 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:04,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:04,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:04,727 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:04,727 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:04,728 INFO L794 eck$LassoCheckResult]: Stem: 999259#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 999260#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1000183#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1000231#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 998949#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 998950#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 999733#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 999499#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 999500#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 999871#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 999872#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1000685#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 999374#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 999070#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 999071#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 999563#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 999564#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1000208#L969-1 assume !(0 == ~M_E~0); 999895#L1281-1 assume !(0 == ~T1_E~0); 999896#L1286-1 assume !(0 == ~T2_E~0); 1000696#L1291-1 assume !(0 == ~T3_E~0); 999383#L1296-1 assume !(0 == ~T4_E~0); 999091#L1301-1 assume !(0 == ~T5_E~0); 999092#L1306-1 assume !(0 == ~T6_E~0); 999582#L1311-1 assume !(0 == ~T7_E~0); 999437#L1316-1 assume !(0 == ~T8_E~0); 999438#L1321-1 assume !(0 == ~T9_E~0); 999989#L1326-1 assume !(0 == ~T10_E~0); 999990#L1331-1 assume !(0 == ~T11_E~0); 1000479#L1336-1 assume !(0 == ~T12_E~0); 999219#L1341-1 assume !(0 == ~T13_E~0); 999033#L1346-1 assume !(0 == ~E_M~0); 999034#L1351-1 assume !(0 == ~E_1~0); 999527#L1356-1 assume !(0 == ~E_2~0); 999528#L1361-1 assume !(0 == ~E_3~0); 1000076#L1366-1 assume !(0 == ~E_4~0); 999969#L1371-1 assume !(0 == ~E_5~0); 999970#L1376-1 assume !(0 == ~E_6~0); 1000595#L1381-1 assume !(0 == ~E_7~0); 999117#L1386-1 assume !(0 == ~E_8~0); 998726#L1391-1 assume !(0 == ~E_9~0); 998727#L1396-1 assume !(0 == ~E_10~0); 999662#L1401-1 assume !(0 == ~E_11~0); 999663#L1406-1 assume !(0 == ~E_12~0); 1000010#L1411-1 assume !(0 == ~E_13~0); 1000011#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1000702#L630 assume !(1 == ~m_pc~0); 1000698#L630-2 is_master_triggered_~__retres1~0 := 0; 999064#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 998777#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 998778#L1593 assume !(0 != activate_threads_~tmp~1); 1000877#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 999769#L649 assume !(1 == ~t1_pc~0); 999727#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 999726#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1000204#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1000205#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1000432#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1000439#L668 assume !(1 == ~t2_pc~0); 1000880#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 999392#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 999360#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 998936#L1609 assume !(0 != activate_threads_~tmp___1~0); 998937#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 998712#L687 assume !(1 == ~t3_pc~0); 998692#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 998693#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 999405#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 999495#L1617 assume !(0 != activate_threads_~tmp___2~0); 999702#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 999705#L706 assume !(1 == ~t4_pc~0); 1000038#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 1000041#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1000655#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1000277#L1625 assume !(0 != activate_threads_~tmp___3~0); 1000278#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 999194#L725 assume !(1 == ~t5_pc~0); 999169#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 999170#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 999707#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 999785#L1633 assume !(0 != activate_threads_~tmp___4~0); 999936#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 999944#L744 assume !(1 == ~t6_pc~0); 1000288#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 1000289#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1000803#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1000681#L1641 assume !(0 != activate_threads_~tmp___5~0); 1000682#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1000545#L763 assume !(1 == ~t7_pc~0); 1000515#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 998791#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 998706#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 998707#L1649 assume !(0 != activate_threads_~tmp___6~0); 999364#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 999369#L782 assume !(1 == ~t8_pc~0); 999569#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 999568#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1000045#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 998860#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 998861#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 998872#L801 assume !(1 == ~t9_pc~0); 1000854#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 999370#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 999187#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 999188#L1665 assume !(0 != activate_threads_~tmp___8~0); 999670#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 998889#L820 assume !(1 == ~t10_pc~0); 998890#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 998893#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 999501#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1000224#L1673 assume !(0 != activate_threads_~tmp___9~0); 1000225#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1000173#L839 assume !(1 == ~t11_pc~0); 1000174#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 1000175#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1000538#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1000539#L1681 assume !(0 != activate_threads_~tmp___10~0); 1000881#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 999311#L858 assume !(1 == ~t12_pc~0); 999245#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 999246#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 999735#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 999736#L1689 assume !(0 != activate_threads_~tmp___11~0); 1000420#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1000236#L877 assume !(1 == ~t13_pc~0); 1000238#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 1000244#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1000787#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 998946#L1697 assume !(0 != activate_threads_~tmp___12~0); 998947#L1697-2 assume !(1 == ~M_E~0); 998948#L1429-1 assume !(1 == ~T1_E~0); 999018#L1434-1 assume !(1 == ~T2_E~0); 999019#L1439-1 assume !(1 == ~T3_E~0); 999514#L1444-1 assume !(1 == ~T4_E~0); 999515#L1449-1 assume !(1 == ~T5_E~0); 1000066#L1454-1 assume !(1 == ~T6_E~0); 999963#L1459-1 assume !(1 == ~T7_E~0); 999964#L1464-1 assume !(1 == ~T8_E~0); 1000618#L1469-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 999148#L1474-1 assume !(1 == ~T10_E~0); 998762#L1479-1 assume !(1 == ~T11_E~0); 998763#L1484-1 assume !(1 == ~T12_E~0); 999668#L1489-1 assume !(1 == ~T13_E~0); 999669#L1494-1 assume !(1 == ~E_M~0); 1000033#L1499-1 assume !(1 == ~E_1~0); 1000034#L1504-1 assume !(1 == ~E_2~0); 1000675#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1000558#L1514-1 assume !(1 == ~E_4~0); 999277#L1519-1 assume !(1 == ~E_5~0); 998913#L1524-1 assume !(1 == ~E_6~0); 998914#L1529-1 assume !(1 == ~E_7~0); 999425#L1534-1 assume !(1 == ~E_8~0); 999426#L1539-1 assume !(1 == ~E_9~0); 1000146#L1544-1 assume !(1 == ~E_10~0); 1000147#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 1000646#L1554-1 assume !(1 == ~E_12~0); 999323#L1559-1 assume !(1 == ~E_13~0); 999324#L1930-1 [2018-11-28 12:51:04,728 INFO L796 eck$LassoCheckResult]: Loop: 999324#L1930-1 assume !false; 1014487#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1014482#L1256 assume !false; 1014481#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1014472#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1014466#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1014465#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1014463#L1069 assume !(0 != eval_~tmp~0); 1014464#L1271 start_simulation_~kernel_st~0 := 2; 1014985#L897-1 start_simulation_~kernel_st~0 := 3; 1014984#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1014983#L1281-4 assume !(0 == ~T1_E~0); 1014982#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1014981#L1291-3 assume !(0 == ~T3_E~0); 1014980#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1014979#L1301-3 assume !(0 == ~T5_E~0); 1014977#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1014975#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1014973#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1014971#L1321-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1014969#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1014967#L1331-3 assume !(0 == ~T11_E~0); 1014965#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1014962#L1341-3 assume !(0 == ~T13_E~0); 1014960#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1014958#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1014956#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1014954#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1014952#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1014950#L1371-3 assume !(0 == ~E_5~0); 1014948#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1014946#L1381-3 assume !(0 == ~E_7~0); 1014944#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1014942#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1014940#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1014937#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1014935#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1014933#L1411-3 assume !(0 == ~E_13~0); 1014931#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1014929#L630-45 assume !(1 == ~m_pc~0); 1014927#L630-47 is_master_triggered_~__retres1~0 := 0; 1014925#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1014923#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1014921#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1014919#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1014917#L649-45 assume !(1 == ~t1_pc~0); 1014914#L649-47 is_transmit1_triggered_~__retres1~1 := 0; 1014911#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1014909#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1014907#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1014905#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1014903#L668-45 assume !(1 == ~t2_pc~0); 1014901#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 1014899#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1014897#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1014895#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1014893#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1014891#L687-45 assume !(1 == ~t3_pc~0); 1014889#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 1014886#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1014884#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1014882#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1014880#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1014878#L706-45 assume !(1 == ~t4_pc~0); 1014876#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 1014873#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1014871#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1014869#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1014867#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1014865#L725-45 assume !(1 == ~t5_pc~0); 1014862#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 1014860#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1014858#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1014856#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 1014854#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1014852#L744-45 assume !(1 == ~t6_pc~0); 1014850#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 1014847#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1014845#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1014843#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1014841#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1014839#L763-45 assume !(1 == ~t7_pc~0); 1014837#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 1014835#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1014833#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1014831#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1014829#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1014827#L782-45 assume !(1 == ~t8_pc~0); 1014825#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 1014821#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1014819#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1014817#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1014815#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1014813#L801-45 assume !(1 == ~t9_pc~0); 1014811#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 1014808#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1014806#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1014804#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 1014802#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1014801#L820-45 assume !(1 == ~t10_pc~0); 1014797#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 1014794#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1014789#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1014788#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1014787#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1014786#L839-45 assume !(1 == ~t11_pc~0); 1014785#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 1014784#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1014783#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1014782#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1014781#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1014780#L858-45 assume !(1 == ~t12_pc~0); 1014779#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 1014777#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1014776#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1014775#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 1014774#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1014773#L877-45 assume !(1 == ~t13_pc~0); 1014771#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 1014770#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1014769#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1014768#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1014767#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1014766#L1429-3 assume !(1 == ~T1_E~0); 1014765#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1014764#L1439-3 assume !(1 == ~T3_E~0); 1014763#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1014762#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1014761#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1014759#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1014757#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1014755#L1469-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1014753#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1014751#L1479-3 assume !(1 == ~T11_E~0); 1014749#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1014747#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1014744#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1014742#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1014740#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1014738#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1014736#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1014734#L1519-3 assume !(1 == ~E_5~0); 1014732#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1014730#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1014728#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1014726#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1014724#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1014722#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1014719#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1014717#L1559-3 assume !(1 == ~E_13~0); 1014715#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1014707#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1014694#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1014692#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 1014528#L1949 assume !(0 == start_simulation_~tmp~3); 1014526#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1014514#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1014501#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1014499#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 1014497#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1014495#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 1014493#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 1014489#L1962 assume !(0 != start_simulation_~tmp___0~1); 999324#L1930-1 [2018-11-28 12:51:04,728 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:04,728 INFO L82 PathProgramCache]: Analyzing trace with hash -275866569, now seen corresponding path program 1 times [2018-11-28 12:51:04,729 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:04,729 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:04,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:04,730 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:04,730 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:04,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:04,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:04,797 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:04,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:51:04,797 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:51:04,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:04,797 INFO L82 PathProgramCache]: Analyzing trace with hash -980527506, now seen corresponding path program 1 times [2018-11-28 12:51:04,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:04,798 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:04,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:04,802 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:04,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:04,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:04,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:04,859 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:04,859 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:04,860 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:04,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:51:04,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:51:04,860 INFO L87 Difference]: Start difference. First operand 181988 states and 257070 transitions. cyclomatic complexity: 75210 Second operand 3 states. [2018-11-28 12:51:05,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:05,230 INFO L93 Difference]: Finished difference Result 181988 states and 256684 transitions. [2018-11-28 12:51:05,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:51:05,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 181988 states and 256684 transitions. [2018-11-28 12:51:05,694 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:05,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 181988 states to 181988 states and 256684 transitions. [2018-11-28 12:51:05,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 181988 [2018-11-28 12:51:06,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 181988 [2018-11-28 12:51:06,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181988 states and 256684 transitions. [2018-11-28 12:51:06,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:06,139 INFO L705 BuchiCegarLoop]: Abstraction has 181988 states and 256684 transitions. [2018-11-28 12:51:06,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181988 states and 256684 transitions. [2018-11-28 12:51:07,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181988 to 181988. [2018-11-28 12:51:07,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 181988 states. [2018-11-28 12:51:07,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181988 states to 181988 states and 256684 transitions. [2018-11-28 12:51:07,853 INFO L728 BuchiCegarLoop]: Abstraction has 181988 states and 256684 transitions. [2018-11-28 12:51:07,853 INFO L608 BuchiCegarLoop]: Abstraction has 181988 states and 256684 transitions. [2018-11-28 12:51:07,853 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-28 12:51:07,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 181988 states and 256684 transitions. [2018-11-28 12:51:08,199 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:08,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:08,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:08,201 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:08,201 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:08,202 INFO L794 eck$LassoCheckResult]: Stem: 1363245#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1363246#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1364165#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1364205#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 1362934#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1362935#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1363713#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1363489#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1363490#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1363854#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1363855#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1364641#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1363362#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1363057#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1363058#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1363552#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1363553#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1364187#L969-1 assume !(0 == ~M_E~0); 1363875#L1281-1 assume !(0 == ~T1_E~0); 1363876#L1286-1 assume !(0 == ~T2_E~0); 1364651#L1291-1 assume !(0 == ~T3_E~0); 1363371#L1296-1 assume !(0 == ~T4_E~0); 1363076#L1301-1 assume !(0 == ~T5_E~0); 1363077#L1306-1 assume !(0 == ~T6_E~0); 1363571#L1311-1 assume !(0 == ~T7_E~0); 1363424#L1316-1 assume !(0 == ~T8_E~0); 1363425#L1321-1 assume !(0 == ~T9_E~0); 1363967#L1326-1 assume !(0 == ~T10_E~0); 1363968#L1331-1 assume !(0 == ~T11_E~0); 1364438#L1336-1 assume !(0 == ~T12_E~0); 1363206#L1341-1 assume !(0 == ~T13_E~0); 1363015#L1346-1 assume !(0 == ~E_M~0); 1363016#L1351-1 assume !(0 == ~E_1~0); 1363516#L1356-1 assume !(0 == ~E_2~0); 1363517#L1361-1 assume !(0 == ~E_3~0); 1364060#L1366-1 assume !(0 == ~E_4~0); 1363947#L1371-1 assume !(0 == ~E_5~0); 1363948#L1376-1 assume !(0 == ~E_6~0); 1364552#L1381-1 assume !(0 == ~E_7~0); 1363102#L1386-1 assume !(0 == ~E_8~0); 1362711#L1391-1 assume !(0 == ~E_9~0); 1362712#L1396-1 assume !(0 == ~E_10~0); 1363649#L1401-1 assume !(0 == ~E_11~0); 1363650#L1406-1 assume !(0 == ~E_12~0); 1363989#L1411-1 assume !(0 == ~E_13~0); 1363990#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1364657#L630 assume !(1 == ~m_pc~0); 1364652#L630-2 is_master_triggered_~__retres1~0 := 0; 1363048#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1362763#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1362764#L1593 assume !(0 != activate_threads_~tmp~1); 1364858#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1363749#L649 assume !(1 == ~t1_pc~0); 1363707#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 1363706#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1364183#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1364184#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1364397#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1364404#L668 assume !(1 == ~t2_pc~0); 1364867#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 1363380#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1363349#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1362922#L1609 assume !(0 != activate_threads_~tmp___1~0); 1362923#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1362697#L687 assume !(1 == ~t3_pc~0); 1362677#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 1362678#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1363392#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1363486#L1617 assume !(0 != activate_threads_~tmp___2~0); 1363684#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1363687#L706 assume !(1 == ~t4_pc~0); 1364019#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 1364022#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1364611#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1364248#L1625 assume !(0 != activate_threads_~tmp___3~0); 1364249#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1363179#L725 assume !(1 == ~t5_pc~0); 1363154#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 1363155#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1363689#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1363766#L1633 assume !(0 != activate_threads_~tmp___4~0); 1363914#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1363922#L744 assume !(1 == ~t6_pc~0); 1364256#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 1364257#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1364778#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1364636#L1641 assume !(0 != activate_threads_~tmp___5~0); 1364637#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1364506#L763 assume !(1 == ~t7_pc~0); 1364474#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 1362776#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1362691#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1362692#L1649 assume !(0 != activate_threads_~tmp___6~0); 1363352#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1363357#L782 assume !(1 == ~t8_pc~0); 1363558#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 1363557#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1364026#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1362846#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1362847#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1362860#L801 assume !(1 == ~t9_pc~0); 1364835#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 1363358#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1363172#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1363173#L1665 assume !(0 != activate_threads_~tmp___8~0); 1363656#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1362875#L820 assume !(1 == ~t10_pc~0); 1362876#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 1362879#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1363491#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1364202#L1673 assume !(0 != activate_threads_~tmp___9~0); 1364203#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1364152#L839 assume !(1 == ~t11_pc~0); 1364153#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 1364156#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1364499#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1364500#L1681 assume !(0 != activate_threads_~tmp___10~0); 1364868#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1363296#L858 assume !(1 == ~t12_pc~0); 1363231#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 1363232#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1363715#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1363716#L1689 assume !(0 != activate_threads_~tmp___11~0); 1364387#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1364211#L877 assume !(1 == ~t13_pc~0); 1364213#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 1364217#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1364761#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1362931#L1697 assume !(0 != activate_threads_~tmp___12~0); 1362932#L1697-2 assume !(1 == ~M_E~0); 1362933#L1429-1 assume !(1 == ~T1_E~0); 1363001#L1434-1 assume !(1 == ~T2_E~0); 1363002#L1439-1 assume !(1 == ~T3_E~0); 1363503#L1444-1 assume !(1 == ~T4_E~0); 1363504#L1449-1 assume !(1 == ~T5_E~0); 1364048#L1454-1 assume !(1 == ~T6_E~0); 1363941#L1459-1 assume !(1 == ~T7_E~0); 1363942#L1464-1 assume !(1 == ~T8_E~0); 1364575#L1469-1 assume !(1 == ~T9_E~0); 1363133#L1474-1 assume !(1 == ~T10_E~0); 1362749#L1479-1 assume !(1 == ~T11_E~0); 1362750#L1484-1 assume !(1 == ~T12_E~0); 1363654#L1489-1 assume !(1 == ~T13_E~0); 1363655#L1494-1 assume !(1 == ~E_M~0); 1364015#L1499-1 assume !(1 == ~E_1~0); 1364016#L1504-1 assume !(1 == ~E_2~0); 1364630#L1509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1364517#L1514-1 assume !(1 == ~E_4~0); 1363262#L1519-1 assume !(1 == ~E_5~0); 1362901#L1524-1 assume !(1 == ~E_6~0); 1362902#L1529-1 assume !(1 == ~E_7~0); 1363413#L1534-1 assume !(1 == ~E_8~0); 1363414#L1539-1 assume !(1 == ~E_9~0); 1364130#L1544-1 assume !(1 == ~E_10~0); 1364131#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 1364601#L1554-1 assume !(1 == ~E_12~0); 1363308#L1559-1 assume !(1 == ~E_13~0); 1363309#L1930-1 [2018-11-28 12:51:08,202 INFO L796 eck$LassoCheckResult]: Loop: 1363309#L1930-1 assume !false; 1395611#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1395605#L1256 assume !false; 1395603#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1395581#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1395574#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1395572#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1395569#L1069 assume !(0 != eval_~tmp~0); 1395570#L1271 start_simulation_~kernel_st~0 := 2; 1395982#L897-1 start_simulation_~kernel_st~0 := 3; 1395979#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1395977#L1281-4 assume !(0 == ~T1_E~0); 1395975#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1395973#L1291-3 assume !(0 == ~T3_E~0); 1395971#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1395969#L1301-3 assume !(0 == ~T5_E~0); 1395967#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1395965#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1395963#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1395961#L1321-3 assume !(0 == ~T9_E~0); 1395959#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1395957#L1331-3 assume !(0 == ~T11_E~0); 1395954#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1395952#L1341-3 assume !(0 == ~T13_E~0); 1395950#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1395948#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1395946#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1395943#L1361-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1395941#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1395939#L1371-3 assume !(0 == ~E_5~0); 1395937#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1395935#L1381-3 assume !(0 == ~E_7~0); 1395931#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1395929#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1395928#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1395927#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1395926#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1395925#L1411-3 assume !(0 == ~E_13~0); 1395924#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1395923#L630-45 assume !(1 == ~m_pc~0); 1395922#L630-47 is_master_triggered_~__retres1~0 := 0; 1395921#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1395920#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1395919#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1395918#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1395917#L649-45 assume !(1 == ~t1_pc~0); 1395916#L649-47 is_transmit1_triggered_~__retres1~1 := 0; 1395914#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1395913#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1395912#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1395911#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1395910#L668-45 assume !(1 == ~t2_pc~0); 1395909#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 1395908#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1395907#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1395906#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1395905#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1395904#L687-45 assume !(1 == ~t3_pc~0); 1395903#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 1395901#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1395900#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1395899#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1395898#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1395897#L706-45 assume !(1 == ~t4_pc~0); 1395896#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 1395895#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1395894#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1395892#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1395890#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1395888#L725-45 assume !(1 == ~t5_pc~0); 1395885#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 1395883#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1395881#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1395879#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 1395876#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1395874#L744-45 assume !(1 == ~t6_pc~0); 1395872#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 1395870#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1395868#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1395866#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1395864#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1395862#L763-45 assume !(1 == ~t7_pc~0); 1395860#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 1395858#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1395856#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1395854#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1395851#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1395849#L782-45 assume !(1 == ~t8_pc~0); 1395847#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 1395844#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1395842#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1395840#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1395838#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1395836#L801-45 assume !(1 == ~t9_pc~0); 1395834#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 1395832#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1395830#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1395829#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 1395826#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1395824#L820-45 assume 1 == ~t10_pc~0; 1395821#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 1395819#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1395817#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1395815#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1395813#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1395811#L839-45 assume !(1 == ~t11_pc~0); 1395809#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 1395807#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1395805#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1395803#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1395801#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1395799#L858-45 assume !(1 == ~t12_pc~0); 1395797#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 1395794#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1395792#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1395790#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 1395788#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1395785#L877-45 assume !(1 == ~t13_pc~0); 1395782#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 1395780#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1395778#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1395776#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1395774#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1395772#L1429-3 assume !(1 == ~T1_E~0); 1395770#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1395768#L1439-3 assume !(1 == ~T3_E~0); 1395766#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1395764#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1395762#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1395759#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1395757#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1395755#L1469-3 assume !(1 == ~T9_E~0); 1395753#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1395751#L1479-3 assume !(1 == ~T11_E~0); 1395749#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1395747#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1395745#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1395743#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1395741#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1395739#L1509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1395737#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1395734#L1519-3 assume !(1 == ~E_5~0); 1395732#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1395730#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1395728#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1395726#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1395723#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1395721#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1395719#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1395717#L1559-3 assume !(1 == ~E_13~0); 1395715#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1395707#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1395694#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1395692#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 1395651#L1949 assume !(0 == start_simulation_~tmp~3); 1395649#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1395637#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1395625#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1395623#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 1395621#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1395619#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 1395617#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 1395615#L1962 assume !(0 != start_simulation_~tmp___0~1); 1363309#L1930-1 [2018-11-28 12:51:08,202 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:08,202 INFO L82 PathProgramCache]: Analyzing trace with hash -1964810311, now seen corresponding path program 1 times [2018-11-28 12:51:08,203 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:08,203 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:08,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:08,203 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:08,204 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:08,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:08,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:08,263 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:08,264 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:51:08,264 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:51:08,264 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:08,264 INFO L82 PathProgramCache]: Analyzing trace with hash -1072399029, now seen corresponding path program 1 times [2018-11-28 12:51:08,264 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:08,264 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:08,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:08,265 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:08,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:08,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:08,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:08,317 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:08,317 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:08,317 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:08,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:51:08,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:51:08,318 INFO L87 Difference]: Start difference. First operand 181988 states and 256684 transitions. cyclomatic complexity: 74824 Second operand 3 states. [2018-11-28 12:51:08,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:08,709 INFO L93 Difference]: Finished difference Result 181988 states and 254761 transitions. [2018-11-28 12:51:08,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:51:08,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 181988 states and 254761 transitions. [2018-11-28 12:51:09,172 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:09,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 181988 states to 181988 states and 254761 transitions. [2018-11-28 12:51:09,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 181988 [2018-11-28 12:51:09,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 181988 [2018-11-28 12:51:09,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181988 states and 254761 transitions. [2018-11-28 12:51:09,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:09,607 INFO L705 BuchiCegarLoop]: Abstraction has 181988 states and 254761 transitions. [2018-11-28 12:51:09,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181988 states and 254761 transitions. [2018-11-28 12:51:11,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181988 to 181988. [2018-11-28 12:51:11,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 181988 states. [2018-11-28 12:51:11,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181988 states to 181988 states and 254761 transitions. [2018-11-28 12:51:11,389 INFO L728 BuchiCegarLoop]: Abstraction has 181988 states and 254761 transitions. [2018-11-28 12:51:11,389 INFO L608 BuchiCegarLoop]: Abstraction has 181988 states and 254761 transitions. [2018-11-28 12:51:11,389 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-28 12:51:11,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 181988 states and 254761 transitions. [2018-11-28 12:51:11,733 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:11,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:11,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:11,735 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:11,736 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:11,736 INFO L794 eck$LassoCheckResult]: Stem: 1727231#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1727232#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1728145#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1728189#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 1726918#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1726919#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1727705#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1727474#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1727475#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1727842#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1727843#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1728629#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1727346#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1727042#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1727043#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1727537#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1727538#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1728168#L969-1 assume !(0 == ~M_E~0); 1727867#L1281-1 assume !(0 == ~T1_E~0); 1727868#L1286-1 assume !(0 == ~T2_E~0); 1728638#L1291-1 assume !(0 == ~T3_E~0); 1727358#L1296-1 assume !(0 == ~T4_E~0); 1727062#L1301-1 assume !(0 == ~T5_E~0); 1727063#L1306-1 assume !(0 == ~T6_E~0); 1727556#L1311-1 assume !(0 == ~T7_E~0); 1727413#L1316-1 assume !(0 == ~T8_E~0); 1727414#L1321-1 assume !(0 == ~T9_E~0); 1727956#L1326-1 assume !(0 == ~T10_E~0); 1727957#L1331-1 assume !(0 == ~T11_E~0); 1728421#L1336-1 assume !(0 == ~T12_E~0); 1727192#L1341-1 assume !(0 == ~T13_E~0); 1727003#L1346-1 assume !(0 == ~E_M~0); 1727004#L1351-1 assume !(0 == ~E_1~0); 1727501#L1356-1 assume !(0 == ~E_2~0); 1727502#L1361-1 assume !(0 == ~E_3~0); 1728044#L1366-1 assume !(0 == ~E_4~0); 1727936#L1371-1 assume !(0 == ~E_5~0); 1727937#L1376-1 assume !(0 == ~E_6~0); 1728536#L1381-1 assume !(0 == ~E_7~0); 1727089#L1386-1 assume !(0 == ~E_8~0); 1726696#L1391-1 assume !(0 == ~E_9~0); 1726697#L1396-1 assume !(0 == ~E_10~0); 1727637#L1401-1 assume !(0 == ~E_11~0); 1727638#L1406-1 assume !(0 == ~E_12~0); 1727979#L1411-1 assume !(0 == ~E_13~0); 1727980#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1728643#L630 assume !(1 == ~m_pc~0); 1728639#L630-2 is_master_triggered_~__retres1~0 := 0; 1727033#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1726748#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1726749#L1593 assume !(0 != activate_threads_~tmp~1); 1728840#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1727742#L649 assume !(1 == ~t1_pc~0); 1727698#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 1727697#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1728164#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1728165#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1728376#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1728384#L668 assume !(1 == ~t2_pc~0); 1728845#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 1727366#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1727333#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1726904#L1609 assume !(0 != activate_threads_~tmp___1~0); 1726905#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1726682#L687 assume !(1 == ~t3_pc~0); 1726662#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 1726663#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1727378#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1727471#L1617 assume !(0 != activate_threads_~tmp___2~0); 1727675#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1727679#L706 assume !(1 == ~t4_pc~0); 1728004#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 1728007#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1728598#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1728232#L1625 assume !(0 != activate_threads_~tmp___3~0); 1728233#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1727165#L725 assume !(1 == ~t5_pc~0); 1727139#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 1727140#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1727680#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1727756#L1633 assume !(0 != activate_threads_~tmp___4~0); 1727905#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1727913#L744 assume !(1 == ~t6_pc~0); 1728241#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 1728242#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1728768#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1728625#L1641 assume !(0 != activate_threads_~tmp___5~0); 1728626#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1728490#L763 assume !(1 == ~t7_pc~0); 1728461#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 1726761#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1726676#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1726677#L1649 assume !(0 != activate_threads_~tmp___6~0); 1727336#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1727341#L782 assume !(1 == ~t8_pc~0); 1727543#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 1727542#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1728011#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1726825#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1726826#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1726836#L801 assume !(1 == ~t9_pc~0); 1728821#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 1727342#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1727157#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1727158#L1665 assume !(0 != activate_threads_~tmp___8~0); 1727644#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1726850#L820 assume !(1 == ~t10_pc~0); 1726851#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 1726854#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1727476#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1728184#L1673 assume !(0 != activate_threads_~tmp___9~0); 1728185#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1728134#L839 assume !(1 == ~t11_pc~0); 1728135#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 1728136#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1728483#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1728484#L1681 assume !(0 != activate_threads_~tmp___10~0); 1728846#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1727285#L858 assume !(1 == ~t12_pc~0); 1727217#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 1727218#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1727706#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1727707#L1689 assume !(0 != activate_threads_~tmp___11~0); 1728365#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1728196#L877 assume !(1 == ~t13_pc~0); 1728198#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 1728203#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1728752#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1726915#L1697 assume !(0 != activate_threads_~tmp___12~0); 1726916#L1697-2 assume !(1 == ~M_E~0); 1726917#L1429-1 assume !(1 == ~T1_E~0); 1726988#L1434-1 assume !(1 == ~T2_E~0); 1726989#L1439-1 assume !(1 == ~T3_E~0); 1727488#L1444-1 assume !(1 == ~T4_E~0); 1727489#L1449-1 assume !(1 == ~T5_E~0); 1728032#L1454-1 assume !(1 == ~T6_E~0); 1727930#L1459-1 assume !(1 == ~T7_E~0); 1727931#L1464-1 assume !(1 == ~T8_E~0); 1728567#L1469-1 assume !(1 == ~T9_E~0); 1727122#L1474-1 assume !(1 == ~T10_E~0); 1726736#L1479-1 assume !(1 == ~T11_E~0); 1726737#L1484-1 assume !(1 == ~T12_E~0); 1727642#L1489-1 assume !(1 == ~T13_E~0); 1727643#L1494-1 assume !(1 == ~E_M~0); 1728000#L1499-1 assume !(1 == ~E_1~0); 1728001#L1504-1 assume !(1 == ~E_2~0); 1728620#L1509-1 assume !(1 == ~E_3~0); 1728501#L1514-1 assume !(1 == ~E_4~0); 1727250#L1519-1 assume !(1 == ~E_5~0); 1726881#L1524-1 assume !(1 == ~E_6~0); 1726882#L1529-1 assume !(1 == ~E_7~0); 1727399#L1534-1 assume !(1 == ~E_8~0); 1727400#L1539-1 assume !(1 == ~E_9~0); 1728107#L1544-1 assume !(1 == ~E_10~0); 1728108#L1549-1 assume 1 == ~E_11~0;~E_11~0 := 2; 1728588#L1554-1 assume !(1 == ~E_12~0); 1727296#L1559-1 assume !(1 == ~E_13~0); 1727297#L1930-1 [2018-11-28 12:51:11,736 INFO L796 eck$LassoCheckResult]: Loop: 1727297#L1930-1 assume !false; 1759807#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1759802#L1256 assume !false; 1759801#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1759792#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1759786#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1759785#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1759783#L1069 assume !(0 != eval_~tmp~0); 1759784#L1271 start_simulation_~kernel_st~0 := 2; 1760305#L897-1 start_simulation_~kernel_st~0 := 3; 1760304#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1760303#L1281-4 assume !(0 == ~T1_E~0); 1760302#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1760301#L1291-3 assume !(0 == ~T3_E~0); 1760300#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1760299#L1301-3 assume !(0 == ~T5_E~0); 1760297#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1760295#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1760293#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1760291#L1321-3 assume !(0 == ~T9_E~0); 1760289#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1760287#L1331-3 assume !(0 == ~T11_E~0); 1760285#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1760282#L1341-3 assume !(0 == ~T13_E~0); 1760280#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1760278#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1760276#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1760274#L1361-3 assume !(0 == ~E_3~0); 1760272#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1760270#L1371-3 assume !(0 == ~E_5~0); 1760268#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1760266#L1381-3 assume !(0 == ~E_7~0); 1760264#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1760262#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1760259#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1760257#L1401-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1760255#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1760253#L1411-3 assume !(0 == ~E_13~0); 1760251#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1760249#L630-45 assume !(1 == ~m_pc~0); 1760247#L630-47 is_master_triggered_~__retres1~0 := 0; 1760245#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1760243#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1760241#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1760239#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1760237#L649-45 assume !(1 == ~t1_pc~0); 1760234#L649-47 is_transmit1_triggered_~__retres1~1 := 0; 1760231#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1760229#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1760227#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1760225#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1760223#L668-45 assume !(1 == ~t2_pc~0); 1760221#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 1760219#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1760217#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1760215#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1760213#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1760211#L687-45 assume !(1 == ~t3_pc~0); 1760208#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 1760206#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1760204#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1760202#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1760200#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1760198#L706-45 assume !(1 == ~t4_pc~0); 1760196#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 1760193#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1760191#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1760189#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1760187#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1760185#L725-45 assume !(1 == ~t5_pc~0); 1760182#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 1760180#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1760178#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1760176#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 1760174#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1760172#L744-45 assume !(1 == ~t6_pc~0); 1760170#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 1760167#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1760165#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1760163#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1760161#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1760159#L763-45 assume !(1 == ~t7_pc~0); 1760157#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 1760155#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1760153#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1760151#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1760149#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1760147#L782-45 assume 1 == ~t8_pc~0; 1760144#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 1760141#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1760139#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1760137#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1760135#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1760133#L801-45 assume !(1 == ~t9_pc~0); 1760131#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 1760128#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1760126#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1760124#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 1760122#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1760121#L820-45 assume 1 == ~t10_pc~0; 1760116#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 1760114#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1760109#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1760108#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1760107#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1760106#L839-45 assume !(1 == ~t11_pc~0); 1760105#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 1760104#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1760103#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1760102#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1760101#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1760100#L858-45 assume 1 == ~t12_pc~0; 1760098#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 1760097#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1760096#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1760095#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 1760094#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1760093#L877-45 assume !(1 == ~t13_pc~0); 1760091#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 1760090#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1760089#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1760088#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1760087#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1760086#L1429-3 assume !(1 == ~T1_E~0); 1760085#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1760084#L1439-3 assume !(1 == ~T3_E~0); 1760083#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1760082#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1760081#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1760079#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1760077#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1760075#L1469-3 assume !(1 == ~T9_E~0); 1760073#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1760071#L1479-3 assume !(1 == ~T11_E~0); 1760069#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1760067#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1760064#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1760062#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1760060#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1760058#L1509-3 assume !(1 == ~E_3~0); 1760056#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1760054#L1519-3 assume !(1 == ~E_5~0); 1760052#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1760050#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1760048#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1760046#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1760044#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1760041#L1549-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1760039#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1760037#L1559-3 assume !(1 == ~E_13~0); 1760035#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1760027#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1760014#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1760012#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 1759848#L1949 assume !(0 == start_simulation_~tmp~3); 1759846#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1759834#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1759821#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1759819#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 1759817#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1759815#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 1759813#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 1759809#L1962 assume !(0 != start_simulation_~tmp___0~1); 1727297#L1930-1 [2018-11-28 12:51:11,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:11,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1263745733, now seen corresponding path program 1 times [2018-11-28 12:51:11,737 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:11,737 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:11,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:11,738 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:11,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:11,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:11,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:11,797 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:11,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 12:51:11,797 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:51:11,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:11,798 INFO L82 PathProgramCache]: Analyzing trace with hash -166073463, now seen corresponding path program 1 times [2018-11-28 12:51:11,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:11,798 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:11,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:11,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:11,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:11,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:11,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:11,836 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:11,836 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:11,837 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:11,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:51:11,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:51:11,837 INFO L87 Difference]: Start difference. First operand 181988 states and 254761 transitions. cyclomatic complexity: 72901 Second operand 3 states. [2018-11-28 12:51:12,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:12,231 INFO L93 Difference]: Finished difference Result 181988 states and 253607 transitions. [2018-11-28 12:51:12,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:51:12,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 181988 states and 253607 transitions. [2018-11-28 12:51:12,693 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:12,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 181988 states to 181988 states and 253607 transitions. [2018-11-28 12:51:12,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 181988 [2018-11-28 12:51:13,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 181988 [2018-11-28 12:51:13,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181988 states and 253607 transitions. [2018-11-28 12:51:13,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:13,138 INFO L705 BuchiCegarLoop]: Abstraction has 181988 states and 253607 transitions. [2018-11-28 12:51:13,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181988 states and 253607 transitions. [2018-11-28 12:51:14,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181988 to 181988. [2018-11-28 12:51:14,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 181988 states. [2018-11-28 12:51:14,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181988 states to 181988 states and 253607 transitions. [2018-11-28 12:51:14,755 INFO L728 BuchiCegarLoop]: Abstraction has 181988 states and 253607 transitions. [2018-11-28 12:51:14,755 INFO L608 BuchiCegarLoop]: Abstraction has 181988 states and 253607 transitions. [2018-11-28 12:51:14,755 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-28 12:51:14,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 181988 states and 253607 transitions. [2018-11-28 12:51:15,091 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 180928 [2018-11-28 12:51:15,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:15,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:15,092 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:15,092 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:15,092 INFO L794 eck$LassoCheckResult]: Stem: 2091203#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 2091204#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 2092104#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2092147#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 2090899#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2090900#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2091672#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2091447#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2091448#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2091813#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2091814#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2092575#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2091319#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2091017#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2091018#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2091510#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 2091511#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 2092127#L969-1 assume !(0 == ~M_E~0); 2091835#L1281-1 assume !(0 == ~T1_E~0); 2091836#L1286-1 assume !(0 == ~T2_E~0); 2092582#L1291-1 assume !(0 == ~T3_E~0); 2091328#L1296-1 assume !(0 == ~T4_E~0); 2091038#L1301-1 assume !(0 == ~T5_E~0); 2091039#L1306-1 assume !(0 == ~T6_E~0); 2091529#L1311-1 assume !(0 == ~T7_E~0); 2091383#L1316-1 assume !(0 == ~T8_E~0); 2091384#L1321-1 assume !(0 == ~T9_E~0); 2091917#L1326-1 assume !(0 == ~T10_E~0); 2091918#L1331-1 assume !(0 == ~T11_E~0); 2092369#L1336-1 assume !(0 == ~T12_E~0); 2091164#L1341-1 assume !(0 == ~T13_E~0); 2090980#L1346-1 assume !(0 == ~E_M~0); 2090981#L1351-1 assume !(0 == ~E_1~0); 2091474#L1356-1 assume !(0 == ~E_2~0); 2091475#L1361-1 assume !(0 == ~E_3~0); 2092003#L1366-1 assume !(0 == ~E_4~0); 2091897#L1371-1 assume !(0 == ~E_5~0); 2091898#L1376-1 assume !(0 == ~E_6~0); 2092483#L1381-1 assume !(0 == ~E_7~0); 2091063#L1386-1 assume !(0 == ~E_8~0); 2090681#L1391-1 assume !(0 == ~E_9~0); 2090682#L1396-1 assume !(0 == ~E_10~0); 2091606#L1401-1 assume !(0 == ~E_11~0); 2091607#L1406-1 assume !(0 == ~E_12~0); 2091938#L1411-1 assume !(0 == ~E_13~0); 2091939#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2092589#L630 assume !(1 == ~m_pc~0); 2092584#L630-2 is_master_triggered_~__retres1~0 := 0; 2091011#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2090732#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2090733#L1593 assume !(0 != activate_threads_~tmp~1); 2092772#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2091708#L649 assume !(1 == ~t1_pc~0); 2091666#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 2091665#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2092123#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2092124#L1601 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2092324#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2092332#L668 assume !(1 == ~t2_pc~0); 2092778#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 2091337#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2091305#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2090887#L1609 assume !(0 != activate_threads_~tmp___1~0); 2090888#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2090667#L687 assume !(1 == ~t3_pc~0); 2090647#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 2090648#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2091350#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2091442#L1617 assume !(0 != activate_threads_~tmp___2~0); 2091643#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2091646#L706 assume !(1 == ~t4_pc~0); 2091966#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 2091969#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2092546#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2092194#L1625 assume !(0 != activate_threads_~tmp___3~0); 2092195#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2091139#L725 assume !(1 == ~t5_pc~0); 2091114#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 2091115#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2091648#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2091724#L1633 assume !(0 != activate_threads_~tmp___4~0); 2091869#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2091876#L744 assume !(1 == ~t6_pc~0); 2092203#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 2092204#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2092703#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2092572#L1641 assume !(0 != activate_threads_~tmp___5~0); 2092573#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2092435#L763 assume !(1 == ~t7_pc~0); 2092408#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 2090746#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2090661#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2090662#L1649 assume !(0 != activate_threads_~tmp___6~0); 2091309#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2091314#L782 assume !(1 == ~t8_pc~0); 2091516#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 2091515#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2091973#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2090809#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2090810#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 2090820#L801 assume !(1 == ~t9_pc~0); 2092755#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 2091315#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 2091132#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 2091133#L1665 assume !(0 != activate_threads_~tmp___8~0); 2091614#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 2090833#L820 assume !(1 == ~t10_pc~0); 2090834#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 2090837#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 2091449#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 2092142#L1673 assume !(0 != activate_threads_~tmp___9~0); 2092143#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 2092096#L839 assume !(1 == ~t11_pc~0); 2092097#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 2092098#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 2092428#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 2092429#L1681 assume !(0 != activate_threads_~tmp___10~0); 2092779#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 2091256#L858 assume !(1 == ~t12_pc~0); 2091189#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 2091190#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 2091674#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 2091675#L1689 assume !(0 != activate_threads_~tmp___11~0); 2092311#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 2092152#L877 assume !(1 == ~t13_pc~0); 2092154#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 2092159#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 2092687#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 2090896#L1697 assume !(0 != activate_threads_~tmp___12~0); 2090897#L1697-2 assume !(1 == ~M_E~0); 2090898#L1429-1 assume !(1 == ~T1_E~0); 2090966#L1434-1 assume !(1 == ~T2_E~0); 2090967#L1439-1 assume !(1 == ~T3_E~0); 2091461#L1444-1 assume !(1 == ~T4_E~0); 2091462#L1449-1 assume !(1 == ~T5_E~0); 2091993#L1454-1 assume !(1 == ~T6_E~0); 2091891#L1459-1 assume !(1 == ~T7_E~0); 2091892#L1464-1 assume !(1 == ~T8_E~0); 2092509#L1469-1 assume !(1 == ~T9_E~0); 2091093#L1474-1 assume !(1 == ~T10_E~0); 2090717#L1479-1 assume !(1 == ~T11_E~0); 2090718#L1484-1 assume !(1 == ~T12_E~0); 2091612#L1489-1 assume !(1 == ~T13_E~0); 2091613#L1494-1 assume !(1 == ~E_M~0); 2091961#L1499-1 assume !(1 == ~E_1~0); 2091962#L1504-1 assume !(1 == ~E_2~0); 2092566#L1509-1 assume !(1 == ~E_3~0); 2092446#L1514-1 assume !(1 == ~E_4~0); 2091221#L1519-1 assume !(1 == ~E_5~0); 2090864#L1524-1 assume !(1 == ~E_6~0); 2090865#L1529-1 assume !(1 == ~E_7~0); 2091370#L1534-1 assume !(1 == ~E_8~0); 2091371#L1539-1 assume !(1 == ~E_9~0); 2092071#L1544-1 assume !(1 == ~E_10~0); 2092072#L1549-1 assume !(1 == ~E_11~0); 2092537#L1554-1 assume !(1 == ~E_12~0); 2091268#L1559-1 assume !(1 == ~E_13~0); 2091269#L1930-1 [2018-11-28 12:51:15,093 INFO L796 eck$LassoCheckResult]: Loop: 2091269#L1930-1 assume !false; 2111467#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 2111462#L1256 assume !false; 2111461#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 2111452#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 2111446#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 2111445#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2111443#L1069 assume !(0 != eval_~tmp~0); 2111444#L1271 start_simulation_~kernel_st~0 := 2; 2111965#L897-1 start_simulation_~kernel_st~0 := 3; 2111964#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2111963#L1281-4 assume !(0 == ~T1_E~0); 2111962#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2111961#L1291-3 assume !(0 == ~T3_E~0); 2111960#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2111959#L1301-3 assume !(0 == ~T5_E~0); 2111957#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2111955#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2111953#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2111951#L1321-3 assume !(0 == ~T9_E~0); 2111949#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2111947#L1331-3 assume !(0 == ~T11_E~0); 2111945#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2111942#L1341-3 assume !(0 == ~T13_E~0); 2111940#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2111938#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2111936#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2111934#L1361-3 assume !(0 == ~E_3~0); 2111932#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2111930#L1371-3 assume !(0 == ~E_5~0); 2111928#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2111926#L1381-3 assume !(0 == ~E_7~0); 2111924#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2111922#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2111919#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2111917#L1401-3 assume !(0 == ~E_11~0); 2111915#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 2111913#L1411-3 assume !(0 == ~E_13~0); 2111911#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2111909#L630-45 assume !(1 == ~m_pc~0); 2111907#L630-47 is_master_triggered_~__retres1~0 := 0; 2111905#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2111903#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2111901#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2111899#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2111897#L649-45 assume 1 == ~t1_pc~0; 2111893#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2111891#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2111889#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2111887#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2111885#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2111883#L668-45 assume !(1 == ~t2_pc~0); 2111881#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 2111879#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2111877#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2111875#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2111873#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2111871#L687-45 assume !(1 == ~t3_pc~0); 2111868#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 2111866#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2111864#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2111862#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2111860#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2111858#L706-45 assume !(1 == ~t4_pc~0); 2111856#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 2111853#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2111851#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2111849#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2111847#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2111845#L725-45 assume !(1 == ~t5_pc~0); 2111842#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 2111840#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2111838#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2111836#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 2111834#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2111832#L744-45 assume !(1 == ~t6_pc~0); 2111830#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 2111827#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2111825#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2111823#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2111821#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2111819#L763-45 assume !(1 == ~t7_pc~0); 2111817#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 2111815#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2111813#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2111811#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2111809#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2111807#L782-45 assume 1 == ~t8_pc~0; 2111804#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2111801#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2111799#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2111797#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2111795#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 2111793#L801-45 assume !(1 == ~t9_pc~0); 2111791#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 2111788#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 2111786#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 2111784#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 2111782#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 2111781#L820-45 assume 1 == ~t10_pc~0; 2111776#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 2111774#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 2111769#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 2111768#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 2111767#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 2111766#L839-45 assume !(1 == ~t11_pc~0); 2111765#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 2111764#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 2111763#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 2111762#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 2111761#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 2111760#L858-45 assume 1 == ~t12_pc~0; 2111758#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 2111757#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 2111756#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 2111755#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 2111754#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 2111753#L877-45 assume !(1 == ~t13_pc~0); 2111751#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 2111750#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 2111749#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 2111748#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 2111747#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 2111746#L1429-3 assume !(1 == ~T1_E~0); 2111745#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2111744#L1439-3 assume !(1 == ~T3_E~0); 2111743#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2111742#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2111741#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2111739#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2111737#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2111735#L1469-3 assume !(1 == ~T9_E~0); 2111733#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2111731#L1479-3 assume !(1 == ~T11_E~0); 2111729#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2111727#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 2111724#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2111722#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2111720#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2111718#L1509-3 assume !(1 == ~E_3~0); 2111716#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2111714#L1519-3 assume !(1 == ~E_5~0); 2111712#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2111710#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2111708#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2111706#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2111704#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2111701#L1549-3 assume !(1 == ~E_11~0); 2111699#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2111697#L1559-3 assume !(1 == ~E_13~0); 2111695#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 2111687#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 2111674#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 2111672#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 2111508#L1949 assume !(0 == start_simulation_~tmp~3); 2111506#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 2111494#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 2111481#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 2111479#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 2111477#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2111475#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 2111473#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 2111469#L1962 assume !(0 != start_simulation_~tmp___0~1); 2091269#L1930-1 [2018-11-28 12:51:15,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:15,093 INFO L82 PathProgramCache]: Analyzing trace with hash -1263743811, now seen corresponding path program 1 times [2018-11-28 12:51:15,093 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:15,093 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:15,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:15,094 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:15,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:15,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:15,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:15,212 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:15,212 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:15,213 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:51:15,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:15,213 INFO L82 PathProgramCache]: Analyzing trace with hash -894658650, now seen corresponding path program 1 times [2018-11-28 12:51:15,213 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:15,213 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:15,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:15,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:15,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:15,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:15,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:15,275 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:15,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:15,275 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:15,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:51:15,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:51:15,276 INFO L87 Difference]: Start difference. First operand 181988 states and 253607 transitions. cyclomatic complexity: 71747 Second operand 5 states. [2018-11-28 12:51:16,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:16,682 INFO L93 Difference]: Finished difference Result 520955 states and 722896 transitions. [2018-11-28 12:51:16,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 12:51:16,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 520955 states and 722896 transitions. [2018-11-28 12:51:18,914 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 517888 [2018-11-28 12:51:19,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 520955 states to 520955 states and 722896 transitions. [2018-11-28 12:51:19,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 520955 [2018-11-28 12:51:19,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 520955 [2018-11-28 12:51:19,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 520955 states and 722896 transitions. [2018-11-28 12:51:19,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:19,871 INFO L705 BuchiCegarLoop]: Abstraction has 520955 states and 722896 transitions. [2018-11-28 12:51:20,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 520955 states and 722896 transitions. [2018-11-28 12:51:21,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 520955 to 186791. [2018-11-28 12:51:21,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186791 states. [2018-11-28 12:51:21,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186791 states to 186791 states and 258410 transitions. [2018-11-28 12:51:21,732 INFO L728 BuchiCegarLoop]: Abstraction has 186791 states and 258410 transitions. [2018-11-28 12:51:21,732 INFO L608 BuchiCegarLoop]: Abstraction has 186791 states and 258410 transitions. [2018-11-28 12:51:21,732 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-28 12:51:21,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186791 states and 258410 transitions. [2018-11-28 12:51:22,087 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 185728 [2018-11-28 12:51:22,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:22,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:22,088 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:22,088 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:22,088 INFO L794 eck$LassoCheckResult]: Stem: 2794177#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 2794178#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 2795117#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2795174#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 2793863#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2793864#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2794665#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2794419#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2794420#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2794821#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2794822#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2795608#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2794291#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2793984#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2793985#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2794483#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 2794484#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 2795140#L969-1 assume !(0 == ~M_E~0); 2794842#L1281-1 assume !(0 == ~T1_E~0); 2794843#L1286-1 assume !(0 == ~T2_E~0); 2795621#L1291-1 assume !(0 == ~T3_E~0); 2794300#L1296-1 assume !(0 == ~T4_E~0); 2794008#L1301-1 assume !(0 == ~T5_E~0); 2794009#L1306-1 assume !(0 == ~T6_E~0); 2794502#L1311-1 assume !(0 == ~T7_E~0); 2794356#L1316-1 assume !(0 == ~T8_E~0); 2794357#L1321-1 assume !(0 == ~T9_E~0); 2794926#L1326-1 assume !(0 == ~T10_E~0); 2794927#L1331-1 assume !(0 == ~T11_E~0); 2795395#L1336-1 assume !(0 == ~T12_E~0); 2794137#L1341-1 assume !(0 == ~T13_E~0); 2793945#L1346-1 assume !(0 == ~E_M~0); 2793946#L1351-1 assume !(0 == ~E_1~0); 2794447#L1356-1 assume !(0 == ~E_2~0); 2794448#L1361-1 assume !(0 == ~E_3~0); 2795011#L1366-1 assume !(0 == ~E_4~0); 2794906#L1371-1 assume !(0 == ~E_5~0); 2794907#L1376-1 assume !(0 == ~E_6~0); 2795522#L1381-1 assume !(0 == ~E_7~0); 2794036#L1386-1 assume !(0 == ~E_8~0); 2793639#L1391-1 assume !(0 == ~E_9~0); 2793640#L1396-1 assume !(0 == ~E_10~0); 2794594#L1401-1 assume !(0 == ~E_11~0); 2794595#L1406-1 assume !(0 == ~E_12~0); 2794946#L1411-1 assume !(0 == ~E_13~0); 2794947#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2795629#L630 assume !(1 == ~m_pc~0); 2795623#L630-2 is_master_triggered_~__retres1~0 := 0; 2793977#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2793690#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2793691#L1593 assume !(0 != activate_threads_~tmp~1); 2795822#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2794716#L649 assume !(1 == ~t1_pc~0); 2794656#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 2794722#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2795165#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2795351#L1601 assume !(0 != activate_threads_~tmp___0~0); 2795352#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2795359#L668 assume !(1 == ~t2_pc~0); 2795825#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 2794310#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2794275#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2793849#L1609 assume !(0 != activate_threads_~tmp___1~0); 2793850#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2793625#L687 assume !(1 == ~t3_pc~0); 2793605#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 2793606#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2794324#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2794415#L1617 assume !(0 != activate_threads_~tmp___2~0); 2794630#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2794633#L706 assume !(1 == ~t4_pc~0); 2794972#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 2794975#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2795577#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2795221#L1625 assume !(0 != activate_threads_~tmp___3~0); 2795222#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2794111#L725 assume !(1 == ~t5_pc~0); 2794086#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 2794087#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2794635#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2794733#L1633 assume !(0 != activate_threads_~tmp___4~0); 2794877#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2794885#L744 assume !(1 == ~t6_pc~0); 2795231#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 2795232#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2795745#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2795602#L1641 assume !(0 != activate_threads_~tmp___5~0); 2795603#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2795468#L763 assume !(1 == ~t7_pc~0); 2795438#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 2793704#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2793619#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2793620#L1649 assume !(0 != activate_threads_~tmp___6~0); 2794279#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2794285#L782 assume !(1 == ~t8_pc~0); 2794489#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 2794488#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2794979#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2793768#L1657 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2793769#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 2793779#L801 assume !(1 == ~t9_pc~0); 2795797#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 2794286#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 2794104#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 2794105#L1665 assume !(0 != activate_threads_~tmp___8~0); 2794602#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 2793792#L820 assume !(1 == ~t10_pc~0); 2793793#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 2793796#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 2794421#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 2795166#L1673 assume !(0 != activate_threads_~tmp___9~0); 2795167#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 2795109#L839 assume !(1 == ~t11_pc~0); 2795110#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 2795111#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 2795460#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 2795461#L1681 assume !(0 != activate_threads_~tmp___10~0); 2795826#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 2794227#L858 assume !(1 == ~t12_pc~0); 2794162#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 2794163#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 2794667#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 2794668#L1689 assume !(0 != activate_threads_~tmp___11~0); 2795340#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 2795179#L877 assume !(1 == ~t13_pc~0); 2795181#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 2795186#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 2795729#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 2793860#L1697 assume !(0 != activate_threads_~tmp___12~0); 2793861#L1697-2 assume !(1 == ~M_E~0); 2793862#L1429-1 assume !(1 == ~T1_E~0); 2793931#L1434-1 assume !(1 == ~T2_E~0); 2793932#L1439-1 assume !(1 == ~T3_E~0); 2794434#L1444-1 assume !(1 == ~T4_E~0); 2794435#L1449-1 assume !(1 == ~T5_E~0); 2795000#L1454-1 assume !(1 == ~T6_E~0); 2794900#L1459-1 assume !(1 == ~T7_E~0); 2794901#L1464-1 assume !(1 == ~T8_E~0); 2795546#L1469-1 assume !(1 == ~T9_E~0); 2794065#L1474-1 assume !(1 == ~T10_E~0); 2793675#L1479-1 assume !(1 == ~T11_E~0); 2793676#L1484-1 assume !(1 == ~T12_E~0); 2794600#L1489-1 assume !(1 == ~T13_E~0); 2794601#L1494-1 assume !(1 == ~E_M~0); 2794967#L1499-1 assume !(1 == ~E_1~0); 2794968#L1504-1 assume !(1 == ~E_2~0); 2795596#L1509-1 assume !(1 == ~E_3~0); 2795480#L1514-1 assume !(1 == ~E_4~0); 2794195#L1519-1 assume !(1 == ~E_5~0); 2793823#L1524-1 assume !(1 == ~E_6~0); 2793824#L1529-1 assume !(1 == ~E_7~0); 2794344#L1534-1 assume !(1 == ~E_8~0); 2794345#L1539-1 assume !(1 == ~E_9~0); 2795082#L1544-1 assume !(1 == ~E_10~0); 2795083#L1549-1 assume !(1 == ~E_11~0); 2795568#L1554-1 assume !(1 == ~E_12~0); 2794239#L1559-1 assume !(1 == ~E_13~0); 2794240#L1930-1 [2018-11-28 12:51:22,089 INFO L796 eck$LassoCheckResult]: Loop: 2794240#L1930-1 assume !false; 2809720#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 2809709#L1256 assume !false; 2809705#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 2809470#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 2809457#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 2809450#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2809440#L1069 assume !(0 != eval_~tmp~0); 2809441#L1271 start_simulation_~kernel_st~0 := 2; 2816086#L897-1 start_simulation_~kernel_st~0 := 3; 2816084#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2816082#L1281-4 assume !(0 == ~T1_E~0); 2816080#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2816078#L1291-3 assume !(0 == ~T3_E~0); 2816075#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2816073#L1301-3 assume !(0 == ~T5_E~0); 2816071#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2816069#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2816067#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2816065#L1321-3 assume !(0 == ~T9_E~0); 2816063#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2816061#L1331-3 assume !(0 == ~T11_E~0); 2816059#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2816057#L1341-3 assume !(0 == ~T13_E~0); 2816055#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2816053#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2816050#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2816048#L1361-3 assume !(0 == ~E_3~0); 2816046#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2816044#L1371-3 assume !(0 == ~E_5~0); 2816042#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2816040#L1381-3 assume !(0 == ~E_7~0); 2816039#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2816038#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2816037#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2816036#L1401-3 assume !(0 == ~E_11~0); 2816035#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 2816034#L1411-3 assume !(0 == ~E_13~0); 2816033#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2816032#L630-45 assume !(1 == ~m_pc~0); 2816031#L630-47 is_master_triggered_~__retres1~0 := 0; 2816030#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2816029#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2816028#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2816027#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2816026#L649-45 assume 1 == ~t1_pc~0; 2816024#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2816022#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2816020#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2816018#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2816016#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2816014#L668-45 assume !(1 == ~t2_pc~0); 2816012#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 2816010#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2816008#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2816006#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2816004#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2816002#L687-45 assume !(1 == ~t3_pc~0); 2815999#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 2815996#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2815994#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2815992#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2815990#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2815988#L706-45 assume !(1 == ~t4_pc~0); 2815986#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 2815984#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2815982#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2815980#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2815978#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2815976#L725-45 assume !(1 == ~t5_pc~0); 2815973#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 2815970#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2815968#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2815966#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 2815964#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2815962#L744-45 assume !(1 == ~t6_pc~0); 2815959#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 2815957#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2815955#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2815953#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2815951#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2815950#L763-45 assume !(1 == ~t7_pc~0); 2815946#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 2815944#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2815943#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2815942#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2815941#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2815940#L782-45 assume !(1 == ~t8_pc~0); 2815938#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 2815935#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2815933#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2815931#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2815929#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 2815927#L801-45 assume !(1 == ~t9_pc~0); 2815925#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 2815923#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 2815920#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 2815917#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 2815915#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 2815913#L820-45 assume 1 == ~t10_pc~0; 2815910#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 2815908#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 2815879#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 2815870#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 2815866#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 2815862#L839-45 assume !(1 == ~t11_pc~0); 2815861#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 2815860#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 2815859#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 2815856#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 2815855#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 2815854#L858-45 assume 1 == ~t12_pc~0; 2815820#L859-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 2815818#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 2815816#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 2815814#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 2815812#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 2815810#L877-45 assume !(1 == ~t13_pc~0); 2815807#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 2815804#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 2815802#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 2815800#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 2815798#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 2815796#L1429-3 assume !(1 == ~T1_E~0); 2815795#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2815792#L1439-3 assume !(1 == ~T3_E~0); 2815790#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2815788#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2815786#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2815784#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2815782#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2815780#L1469-3 assume !(1 == ~T9_E~0); 2815778#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2815776#L1479-3 assume !(1 == ~T11_E~0); 2815774#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2815772#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 2815770#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2815768#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2815766#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2815764#L1509-3 assume !(1 == ~E_3~0); 2815762#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2815760#L1519-3 assume !(1 == ~E_5~0); 2815758#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2815756#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2815755#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2815754#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2815697#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2815686#L1549-3 assume !(1 == ~E_11~0); 2815676#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2815669#L1559-3 assume !(1 == ~E_13~0); 2815663#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 2814921#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 2814865#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 2814855#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 2814843#L1949 assume !(0 == start_simulation_~tmp~3); 2814837#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 2813715#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 2813694#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 2813685#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 2813676#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2813556#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 2813550#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 2809743#L1962 assume !(0 != start_simulation_~tmp___0~1); 2794240#L1930-1 [2018-11-28 12:51:22,089 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:22,089 INFO L82 PathProgramCache]: Analyzing trace with hash 1724081087, now seen corresponding path program 1 times [2018-11-28 12:51:22,089 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:22,089 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:22,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:22,090 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:22,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:22,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:22,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:22,181 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:22,181 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:22,181 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:51:22,181 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:22,181 INFO L82 PathProgramCache]: Analyzing trace with hash -815540795, now seen corresponding path program 1 times [2018-11-28 12:51:22,181 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:22,181 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:22,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:22,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:22,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:22,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:22,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:22,223 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:22,223 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:22,224 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:22,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:51:22,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:51:22,224 INFO L87 Difference]: Start difference. First operand 186791 states and 258410 transitions. cyclomatic complexity: 71747 Second operand 5 states. [2018-11-28 12:51:23,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:23,654 INFO L93 Difference]: Finished difference Result 455140 states and 632675 transitions. [2018-11-28 12:51:23,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 12:51:23,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 455140 states and 632675 transitions. [2018-11-28 12:51:24,944 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 452160 [2018-11-28 12:51:25,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 455140 states to 455140 states and 632675 transitions. [2018-11-28 12:51:25,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 455140 [2018-11-28 12:51:25,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 455140 [2018-11-28 12:51:25,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 455140 states and 632675 transitions. [2018-11-28 12:51:26,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:26,072 INFO L705 BuchiCegarLoop]: Abstraction has 455140 states and 632675 transitions. [2018-11-28 12:51:26,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 455140 states and 632675 transitions. [2018-11-28 12:51:32,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 455140 to 191594. [2018-11-28 12:51:32,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191594 states. [2018-11-28 12:51:32,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191594 states to 191594 states and 263213 transitions. [2018-11-28 12:51:32,873 INFO L728 BuchiCegarLoop]: Abstraction has 191594 states and 263213 transitions. [2018-11-28 12:51:32,873 INFO L608 BuchiCegarLoop]: Abstraction has 191594 states and 263213 transitions. [2018-11-28 12:51:32,873 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-28 12:51:32,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191594 states and 263213 transitions. [2018-11-28 12:51:33,236 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 190528 [2018-11-28 12:51:33,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:33,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:33,237 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:33,237 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:33,237 INFO L794 eck$LassoCheckResult]: Stem: 3436118#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 3436119#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 3437124#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3437174#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 3435807#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3435808#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3436643#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3436362#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3436363#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3436794#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3436795#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3437601#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3436234#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3435927#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3435928#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3436434#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3436435#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 3437151#L969-1 assume !(0 == ~M_E~0); 3436816#L1281-1 assume !(0 == ~T1_E~0); 3436817#L1286-1 assume !(0 == ~T2_E~0); 3437609#L1291-1 assume !(0 == ~T3_E~0); 3436245#L1296-1 assume !(0 == ~T4_E~0); 3435947#L1301-1 assume !(0 == ~T5_E~0); 3435948#L1306-1 assume !(0 == ~T6_E~0); 3436465#L1311-1 assume !(0 == ~T7_E~0); 3436301#L1316-1 assume !(0 == ~T8_E~0); 3436302#L1321-1 assume !(0 == ~T9_E~0); 3436893#L1326-1 assume !(0 == ~T10_E~0); 3436894#L1331-1 assume !(0 == ~T11_E~0); 3437411#L1336-1 assume !(0 == ~T12_E~0); 3436078#L1341-1 assume !(0 == ~T13_E~0); 3435889#L1346-1 assume !(0 == ~E_M~0); 3435890#L1351-1 assume !(0 == ~E_1~0); 3436390#L1356-1 assume !(0 == ~E_2~0); 3436391#L1361-1 assume !(0 == ~E_3~0); 3436992#L1366-1 assume !(0 == ~E_4~0); 3436874#L1371-1 assume !(0 == ~E_5~0); 3436875#L1376-1 assume !(0 == ~E_6~0); 3437520#L1381-1 assume !(0 == ~E_7~0); 3435976#L1386-1 assume !(0 == ~E_8~0); 3435585#L1391-1 assume !(0 == ~E_9~0); 3435586#L1396-1 assume !(0 == ~E_10~0); 3436563#L1401-1 assume !(0 == ~E_11~0); 3436564#L1406-1 assume !(0 == ~E_12~0); 3436915#L1411-1 assume !(0 == ~E_13~0); 3436916#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3437614#L630 assume !(1 == ~m_pc~0); 3437610#L630-2 is_master_triggered_~__retres1~0 := 0; 3435919#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3435637#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3435638#L1593 assume !(0 != activate_threads_~tmp~1); 3437783#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3436687#L649 assume !(1 == ~t1_pc~0); 3436635#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 3436692#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3437795#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3437367#L1601 assume !(0 != activate_threads_~tmp___0~0); 3437368#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3437374#L668 assume !(1 == ~t2_pc~0); 3437790#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 3436255#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3436221#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3435795#L1609 assume !(0 != activate_threads_~tmp___1~0); 3435796#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3435571#L687 assume !(1 == ~t3_pc~0); 3435551#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 3435552#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3436267#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3436359#L1617 assume !(0 != activate_threads_~tmp___2~0); 3436607#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3436610#L706 assume !(1 == ~t4_pc~0); 3436947#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 3436952#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3437573#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3437220#L1625 assume !(0 != activate_threads_~tmp___3~0); 3437221#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3436052#L725 assume !(1 == ~t5_pc~0); 3436027#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 3436028#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3436611#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3436705#L1633 assume !(0 != activate_threads_~tmp___4~0); 3436847#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3436854#L744 assume !(1 == ~t6_pc~0); 3437230#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 3437231#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3437713#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 3437598#L1641 assume !(0 != activate_threads_~tmp___5~0); 3437599#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3437470#L763 assume !(1 == ~t7_pc~0); 3437444#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 3435650#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3435565#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 3435566#L1649 assume !(0 != activate_threads_~tmp___6~0); 3436224#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3436229#L782 assume !(1 == ~t8_pc~0); 3436445#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 3436624#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3437138#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 3435713#L1657 assume !(0 != activate_threads_~tmp___7~0); 3435714#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 3435724#L801 assume !(1 == ~t9_pc~0); 3437764#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 3436230#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3436045#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3436046#L1665 assume !(0 != activate_threads_~tmp___8~0); 3436572#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 3435738#L820 assume !(1 == ~t10_pc~0); 3435739#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 3435742#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 3436364#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 3437170#L1673 assume !(0 != activate_threads_~tmp___9~0); 3437171#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 3437110#L839 assume !(1 == ~t11_pc~0); 3437111#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 3437113#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 3437462#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 3437463#L1681 assume !(0 != activate_threads_~tmp___10~0); 3437791#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 3436171#L858 assume !(1 == ~t12_pc~0); 3436104#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 3436105#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 3436644#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 3436645#L1689 assume !(0 != activate_threads_~tmp___11~0); 3437356#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 3437180#L877 assume !(1 == ~t13_pc~0); 3437182#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 3437186#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 3437696#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 3435804#L1697 assume !(0 != activate_threads_~tmp___12~0); 3435805#L1697-2 assume !(1 == ~M_E~0); 3435806#L1429-1 assume !(1 == ~T1_E~0); 3435875#L1434-1 assume !(1 == ~T2_E~0); 3435876#L1439-1 assume !(1 == ~T3_E~0); 3436375#L1444-1 assume !(1 == ~T4_E~0); 3436376#L1449-1 assume !(1 == ~T5_E~0); 3436980#L1454-1 assume !(1 == ~T6_E~0); 3436868#L1459-1 assume !(1 == ~T7_E~0); 3436869#L1464-1 assume !(1 == ~T8_E~0); 3437542#L1469-1 assume !(1 == ~T9_E~0); 3436010#L1474-1 assume !(1 == ~T10_E~0); 3435625#L1479-1 assume !(1 == ~T11_E~0); 3435626#L1484-1 assume !(1 == ~T12_E~0); 3436570#L1489-1 assume !(1 == ~T13_E~0); 3436571#L1494-1 assume !(1 == ~E_M~0); 3436942#L1499-1 assume !(1 == ~E_1~0); 3436943#L1504-1 assume !(1 == ~E_2~0); 3437592#L1509-1 assume !(1 == ~E_3~0); 3437481#L1514-1 assume !(1 == ~E_4~0); 3436137#L1519-1 assume !(1 == ~E_5~0); 3435771#L1524-1 assume !(1 == ~E_6~0); 3435772#L1529-1 assume !(1 == ~E_7~0); 3436288#L1534-1 assume !(1 == ~E_8~0); 3436289#L1539-1 assume !(1 == ~E_9~0); 3437074#L1544-1 assume !(1 == ~E_10~0); 3437075#L1549-1 assume !(1 == ~E_11~0); 3437564#L1554-1 assume !(1 == ~E_12~0); 3436183#L1559-1 assume !(1 == ~E_13~0); 3436184#L1930-1 [2018-11-28 12:51:33,238 INFO L796 eck$LassoCheckResult]: Loop: 3436184#L1930-1 assume !false; 3466551#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 3466545#L1256 assume !false; 3466543#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 3466523#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 3466516#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 3466514#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3466511#L1069 assume !(0 != eval_~tmp~0); 3466512#L1271 start_simulation_~kernel_st~0 := 2; 3480251#L897-1 start_simulation_~kernel_st~0 := 3; 3480246#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3480241#L1281-4 assume !(0 == ~T1_E~0); 3480237#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3480233#L1291-3 assume !(0 == ~T3_E~0); 3480216#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3480160#L1301-3 assume !(0 == ~T5_E~0); 3480155#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3480149#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3480143#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3480139#L1321-3 assume !(0 == ~T9_E~0); 3480134#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3480066#L1331-3 assume !(0 == ~T11_E~0); 3480062#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3480058#L1341-3 assume !(0 == ~T13_E~0); 3480053#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3480047#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3480042#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3480037#L1361-3 assume !(0 == ~E_3~0); 3480032#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3480026#L1371-3 assume !(0 == ~E_5~0); 3480018#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3480014#L1381-3 assume !(0 == ~E_7~0); 3480008#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3480002#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3479998#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3479995#L1401-3 assume !(0 == ~E_11~0); 3479991#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 3479974#L1411-3 assume !(0 == ~E_13~0); 3479918#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3479917#L630-45 assume !(1 == ~m_pc~0); 3479916#L630-47 is_master_triggered_~__retres1~0 := 0; 3479915#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3479914#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3479913#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3479912#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3479911#L649-45 assume 1 == ~t1_pc~0; 3479909#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3479907#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3479905#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3479903#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3479902#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3479901#L668-45 assume !(1 == ~t2_pc~0); 3479900#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 3479899#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3479898#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3479897#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3479896#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3479895#L687-45 assume !(1 == ~t3_pc~0); 3479893#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 3479892#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3479891#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3479890#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3479889#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3479888#L706-45 assume !(1 == ~t4_pc~0); 3479887#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 3479886#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3479885#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3479884#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3479883#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3479882#L725-45 assume !(1 == ~t5_pc~0); 3479880#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 3479879#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3479878#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3479877#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 3479876#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3479875#L744-45 assume !(1 == ~t6_pc~0); 3479874#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 3479873#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3479872#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 3479871#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3479870#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3479869#L763-45 assume !(1 == ~t7_pc~0); 3479868#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 3479867#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3479866#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 3479865#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3479864#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3479863#L782-45 assume 1 == ~t8_pc~0; 3479861#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3479859#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3479857#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 3479855#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 3479850#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 3479845#L801-45 assume !(1 == ~t9_pc~0); 3479839#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 3479834#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3479829#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3479824#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 3479820#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 3479816#L820-45 assume !(1 == ~t10_pc~0); 3479748#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 3466715#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 3466713#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 3466711#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 3466709#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 3466707#L839-45 assume !(1 == ~t11_pc~0); 3466705#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 3466703#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 3466701#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 3466699#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 3466696#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 3466694#L858-45 assume !(1 == ~t12_pc~0); 3466692#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 3466689#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 3466687#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 3466685#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 3466683#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 3466681#L877-45 assume !(1 == ~t13_pc~0); 3466678#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 3466676#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 3466674#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 3466672#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 3466669#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 3466667#L1429-3 assume !(1 == ~T1_E~0); 3466665#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3466663#L1439-3 assume !(1 == ~T3_E~0); 3466661#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3466658#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3466656#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3466654#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3466652#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3466650#L1469-3 assume !(1 == ~T9_E~0); 3466648#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3466646#L1479-3 assume !(1 == ~T11_E~0); 3466644#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 3466642#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 3466640#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3466638#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3466636#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3466634#L1509-3 assume !(1 == ~E_3~0); 3466632#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3466630#L1519-3 assume !(1 == ~E_5~0); 3466628#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3466626#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3466624#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3466622#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3466620#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3466618#L1549-3 assume !(1 == ~E_11~0); 3466616#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3466614#L1559-3 assume !(1 == ~E_13~0); 3466612#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 3466604#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 3466591#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 3466589#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 3466585#L1949 assume !(0 == start_simulation_~tmp~3); 3466584#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 3466576#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 3466564#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 3466562#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 3466560#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3466558#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 3466556#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 3466554#L1962 assume !(0 != start_simulation_~tmp___0~1); 3436184#L1930-1 [2018-11-28 12:51:33,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:33,238 INFO L82 PathProgramCache]: Analyzing trace with hash -2010186431, now seen corresponding path program 1 times [2018-11-28 12:51:33,238 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:33,238 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:33,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:33,239 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:33,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:33,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:51:33,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:51:33,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:33,342 INFO L82 PathProgramCache]: Analyzing trace with hash -891308188, now seen corresponding path program 1 times [2018-11-28 12:51:33,342 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:33,342 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:33,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:33,342 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:33,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:33,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:33,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:33,386 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:33,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:33,386 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:33,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:51:33,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:51:33,386 INFO L87 Difference]: Start difference. First operand 191594 states and 263213 transitions. cyclomatic complexity: 71747 Second operand 5 states. [2018-11-28 12:51:34,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:34,166 INFO L93 Difference]: Finished difference Result 359786 states and 490093 transitions. [2018-11-28 12:51:34,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 12:51:34,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 359786 states and 490093 transitions. [2018-11-28 12:51:35,113 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 357824 [2018-11-28 12:51:35,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 359786 states to 359786 states and 490093 transitions. [2018-11-28 12:51:35,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 359786 [2018-11-28 12:51:35,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 359786 [2018-11-28 12:51:35,848 INFO L73 IsDeterministic]: Start isDeterministic. Operand 359786 states and 490093 transitions. [2018-11-28 12:51:36,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:36,745 INFO L705 BuchiCegarLoop]: Abstraction has 359786 states and 490093 transitions. [2018-11-28 12:51:36,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 359786 states and 490093 transitions. [2018-11-28 12:51:38,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 359786 to 191978. [2018-11-28 12:51:38,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191978 states. [2018-11-28 12:51:38,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191978 states to 191978 states and 263597 transitions. [2018-11-28 12:51:38,325 INFO L728 BuchiCegarLoop]: Abstraction has 191978 states and 263597 transitions. [2018-11-28 12:51:38,325 INFO L608 BuchiCegarLoop]: Abstraction has 191978 states and 263597 transitions. [2018-11-28 12:51:38,325 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-28 12:51:38,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191978 states and 263597 transitions. [2018-11-28 12:51:38,696 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 190912 [2018-11-28 12:51:38,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:38,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:38,698 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:38,698 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:38,699 INFO L794 eck$LassoCheckResult]: Stem: 3987518#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 3987519#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 3988470#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3988519#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 3987202#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3987203#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3988019#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3987759#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3987760#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3988172#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3988173#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3988953#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3987634#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3987329#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3987330#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3987831#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3987832#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 3988493#L969-1 assume !(0 == ~M_E~0); 3988194#L1281-1 assume !(0 == ~T1_E~0); 3988195#L1286-1 assume !(0 == ~T2_E~0); 3988966#L1291-1 assume !(0 == ~T3_E~0); 3987644#L1296-1 assume !(0 == ~T4_E~0); 3987350#L1301-1 assume !(0 == ~T5_E~0); 3987351#L1306-1 assume !(0 == ~T6_E~0); 3987852#L1311-1 assume !(0 == ~T7_E~0); 3987698#L1316-1 assume !(0 == ~T8_E~0); 3987699#L1321-1 assume !(0 == ~T9_E~0); 3988274#L1326-1 assume !(0 == ~T10_E~0); 3988275#L1331-1 assume !(0 == ~T11_E~0); 3988750#L1336-1 assume !(0 == ~T12_E~0); 3987479#L1341-1 assume !(0 == ~T13_E~0); 3987289#L1346-1 assume !(0 == ~E_M~0); 3987290#L1351-1 assume !(0 == ~E_1~0); 3987789#L1356-1 assume !(0 == ~E_2~0); 3987790#L1361-1 assume !(0 == ~E_3~0); 3988363#L1366-1 assume !(0 == ~E_4~0); 3988254#L1371-1 assume !(0 == ~E_5~0); 3988255#L1376-1 assume !(0 == ~E_6~0); 3988873#L1381-1 assume !(0 == ~E_7~0); 3987376#L1386-1 assume !(0 == ~E_8~0); 3986981#L1391-1 assume !(0 == ~E_9~0); 3986982#L1396-1 assume !(0 == ~E_10~0); 3987945#L1401-1 assume !(0 == ~E_11~0); 3987946#L1406-1 assume !(0 == ~E_12~0); 3988295#L1411-1 assume !(0 == ~E_13~0); 3988296#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3988970#L630 assume !(1 == ~m_pc~0); 3988967#L630-2 is_master_triggered_~__retres1~0 := 0; 3987320#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3987034#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3987035#L1593 assume !(0 != activate_threads_~tmp~1); 3989177#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3988068#L649 assume !(1 == ~t1_pc~0); 3988011#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 3988072#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3988513#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3988704#L1601 assume !(0 != activate_threads_~tmp___0~0); 3988705#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3988711#L668 assume !(1 == ~t2_pc~0); 3989184#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 3987652#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3987621#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3987190#L1609 assume !(0 != activate_threads_~tmp___1~0); 3987191#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3986967#L687 assume !(1 == ~t3_pc~0); 3986947#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 3986948#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3987664#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3987755#L1617 assume !(0 != activate_threads_~tmp___2~0); 3987985#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3987988#L706 assume !(1 == ~t4_pc~0); 3988323#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 3988326#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3988923#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3988566#L1625 assume !(0 != activate_threads_~tmp___3~0); 3988567#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3987452#L725 assume !(1 == ~t5_pc~0); 3987427#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 3987428#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3987989#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3988083#L1633 assume !(0 != activate_threads_~tmp___4~0); 3988226#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3988233#L744 assume !(1 == ~t6_pc~0); 3988575#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 3988576#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3989099#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 3988948#L1641 assume !(0 != activate_threads_~tmp___5~0); 3988949#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3988822#L763 assume !(1 == ~t7_pc~0); 3988795#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 3987047#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3986961#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 3986962#L1649 assume !(0 != activate_threads_~tmp___6~0); 3987624#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3987629#L782 assume !(1 == ~t8_pc~0); 3987838#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 3988003#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3988330#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 3987111#L1657 assume !(0 != activate_threads_~tmp___7~0); 3987112#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 3987122#L801 assume !(1 == ~t9_pc~0); 3989156#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 3987630#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3987445#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3987446#L1665 assume !(0 != activate_threads_~tmp___8~0); 3987952#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 3987136#L820 assume !(1 == ~t10_pc~0); 3987137#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 3987140#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 3987761#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 3988514#L1673 assume !(0 != activate_threads_~tmp___9~0); 3988515#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 3988461#L839 assume !(1 == ~t11_pc~0); 3988462#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 3988463#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 3988815#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 3988816#L1681 assume !(0 != activate_threads_~tmp___10~0); 3989185#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 3987570#L858 assume !(1 == ~t12_pc~0); 3987504#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 3987505#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 3988020#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 3988021#L1689 assume !(0 != activate_threads_~tmp___11~0); 3988693#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 3988526#L877 assume !(1 == ~t13_pc~0); 3988528#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 3988532#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 3989080#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 3987199#L1697 assume !(0 != activate_threads_~tmp___12~0); 3987200#L1697-2 assume !(1 == ~M_E~0); 3987201#L1429-1 assume !(1 == ~T1_E~0); 3987275#L1434-1 assume !(1 == ~T2_E~0); 3987276#L1439-1 assume !(1 == ~T3_E~0); 3987775#L1444-1 assume !(1 == ~T4_E~0); 3987776#L1449-1 assume !(1 == ~T5_E~0); 3988352#L1454-1 assume !(1 == ~T6_E~0); 3988248#L1459-1 assume !(1 == ~T7_E~0); 3988249#L1464-1 assume !(1 == ~T8_E~0); 3988893#L1469-1 assume !(1 == ~T9_E~0); 3987409#L1474-1 assume !(1 == ~T10_E~0); 3987021#L1479-1 assume !(1 == ~T11_E~0); 3987022#L1484-1 assume !(1 == ~T12_E~0); 3987950#L1489-1 assume !(1 == ~T13_E~0); 3987951#L1494-1 assume !(1 == ~E_M~0); 3988318#L1499-1 assume !(1 == ~E_1~0); 3988319#L1504-1 assume !(1 == ~E_2~0); 3988942#L1509-1 assume !(1 == ~E_3~0); 3988836#L1514-1 assume !(1 == ~E_4~0); 3987537#L1519-1 assume !(1 == ~E_5~0); 3987168#L1524-1 assume !(1 == ~E_6~0); 3987169#L1529-1 assume !(1 == ~E_7~0); 3987685#L1534-1 assume !(1 == ~E_8~0); 3987686#L1539-1 assume !(1 == ~E_9~0); 3988431#L1544-1 assume !(1 == ~E_10~0); 3988432#L1549-1 assume !(1 == ~E_11~0); 3988913#L1554-1 assume !(1 == ~E_12~0); 3987582#L1559-1 assume !(1 == ~E_13~0); 3987583#L1930-1 [2018-11-28 12:51:38,699 INFO L796 eck$LassoCheckResult]: Loop: 3987583#L1930-1 assume !false; 4027747#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 4027678#L1256 assume !false; 4027306#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4027292#L982 assume !(0 == ~m_st~0); 4027293#L986 assume !(0 == ~t1_st~0); 4027296#L990 assume !(0 == ~t2_st~0); 4027298#L994 assume !(0 == ~t3_st~0); 4027300#L998 assume !(0 == ~t4_st~0); 4027287#L1002 assume !(0 == ~t5_st~0); 4027288#L1006 assume !(0 == ~t6_st~0); 4027291#L1010 assume !(0 == ~t7_st~0); 4027295#L1014 assume !(0 == ~t8_st~0); 4027297#L1018 assume !(0 == ~t9_st~0); 4027299#L1022 assume !(0 == ~t10_st~0); 4027301#L1026 assume !(0 == ~t11_st~0); 4027289#L1030 assume !(0 == ~t12_st~0); 4027290#L1034 assume !(0 == ~t13_st~0);exists_runnable_thread_~__retres1~14 := 0; 4027294#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4000918#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4000919#L1069 assume !(0 != eval_~tmp~0); 4028255#L1271 start_simulation_~kernel_st~0 := 2; 4028254#L897-1 start_simulation_~kernel_st~0 := 3; 4028253#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4028252#L1281-4 assume !(0 == ~T1_E~0); 4028251#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4028250#L1291-3 assume !(0 == ~T3_E~0); 4028249#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4028248#L1301-3 assume !(0 == ~T5_E~0); 4028247#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4028246#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4028245#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4028244#L1321-3 assume !(0 == ~T9_E~0); 4028243#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4028242#L1331-3 assume !(0 == ~T11_E~0); 4028241#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4028240#L1341-3 assume !(0 == ~T13_E~0); 4028239#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4028238#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4028237#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4028236#L1361-3 assume !(0 == ~E_3~0); 4028235#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4028234#L1371-3 assume !(0 == ~E_5~0); 4028233#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4028232#L1381-3 assume !(0 == ~E_7~0); 4028231#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4028230#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4028229#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4028228#L1401-3 assume !(0 == ~E_11~0); 4028227#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4028226#L1411-3 assume !(0 == ~E_13~0); 4028225#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4028224#L630-45 assume !(1 == ~m_pc~0); 4028223#L630-47 is_master_triggered_~__retres1~0 := 0; 4028222#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4028221#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4028220#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4028219#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4028218#L649-45 assume !(1 == ~t1_pc~0); 4028217#L649-47 is_transmit1_triggered_~__retres1~1 := 0; 4028215#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4028213#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4028211#L1601-45 assume !(0 != activate_threads_~tmp___0~0); 4028209#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4028208#L668-45 assume !(1 == ~t2_pc~0); 4028207#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 4028206#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4028205#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4028204#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4028203#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4028202#L687-45 assume !(1 == ~t3_pc~0); 4028200#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 4028199#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4028198#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4028197#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4028196#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4028195#L706-45 assume !(1 == ~t4_pc~0); 4028194#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 4028193#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4028192#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4028191#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4028190#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4028189#L725-45 assume !(1 == ~t5_pc~0); 4028187#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 4028186#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4028185#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4028184#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 4028183#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4028182#L744-45 assume !(1 == ~t6_pc~0); 4028181#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 4028180#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4028179#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4028178#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4028177#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4028176#L763-45 assume !(1 == ~t7_pc~0); 4028175#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 4028174#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4028173#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4028172#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4028171#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4028170#L782-45 assume !(1 == ~t8_pc~0); 4028169#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 4028167#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4028165#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4028163#L1657-45 assume !(0 != activate_threads_~tmp___7~0); 4028161#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4028160#L801-45 assume !(1 == ~t9_pc~0); 4028159#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 4028158#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4028157#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4028156#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 4028155#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4028154#L820-45 assume !(1 == ~t10_pc~0); 4028153#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 4028151#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 4028150#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4028149#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 4028148#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 4028147#L839-45 assume !(1 == ~t11_pc~0); 4028146#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 4028145#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 4028144#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4028143#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 4028142#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 4028141#L858-45 assume !(1 == ~t12_pc~0); 4028140#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 4028138#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4028137#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 4028136#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 4028135#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 4028134#L877-45 assume !(1 == ~t13_pc~0); 4028132#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 4028131#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 4028130#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4028129#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 4028128#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 4028127#L1429-3 assume !(1 == ~T1_E~0); 4028126#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4028125#L1439-3 assume !(1 == ~T3_E~0); 4028124#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4028123#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4028122#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4028121#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4028120#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4028119#L1469-3 assume !(1 == ~T9_E~0); 4028118#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4028117#L1479-3 assume !(1 == ~T11_E~0); 4028116#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4028115#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4028114#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4028113#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4028112#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4028111#L1509-3 assume !(1 == ~E_3~0); 4028110#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4028109#L1519-3 assume !(1 == ~E_5~0); 4028108#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4028107#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4028106#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4028105#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4028104#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4028103#L1549-3 assume !(1 == ~E_11~0); 4028102#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4028101#L1559-3 assume !(1 == ~E_13~0); 4028100#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4028097#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4028082#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4028078#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 4028074#L1949 assume !(0 == start_simulation_~tmp~3); 4028072#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4028068#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4028056#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4027789#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 4027773#L1904 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4027771#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 4027770#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 4027754#L1962 assume !(0 != start_simulation_~tmp___0~1); 3987583#L1930-1 [2018-11-28 12:51:38,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:38,700 INFO L82 PathProgramCache]: Analyzing trace with hash -2010186431, now seen corresponding path program 2 times [2018-11-28 12:51:38,700 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:38,700 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:38,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:38,700 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:38,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:38,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:51:38,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:51:38,766 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:38,766 INFO L82 PathProgramCache]: Analyzing trace with hash 700801379, now seen corresponding path program 1 times [2018-11-28 12:51:38,767 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:38,767 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:38,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:38,767 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:51:38,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:38,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:38,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:38,829 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:38,829 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:38,830 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:38,830 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:51:38,830 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:51:38,830 INFO L87 Difference]: Start difference. First operand 191978 states and 263597 transitions. cyclomatic complexity: 71747 Second operand 5 states. [2018-11-28 12:51:40,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:40,387 INFO L93 Difference]: Finished difference Result 710442 states and 965229 transitions. [2018-11-28 12:51:40,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 12:51:40,387 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 710442 states and 965229 transitions. [2018-11-28 12:51:42,978 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 706688 [2018-11-28 12:51:43,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 710442 states to 710442 states and 965229 transitions. [2018-11-28 12:51:43,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 710442 [2018-11-28 12:51:44,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 710442 [2018-11-28 12:51:44,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 710442 states and 965229 transitions. [2018-11-28 12:51:50,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:50,578 INFO L705 BuchiCegarLoop]: Abstraction has 710442 states and 965229 transitions. [2018-11-28 12:51:50,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 710442 states and 965229 transitions. [2018-11-28 12:51:53,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 710442 to 192362. [2018-11-28 12:51:53,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192362 states. [2018-11-28 12:51:53,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192362 states to 192362 states and 263981 transitions. [2018-11-28 12:51:53,205 INFO L728 BuchiCegarLoop]: Abstraction has 192362 states and 263981 transitions. [2018-11-28 12:51:53,205 INFO L608 BuchiCegarLoop]: Abstraction has 192362 states and 263981 transitions. [2018-11-28 12:51:53,205 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-11-28 12:51:53,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192362 states and 263981 transitions. [2018-11-28 12:51:53,567 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 191296 [2018-11-28 12:51:53,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:53,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:53,569 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:53,569 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:53,569 INFO L794 eck$LassoCheckResult]: Stem: 4889949#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4889950#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4890894#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4890939#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 4889639#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4889640#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4890446#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4890193#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4890194#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4890593#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4890594#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4891365#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4890067#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4889760#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4889761#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4890262#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 4890263#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 4890917#L969-1 assume !(0 == ~M_E~0); 4890615#L1281-1 assume !(0 == ~T1_E~0); 4890616#L1286-1 assume !(0 == ~T2_E~0); 4891374#L1291-1 assume !(0 == ~T3_E~0); 4890078#L1296-1 assume !(0 == ~T4_E~0); 4889779#L1301-1 assume !(0 == ~T5_E~0); 4889780#L1306-1 assume !(0 == ~T6_E~0); 4890283#L1311-1 assume !(0 == ~T7_E~0); 4890133#L1316-1 assume !(0 == ~T8_E~0); 4890134#L1321-1 assume !(0 == ~T9_E~0); 4890694#L1326-1 assume !(0 == ~T10_E~0); 4890695#L1331-1 assume !(0 == ~T11_E~0); 4891168#L1336-1 assume !(0 == ~T12_E~0); 4889908#L1341-1 assume !(0 == ~T13_E~0); 4889721#L1346-1 assume !(0 == ~E_M~0); 4889722#L1351-1 assume !(0 == ~E_1~0); 4890220#L1356-1 assume !(0 == ~E_2~0); 4890221#L1361-1 assume !(0 == ~E_3~0); 4890785#L1366-1 assume !(0 == ~E_4~0); 4890675#L1371-1 assume !(0 == ~E_5~0); 4890676#L1376-1 assume !(0 == ~E_6~0); 4891285#L1381-1 assume !(0 == ~E_7~0); 4889806#L1386-1 assume !(0 == ~E_8~0); 4889418#L1391-1 assume !(0 == ~E_9~0); 4889419#L1396-1 assume !(0 == ~E_10~0); 4890374#L1401-1 assume !(0 == ~E_11~0); 4890375#L1406-1 assume !(0 == ~E_12~0); 4890718#L1411-1 assume !(0 == ~E_13~0); 4890719#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4891378#L630 assume !(1 == ~m_pc~0); 4891375#L630-2 is_master_triggered_~__retres1~0 := 0; 4889751#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4889470#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4889471#L1593 assume !(0 != activate_threads_~tmp~1); 4891576#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4890493#L649 assume !(1 == ~t1_pc~0); 4890438#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 4890497#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4890935#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4891117#L1601 assume !(0 != activate_threads_~tmp___0~0); 4891118#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4891125#L668 assume !(1 == ~t2_pc~0); 4891580#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 4890086#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4890053#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4889627#L1609 assume !(0 != activate_threads_~tmp___1~0); 4889628#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4889404#L687 assume !(1 == ~t3_pc~0); 4889384#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 4889385#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4890098#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4890190#L1617 assume !(0 != activate_threads_~tmp___2~0); 4890414#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4890417#L706 assume !(1 == ~t4_pc~0); 4890744#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 4890748#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4891335#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4890985#L1625 assume !(0 != activate_threads_~tmp___3~0); 4890986#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4889882#L725 assume !(1 == ~t5_pc~0); 4889857#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 4889858#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4890418#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4890506#L1633 assume !(0 != activate_threads_~tmp___4~0); 4890647#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4890655#L744 assume !(1 == ~t6_pc~0); 4890994#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 4890995#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4891501#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4891361#L1641 assume !(0 != activate_threads_~tmp___5~0); 4891362#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4891235#L763 assume !(1 == ~t7_pc~0); 4891207#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 4889483#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4889398#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4889399#L1649 assume !(0 != activate_threads_~tmp___6~0); 4890056#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4890062#L782 assume !(1 == ~t8_pc~0); 4890269#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 4890430#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4890752#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4889547#L1657 assume !(0 != activate_threads_~tmp___7~0); 4889548#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4889558#L801 assume !(1 == ~t9_pc~0); 4891556#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 4890063#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4889875#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4889876#L1665 assume !(0 != activate_threads_~tmp___8~0); 4890383#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4889572#L820 assume !(1 == ~t10_pc~0); 4889573#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 4889576#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 4890195#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4890936#L1673 assume !(0 != activate_threads_~tmp___9~0); 4890937#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 4890886#L839 assume !(1 == ~t11_pc~0); 4890887#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 4890888#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 4891228#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4891229#L1681 assume !(0 != activate_threads_~tmp___10~0); 4891581#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 4890002#L858 assume !(1 == ~t12_pc~0); 4889935#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 4889936#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4890447#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 4890448#L1689 assume !(0 != activate_threads_~tmp___11~0); 4891107#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 4890946#L877 assume !(1 == ~t13_pc~0); 4890948#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 4890952#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 4891483#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4889636#L1697 assume !(0 != activate_threads_~tmp___12~0); 4889637#L1697-2 assume !(1 == ~M_E~0); 4889638#L1429-1 assume !(1 == ~T1_E~0); 4889707#L1434-1 assume !(1 == ~T2_E~0); 4889708#L1439-1 assume !(1 == ~T3_E~0); 4890206#L1444-1 assume !(1 == ~T4_E~0); 4890207#L1449-1 assume !(1 == ~T5_E~0); 4890774#L1454-1 assume !(1 == ~T6_E~0); 4890669#L1459-1 assume !(1 == ~T7_E~0); 4890670#L1464-1 assume !(1 == ~T8_E~0); 4891306#L1469-1 assume !(1 == ~T9_E~0); 4889839#L1474-1 assume !(1 == ~T10_E~0); 4889458#L1479-1 assume !(1 == ~T11_E~0); 4889459#L1484-1 assume !(1 == ~T12_E~0); 4890381#L1489-1 assume !(1 == ~T13_E~0); 4890382#L1494-1 assume !(1 == ~E_M~0); 4890739#L1499-1 assume !(1 == ~E_1~0); 4890740#L1504-1 assume !(1 == ~E_2~0); 4891356#L1509-1 assume !(1 == ~E_3~0); 4891246#L1514-1 assume !(1 == ~E_4~0); 4889967#L1519-1 assume !(1 == ~E_5~0); 4889605#L1524-1 assume !(1 == ~E_6~0); 4889606#L1529-1 assume !(1 == ~E_7~0); 4890119#L1534-1 assume !(1 == ~E_8~0); 4890120#L1539-1 assume !(1 == ~E_9~0); 4890858#L1544-1 assume !(1 == ~E_10~0); 4890859#L1549-1 assume !(1 == ~E_11~0); 4891326#L1554-1 assume !(1 == ~E_12~0); 4890013#L1559-1 assume !(1 == ~E_13~0); 4890014#L1930-1 [2018-11-28 12:51:53,570 INFO L796 eck$LassoCheckResult]: Loop: 4890014#L1930-1 assume !false; 4912262#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 4912249#L1256 assume !false; 4912240#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4912230#L982 assume !(0 == ~m_st~0); 4912231#L986 assume !(0 == ~t1_st~0); 4912234#L990 assume !(0 == ~t2_st~0); 4912236#L994 assume !(0 == ~t3_st~0); 4912238#L998 assume !(0 == ~t4_st~0); 4912225#L1002 assume !(0 == ~t5_st~0); 4912226#L1006 assume !(0 == ~t6_st~0); 4912229#L1010 assume !(0 == ~t7_st~0); 4912233#L1014 assume !(0 == ~t8_st~0); 4912235#L1018 assume !(0 == ~t9_st~0); 4912237#L1022 assume !(0 == ~t10_st~0); 4912239#L1026 assume !(0 == ~t11_st~0); 4912227#L1030 assume !(0 == ~t12_st~0); 4912228#L1034 assume !(0 == ~t13_st~0);exists_runnable_thread_~__retres1~14 := 0; 4912232#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4912130#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4912131#L1069 assume !(0 != eval_~tmp~0); 4912553#L1271 start_simulation_~kernel_st~0 := 2; 4912552#L897-1 start_simulation_~kernel_st~0 := 3; 4912551#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4912550#L1281-4 assume !(0 == ~T1_E~0); 4912549#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4912548#L1291-3 assume !(0 == ~T3_E~0); 4912547#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4912546#L1301-3 assume !(0 == ~T5_E~0); 4912545#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4912544#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4912543#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4912542#L1321-3 assume !(0 == ~T9_E~0); 4912541#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4912540#L1331-3 assume !(0 == ~T11_E~0); 4912539#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4912538#L1341-3 assume !(0 == ~T13_E~0); 4912537#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4912536#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4912535#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4912534#L1361-3 assume !(0 == ~E_3~0); 4912533#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4912532#L1371-3 assume !(0 == ~E_5~0); 4912531#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4912530#L1381-3 assume !(0 == ~E_7~0); 4912529#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4912528#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4912527#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4912526#L1401-3 assume !(0 == ~E_11~0); 4912525#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4912524#L1411-3 assume !(0 == ~E_13~0); 4912523#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4912522#L630-45 assume !(1 == ~m_pc~0); 4912521#L630-47 is_master_triggered_~__retres1~0 := 0; 4912520#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4912519#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4912518#L1593-45 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4912517#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4912516#L649-45 assume 1 == ~t1_pc~0; 4912514#L650-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4912512#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4912510#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4912508#L1601-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4912507#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4912506#L668-45 assume !(1 == ~t2_pc~0); 4912505#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 4912504#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4912503#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4912502#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4912501#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4912500#L687-45 assume !(1 == ~t3_pc~0); 4912498#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 4912497#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4912496#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4912495#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4912494#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4912493#L706-45 assume !(1 == ~t4_pc~0); 4912492#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 4912491#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4912490#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4912489#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4912488#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4912487#L725-45 assume !(1 == ~t5_pc~0); 4912485#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 4912484#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4912483#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4912482#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 4912481#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4912480#L744-45 assume !(1 == ~t6_pc~0); 4912479#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 4912478#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4912477#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4912476#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4912475#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4912474#L763-45 assume !(1 == ~t7_pc~0); 4912473#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 4912472#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4912471#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4912470#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4912469#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4912468#L782-45 assume 1 == ~t8_pc~0; 4912466#L783-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4912464#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4912462#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4912460#L1657-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4912459#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4912458#L801-45 assume !(1 == ~t9_pc~0); 4912457#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 4912456#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4912455#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4912454#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 4912453#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4912452#L820-45 assume 1 == ~t10_pc~0; 4912450#L821-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 4912449#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 4912448#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4912447#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 4912446#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 4912445#L839-45 assume !(1 == ~t11_pc~0); 4912444#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 4912443#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 4912442#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4912441#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 4912440#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 4912439#L858-45 assume !(1 == ~t12_pc~0); 4912438#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 4912436#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4912435#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 4912434#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 4912433#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 4912432#L877-45 assume !(1 == ~t13_pc~0); 4912430#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 4912429#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 4912428#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4912427#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 4912426#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 4912425#L1429-3 assume !(1 == ~T1_E~0); 4912424#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4912423#L1439-3 assume !(1 == ~T3_E~0); 4912422#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4912421#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4912420#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4912419#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4912418#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4912417#L1469-3 assume !(1 == ~T9_E~0); 4912416#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4912415#L1479-3 assume !(1 == ~T11_E~0); 4912414#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4912413#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4912412#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4912411#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4912410#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4912409#L1509-3 assume !(1 == ~E_3~0); 4912408#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4912407#L1519-3 assume !(1 == ~E_5~0); 4912406#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4912405#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4912404#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4912403#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4912402#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4912401#L1549-3 assume !(1 == ~E_11~0); 4912400#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4912399#L1559-3 assume !(1 == ~E_13~0); 4912398#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4912395#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4912382#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4912380#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 4912292#L1949 assume !(0 == start_simulation_~tmp~3); 4912286#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4912282#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4912271#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4912269#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 4912267#L1904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4912265#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 4912264#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 4912263#L1962 assume !(0 != start_simulation_~tmp___0~1); 4890014#L1930-1 [2018-11-28 12:51:53,570 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:53,570 INFO L82 PathProgramCache]: Analyzing trace with hash -2010186431, now seen corresponding path program 3 times [2018-11-28 12:51:53,570 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:53,570 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:53,571 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:53,571 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:53,571 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:53,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:51:53,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:51:53,630 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:53,630 INFO L82 PathProgramCache]: Analyzing trace with hash -1284826996, now seen corresponding path program 1 times [2018-11-28 12:51:53,630 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:53,630 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:53,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:53,631 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:51:53,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:53,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:53,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:53,689 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:53,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 12:51:53,689 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:53,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 12:51:53,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 12:51:53,698 INFO L87 Difference]: Start difference. First operand 192362 states and 263981 transitions. cyclomatic complexity: 71747 Second operand 5 states. [2018-11-28 12:51:54,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:51:54,997 INFO L93 Difference]: Finished difference Result 384874 states and 526220 transitions. [2018-11-28 12:51:54,997 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 12:51:54,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384874 states and 526220 transitions. [2018-11-28 12:51:55,938 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 383040 [2018-11-28 12:51:56,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384874 states to 384874 states and 526220 transitions. [2018-11-28 12:51:56,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384874 [2018-11-28 12:51:56,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384874 [2018-11-28 12:51:56,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384874 states and 526220 transitions. [2018-11-28 12:51:56,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:51:56,768 INFO L705 BuchiCegarLoop]: Abstraction has 384874 states and 526220 transitions. [2018-11-28 12:51:56,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384874 states and 526220 transitions. [2018-11-28 12:51:58,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384874 to 194858. [2018-11-28 12:51:58,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194858 states. [2018-11-28 12:51:59,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194858 states to 194858 states and 265708 transitions. [2018-11-28 12:51:59,078 INFO L728 BuchiCegarLoop]: Abstraction has 194858 states and 265708 transitions. [2018-11-28 12:51:59,078 INFO L608 BuchiCegarLoop]: Abstraction has 194858 states and 265708 transitions. [2018-11-28 12:51:59,078 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2018-11-28 12:51:59,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194858 states and 265708 transitions. [2018-11-28 12:51:59,440 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 193792 [2018-11-28 12:51:59,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:51:59,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:51:59,441 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:59,442 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:51:59,442 INFO L794 eck$LassoCheckResult]: Stem: 5467211#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 5467212#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5468164#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5468207#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 5466888#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5466889#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5467716#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5467458#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5467459#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5467869#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5467870#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5468674#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5467328#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5467024#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5467025#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 5467530#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 5467531#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 5468188#L969-1 assume !(0 == ~M_E~0); 5467891#L1281-1 assume !(0 == ~T1_E~0); 5467892#L1286-1 assume !(0 == ~T2_E~0); 5468684#L1291-1 assume !(0 == ~T3_E~0); 5467337#L1296-1 assume !(0 == ~T4_E~0); 5467045#L1301-1 assume !(0 == ~T5_E~0); 5467046#L1306-1 assume !(0 == ~T6_E~0); 5467552#L1311-1 assume !(0 == ~T7_E~0); 5467396#L1316-1 assume !(0 == ~T8_E~0); 5467397#L1321-1 assume !(0 == ~T9_E~0); 5467969#L1326-1 assume !(0 == ~T10_E~0); 5467970#L1331-1 assume !(0 == ~T11_E~0); 5468453#L1336-1 assume !(0 == ~T12_E~0); 5467172#L1341-1 assume !(0 == ~T13_E~0); 5466977#L1346-1 assume !(0 == ~E_M~0); 5466978#L1351-1 assume !(0 == ~E_1~0); 5467488#L1356-1 assume !(0 == ~E_2~0); 5467489#L1361-1 assume !(0 == ~E_3~0); 5468059#L1366-1 assume !(0 == ~E_4~0); 5467949#L1371-1 assume !(0 == ~E_5~0); 5467950#L1376-1 assume !(0 == ~E_6~0); 5468583#L1381-1 assume !(0 == ~E_7~0); 5467071#L1386-1 assume !(0 == ~E_8~0); 5466667#L1391-1 assume !(0 == ~E_9~0); 5466668#L1396-1 assume !(0 == ~E_10~0); 5467644#L1401-1 assume !(0 == ~E_11~0); 5467645#L1406-1 assume !(0 == ~E_12~0); 5467991#L1411-1 assume !(0 == ~E_13~0); 5467992#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5468690#L630 assume !(1 == ~m_pc~0); 5468685#L630-2 is_master_triggered_~__retres1~0 := 0; 5467013#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5466719#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5466720#L1593 assume !(0 != activate_threads_~tmp~1); 5468894#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5467764#L649 assume !(1 == ~t1_pc~0); 5467709#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 5467768#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5468203#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5468401#L1601 assume !(0 != activate_threads_~tmp___0~0); 5468402#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5468408#L668 assume !(1 == ~t2_pc~0); 5468898#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 5467349#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5467315#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5466876#L1609 assume !(0 != activate_threads_~tmp___1~0); 5466877#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5466653#L687 assume !(1 == ~t3_pc~0); 5466633#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 5466634#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5467361#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5467455#L1617 assume !(0 != activate_threads_~tmp___2~0); 5467682#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5467685#L706 assume !(1 == ~t4_pc~0); 5468019#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 5468022#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5468644#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5468247#L1625 assume !(0 != activate_threads_~tmp___3~0); 5468248#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5467147#L725 assume !(1 == ~t5_pc~0); 5467121#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 5467122#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5467686#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5467780#L1633 assume !(0 != activate_threads_~tmp___4~0); 5467920#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5467928#L744 assume !(1 == ~t6_pc~0); 5468255#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 5468256#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5468807#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5468669#L1641 assume !(0 != activate_threads_~tmp___5~0); 5468670#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5468533#L763 assume !(1 == ~t7_pc~0); 5468499#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 5466732#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5466647#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5466648#L1649 assume !(0 != activate_threads_~tmp___6~0); 5467318#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5467323#L782 assume !(1 == ~t8_pc~0); 5467538#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 5467700#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5468026#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5466795#L1657 assume !(0 != activate_threads_~tmp___7~0); 5466796#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5466806#L801 assume !(1 == ~t9_pc~0); 5468870#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 5467324#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 5467140#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5467141#L1665 assume !(0 != activate_threads_~tmp___8~0); 5467651#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 5466821#L820 assume !(1 == ~t10_pc~0); 5466822#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 5466826#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 5467460#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5468204#L1673 assume !(0 != activate_threads_~tmp___9~0); 5468205#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 5468157#L839 assume !(1 == ~t11_pc~0); 5468158#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 5468159#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 5468525#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 5468526#L1681 assume !(0 != activate_threads_~tmp___10~0); 5468899#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 5467266#L858 assume !(1 == ~t12_pc~0); 5467197#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 5467198#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 5467718#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 5467719#L1689 assume !(0 != activate_threads_~tmp___11~0); 5468390#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 5468213#L877 assume !(1 == ~t13_pc~0); 5468215#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 5468219#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 5468790#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 5466885#L1697 assume !(0 != activate_threads_~tmp___12~0); 5466886#L1697-2 assume !(1 == ~M_E~0); 5466887#L1429-1 assume !(1 == ~T1_E~0); 5466960#L1434-1 assume !(1 == ~T2_E~0); 5466961#L1439-1 assume !(1 == ~T3_E~0); 5467474#L1444-1 assume !(1 == ~T4_E~0); 5467475#L1449-1 assume !(1 == ~T5_E~0); 5468049#L1454-1 assume !(1 == ~T6_E~0); 5467943#L1459-1 assume !(1 == ~T7_E~0); 5467944#L1464-1 assume !(1 == ~T8_E~0); 5468611#L1469-1 assume !(1 == ~T9_E~0); 5467104#L1474-1 assume !(1 == ~T10_E~0); 5466705#L1479-1 assume !(1 == ~T11_E~0); 5466706#L1484-1 assume !(1 == ~T12_E~0); 5467649#L1489-1 assume !(1 == ~T13_E~0); 5467650#L1494-1 assume !(1 == ~E_M~0); 5468015#L1499-1 assume !(1 == ~E_1~0); 5468016#L1504-1 assume !(1 == ~E_2~0); 5468664#L1509-1 assume !(1 == ~E_3~0); 5468548#L1514-1 assume !(1 == ~E_4~0); 5467229#L1519-1 assume !(1 == ~E_5~0); 5466854#L1524-1 assume !(1 == ~E_6~0); 5466855#L1529-1 assume !(1 == ~E_7~0); 5467383#L1534-1 assume !(1 == ~E_8~0); 5467384#L1539-1 assume !(1 == ~E_9~0); 5468130#L1544-1 assume !(1 == ~E_10~0); 5468131#L1549-1 assume !(1 == ~E_11~0); 5468635#L1554-1 assume !(1 == ~E_12~0); 5467277#L1559-1 assume !(1 == ~E_13~0); 5467278#L1930-1 [2018-11-28 12:51:59,442 INFO L796 eck$LassoCheckResult]: Loop: 5467278#L1930-1 assume !false; 5502245#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 5502240#L1256 assume !false; 5502239#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5502229#L982 assume !(0 == ~m_st~0); 5502230#L986 assume !(0 == ~t1_st~0); 5502233#L990 assume !(0 == ~t2_st~0); 5502235#L994 assume !(0 == ~t3_st~0); 5502237#L998 assume !(0 == ~t4_st~0); 5502224#L1002 assume !(0 == ~t5_st~0); 5502225#L1006 assume !(0 == ~t6_st~0); 5502228#L1010 assume !(0 == ~t7_st~0); 5502232#L1014 assume !(0 == ~t8_st~0); 5502234#L1018 assume !(0 == ~t9_st~0); 5502236#L1022 assume !(0 == ~t10_st~0); 5502238#L1026 assume !(0 == ~t11_st~0); 5502226#L1030 assume !(0 == ~t12_st~0); 5502227#L1034 assume !(0 == ~t13_st~0);exists_runnable_thread_~__retres1~14 := 0; 5502231#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5492232#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5492233#L1069 assume !(0 != eval_~tmp~0); 5502883#L1271 start_simulation_~kernel_st~0 := 2; 5502882#L897-1 start_simulation_~kernel_st~0 := 3; 5502881#L1281-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5502880#L1281-4 assume !(0 == ~T1_E~0); 5502879#L1286-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5502878#L1291-3 assume !(0 == ~T3_E~0); 5502877#L1296-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5502876#L1301-3 assume !(0 == ~T5_E~0); 5502875#L1306-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5502874#L1311-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5502873#L1316-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5502872#L1321-3 assume !(0 == ~T9_E~0); 5502871#L1326-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5502870#L1331-3 assume !(0 == ~T11_E~0); 5502869#L1336-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5502868#L1341-3 assume !(0 == ~T13_E~0); 5502867#L1346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5502866#L1351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5502865#L1356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5502864#L1361-3 assume !(0 == ~E_3~0); 5502863#L1366-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5502862#L1371-3 assume !(0 == ~E_5~0); 5502861#L1376-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5502860#L1381-3 assume !(0 == ~E_7~0); 5502859#L1386-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5502858#L1391-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5502857#L1396-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5502856#L1401-3 assume !(0 == ~E_11~0); 5502855#L1406-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5502854#L1411-3 assume !(0 == ~E_13~0); 5502853#L1416-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5502852#L630-45 assume !(1 == ~m_pc~0); 5502851#L630-47 is_master_triggered_~__retres1~0 := 0; 5502850#L641-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5502849#L642-15 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5502848#L1593-45 assume !(0 != activate_threads_~tmp~1); 5502847#L1593-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5502846#L649-45 assume !(1 == ~t1_pc~0); 5502845#L649-47 is_transmit1_triggered_~__retres1~1 := 0; 5502843#L660-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5502841#L661-15 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5502839#L1601-45 assume !(0 != activate_threads_~tmp___0~0); 5502837#L1601-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5502836#L668-45 assume !(1 == ~t2_pc~0); 5502835#L668-47 is_transmit2_triggered_~__retres1~2 := 0; 5502834#L679-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5502833#L680-15 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5502832#L1609-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5502831#L1609-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5502830#L687-45 assume !(1 == ~t3_pc~0); 5502828#L687-47 is_transmit3_triggered_~__retres1~3 := 0; 5502827#L698-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5502826#L699-15 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5502825#L1617-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5502823#L1617-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5502821#L706-45 assume !(1 == ~t4_pc~0); 5502819#L706-47 is_transmit4_triggered_~__retres1~4 := 0; 5502817#L717-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5502815#L718-15 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5502813#L1625-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5502811#L1625-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5502808#L725-45 assume !(1 == ~t5_pc~0); 5502804#L725-47 is_transmit5_triggered_~__retres1~5 := 0; 5502801#L736-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5502798#L737-15 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5502796#L1633-45 assume !(0 != activate_threads_~tmp___4~0); 5502794#L1633-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5502792#L744-45 assume !(1 == ~t6_pc~0); 5502790#L744-47 is_transmit6_triggered_~__retres1~6 := 0; 5502788#L755-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5502786#L756-15 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5502784#L1641-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5502781#L1641-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5502779#L763-45 assume !(1 == ~t7_pc~0); 5502777#L763-47 is_transmit7_triggered_~__retres1~7 := 0; 5502775#L774-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5502773#L775-15 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5502771#L1649-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5502769#L1649-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5502767#L782-45 assume !(1 == ~t8_pc~0); 5502765#L782-47 is_transmit8_triggered_~__retres1~8 := 0; 5502762#L793-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5502759#L794-15 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5502756#L1657-45 assume !(0 != activate_threads_~tmp___7~0); 5502752#L1657-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5502750#L801-45 assume !(1 == ~t9_pc~0); 5502748#L801-47 is_transmit9_triggered_~__retres1~9 := 0; 5502746#L812-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 5502744#L813-15 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5502742#L1665-45 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 5502740#L1665-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 5502738#L820-45 assume !(1 == ~t10_pc~0); 5502736#L820-47 is_transmit10_triggered_~__retres1~10 := 0; 5502733#L831-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 5502731#L832-15 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5502729#L1673-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 5502727#L1673-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 5502725#L839-45 assume !(1 == ~t11_pc~0); 5502723#L839-47 is_transmit11_triggered_~__retres1~11 := 0; 5502721#L850-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 5502719#L851-15 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 5502717#L1681-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 5502715#L1681-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 5502712#L858-45 assume !(1 == ~t12_pc~0); 5502709#L858-47 is_transmit12_triggered_~__retres1~12 := 0; 5502699#L869-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 5502696#L870-15 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 5502694#L1689-45 assume !(0 != activate_threads_~tmp___11~0); 5502692#L1689-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 5502690#L877-45 assume !(1 == ~t13_pc~0); 5502686#L877-47 is_transmit13_triggered_~__retres1~13 := 0; 5502683#L888-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 5502680#L889-15 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 5502677#L1697-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 5502674#L1697-47 assume 1 == ~M_E~0;~M_E~0 := 2; 5502670#L1429-3 assume !(1 == ~T1_E~0); 5502667#L1434-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5502663#L1439-3 assume !(1 == ~T3_E~0); 5502659#L1444-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5502655#L1449-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5502651#L1454-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5502648#L1459-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5502645#L1464-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5502642#L1469-3 assume !(1 == ~T9_E~0); 5502639#L1474-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5502636#L1479-3 assume !(1 == ~T11_E~0); 5502633#L1484-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5502629#L1489-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5502625#L1494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5502622#L1499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5502619#L1504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5502616#L1509-3 assume !(1 == ~E_3~0); 5502612#L1514-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5502609#L1519-3 assume !(1 == ~E_5~0); 5502606#L1524-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5502603#L1529-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5502600#L1534-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5502597#L1539-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5502594#L1544-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5502591#L1549-3 assume !(1 == ~E_11~0); 5502585#L1554-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5502579#L1559-3 assume !(1 == ~E_13~0); 5502575#L1564-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5502458#L982-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 5502442#L1054-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5502437#L1055-1 start_simulation_#t~ret32 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret32;havoc start_simulation_#t~ret32; 5502430#L1949 assume !(0 == start_simulation_~tmp~3); 5502427#L1949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret31, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5502303#L982-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 5502289#L1054-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5502282#L1055-2 stop_simulation_#t~ret31 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret31;havoc stop_simulation_#t~ret31; 5502277#L1904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5502270#L1911 stop_simulation_#res := stop_simulation_~__retres2~0; 5502266#L1912 start_simulation_#t~ret33 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 5502258#L1962 assume !(0 != start_simulation_~tmp___0~1); 5467278#L1930-1 [2018-11-28 12:51:59,442 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:59,442 INFO L82 PathProgramCache]: Analyzing trace with hash -2010186431, now seen corresponding path program 4 times [2018-11-28 12:51:59,442 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:59,442 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:59,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:59,443 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:51:59,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:59,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:51:59,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:51:59,509 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:51:59,510 INFO L82 PathProgramCache]: Analyzing trace with hash -391893405, now seen corresponding path program 1 times [2018-11-28 12:51:59,510 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:51:59,510 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:51:59,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:59,511 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:51:59,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:51:59,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:51:59,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:51:59,570 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:51:59,570 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:51:59,570 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 12:51:59,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:51:59,571 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:51:59,571 INFO L87 Difference]: Start difference. First operand 194858 states and 265708 transitions. cyclomatic complexity: 70978 Second operand 3 states. [2018-11-28 12:52:00,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:52:00,231 INFO L93 Difference]: Finished difference Result 360300 states and 486126 transitions. [2018-11-28 12:52:00,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:52:00,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 360300 states and 486126 transitions. [2018-11-28 12:52:01,154 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 358464 [2018-11-28 12:52:02,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 360300 states to 360300 states and 486126 transitions. [2018-11-28 12:52:02,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 360300 [2018-11-28 12:52:02,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 360300 [2018-11-28 12:52:02,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 360300 states and 486126 transitions. [2018-11-28 12:52:02,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:52:02,632 INFO L705 BuchiCegarLoop]: Abstraction has 360300 states and 486126 transitions. [2018-11-28 12:52:02,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 360300 states and 486126 transitions. [2018-11-28 12:52:04,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 360300 to 354220. [2018-11-28 12:52:04,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354220 states. [2018-11-28 12:52:04,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354220 states to 354220 states and 478158 transitions. [2018-11-28 12:52:04,779 INFO L728 BuchiCegarLoop]: Abstraction has 354220 states and 478158 transitions. [2018-11-28 12:52:04,779 INFO L608 BuchiCegarLoop]: Abstraction has 354220 states and 478158 transitions. [2018-11-28 12:52:04,779 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2018-11-28 12:52:04,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 354220 states and 478158 transitions. [2018-11-28 12:52:05,833 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 352384 [2018-11-28 12:52:05,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:52:05,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:52:05,834 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:52:05,834 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:52:05,835 INFO L794 eck$LassoCheckResult]: Stem: 6022363#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 6022364#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 6023322#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6023367#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 6022049#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6022050#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6022867#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6022605#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6022606#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6023014#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6023015#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6023798#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6022480#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6022174#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 6022175#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 6022678#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 6022679#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 6023345#L969-1 assume !(0 == ~M_E~0); 6023038#L1281-1 assume !(0 == ~T1_E~0); 6023039#L1286-1 assume !(0 == ~T2_E~0); 6023809#L1291-1 assume !(0 == ~T3_E~0); 6022490#L1296-1 assume !(0 == ~T4_E~0); 6022195#L1301-1 assume !(0 == ~T5_E~0); 6022196#L1306-1 assume !(0 == ~T6_E~0); 6022700#L1311-1 assume !(0 == ~T7_E~0); 6022545#L1316-1 assume !(0 == ~T8_E~0); 6022546#L1321-1 assume !(0 == ~T9_E~0); 6023119#L1326-1 assume !(0 == ~T10_E~0); 6023120#L1331-1 assume !(0 == ~T11_E~0); 6023592#L1336-1 assume !(0 == ~T12_E~0); 6022324#L1341-1 assume !(0 == ~T13_E~0); 6022132#L1346-1 assume !(0 == ~E_M~0); 6022133#L1351-1 assume !(0 == ~E_1~0); 6022636#L1356-1 assume !(0 == ~E_2~0); 6022637#L1361-1 assume !(0 == ~E_3~0); 6023208#L1366-1 assume !(0 == ~E_4~0); 6023099#L1371-1 assume !(0 == ~E_5~0); 6023100#L1376-1 assume !(0 == ~E_6~0); 6023717#L1381-1 assume !(0 == ~E_7~0); 6022222#L1386-1 assume !(0 == ~E_8~0); 6021831#L1391-1 assume !(0 == ~E_9~0); 6021832#L1396-1 assume !(0 == ~E_10~0); 6022795#L1401-1 assume !(0 == ~E_11~0); 6022796#L1406-1 assume !(0 == ~E_12~0); 6023141#L1411-1 assume !(0 == ~E_13~0); 6023142#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6023818#L630 assume !(1 == ~m_pc~0); 6023810#L630-2 is_master_triggered_~__retres1~0 := 0; 6022165#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6021883#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6021884#L1593 assume !(0 != activate_threads_~tmp~1); 6024029#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6022909#L649 assume !(1 == ~t1_pc~0); 6022859#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 6022913#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6023362#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6023544#L1601 assume !(0 != activate_threads_~tmp___0~0); 6023545#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6023551#L668 assume !(1 == ~t2_pc~0); 6024034#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 6022498#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6022467#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6022037#L1609 assume !(0 != activate_threads_~tmp___1~0); 6022038#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6021817#L687 assume !(1 == ~t3_pc~0); 6021797#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 6021798#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6022510#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6022602#L1617 assume !(0 != activate_threads_~tmp___2~0); 6022833#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6022836#L706 assume !(1 == ~t4_pc~0); 6023169#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 6023172#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6023768#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6023413#L1625 assume !(0 != activate_threads_~tmp___3~0); 6023414#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6022298#L725 assume !(1 == ~t5_pc~0); 6022273#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 6022274#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6022837#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 6022922#L1633 assume !(0 != activate_threads_~tmp___4~0); 6023071#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6023078#L744 assume !(1 == ~t6_pc~0); 6023423#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 6023424#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6023946#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 6023793#L1641 assume !(0 != activate_threads_~tmp___5~0); 6023794#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6023670#L763 assume !(1 == ~t7_pc~0); 6023641#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 6021896#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6021811#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 6021812#L1649 assume !(0 != activate_threads_~tmp___6~0); 6022470#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6022475#L782 assume !(1 == ~t8_pc~0); 6022686#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 6022851#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6023175#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 6021959#L1657 assume !(0 != activate_threads_~tmp___7~0); 6021960#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 6021970#L801 assume !(1 == ~t9_pc~0); 6024006#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 6022476#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 6022291#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 6022292#L1665 assume !(0 != activate_threads_~tmp___8~0); 6022802#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 6021984#L820 assume !(1 == ~t10_pc~0); 6021985#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 6021988#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 6022607#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 6023363#L1673 assume !(0 != activate_threads_~tmp___9~0); 6023364#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 6023313#L839 assume !(1 == ~t11_pc~0); 6023314#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 6023315#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 6023663#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 6023664#L1681 assume !(0 != activate_threads_~tmp___10~0); 6024035#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 6022416#L858 assume !(1 == ~t12_pc~0); 6022349#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 6022350#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 6022868#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 6022869#L1689 assume !(0 != activate_threads_~tmp___11~0); 6023533#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 6023374#L877 assume !(1 == ~t13_pc~0); 6023376#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 6023380#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 6023928#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 6022046#L1697 assume !(0 != activate_threads_~tmp___12~0); 6022047#L1697-2 assume !(1 == ~M_E~0); 6022048#L1429-1 assume !(1 == ~T1_E~0); 6022117#L1434-1 assume !(1 == ~T2_E~0); 6022118#L1439-1 assume !(1 == ~T3_E~0); 6022621#L1444-1 assume !(1 == ~T4_E~0); 6022622#L1449-1 assume !(1 == ~T5_E~0); 6023196#L1454-1 assume !(1 == ~T6_E~0); 6023093#L1459-1 assume !(1 == ~T7_E~0); 6023094#L1464-1 assume !(1 == ~T8_E~0); 6023739#L1469-1 assume !(1 == ~T9_E~0); 6022255#L1474-1 assume !(1 == ~T10_E~0); 6021871#L1479-1 assume !(1 == ~T11_E~0); 6021872#L1484-1 assume !(1 == ~T12_E~0); 6022800#L1489-1 assume !(1 == ~T13_E~0); 6022801#L1494-1 assume !(1 == ~E_M~0); 6023164#L1499-1 assume !(1 == ~E_1~0); 6023165#L1504-1 assume !(1 == ~E_2~0); 6023788#L1509-1 assume !(1 == ~E_3~0); 6023682#L1514-1 assume !(1 == ~E_4~0); 6022381#L1519-1 assume !(1 == ~E_5~0); 6022015#L1524-1 assume !(1 == ~E_6~0); 6022016#L1529-1 assume !(1 == ~E_7~0); 6022532#L1534-1 assume !(1 == ~E_8~0); 6022533#L1539-1 assume !(1 == ~E_9~0); 6023277#L1544-1 assume !(1 == ~E_10~0); 6023278#L1549-1 assume !(1 == ~E_11~0); 6023759#L1554-1 assume !(1 == ~E_12~0); 6022427#L1559-1 assume !(1 == ~E_13~0); 6022428#L1930-1 assume !false; 6109844#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 6109829#L1256 [2018-11-28 12:52:05,835 INFO L796 eck$LassoCheckResult]: Loop: 6109829#L1256 assume !false; 6109820#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 6109808#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 6109800#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 6109792#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6109783#L1069 assume 0 != eval_~tmp~0; 6109774#L1069-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 6109668#L1077 assume !(0 != eval_~tmp_ndt_1~0); 6109610#L1074 assume !(0 == ~t1_st~0); 6109603#L1088 assume !(0 == ~t2_st~0); 6109576#L1102 assume !(0 == ~t3_st~0); 6109565#L1116 assume !(0 == ~t4_st~0); 6109554#L1130 assume !(0 == ~t5_st~0); 6109551#L1144 assume !(0 == ~t6_st~0); 6109548#L1158 assume !(0 == ~t7_st~0); 6109487#L1172 assume !(0 == ~t8_st~0); 6109476#L1186 assume !(0 == ~t9_st~0); 6109467#L1200 assume !(0 == ~t10_st~0); 6109456#L1214 assume !(0 == ~t11_st~0); 6109448#L1228 assume !(0 == ~t12_st~0); 6109842#L1242 assume !(0 == ~t13_st~0); 6109829#L1256 [2018-11-28 12:52:05,835 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:52:05,835 INFO L82 PathProgramCache]: Analyzing trace with hash 946147331, now seen corresponding path program 1 times [2018-11-28 12:52:05,835 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:52:05,835 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:52:05,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:05,836 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:52:05,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:05,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:05,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:05,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:52:05,899 INFO L82 PathProgramCache]: Analyzing trace with hash -1071803235, now seen corresponding path program 1 times [2018-11-28 12:52:05,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:52:05,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:52:05,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:05,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:52:05,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:05,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:05,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:05,906 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:52:05,906 INFO L82 PathProgramCache]: Analyzing trace with hash -1852966437, now seen corresponding path program 1 times [2018-11-28 12:52:05,907 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:52:05,907 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:52:05,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:05,907 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:52:05,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:05,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:52:05,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:52:05,962 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:52:05,962 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:52:06,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:52:06,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:52:06,054 INFO L87 Difference]: Start difference. First operand 354220 states and 478158 transitions. cyclomatic complexity: 124130 Second operand 3 states. [2018-11-28 12:52:07,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:52:07,301 INFO L93 Difference]: Finished difference Result 690899 states and 928022 transitions. [2018-11-28 12:52:07,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:52:07,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 690899 states and 928022 transitions. [2018-11-28 12:52:14,684 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 687232 [2018-11-28 12:52:15,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 690899 states to 690899 states and 928022 transitions. [2018-11-28 12:52:15,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690899 [2018-11-28 12:52:15,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690899 [2018-11-28 12:52:15,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690899 states and 928022 transitions. [2018-11-28 12:52:16,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:52:16,187 INFO L705 BuchiCegarLoop]: Abstraction has 690899 states and 928022 transitions. [2018-11-28 12:52:16,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690899 states and 928022 transitions. [2018-11-28 12:52:19,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690899 to 668627. [2018-11-28 12:52:19,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 668627 states. [2018-11-28 12:52:21,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668627 states to 668627 states and 898966 transitions. [2018-11-28 12:52:21,750 INFO L728 BuchiCegarLoop]: Abstraction has 668627 states and 898966 transitions. [2018-11-28 12:52:21,750 INFO L608 BuchiCegarLoop]: Abstraction has 668627 states and 898966 transitions. [2018-11-28 12:52:21,750 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2018-11-28 12:52:21,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 668627 states and 898966 transitions. [2018-11-28 12:52:22,691 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 664960 [2018-11-28 12:52:22,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:52:22,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:52:22,692 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:52:22,692 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:52:22,692 INFO L794 eck$LassoCheckResult]: Stem: 7067499#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 7067500#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 7068489#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7068541#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 7067181#L904-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 7067182#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7068018#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7068019#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7068539#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7068540#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7069111#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7069112#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7067623#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7067304#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 7067305#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 7067821#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 7067822#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 7068513#L969-1 assume !(0 == ~M_E~0); 7068514#L1281-1 assume !(0 == ~T1_E~0); 7069142#L1286-1 assume !(0 == ~T2_E~0); 7069143#L1291-1 assume !(0 == ~T3_E~0); 7067632#L1296-1 assume !(0 == ~T4_E~0); 7067633#L1301-1 assume !(0 == ~T5_E~0); 7068093#L1306-1 assume !(0 == ~T6_E~0); 7068094#L1311-1 assume !(0 == ~T7_E~0); 7067689#L1316-1 assume !(0 == ~T8_E~0); 7067690#L1321-1 assume !(0 == ~T9_E~0); 7068280#L1326-1 assume !(0 == ~T10_E~0); 7068281#L1331-1 assume !(0 == ~T11_E~0); 7068796#L1336-1 assume !(0 == ~T12_E~0); 7068797#L1341-1 assume !(0 == ~T13_E~0); 7067264#L1346-1 assume !(0 == ~E_M~0); 7067265#L1351-1 assume !(0 == ~E_1~0); 7067779#L1356-1 assume !(0 == ~E_2~0); 7067780#L1361-1 assume !(0 == ~E_3~0); 7068368#L1366-1 assume !(0 == ~E_4~0); 7068369#L1371-1 assume !(0 == ~E_5~0); 7069147#L1376-1 assume !(0 == ~E_6~0); 7069148#L1381-1 assume !(0 == ~E_7~0); 7067353#L1386-1 assume !(0 == ~E_8~0); 7067354#L1391-1 assume !(0 == ~E_9~0); 7067990#L1396-1 assume !(0 == ~E_10~0); 7067991#L1401-1 assume !(0 == ~E_11~0); 7068682#L1406-1 assume !(0 == ~E_12~0); 7068683#L1411-1 assume !(0 == ~E_13~0); 7069160#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7069161#L630 assume !(1 == ~m_pc~0); 7069034#L630-2 is_master_triggered_~__retres1~0 := 0; 7069035#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7067009#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7067010#L1593 assume !(0 != activate_threads_~tmp~1); 7069240#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7069241#L649 assume !(1 == ~t1_pc~0); 7087723#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 7087722#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7087721#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7087720#L1601 assume !(0 != activate_threads_~tmp___0~0); 7087718#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7087717#L668 assume !(1 == ~t2_pc~0); 7087716#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 7087715#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7087714#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7087713#L1609 assume !(0 != activate_threads_~tmp___1~0); 7087712#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7087711#L687 assume !(1 == ~t3_pc~0); 7087709#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 7087708#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7087707#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7087706#L1617 assume !(0 != activate_threads_~tmp___2~0); 7087705#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7087704#L706 assume !(1 == ~t4_pc~0); 7087703#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 7087702#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7087701#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7087700#L1625 assume !(0 != activate_threads_~tmp___3~0); 7087699#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7087697#L725 assume !(1 == ~t5_pc~0); 7087696#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 7087695#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7087694#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 7087693#L1633 assume !(0 != activate_threads_~tmp___4~0); 7087692#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7087691#L744 assume !(1 == ~t6_pc~0); 7087690#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 7087689#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7087688#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7087687#L1641 assume !(0 != activate_threads_~tmp___5~0); 7087686#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7087685#L763 assume !(1 == ~t7_pc~0); 7087684#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 7087683#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7087682#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7087681#L1649 assume !(0 != activate_threads_~tmp___6~0); 7087680#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7087679#L782 assume !(1 == ~t8_pc~0); 7068000#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 7068001#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7068334#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 7068335#L1657 assume !(0 != activate_threads_~tmp___7~0); 7087673#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 7087672#L801 assume !(1 == ~t9_pc~0); 7087671#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 7087670#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 7087669#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7087668#L1665 assume !(0 != activate_threads_~tmp___8~0); 7087667#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 7087666#L820 assume !(1 == ~t10_pc~0); 7087665#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 7087663#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 7087662#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 7087661#L1673 assume !(0 != activate_threads_~tmp___9~0); 7087660#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 7087659#L839 assume !(1 == ~t11_pc~0); 7087658#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 7087657#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 7087656#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 7087655#L1681 assume !(0 != activate_threads_~tmp___10~0); 7087654#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 7087653#L858 assume !(1 == ~t12_pc~0); 7067485#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 7067486#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 7068021#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 7068022#L1689 assume !(0 != activate_threads_~tmp___11~0); 7068731#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 7068737#L877 assume !(1 == ~t13_pc~0); 7068554#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 7068555#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 7086877#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 7086875#L1697 assume !(0 != activate_threads_~tmp___12~0); 7067179#L1697-2 assume !(1 == ~M_E~0); 7067180#L1429-1 assume !(1 == ~T1_E~0); 7067249#L1434-1 assume !(1 == ~T2_E~0); 7067250#L1439-1 assume !(1 == ~T3_E~0); 7067765#L1444-1 assume !(1 == ~T4_E~0); 7067766#L1449-1 assume !(1 == ~T5_E~0); 7068585#L1454-1 assume !(1 == ~T6_E~0); 7086801#L1459-1 assume !(1 == ~T7_E~0); 7086799#L1464-1 assume !(1 == ~T8_E~0); 7086794#L1469-1 assume !(1 == ~T9_E~0); 7086792#L1474-1 assume !(1 == ~T10_E~0); 7066994#L1479-1 assume !(1 == ~T11_E~0); 7066995#L1484-1 assume !(1 == ~T12_E~0); 7067944#L1489-1 assume !(1 == ~T13_E~0); 7067945#L1494-1 assume !(1 == ~E_M~0); 7068322#L1499-1 assume !(1 == ~E_1~0); 7068323#L1504-1 assume !(1 == ~E_2~0); 7069007#L1509-1 assume !(1 == ~E_3~0); 7068891#L1514-1 assume !(1 == ~E_4~0); 7068892#L1519-1 assume !(1 == ~E_5~0); 7086717#L1524-1 assume !(1 == ~E_6~0); 7067972#L1529-1 assume !(1 == ~E_7~0); 7067677#L1534-1 assume !(1 == ~E_8~0); 7067678#L1539-1 assume !(1 == ~E_9~0); 7068622#L1544-1 assume !(1 == ~E_10~0); 7086694#L1549-1 assume !(1 == ~E_11~0); 7086692#L1554-1 assume !(1 == ~E_12~0); 7067568#L1559-1 assume !(1 == ~E_13~0); 7067569#L1930-1 assume !false; 7086676#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 7086662#L1256 [2018-11-28 12:52:22,693 INFO L796 eck$LassoCheckResult]: Loop: 7086662#L1256 assume !false; 7086651#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 7086641#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 7086632#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 7086611#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7086600#L1069 assume 0 != eval_~tmp~0; 7086588#L1069-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 7086579#L1077 assume !(0 != eval_~tmp_ndt_1~0); 7086555#L1074 assume !(0 == ~t1_st~0); 7086547#L1088 assume !(0 == ~t2_st~0); 7086537#L1102 assume !(0 == ~t3_st~0); 7086532#L1116 assume !(0 == ~t4_st~0); 7086528#L1130 assume !(0 == ~t5_st~0); 7086526#L1144 assume !(0 == ~t6_st~0); 7086481#L1158 assume !(0 == ~t7_st~0); 7086477#L1172 assume !(0 == ~t8_st~0); 7086475#L1186 assume !(0 == ~t9_st~0); 7086906#L1200 assume !(0 == ~t10_st~0); 7086897#L1214 assume !(0 == ~t11_st~0); 7086742#L1228 assume !(0 == ~t12_st~0); 7086674#L1242 assume !(0 == ~t13_st~0); 7086662#L1256 [2018-11-28 12:52:22,693 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:52:22,693 INFO L82 PathProgramCache]: Analyzing trace with hash -823324283, now seen corresponding path program 1 times [2018-11-28 12:52:22,693 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:52:22,693 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:52:22,693 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:22,693 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:52:22,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:22,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:52:22,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:52:22,736 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:52:22,736 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:52:22,736 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 12:52:22,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:52:22,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1071803235, now seen corresponding path program 2 times [2018-11-28 12:52:22,737 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:52:22,737 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:52:22,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:22,737 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:52:22,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:22,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:22,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:22,853 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:52:22,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:52:22,853 INFO L87 Difference]: Start difference. First operand 668627 states and 898966 transitions. cyclomatic complexity: 230531 Second operand 3 states. [2018-11-28 12:52:24,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:52:24,223 INFO L93 Difference]: Finished difference Result 668460 states and 898733 transitions. [2018-11-28 12:52:24,223 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:52:24,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 668460 states and 898733 transitions. [2018-11-28 12:52:32,433 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 664960 [2018-11-28 12:52:33,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 668460 states to 668460 states and 898733 transitions. [2018-11-28 12:52:33,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 668460 [2018-11-28 12:52:33,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 668460 [2018-11-28 12:52:33,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 668460 states and 898733 transitions. [2018-11-28 12:52:33,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:52:33,555 INFO L705 BuchiCegarLoop]: Abstraction has 668460 states and 898733 transitions. [2018-11-28 12:52:33,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668460 states and 898733 transitions. [2018-11-28 12:52:37,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668460 to 668460. [2018-11-28 12:52:37,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 668460 states. [2018-11-28 12:52:38,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668460 states to 668460 states and 898733 transitions. [2018-11-28 12:52:38,033 INFO L728 BuchiCegarLoop]: Abstraction has 668460 states and 898733 transitions. [2018-11-28 12:52:38,033 INFO L608 BuchiCegarLoop]: Abstraction has 668460 states and 898733 transitions. [2018-11-28 12:52:38,033 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2018-11-28 12:52:38,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 668460 states and 898733 transitions. [2018-11-28 12:52:39,265 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 664960 [2018-11-28 12:52:39,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:52:39,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:52:39,266 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:52:39,266 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:52:39,267 INFO L794 eck$LassoCheckResult]: Stem: 8404593#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8404594#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8405606#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8405658#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 8404272#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8404273#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8405122#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8404847#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8404848#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8405290#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8405291#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8406159#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8404717#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8404398#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 8404399#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 8404921#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 8404922#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 8405631#L969-1 assume !(0 == ~M_E~0); 8405312#L1281-1 assume !(0 == ~T1_E~0); 8405313#L1286-1 assume !(0 == ~T2_E~0); 8406171#L1291-1 assume !(0 == ~T3_E~0); 8404727#L1296-1 assume !(0 == ~T4_E~0); 8404419#L1301-1 assume !(0 == ~T5_E~0); 8404420#L1306-1 assume !(0 == ~T6_E~0); 8404945#L1311-1 assume !(0 == ~T7_E~0); 8404784#L1316-1 assume !(0 == ~T8_E~0); 8404785#L1321-1 assume !(0 == ~T9_E~0); 8405387#L1326-1 assume !(0 == ~T10_E~0); 8405388#L1331-1 assume !(0 == ~T11_E~0); 8405907#L1336-1 assume !(0 == ~T12_E~0); 8404549#L1341-1 assume !(0 == ~T13_E~0); 8404356#L1346-1 assume !(0 == ~E_M~0); 8404357#L1351-1 assume !(0 == ~E_1~0); 8404878#L1356-1 assume !(0 == ~E_2~0); 8404879#L1361-1 assume !(0 == ~E_3~0); 8405480#L1366-1 assume !(0 == ~E_4~0); 8405368#L1371-1 assume !(0 == ~E_5~0); 8405369#L1376-1 assume !(0 == ~E_6~0); 8406049#L1381-1 assume !(0 == ~E_7~0); 8404445#L1386-1 assume !(0 == ~E_8~0); 8404051#L1391-1 assume !(0 == ~E_9~0); 8404052#L1396-1 assume !(0 == ~E_10~0); 8405041#L1401-1 assume !(0 == ~E_11~0); 8405042#L1406-1 assume !(0 == ~E_12~0); 8405410#L1411-1 assume !(0 == ~E_13~0); 8405411#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8406183#L630 assume !(1 == ~m_pc~0); 8406174#L630-2 is_master_triggered_~__retres1~0 := 0; 8404388#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8404102#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8404103#L1593 assume !(0 != activate_threads_~tmp~1); 8406372#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8405173#L649 assume !(1 == ~t1_pc~0); 8405114#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 8405179#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8405651#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8405852#L1601 assume !(0 != activate_threads_~tmp___0~0); 8405853#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8405859#L668 assume !(1 == ~t2_pc~0); 8406386#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 8404737#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8404701#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8404259#L1609 assume !(0 != activate_threads_~tmp___1~0); 8404260#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8404037#L687 assume !(1 == ~t3_pc~0); 8404017#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 8404018#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8404750#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8404843#L1617 assume !(0 != activate_threads_~tmp___2~0); 8405083#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8405086#L706 assume !(1 == ~t4_pc~0); 8405439#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 8405443#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8406119#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 8405704#L1625 assume !(0 != activate_threads_~tmp___3~0); 8405705#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8404522#L725 assume !(1 == ~t5_pc~0); 8404496#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 8404497#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8405088#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 8405198#L1633 assume !(0 != activate_threads_~tmp___4~0); 8405341#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8405348#L744 assume !(1 == ~t6_pc~0); 8405715#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 8405716#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8406286#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8406152#L1641 assume !(0 != activate_threads_~tmp___5~0); 8406153#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8405988#L763 assume !(1 == ~t7_pc~0); 8405955#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 8404116#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8404031#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8404032#L1649 assume !(0 != activate_threads_~tmp___6~0); 8404706#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8404711#L782 assume !(1 == ~t8_pc~0); 8404928#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 8405103#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8405447#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8404179#L1657 assume !(0 != activate_threads_~tmp___7~0); 8404180#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 8404190#L801 assume !(1 == ~t9_pc~0); 8406344#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 8404712#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 8404515#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 8404516#L1665 assume !(0 != activate_threads_~tmp___8~0); 8405051#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 8404203#L820 assume !(1 == ~t10_pc~0); 8404204#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 8404207#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 8404849#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 8405649#L1673 assume !(0 != activate_threads_~tmp___9~0); 8405650#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 8405593#L839 assume !(1 == ~t11_pc~0); 8405594#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 8405597#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 8405981#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 8405982#L1681 assume !(0 != activate_threads_~tmp___10~0); 8406387#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 8404647#L858 assume !(1 == ~t12_pc~0); 8404579#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 8404580#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 8405124#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8405125#L1689 assume !(0 != activate_threads_~tmp___11~0); 8405840#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 8405663#L877 assume !(1 == ~t13_pc~0); 8405665#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 8405670#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 8406268#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8404269#L1697 assume !(0 != activate_threads_~tmp___12~0); 8404270#L1697-2 assume !(1 == ~M_E~0); 8404271#L1429-1 assume !(1 == ~T1_E~0); 8404341#L1434-1 assume !(1 == ~T2_E~0); 8404342#L1439-1 assume !(1 == ~T3_E~0); 8404864#L1444-1 assume !(1 == ~T4_E~0); 8404865#L1449-1 assume !(1 == ~T5_E~0); 8405469#L1454-1 assume !(1 == ~T6_E~0); 8405363#L1459-1 assume !(1 == ~T7_E~0); 8405364#L1464-1 assume !(1 == ~T8_E~0); 8406074#L1469-1 assume !(1 == ~T9_E~0); 8404474#L1474-1 assume !(1 == ~T10_E~0); 8404087#L1479-1 assume !(1 == ~T11_E~0); 8404088#L1484-1 assume !(1 == ~T12_E~0); 8405049#L1489-1 assume !(1 == ~T13_E~0); 8405050#L1494-1 assume !(1 == ~E_M~0); 8405433#L1499-1 assume !(1 == ~E_1~0); 8405434#L1504-1 assume !(1 == ~E_2~0); 8406144#L1509-1 assume !(1 == ~E_3~0); 8406002#L1514-1 assume !(1 == ~E_4~0); 8404612#L1519-1 assume !(1 == ~E_5~0); 8404234#L1524-1 assume !(1 == ~E_6~0); 8404235#L1529-1 assume !(1 == ~E_7~0); 8404771#L1534-1 assume !(1 == ~E_8~0); 8404772#L1539-1 assume !(1 == ~E_9~0); 8405555#L1544-1 assume !(1 == ~E_10~0); 8405556#L1549-1 assume !(1 == ~E_11~0); 8406107#L1554-1 assume !(1 == ~E_12~0); 8404659#L1559-1 assume !(1 == ~E_13~0); 8404660#L1930-1 assume !false; 8430535#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 8430527#L1256 [2018-11-28 12:52:39,267 INFO L796 eck$LassoCheckResult]: Loop: 8430527#L1256 assume !false; 8430525#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 8430519#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8430517#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 8430515#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8430512#L1069 assume 0 != eval_~tmp~0; 8430509#L1069-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 8430506#L1077 assume !(0 != eval_~tmp_ndt_1~0); 8430504#L1074 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 8430492#L1091 assume !(0 != eval_~tmp_ndt_2~0); 8430498#L1088 assume !(0 == ~t2_st~0); 8430497#L1102 assume !(0 == ~t3_st~0); 8453841#L1116 assume !(0 == ~t4_st~0); 8453839#L1130 assume !(0 == ~t5_st~0); 8469286#L1144 assume !(0 == ~t6_st~0); 8469278#L1158 assume !(0 == ~t7_st~0); 8470124#L1172 assume !(0 == ~t8_st~0); 8470120#L1186 assume !(0 == ~t9_st~0); 8470061#L1200 assume !(0 == ~t10_st~0); 8470049#L1214 assume !(0 == ~t11_st~0); 8470041#L1228 assume !(0 == ~t12_st~0); 8430533#L1242 assume !(0 == ~t13_st~0); 8430527#L1256 [2018-11-28 12:52:39,267 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:52:39,267 INFO L82 PathProgramCache]: Analyzing trace with hash 946147331, now seen corresponding path program 2 times [2018-11-28 12:52:39,267 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:52:39,268 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:52:39,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:39,268 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:52:39,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:39,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:39,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:39,353 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:52:39,353 INFO L82 PathProgramCache]: Analyzing trace with hash 218801437, now seen corresponding path program 1 times [2018-11-28 12:52:39,353 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:52:39,353 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:52:39,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:39,355 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:52:39,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:39,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:39,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:52:39,361 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:52:39,361 INFO L82 PathProgramCache]: Analyzing trace with hash 1772545951, now seen corresponding path program 1 times [2018-11-28 12:52:39,361 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:52:39,361 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:52:39,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:39,362 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:52:39,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:52:39,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:52:39,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:52:39,427 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:52:39,428 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:52:39,562 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:52:39,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:52:39,562 INFO L87 Difference]: Start difference. First operand 668460 states and 898733 transitions. cyclomatic complexity: 230465 Second operand 3 states. [2018-11-28 12:52:42,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:52:42,779 INFO L93 Difference]: Finished difference Result 947532 states and 1269165 transitions. [2018-11-28 12:52:42,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:52:42,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 947532 states and 1269165 transitions. [2018-11-28 12:52:53,304 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 942624 [2018-11-28 12:52:54,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 947532 states to 947532 states and 1269165 transitions. [2018-11-28 12:52:54,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 947532 [2018-11-28 12:52:55,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 947532 [2018-11-28 12:52:55,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 947532 states and 1269165 transitions. [2018-11-28 12:52:55,214 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:52:55,214 INFO L705 BuchiCegarLoop]: Abstraction has 947532 states and 1269165 transitions. [2018-11-28 12:52:55,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 947532 states and 1269165 transitions. [2018-11-28 12:53:00,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 947532 to 926924. [2018-11-28 12:53:00,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 926924 states. [2018-11-28 12:53:01,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 926924 states to 926924 states and 1242029 transitions. [2018-11-28 12:53:01,755 INFO L728 BuchiCegarLoop]: Abstraction has 926924 states and 1242029 transitions. [2018-11-28 12:53:01,755 INFO L608 BuchiCegarLoop]: Abstraction has 926924 states and 1242029 transitions. [2018-11-28 12:53:01,755 INFO L442 BuchiCegarLoop]: ======== Iteration 37============ [2018-11-28 12:53:01,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 926924 states and 1242029 transitions. [2018-11-28 12:53:04,275 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 922016 [2018-11-28 12:53:04,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:53:04,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:53:04,276 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:53:04,276 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:53:04,277 INFO L794 eck$LassoCheckResult]: Stem: 10020590#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 10020591#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 10021546#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10021595#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 10020271#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10020272#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10021113#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10020844#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10020845#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10021270#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10021271#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 10022023#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 10020717#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10020398#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 10020399#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 10020916#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 10020917#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 10021571#L969-1 assume !(0 == ~M_E~0); 10021291#L1281-1 assume !(0 == ~T1_E~0); 10021292#L1286-1 assume !(0 == ~T2_E~0); 10022033#L1291-1 assume !(0 == ~T3_E~0); 10020728#L1296-1 assume !(0 == ~T4_E~0); 10020419#L1301-1 assume !(0 == ~T5_E~0); 10020420#L1306-1 assume !(0 == ~T6_E~0); 10020939#L1311-1 assume !(0 == ~T7_E~0); 10020782#L1316-1 assume !(0 == ~T8_E~0); 10020783#L1321-1 assume !(0 == ~T9_E~0); 10021367#L1326-1 assume !(0 == ~T10_E~0); 10021368#L1331-1 assume !(0 == ~T11_E~0); 10021814#L1336-1 assume !(0 == ~T12_E~0); 10020549#L1341-1 assume !(0 == ~T13_E~0); 10020358#L1346-1 assume !(0 == ~E_M~0); 10020359#L1351-1 assume !(0 == ~E_1~0); 10020874#L1356-1 assume !(0 == ~E_2~0); 10020875#L1361-1 assume !(0 == ~E_3~0); 10021458#L1366-1 assume !(0 == ~E_4~0); 10021348#L1371-1 assume !(0 == ~E_5~0); 10021349#L1376-1 assume !(0 == ~E_6~0); 10021945#L1381-1 assume !(0 == ~E_7~0); 10020445#L1386-1 assume !(0 == ~E_8~0); 10020052#L1391-1 assume !(0 == ~E_9~0); 10020053#L1396-1 assume !(0 == ~E_10~0); 10021036#L1401-1 assume !(0 == ~E_11~0); 10021037#L1406-1 assume !(0 == ~E_12~0); 10021387#L1411-1 assume !(0 == ~E_13~0); 10021388#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10022040#L630 assume !(1 == ~m_pc~0); 10022035#L630-2 is_master_triggered_~__retres1~0 := 0; 10020391#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10020103#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10020104#L1593 assume !(0 != activate_threads_~tmp~1); 10022217#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10021158#L649 assume !(1 == ~t1_pc~0); 10021105#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 10021164#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10021591#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10021767#L1601 assume !(0 != activate_threads_~tmp___0~0); 10021768#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10021774#L668 assume !(1 == ~t2_pc~0); 10022225#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 10020737#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10020703#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10020259#L1609 assume !(0 != activate_threads_~tmp___1~0); 10020260#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10020038#L687 assume !(1 == ~t3_pc~0); 10020017#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 10020018#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10020749#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10020840#L1617 assume !(0 != activate_threads_~tmp___2~0); 10021074#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10021077#L706 assume !(1 == ~t4_pc~0); 10021417#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 10021422#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10021994#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10021643#L1625 assume !(0 != activate_threads_~tmp___3~0); 10021644#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10020523#L725 assume !(1 == ~t5_pc~0); 10020497#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 10020498#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10021079#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 10021175#L1633 assume !(0 != activate_threads_~tmp___4~0); 10021321#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10021328#L744 assume !(1 == ~t6_pc~0); 10021652#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 10021653#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10022146#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 10022019#L1641 assume !(0 != activate_threads_~tmp___5~0); 10022020#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10021890#L763 assume !(1 == ~t7_pc~0); 10021859#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 10020117#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10020032#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10020033#L1649 assume !(0 != activate_threads_~tmp___6~0); 10020707#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 10020712#L782 assume !(1 == ~t8_pc~0); 10020924#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 10021093#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10021427#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 10020180#L1657 assume !(0 != activate_threads_~tmp___7~0); 10020181#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 10020191#L801 assume !(1 == ~t9_pc~0); 10022197#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 10020713#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 10020516#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 10020517#L1665 assume !(0 != activate_threads_~tmp___8~0); 10021044#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 10020205#L820 assume !(1 == ~t10_pc~0); 10020206#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 10020209#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 10020846#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 10021592#L1673 assume !(0 != activate_threads_~tmp___9~0); 10021593#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 10021541#L839 assume !(1 == ~t11_pc~0); 10021542#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 10021543#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 10021883#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 10021884#L1681 assume !(0 != activate_threads_~tmp___10~0); 10022226#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 10020650#L858 assume !(1 == ~t12_pc~0); 10020575#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 10020576#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 10021115#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 10021116#L1689 assume !(0 != activate_threads_~tmp___11~0); 10021756#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 10021600#L877 assume !(1 == ~t13_pc~0); 10021602#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 10021608#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 10022129#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 10020268#L1697 assume !(0 != activate_threads_~tmp___12~0); 10020269#L1697-2 assume !(1 == ~M_E~0); 10020270#L1429-1 assume !(1 == ~T1_E~0); 10020343#L1434-1 assume !(1 == ~T2_E~0); 10020344#L1439-1 assume !(1 == ~T3_E~0); 10020860#L1444-1 assume !(1 == ~T4_E~0); 10020861#L1449-1 assume !(1 == ~T5_E~0); 10021447#L1454-1 assume !(1 == ~T6_E~0); 10021342#L1459-1 assume !(1 == ~T7_E~0); 10021343#L1464-1 assume !(1 == ~T8_E~0); 10021964#L1469-1 assume !(1 == ~T9_E~0); 10020475#L1474-1 assume !(1 == ~T10_E~0); 10020088#L1479-1 assume !(1 == ~T11_E~0); 10020089#L1484-1 assume !(1 == ~T12_E~0); 10021042#L1489-1 assume !(1 == ~T13_E~0); 10021043#L1494-1 assume !(1 == ~E_M~0); 10021410#L1499-1 assume !(1 == ~E_1~0); 10021411#L1504-1 assume !(1 == ~E_2~0); 10022013#L1509-1 assume !(1 == ~E_3~0); 10021902#L1514-1 assume !(1 == ~E_4~0); 10020608#L1519-1 assume !(1 == ~E_5~0); 10020236#L1524-1 assume !(1 == ~E_6~0); 10020237#L1529-1 assume !(1 == ~E_7~0); 10020770#L1534-1 assume !(1 == ~E_8~0); 10020771#L1539-1 assume !(1 == ~E_9~0); 10021520#L1544-1 assume !(1 == ~E_10~0); 10021521#L1549-1 assume !(1 == ~E_11~0); 10021985#L1554-1 assume !(1 == ~E_12~0); 10020662#L1559-1 assume !(1 == ~E_13~0); 10020663#L1930-1 assume !false; 10023956#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 10023945#L1256 [2018-11-28 12:53:04,277 INFO L796 eck$LassoCheckResult]: Loop: 10023945#L1256 assume !false; 10023939#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 10023935#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 10023931#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 10023927#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 10023924#L1069 assume 0 != eval_~tmp~0; 10023920#L1069-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 10023916#L1077 assume !(0 != eval_~tmp_ndt_1~0); 10023910#L1074 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 10023904#L1091 assume !(0 != eval_~tmp_ndt_2~0); 10023898#L1088 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 10023899#L1105 assume !(0 != eval_~tmp_ndt_3~0); 10023725#L1102 assume !(0 == ~t3_st~0); 10023724#L1116 assume !(0 == ~t4_st~0); 10024132#L1130 assume !(0 == ~t5_st~0); 10024129#L1144 assume !(0 == ~t6_st~0); 10024126#L1158 assume !(0 == ~t7_st~0); 10024046#L1172 assume !(0 == ~t8_st~0); 10024033#L1186 assume !(0 == ~t9_st~0); 10024024#L1200 assume !(0 == ~t10_st~0); 10024015#L1214 assume !(0 == ~t11_st~0); 10023967#L1228 assume !(0 == ~t12_st~0); 10023954#L1242 assume !(0 == ~t13_st~0); 10023945#L1256 [2018-11-28 12:53:04,277 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:53:04,277 INFO L82 PathProgramCache]: Analyzing trace with hash 946147331, now seen corresponding path program 3 times [2018-11-28 12:53:04,277 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:53:04,277 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:53:04,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:53:04,278 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:53:04,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:53:04,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:53:04,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:53:04,331 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:53:04,331 INFO L82 PathProgramCache]: Analyzing trace with hash -1975148544, now seen corresponding path program 1 times [2018-11-28 12:53:04,332 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:53:04,332 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:53:04,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:53:04,332 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:53:04,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:53:04,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:53:04,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:53:04,337 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:53:04,338 INFO L82 PathProgramCache]: Analyzing trace with hash -1053708866, now seen corresponding path program 1 times [2018-11-28 12:53:04,338 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:53:04,338 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:53:04,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:53:04,338 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:53:04,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:53:04,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:53:04,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:53:04,395 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:53:04,395 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:53:04,476 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:53:04,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:53:04,476 INFO L87 Difference]: Start difference. First operand 926924 states and 1242029 transitions. cyclomatic complexity: 315297 Second operand 3 states. [2018-11-28 12:53:15,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:53:15,555 INFO L93 Difference]: Finished difference Result 1817324 states and 2432365 transitions. [2018-11-28 12:53:15,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:53:15,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1817324 states and 2432365 transitions. [2018-11-28 12:53:22,410 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 1807680 [2018-11-28 12:53:25,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1817324 states to 1817324 states and 2432365 transitions. [2018-11-28 12:53:25,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1817324 [2018-11-28 12:53:25,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1817324 [2018-11-28 12:53:25,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1817324 states and 2432365 transitions. [2018-11-28 12:53:26,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:53:26,262 INFO L705 BuchiCegarLoop]: Abstraction has 1817324 states and 2432365 transitions. [2018-11-28 12:53:26,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1817324 states and 2432365 transitions. [2018-11-28 12:53:50,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1817324 to 1760876. [2018-11-28 12:53:50,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1760876 states. [2018-11-28 12:53:54,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1760876 states to 1760876 states and 2358637 transitions. [2018-11-28 12:53:54,012 INFO L728 BuchiCegarLoop]: Abstraction has 1760876 states and 2358637 transitions. [2018-11-28 12:53:54,013 INFO L608 BuchiCegarLoop]: Abstraction has 1760876 states and 2358637 transitions. [2018-11-28 12:53:54,013 INFO L442 BuchiCegarLoop]: ======== Iteration 38============ [2018-11-28 12:53:54,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1760876 states and 2358637 transitions. [2018-11-28 12:54:04,963 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 1751232 [2018-11-28 12:54:04,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 12:54:04,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 12:54:04,964 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:54:04,964 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 12:54:04,964 INFO L794 eck$LassoCheckResult]: Stem: 12764875#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12764876#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12766003#L1893 havoc start_simulation_#t~ret32, start_simulation_#t~ret33, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12766065#L897 assume 1 == ~m_i~0;~m_st~0 := 0; 12764536#L904-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12764537#L909-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12765459#L914-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12765163#L919-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12765164#L924-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12765665#L929-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12765666#L934-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12766592#L939-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 12765019#L944-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12764673#L949-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 12764674#L954-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 12765238#L959-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 12765239#L964-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 12766032#L969-1 assume !(0 == ~M_E~0); 12765691#L1281-1 assume !(0 == ~T1_E~0); 12765692#L1286-1 assume !(0 == ~T2_E~0); 12766607#L1291-1 assume !(0 == ~T3_E~0); 12765030#L1296-1 assume !(0 == ~T4_E~0); 12764697#L1301-1 assume !(0 == ~T5_E~0); 12764698#L1306-1 assume !(0 == ~T6_E~0); 12765264#L1311-1 assume !(0 == ~T7_E~0); 12765097#L1316-1 assume !(0 == ~T8_E~0); 12765098#L1321-1 assume !(0 == ~T9_E~0); 12765771#L1326-1 assume !(0 == ~T10_E~0); 12765772#L1331-1 assume !(0 == ~T11_E~0); 12766332#L1336-1 assume !(0 == ~T12_E~0); 12764833#L1341-1 assume !(0 == ~T13_E~0); 12764623#L1346-1 assume !(0 == ~E_M~0); 12764624#L1351-1 assume !(0 == ~E_1~0); 12765194#L1356-1 assume !(0 == ~E_2~0); 12765195#L1361-1 assume !(0 == ~E_3~0); 12765879#L1366-1 assume !(0 == ~E_4~0); 12765751#L1371-1 assume !(0 == ~E_5~0); 12765752#L1376-1 assume !(0 == ~E_6~0); 12766478#L1381-1 assume !(0 == ~E_7~0); 12764726#L1386-1 assume !(0 == ~E_8~0); 12764307#L1391-1 assume !(0 == ~E_9~0); 12764308#L1396-1 assume !(0 == ~E_10~0); 12765369#L1401-1 assume !(0 == ~E_11~0); 12765370#L1406-1 assume !(0 == ~E_12~0); 12765799#L1411-1 assume !(0 == ~E_13~0); 12765800#L1416-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12766618#L630 assume !(1 == ~m_pc~0); 12766609#L630-2 is_master_triggered_~__retres1~0 := 0; 12764659#L641 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12764359#L642 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12764360#L1593 assume !(0 != activate_threads_~tmp~1); 12766886#L1593-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12765521#L649 assume !(1 == ~t1_pc~0); 12765451#L649-2 is_transmit1_triggered_~__retres1~1 := 0; 12765527#L660 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12766059#L661 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12766279#L1601 assume !(0 != activate_threads_~tmp___0~0); 12766280#L1601-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12766288#L668 assume !(1 == ~t2_pc~0); 12766897#L668-2 is_transmit2_triggered_~__retres1~2 := 0; 12765042#L679 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12765002#L680 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12764524#L1609 assume !(0 != activate_threads_~tmp___1~0); 12764525#L1609-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12764293#L687 assume !(1 == ~t3_pc~0); 12764273#L687-2 is_transmit3_triggered_~__retres1~3 := 0; 12764274#L698 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12765057#L699 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12765159#L1617 assume !(0 != activate_threads_~tmp___2~0); 12765420#L1617-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12765423#L706 assume !(1 == ~t4_pc~0); 12765832#L706-2 is_transmit4_triggered_~__retres1~4 := 0; 12765837#L717 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12766552#L718 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12766113#L1625 assume !(0 != activate_threads_~tmp___3~0); 12766114#L1625-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12764805#L725 assume !(1 == ~t5_pc~0); 12764780#L725-2 is_transmit5_triggered_~__retres1~5 := 0; 12764781#L736 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12765425#L737 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12765547#L1633 assume !(0 != activate_threads_~tmp___4~0); 12765724#L1633-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12765731#L744 assume !(1 == ~t6_pc~0); 12766124#L744-2 is_transmit6_triggered_~__retres1~6 := 0; 12766127#L755 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12766781#L756 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12766587#L1641 assume !(0 != activate_threads_~tmp___5~0); 12766588#L1641-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12766415#L763 assume !(1 == ~t7_pc~0); 12766383#L763-2 is_transmit7_triggered_~__retres1~7 := 0; 12764374#L774 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12764287#L775 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12764288#L1649 assume !(0 != activate_threads_~tmp___6~0); 12765007#L1649-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12765012#L782 assume !(1 == ~t8_pc~0); 12765248#L782-2 is_transmit8_triggered_~__retres1~8 := 0; 12765439#L793 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12765842#L794 activate_threads_#t~ret25 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12764439#L1657 assume !(0 != activate_threads_~tmp___7~0); 12764440#L1657-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12764450#L801 assume !(1 == ~t9_pc~0); 12766848#L801-2 is_transmit9_triggered_~__retres1~9 := 0; 12765013#L812 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12764798#L813 activate_threads_#t~ret26 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12764799#L1665 assume !(0 != activate_threads_~tmp___8~0); 12765379#L1665-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12764464#L820 assume !(1 == ~t10_pc~0); 12764465#L820-2 is_transmit10_triggered_~__retres1~10 := 0; 12764468#L831 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 12765165#L832 activate_threads_#t~ret27 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12766060#L1673 assume !(0 != activate_threads_~tmp___9~0); 12766061#L1673-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 12765989#L839 assume !(1 == ~t11_pc~0); 12765990#L839-2 is_transmit11_triggered_~__retres1~11 := 0; 12765993#L850 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 12766406#L851 activate_threads_#t~ret28 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 12766407#L1681 assume !(0 != activate_threads_~tmp___10~0); 12766898#L1681-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 12764941#L858 assume !(1 == ~t12_pc~0); 12764861#L858-2 is_transmit12_triggered_~__retres1~12 := 0; 12764862#L869 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 12765461#L870 activate_threads_#t~ret29 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 12765462#L1689 assume !(0 != activate_threads_~tmp___11~0); 12766266#L1689-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 12766070#L877 assume !(1 == ~t13_pc~0); 12766072#L877-2 is_transmit13_triggered_~__retres1~13 := 0; 12766076#L888 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 12766758#L889 activate_threads_#t~ret30 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12764533#L1697 assume !(0 != activate_threads_~tmp___12~0); 12764534#L1697-2 assume !(1 == ~M_E~0); 12764535#L1429-1 assume !(1 == ~T1_E~0); 12764609#L1434-1 assume !(1 == ~T2_E~0); 12764610#L1439-1 assume !(1 == ~T3_E~0); 12765180#L1444-1 assume !(1 == ~T4_E~0); 12765181#L1449-1 assume !(1 == ~T5_E~0); 12765866#L1454-1 assume !(1 == ~T6_E~0); 12765745#L1459-1 assume !(1 == ~T7_E~0); 12765746#L1464-1 assume !(1 == ~T8_E~0); 12766512#L1469-1 assume !(1 == ~T9_E~0); 12764757#L1474-1 assume !(1 == ~T10_E~0); 12764346#L1479-1 assume !(1 == ~T11_E~0); 12764347#L1484-1 assume !(1 == ~T12_E~0); 12765377#L1489-1 assume !(1 == ~T13_E~0); 12765378#L1494-1 assume !(1 == ~E_M~0); 12765825#L1499-1 assume !(1 == ~E_1~0); 12765826#L1504-1 assume !(1 == ~E_2~0); 12766581#L1509-1 assume !(1 == ~E_3~0); 12766428#L1514-1 assume !(1 == ~E_4~0); 12764896#L1519-1 assume !(1 == ~E_5~0); 12764497#L1524-1 assume !(1 == ~E_6~0); 12764498#L1529-1 assume !(1 == ~E_7~0); 12765080#L1534-1 assume !(1 == ~E_8~0); 12765081#L1539-1 assume !(1 == ~E_9~0); 12765956#L1544-1 assume !(1 == ~E_10~0); 12765957#L1549-1 assume !(1 == ~E_11~0); 12766541#L1554-1 assume !(1 == ~E_12~0); 12764955#L1559-1 assume !(1 == ~E_13~0); 12764956#L1930-1 assume !false; 12826563#L1931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_#t~nondet12, eval_~tmp_ndt_10~0, eval_#t~nondet13, eval_~tmp_ndt_11~0, eval_#t~nondet14, eval_~tmp_ndt_12~0, eval_#t~nondet15, eval_~tmp_ndt_13~0, eval_#t~nondet16, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 12826557#L1256 [2018-11-28 12:54:04,964 INFO L796 eck$LassoCheckResult]: Loop: 12826557#L1256 assume !false; 12826550#L1065 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 12826528#L982 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12826520#L1054 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 12826512#L1055 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 12826504#L1069 assume 0 != eval_~tmp~0; 12826339#L1069-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 12826332#L1077 assume !(0 != eval_~tmp_ndt_1~0); 12814158#L1074 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 12814154#L1091 assume !(0 != eval_~tmp_ndt_2~0); 12814152#L1088 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 12814149#L1105 assume !(0 != eval_~tmp_ndt_3~0); 12814150#L1102 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 12795124#L1119 assume !(0 != eval_~tmp_ndt_4~0); 12825532#L1116 assume !(0 == ~t4_st~0); 12825318#L1130 assume !(0 == ~t5_st~0); 12825312#L1144 assume !(0 == ~t6_st~0); 12825139#L1158 assume !(0 == ~t7_st~0); 12828844#L1172 assume !(0 == ~t8_st~0); 12828840#L1186 assume !(0 == ~t9_st~0); 12828691#L1200 assume !(0 == ~t10_st~0); 12828677#L1214 assume !(0 == ~t11_st~0); 12828456#L1228 assume !(0 == ~t12_st~0); 12826561#L1242 assume !(0 == ~t13_st~0); 12826557#L1256 [2018-11-28 12:54:04,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:54:04,964 INFO L82 PathProgramCache]: Analyzing trace with hash 946147331, now seen corresponding path program 4 times [2018-11-28 12:54:04,965 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:54:04,965 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:54:04,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:54:04,965 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:54:04,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:54:04,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:54:04,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:54:05,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:54:05,021 INFO L82 PathProgramCache]: Analyzing trace with hash -1521119814, now seen corresponding path program 1 times [2018-11-28 12:54:05,021 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:54:05,021 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:54:05,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:54:05,021 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 12:54:05,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:54:05,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:54:05,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 12:54:05,026 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 12:54:05,026 INFO L82 PathProgramCache]: Analyzing trace with hash 1273706428, now seen corresponding path program 1 times [2018-11-28 12:54:05,026 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 12:54:05,027 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 12:54:05,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:54:05,027 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 12:54:05,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 12:54:05,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 12:54:05,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 12:54:05,079 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 12:54:05,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 12:54:05,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 12:54:05,188 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 12:54:05,188 INFO L87 Difference]: Start difference. First operand 1760876 states and 2358637 transitions. cyclomatic complexity: 597953 Second operand 3 states. [2018-11-28 12:54:10,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 12:54:10,269 INFO L93 Difference]: Finished difference Result 2546732 states and 3407949 transitions. [2018-11-28 12:54:10,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 12:54:10,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2546732 states and 3407949 transitions. [2018-11-28 12:54:19,466 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 2533120 [2018-11-28 12:54:42,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2546732 states to 2546732 states and 3407949 transitions. [2018-11-28 12:54:42,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2546732 [2018-11-28 12:54:42,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2546732 [2018-11-28 12:54:42,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2546732 states and 3407949 transitions. [2018-11-28 12:54:43,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 12:54:43,104 INFO L705 BuchiCegarLoop]: Abstraction has 2546732 states and 3407949 transitions. [2018-11-28 12:54:43,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2546732 states and 3407949 transitions. [2018-11-28 12:55:24,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2546732 to 2495276. [2018-11-28 12:55:24,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2495276 states. [2018-11-28 12:55:56,781 FATAL L292 ToolchainWalker]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.OutOfMemoryError: Java heap space at java.util.HashMap.resize(HashMap.java:704) at java.util.HashMap.putVal(HashMap.java:663) at java.util.HashMap.put(HashMap.java:612) at java.util.HashSet.add(HashSet.java:220) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.addState(NestedWordAutomatonReachableStates.java:1043) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.addInternalsAndSuccessors(NestedWordAutomatonReachableStates.java:1074) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.(NestedWordAutomatonReachableStates.java:968) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates.(NestedWordAutomatonReachableStates.java:188) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.RemoveUnreachable.(RemoveUnreachable.java:67) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.automataminimization.AutomataMinimization.(AutomataMinimization.java:145) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.reduceAbstractionSize(BuchiCegarLoop.java:711) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:551) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:145) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:384) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-11-28 12:55:56,784 INFO L168 Benchmark]: Toolchain (without parser) took 313643.72 ms. Allocated memory was 1.0 GB in the beginning and 9.0 GB in the end (delta: 8.0 GB). Free memory was 950.6 MB in the beginning and 9.0 GB in the end (delta: -8.0 GB). Peak memory consumption was 11.4 GB. Max. memory is 11.5 GB. [2018-11-28 12:55:56,785 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 12:55:56,785 INFO L168 Benchmark]: CACSL2BoogieTranslator took 421.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 126.9 MB). Free memory was 950.6 MB in the beginning and 1.1 GB in the end (delta: -167.7 MB). Peak memory consumption was 36.7 MB. Max. memory is 11.5 GB. [2018-11-28 12:55:56,786 INFO L168 Benchmark]: Boogie Procedure Inliner took 90.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-28 12:55:56,787 INFO L168 Benchmark]: Boogie Preprocessor took 89.34 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. [2018-11-28 12:55:56,787 INFO L168 Benchmark]: RCFGBuilder took 2048.03 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 963.4 MB in the end (delta: 122.6 MB). Peak memory consumption was 240.9 MB. Max. memory is 11.5 GB. [2018-11-28 12:55:56,787 INFO L168 Benchmark]: BuchiAutomizer took 310991.88 ms. Allocated memory was 1.2 GB in the beginning and 9.0 GB in the end (delta: 7.9 GB). Free memory was 963.4 MB in the beginning and 9.0 GB in the end (delta: -8.0 GB). Peak memory consumption was 11.3 GB. Max. memory is 11.5 GB. [2018-11-28 12:55:56,791 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 421.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 126.9 MB). Free memory was 950.6 MB in the beginning and 1.1 GB in the end (delta: -167.7 MB). Peak memory consumption was 36.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 90.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 89.34 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 2048.03 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 963.4 MB in the end (delta: 122.6 MB). Peak memory consumption was 240.9 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 310991.88 ms. Allocated memory was 1.2 GB in the beginning and 9.0 GB in the end (delta: 7.9 GB). Free memory was 963.4 MB in the beginning and 9.0 GB in the end (delta: -8.0 GB). Peak memory consumption was 11.3 GB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: OutOfMemoryError: Java heap space de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: OutOfMemoryError: Java heap space: java.util.HashMap.resize(HashMap.java:704) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...