./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.07_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0cd3be1d Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.07_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7065f281083809b042f9cd06530419b32b632e49 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-0cd3be1 [2018-11-28 11:38:33,885 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-28 11:38:33,887 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-28 11:38:33,894 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-28 11:38:33,894 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-28 11:38:33,895 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-28 11:38:33,897 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-28 11:38:33,898 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-28 11:38:33,899 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-28 11:38:33,900 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-28 11:38:33,901 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-28 11:38:33,901 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-28 11:38:33,902 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-28 11:38:33,903 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-28 11:38:33,904 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-28 11:38:33,904 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-28 11:38:33,905 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-28 11:38:33,907 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-28 11:38:33,908 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-28 11:38:33,910 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-28 11:38:33,911 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-28 11:38:33,912 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-28 11:38:33,913 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-28 11:38:33,914 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-28 11:38:33,914 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-28 11:38:33,915 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-28 11:38:33,916 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-28 11:38:33,917 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-28 11:38:33,917 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-28 11:38:33,918 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-28 11:38:33,919 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-28 11:38:33,919 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-28 11:38:33,919 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-28 11:38:33,920 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-28 11:38:33,920 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-28 11:38:33,921 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-28 11:38:33,921 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-28 11:38:33,934 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-28 11:38:33,934 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-28 11:38:33,935 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-28 11:38:33,935 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-28 11:38:33,936 INFO L133 SettingsManager]: * Use SBE=true [2018-11-28 11:38:33,936 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-28 11:38:33,936 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-28 11:38:33,936 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-28 11:38:33,936 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-28 11:38:33,936 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-28 11:38:33,937 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-28 11:38:33,937 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-28 11:38:33,937 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-28 11:38:33,937 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-28 11:38:33,937 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-28 11:38:33,937 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-28 11:38:33,938 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-28 11:38:33,938 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-28 11:38:33,938 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-28 11:38:33,938 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-28 11:38:33,938 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-28 11:38:33,938 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-28 11:38:33,939 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-28 11:38:33,939 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-28 11:38:33,939 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-28 11:38:33,939 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-28 11:38:33,939 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-28 11:38:33,940 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-28 11:38:33,940 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-28 11:38:33,940 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-28 11:38:33,940 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-28 11:38:33,941 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-28 11:38:33,941 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7065f281083809b042f9cd06530419b32b632e49 [2018-11-28 11:38:33,971 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-28 11:38:33,982 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-28 11:38:33,985 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-28 11:38:33,987 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-28 11:38:33,987 INFO L276 PluginConnector]: CDTParser initialized [2018-11-28 11:38:33,988 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.07_false-unreach-call_false-termination.cil.c [2018-11-28 11:38:34,041 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/data/20eb01984/e5516fa4bcf04f27ba5cff500b06b808/FLAG92ec61832 [2018-11-28 11:38:34,409 INFO L307 CDTParser]: Found 1 translation units. [2018-11-28 11:38:34,410 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/sv-benchmarks/c/systemc/transmitter.07_false-unreach-call_false-termination.cil.c [2018-11-28 11:38:34,421 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/data/20eb01984/e5516fa4bcf04f27ba5cff500b06b808/FLAG92ec61832 [2018-11-28 11:38:34,798 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/data/20eb01984/e5516fa4bcf04f27ba5cff500b06b808 [2018-11-28 11:38:34,801 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-28 11:38:34,802 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-28 11:38:34,803 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-28 11:38:34,803 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-28 11:38:34,806 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-28 11:38:34,806 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:38:34" (1/1) ... [2018-11-28 11:38:34,808 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b0bf2a3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:34, skipping insertion in model container [2018-11-28 11:38:34,808 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:38:34" (1/1) ... [2018-11-28 11:38:34,813 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-28 11:38:34,842 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-28 11:38:35,025 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:38:35,031 INFO L191 MainTranslator]: Completed pre-run [2018-11-28 11:38:35,081 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-11-28 11:38:35,099 INFO L195 MainTranslator]: Completed translation [2018-11-28 11:38:35,100 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35 WrapperNode [2018-11-28 11:38:35,100 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-28 11:38:35,101 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-28 11:38:35,101 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-28 11:38:35,101 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-28 11:38:35,149 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,155 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,192 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-28 11:38:35,193 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-28 11:38:35,193 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-28 11:38:35,193 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-28 11:38:35,203 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,203 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,208 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,208 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,224 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,245 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,248 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... [2018-11-28 11:38:35,255 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-28 11:38:35,255 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-28 11:38:35,255 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-28 11:38:35,255 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-28 11:38:35,256 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-28 11:38:35,318 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-28 11:38:35,318 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-28 11:38:36,500 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-28 11:38:36,500 INFO L280 CfgBuilder]: Removed 259 assue(true) statements. [2018-11-28 11:38:36,500 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:38:36 BoogieIcfgContainer [2018-11-28 11:38:36,500 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-28 11:38:36,501 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-28 11:38:36,501 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-28 11:38:36,504 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-28 11:38:36,505 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-28 11:38:36,505 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 11:38:34" (1/3) ... [2018-11-28 11:38:36,506 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b0c1991 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 11:38:36, skipping insertion in model container [2018-11-28 11:38:36,507 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-28 11:38:36,507 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:38:35" (2/3) ... [2018-11-28 11:38:36,507 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b0c1991 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 11:38:36, skipping insertion in model container [2018-11-28 11:38:36,507 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-28 11:38:36,507 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:38:36" (3/3) ... [2018-11-28 11:38:36,509 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.07_false-unreach-call_false-termination.cil.c [2018-11-28 11:38:36,557 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-28 11:38:36,558 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-28 11:38:36,558 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-28 11:38:36,558 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-28 11:38:36,559 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-28 11:38:36,559 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-28 11:38:36,559 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-28 11:38:36,559 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-28 11:38:36,559 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-28 11:38:36,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 751 states. [2018-11-28 11:38:36,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 650 [2018-11-28 11:38:36,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:36,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:36,637 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:36,637 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:36,638 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-28 11:38:36,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 751 states. [2018-11-28 11:38:36,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 650 [2018-11-28 11:38:36,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:36,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:36,650 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:36,651 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:36,660 INFO L794 eck$LassoCheckResult]: Stem: 484#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 356#L-1true havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 466#L1101true havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 671#L504true assume !(1 == ~m_i~0);~m_st~0 := 2; 166#L511-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 381#L516-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 63#L521-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 672#L526-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 306#L531-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 736#L536-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 191#L541-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 631#L546-1true assume !(0 == ~M_E~0); 644#L744-1true assume 0 == ~T1_E~0;~T1_E~0 := 1; 443#L749-1true assume !(0 == ~T2_E~0); 138#L754-1true assume !(0 == ~T3_E~0); 543#L759-1true assume !(0 == ~T4_E~0); 14#L764-1true assume !(0 == ~T5_E~0); 402#L769-1true assume !(0 == ~T6_E~0); 95#L774-1true assume !(0 == ~T7_E~0); 695#L779-1true assume !(0 == ~E_1~0); 328#L784-1true assume 0 == ~E_2~0;~E_2~0 := 1; 741#L789-1true assume !(0 == ~E_3~0); 195#L794-1true assume !(0 == ~E_4~0); 639#L799-1true assume !(0 == ~E_5~0); 438#L804-1true assume !(0 == ~E_6~0); 135#L809-1true assume !(0 == ~E_7~0); 539#L814-1true havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 389#L351true assume 1 == ~m_pc~0; 515#L352true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 387#L362true is_master_triggered_#res := is_master_triggered_~__retres1~0; 513#L363true activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 651#L920true assume !(0 != activate_threads_~tmp~1); 654#L920-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 604#L370true assume !(1 == ~t1_pc~0); 614#L370-2true is_transmit1_triggered_~__retres1~1 := 0; 602#L381true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 717#L382true activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 276#L928true assume !(0 != activate_threads_~tmp___0~0); 88#L928-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 73#L389true assume 1 == ~t2_pc~0; 171#L390true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 71#L400true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 170#L401true activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 453#L936true assume !(0 != activate_threads_~tmp___1~0); 455#L936-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 245#L408true assume !(1 == ~t3_pc~0); 253#L408-2true is_transmit3_triggered_~__retres1~3 := 0; 243#L419true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 175#L420true activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 699#L944true assume !(0 != activate_threads_~tmp___2~0); 690#L944-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 678#L427true assume 1 == ~t4_pc~0; 383#L428true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 677#L438true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 382#L439true activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 146#L952true assume !(0 != activate_threads_~tmp___3~0); 148#L952-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 114#L446true assume 1 == ~t5_pc~0; 636#L447true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 112#L457true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 634#L458true activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 334#L960true assume !(0 != activate_threads_~tmp___4~0); 322#L960-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 309#L465true assume !(1 == ~t6_pc~0); 313#L465-2true is_transmit6_triggered_~__retres1~6 := 0; 308#L476true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 64#L477true activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 552#L968true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 554#L968-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 502#L484true assume 1 == ~t7_pc~0; 268#L485true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 535#L495true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 267#L496true activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 575#L976true assume !(0 != activate_threads_~tmp___6~0); 558#L976-2true assume !(1 == ~M_E~0); 205#L827-1true assume !(1 == ~T1_E~0); 659#L832-1true assume !(1 == ~T2_E~0); 436#L837-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 132#L842-1true assume !(1 == ~T4_E~0); 536#L847-1true assume !(1 == ~T5_E~0); 10#L852-1true assume !(1 == ~T6_E~0); 398#L857-1true assume !(1 == ~T7_E~0); 89#L862-1true assume !(1 == ~E_1~0); 692#L867-1true assume !(1 == ~E_2~0); 324#L872-1true assume !(1 == ~E_3~0); 561#L877-1true assume 1 == ~E_4~0;~E_4~0 := 2; 203#L882-1true assume !(1 == ~E_5~0); 655#L887-1true assume !(1 == ~E_6~0); 456#L892-1true assume !(1 == ~E_7~0); 31#L1138-1true [2018-11-28 11:38:36,662 INFO L796 eck$LassoCheckResult]: Loop: 31#L1138-1true assume !false; 151#L1139true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 98#L719true assume false; 742#L734true start_simulation_~kernel_st~0 := 2; 675#L504-1true start_simulation_~kernel_st~0 := 3; 647#L744-2true assume 0 == ~M_E~0;~M_E~0 := 1; 621#L744-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 449#L749-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 143#L754-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 521#L759-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 3#L764-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 391#L769-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 80#L774-3true assume !(0 == ~T7_E~0); 682#L779-3true assume 0 == ~E_1~0;~E_1~0 := 1; 316#L784-3true assume 0 == ~E_2~0;~E_2~0 := 1; 746#L789-3true assume 0 == ~E_3~0;~E_3~0 := 1; 198#L794-3true assume 0 == ~E_4~0;~E_4~0 := 1; 646#L799-3true assume 0 == ~E_5~0;~E_5~0 := 1; 446#L804-3true assume 0 == ~E_6~0;~E_6~0 := 1; 139#L809-3true assume 0 == ~E_7~0;~E_7~0 := 1; 545#L814-3true havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 529#L351-24true assume 1 == ~m_pc~0; 467#L352-8true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 351#L362-8true is_master_triggered_#res := is_master_triggered_~__retres1~0; 465#L363-8true activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 594#L920-24true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 569#L920-26true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 753#L370-24true assume 1 == ~t1_pc~0; 712#L371-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 595#L381-8true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 710#L382-8true activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27#L928-24true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 33#L928-26true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6#L389-24true assume !(1 == ~t2_pc~0); 7#L389-26true is_transmit2_triggered_~__retres1~2 := 0; 28#L400-8true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 150#L401-8true activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 236#L936-24true assume !(0 != activate_threads_~tmp___1~0); 209#L936-26true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 200#L408-24true assume 1 == ~t3_pc~0; 342#L409-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 233#L419-8true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 341#L420-8true activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 412#L944-24true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 417#L944-26true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 392#L427-24true assume !(1 == ~t4_pc~0); 393#L427-26true is_transmit4_triggered_~__retres1~4 := 0; 409#L438-8true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 378#L439-8true activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 109#L952-24true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 660#L952-26true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 648#L446-24true assume 1 == ~t5_pc~0; 588#L447-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 107#L457-8true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 586#L458-8true activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 285#L960-24true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 288#L960-26true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 79#L465-24true assume !(1 == ~t6_pc~0); 83#L465-26true is_transmit6_triggered_~__retres1~6 := 0; 280#L476-8true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 54#L477-8true activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 498#L968-24true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 464#L968-26true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 444#L484-24true assume 1 == ~t7_pc~0; 226#L485-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 490#L495-8true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 224#L496-8true activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 706#L976-24true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 711#L976-26true assume 1 == ~M_E~0;~M_E~0 := 2; 197#L827-3true assume !(1 == ~T1_E~0); 641#L832-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 442#L837-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 137#L842-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 542#L847-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 13#L852-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 401#L857-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 94#L862-3true assume 1 == ~E_1~0;~E_1~0 := 2; 694#L867-3true assume !(1 == ~E_2~0); 326#L872-3true assume 1 == ~E_3~0;~E_3~0 := 2; 566#L877-3true assume 1 == ~E_4~0;~E_4~0 := 2; 206#L882-3true assume 1 == ~E_5~0;~E_5~0 := 2; 637#L887-3true assume 1 == ~E_6~0;~E_6~0 := 2; 437#L892-3true assume 1 == ~E_7~0;~E_7~0 := 2; 133#L897-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 670#L559-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 626#L601-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 732#L602-1true start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 237#L1157true assume !(0 == start_simulation_~tmp~3); 208#L1157-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 673#L559-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 629#L601-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 734#L602-2true stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 469#L1112true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 597#L1119true stop_simulation_#res := stop_simulation_~__retres2~0; 713#L1120true start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 286#L1170true assume !(0 != start_simulation_~tmp___0~1); 31#L1138-1true [2018-11-28 11:38:36,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:36,675 INFO L82 PathProgramCache]: Analyzing trace with hash 566963146, now seen corresponding path program 1 times [2018-11-28 11:38:36,677 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:36,678 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:36,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:36,727 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:36,727 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:36,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:36,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:36,831 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:36,832 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:36,835 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:36,835 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:36,835 INFO L82 PathProgramCache]: Analyzing trace with hash -2014644323, now seen corresponding path program 1 times [2018-11-28 11:38:36,835 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:36,836 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:36,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:36,837 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:36,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:36,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:36,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:36,857 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:36,857 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:36,858 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:36,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:36,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:36,869 INFO L87 Difference]: Start difference. First operand 751 states. Second operand 3 states. [2018-11-28 11:38:36,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:36,913 INFO L93 Difference]: Finished difference Result 751 states and 1131 transitions. [2018-11-28 11:38:36,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:36,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 751 states and 1131 transitions. [2018-11-28 11:38:36,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:36,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 751 states to 746 states and 1126 transitions. [2018-11-28 11:38:36,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:36,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:36,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1126 transitions. [2018-11-28 11:38:36,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:36,940 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1126 transitions. [2018-11-28 11:38:36,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1126 transitions. [2018-11-28 11:38:36,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:36,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:36,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1126 transitions. [2018-11-28 11:38:36,983 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1126 transitions. [2018-11-28 11:38:36,983 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1126 transitions. [2018-11-28 11:38:36,984 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-28 11:38:36,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1126 transitions. [2018-11-28 11:38:36,988 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:36,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:36,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:36,990 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:36,990 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:36,991 INFO L794 eck$LassoCheckResult]: Stem: 2123#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2017#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2018#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2107#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 1774#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1775#L516-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1623#L521-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1624#L526-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1958#L531-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1959#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1817#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1818#L546-1 assume !(0 == ~M_E~0); 2229#L744-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2091#L749-1 assume !(0 == ~T2_E~0); 1748#L754-1 assume !(0 == ~T3_E~0); 1749#L759-1 assume !(0 == ~T4_E~0); 1535#L764-1 assume !(0 == ~T5_E~0); 1536#L769-1 assume !(0 == ~T6_E~0); 1673#L774-1 assume !(0 == ~T7_E~0); 1674#L779-1 assume !(0 == ~E_1~0); 1981#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1982#L789-1 assume !(0 == ~E_3~0); 1823#L794-1 assume !(0 == ~E_4~0); 1824#L799-1 assume !(0 == ~E_5~0); 2087#L804-1 assume !(0 == ~E_6~0); 1742#L809-1 assume !(0 == ~E_7~0); 1743#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2067#L351 assume 1 == ~m_pc~0; 2068#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2031#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2066#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2138#L920 assume !(0 != activate_threads_~tmp~1); 2234#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2208#L370 assume !(1 == ~t1_pc~0); 2209#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 2206#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2207#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1937#L928 assume !(0 != activate_threads_~tmp___0~0); 1665#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1643#L389 assume 1 == ~t2_pc~0; 1644#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1583#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1642#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1778#L936 assume !(0 != activate_threads_~tmp___1~0); 2095#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1897#L408 assume !(1 == ~t3_pc~0); 1785#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 1784#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1781#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1782#L944 assume !(0 != activate_threads_~tmp___2~0); 2242#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2239#L427 assume 1 == ~t4_pc~0; 2055#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2056#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2054#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1763#L952 assume !(0 != activate_threads_~tmp___3~0); 1764#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1708#L446 assume 1 == ~t5_pc~0; 1709#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1706#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1707#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1988#L960 assume !(0 != activate_threads_~tmp___4~0); 1973#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1962#L465 assume !(1 == ~t6_pc~0); 1629#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 1628#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1625#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1626#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2152#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2135#L484 assume 1 == ~t7_pc~0; 1926#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1927#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1924#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1925#L976 assume !(0 != activate_threads_~tmp___6~0); 2156#L976-2 assume !(1 == ~M_E~0); 1843#L827-1 assume !(1 == ~T1_E~0); 1844#L832-1 assume !(1 == ~T2_E~0); 2084#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1737#L842-1 assume !(1 == ~T4_E~0); 1738#L847-1 assume !(1 == ~T5_E~0); 1530#L852-1 assume !(1 == ~T6_E~0); 1531#L857-1 assume !(1 == ~T7_E~0); 1666#L862-1 assume !(1 == ~E_1~0); 1667#L867-1 assume !(1 == ~E_2~0); 1976#L872-1 assume !(1 == ~E_3~0); 1977#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1839#L882-1 assume !(1 == ~E_5~0); 1840#L887-1 assume !(1 == ~E_6~0); 2097#L892-1 assume !(1 == ~E_7~0); 1570#L1138-1 [2018-11-28 11:38:36,991 INFO L796 eck$LassoCheckResult]: Loop: 1570#L1138-1 assume !false; 1571#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1676#L719 assume !false; 1677#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2221#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1662#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2223#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2140#L616 assume !(0 != eval_~tmp~0); 2142#L734 start_simulation_~kernel_st~0 := 2; 2237#L504-1 start_simulation_~kernel_st~0 := 3; 2233#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2222#L744-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2094#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1759#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1760#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1511#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1512#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1655#L774-3 assume !(0 == ~T7_E~0); 1656#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1964#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1965#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1830#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1831#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2093#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1750#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1751#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2144#L351-24 assume 1 == ~m_pc~0; 2104#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2007#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2008#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2103#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2171#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2172#L370-24 assume 1 == ~t1_pc~0; 2249#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2201#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2202#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1560#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1561#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1515#L389-24 assume !(1 == ~t2_pc~0); 1516#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 1521#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1562#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1767#L936-24 assume !(0 != activate_threads_~tmp___1~0); 1852#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1833#L408-24 assume !(1 == ~t3_pc~0); 1810#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 1811#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1882#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1991#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2076#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2069#L427-24 assume 1 == ~t4_pc~0; 1993#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1995#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2053#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1697#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1698#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2232#L446-24 assume !(1 == ~t5_pc~0); 2192#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 1694#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1695#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1942#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1943#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1654#L465-24 assume 1 == ~t6_pc~0; 1610#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1611#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1607#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1608#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2102#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2090#L484-24 assume !(1 == ~t7_pc~0); 1873#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 1872#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1868#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1869#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2246#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 1828#L827-3 assume !(1 == ~T1_E~0); 1829#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2089#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1746#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1747#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1533#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1534#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1671#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1672#L867-3 assume !(1 == ~E_2~0); 1978#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1979#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1845#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1846#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2085#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1739#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1740#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1664#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2225#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1883#L1157 assume !(0 == start_simulation_~tmp~3); 1850#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1851#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1620#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2227#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 2108#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2109#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 2203#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1944#L1170 assume !(0 != start_simulation_~tmp___0~1); 1570#L1138-1 [2018-11-28 11:38:36,991 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:36,992 INFO L82 PathProgramCache]: Analyzing trace with hash -1769429364, now seen corresponding path program 1 times [2018-11-28 11:38:36,992 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:36,992 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:36,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:36,993 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:36,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,039 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,039 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,040 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:37,040 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,040 INFO L82 PathProgramCache]: Analyzing trace with hash -164715871, now seen corresponding path program 1 times [2018-11-28 11:38:37,040 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,041 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,041 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,042 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,116 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,116 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,117 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:37,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:37,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:37,117 INFO L87 Difference]: Start difference. First operand 746 states and 1126 transitions. cyclomatic complexity: 381 Second operand 3 states. [2018-11-28 11:38:37,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:37,133 INFO L93 Difference]: Finished difference Result 746 states and 1125 transitions. [2018-11-28 11:38:37,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:37,134 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1125 transitions. [2018-11-28 11:38:37,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1125 transitions. [2018-11-28 11:38:37,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:37,145 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:37,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1125 transitions. [2018-11-28 11:38:37,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:37,148 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1125 transitions. [2018-11-28 11:38:37,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1125 transitions. [2018-11-28 11:38:37,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:37,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:37,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1125 transitions. [2018-11-28 11:38:37,162 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1125 transitions. [2018-11-28 11:38:37,162 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1125 transitions. [2018-11-28 11:38:37,162 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-28 11:38:37,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1125 transitions. [2018-11-28 11:38:37,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:37,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:37,168 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,168 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,169 INFO L794 eck$LassoCheckResult]: Stem: 3621#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3515#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3516#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3603#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 3273#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3274#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3122#L521-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3123#L526-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3457#L531-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3458#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3316#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3317#L546-1 assume !(0 == ~M_E~0); 3728#L744-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3589#L749-1 assume !(0 == ~T2_E~0); 3247#L754-1 assume !(0 == ~T3_E~0); 3248#L759-1 assume !(0 == ~T4_E~0); 3034#L764-1 assume !(0 == ~T5_E~0); 3035#L769-1 assume !(0 == ~T6_E~0); 3172#L774-1 assume !(0 == ~T7_E~0); 3173#L779-1 assume !(0 == ~E_1~0); 3480#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3481#L789-1 assume !(0 == ~E_3~0); 3322#L794-1 assume !(0 == ~E_4~0); 3323#L799-1 assume !(0 == ~E_5~0); 3585#L804-1 assume !(0 == ~E_6~0); 3241#L809-1 assume !(0 == ~E_7~0); 3242#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3566#L351 assume 1 == ~m_pc~0; 3567#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3530#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3562#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3637#L920 assume !(0 != activate_threads_~tmp~1); 3733#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3707#L370 assume !(1 == ~t1_pc~0); 3708#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 3705#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3706#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3436#L928 assume !(0 != activate_threads_~tmp___0~0); 3164#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3142#L389 assume 1 == ~t2_pc~0; 3143#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3082#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3138#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3277#L936 assume !(0 != activate_threads_~tmp___1~0); 3594#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3396#L408 assume !(1 == ~t3_pc~0); 3284#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 3283#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3280#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3281#L944 assume !(0 != activate_threads_~tmp___2~0); 3741#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3738#L427 assume 1 == ~t4_pc~0; 3554#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3555#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3553#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3262#L952 assume !(0 != activate_threads_~tmp___3~0); 3263#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3207#L446 assume 1 == ~t5_pc~0; 3208#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3203#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3204#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3487#L960 assume !(0 != activate_threads_~tmp___4~0); 3472#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3459#L465 assume !(1 == ~t6_pc~0); 3128#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 3127#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3124#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3125#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3651#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3634#L484 assume 1 == ~t7_pc~0; 3425#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3426#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3423#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3424#L976 assume !(0 != activate_threads_~tmp___6~0); 3655#L976-2 assume !(1 == ~M_E~0); 3342#L827-1 assume !(1 == ~T1_E~0); 3343#L832-1 assume !(1 == ~T2_E~0); 3583#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3236#L842-1 assume !(1 == ~T4_E~0); 3237#L847-1 assume !(1 == ~T5_E~0); 3026#L852-1 assume !(1 == ~T6_E~0); 3027#L857-1 assume !(1 == ~T7_E~0); 3165#L862-1 assume !(1 == ~E_1~0); 3166#L867-1 assume !(1 == ~E_2~0); 3475#L872-1 assume !(1 == ~E_3~0); 3476#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3338#L882-1 assume !(1 == ~E_5~0); 3339#L887-1 assume !(1 == ~E_6~0); 3596#L892-1 assume !(1 == ~E_7~0); 3066#L1138-1 [2018-11-28 11:38:37,169 INFO L796 eck$LassoCheckResult]: Loop: 3066#L1138-1 assume !false; 3067#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3175#L719 assume !false; 3176#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3720#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3161#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3722#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3639#L616 assume !(0 != eval_~tmp~0); 3641#L734 start_simulation_~kernel_st~0 := 2; 3736#L504-1 start_simulation_~kernel_st~0 := 3; 3731#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3721#L744-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3593#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3257#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3258#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3010#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3011#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3154#L774-3 assume !(0 == ~T7_E~0); 3155#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3463#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3464#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3329#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3330#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3592#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3249#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3250#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3645#L351-24 assume 1 == ~m_pc~0; 3604#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3506#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3507#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3602#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3670#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3671#L370-24 assume 1 == ~t1_pc~0; 3748#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3700#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3701#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3059#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3060#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3017#L389-24 assume !(1 == ~t2_pc~0); 3018#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 3020#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3061#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3266#L936-24 assume !(0 != activate_threads_~tmp___1~0); 3351#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3332#L408-24 assume 1 == ~t3_pc~0; 3333#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3310#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3381#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3490#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3575#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3568#L427-24 assume 1 == ~t4_pc~0; 3494#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3496#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3552#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3196#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3197#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3732#L446-24 assume 1 == ~t5_pc~0; 3690#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3193#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3194#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3441#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3442#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3153#L465-24 assume 1 == ~t6_pc~0; 3109#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3110#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3106#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3107#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3601#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3590#L484-24 assume 1 == ~t7_pc~0; 3370#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3371#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3367#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3368#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3745#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 3327#L827-3 assume !(1 == ~T1_E~0); 3328#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3588#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3245#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3246#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3032#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3033#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3170#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3171#L867-3 assume !(1 == ~E_2~0); 3477#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3478#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3344#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3345#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3584#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3238#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3239#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3163#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3724#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 3383#L1157 assume !(0 == start_simulation_~tmp~3); 3349#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3350#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3119#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3726#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 3607#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3608#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 3703#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3443#L1170 assume !(0 != start_simulation_~tmp___0~1); 3066#L1138-1 [2018-11-28 11:38:37,170 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,170 INFO L82 PathProgramCache]: Analyzing trace with hash 109701582, now seen corresponding path program 1 times [2018-11-28 11:38:37,170 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,170 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,199 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,199 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,200 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:37,200 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,200 INFO L82 PathProgramCache]: Analyzing trace with hash 2045052254, now seen corresponding path program 1 times [2018-11-28 11:38:37,200 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,200 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,201 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,201 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,201 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,260 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,260 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,260 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:37,261 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:37,261 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:37,261 INFO L87 Difference]: Start difference. First operand 746 states and 1125 transitions. cyclomatic complexity: 380 Second operand 3 states. [2018-11-28 11:38:37,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:37,275 INFO L93 Difference]: Finished difference Result 746 states and 1124 transitions. [2018-11-28 11:38:37,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:37,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1124 transitions. [2018-11-28 11:38:37,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1124 transitions. [2018-11-28 11:38:37,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:37,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:37,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1124 transitions. [2018-11-28 11:38:37,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:37,288 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1124 transitions. [2018-11-28 11:38:37,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1124 transitions. [2018-11-28 11:38:37,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:37,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:37,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1124 transitions. [2018-11-28 11:38:37,301 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1124 transitions. [2018-11-28 11:38:37,301 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1124 transitions. [2018-11-28 11:38:37,301 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-28 11:38:37,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1124 transitions. [2018-11-28 11:38:37,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:37,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:37,307 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,307 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,307 INFO L794 eck$LassoCheckResult]: Stem: 5121#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 5015#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5016#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5103#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 4772#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4773#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4621#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4622#L526-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4956#L531-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4957#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4815#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4816#L546-1 assume !(0 == ~M_E~0); 5227#L744-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5089#L749-1 assume !(0 == ~T2_E~0); 4746#L754-1 assume !(0 == ~T3_E~0); 4747#L759-1 assume !(0 == ~T4_E~0); 4533#L764-1 assume !(0 == ~T5_E~0); 4534#L769-1 assume !(0 == ~T6_E~0); 4671#L774-1 assume !(0 == ~T7_E~0); 4672#L779-1 assume !(0 == ~E_1~0); 4979#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4980#L789-1 assume !(0 == ~E_3~0); 4821#L794-1 assume !(0 == ~E_4~0); 4822#L799-1 assume !(0 == ~E_5~0); 5084#L804-1 assume !(0 == ~E_6~0); 4740#L809-1 assume !(0 == ~E_7~0); 4741#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5065#L351 assume 1 == ~m_pc~0; 5066#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5029#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5064#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5136#L920 assume !(0 != activate_threads_~tmp~1); 5232#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5206#L370 assume !(1 == ~t1_pc~0); 5207#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 5204#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5205#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4935#L928 assume !(0 != activate_threads_~tmp___0~0); 4663#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4641#L389 assume 1 == ~t2_pc~0; 4642#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4581#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4640#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4776#L936 assume !(0 != activate_threads_~tmp___1~0); 5093#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4895#L408 assume !(1 == ~t3_pc~0); 4783#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 4782#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4779#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4780#L944 assume !(0 != activate_threads_~tmp___2~0); 5240#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5237#L427 assume 1 == ~t4_pc~0; 5053#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5054#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5052#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4761#L952 assume !(0 != activate_threads_~tmp___3~0); 4762#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4706#L446 assume 1 == ~t5_pc~0; 4707#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4704#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4705#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4986#L960 assume !(0 != activate_threads_~tmp___4~0); 4971#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4960#L465 assume !(1 == ~t6_pc~0); 4627#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 4626#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4623#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4624#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5150#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5133#L484 assume 1 == ~t7_pc~0; 4924#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4925#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4922#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4923#L976 assume !(0 != activate_threads_~tmp___6~0); 5154#L976-2 assume !(1 == ~M_E~0); 4841#L827-1 assume !(1 == ~T1_E~0); 4842#L832-1 assume !(1 == ~T2_E~0); 5082#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4735#L842-1 assume !(1 == ~T4_E~0); 4736#L847-1 assume !(1 == ~T5_E~0); 4525#L852-1 assume !(1 == ~T6_E~0); 4526#L857-1 assume !(1 == ~T7_E~0); 4664#L862-1 assume !(1 == ~E_1~0); 4665#L867-1 assume !(1 == ~E_2~0); 4974#L872-1 assume !(1 == ~E_3~0); 4975#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4837#L882-1 assume !(1 == ~E_5~0); 4838#L887-1 assume !(1 == ~E_6~0); 5095#L892-1 assume !(1 == ~E_7~0); 4565#L1138-1 [2018-11-28 11:38:37,308 INFO L796 eck$LassoCheckResult]: Loop: 4565#L1138-1 assume !false; 4566#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 4674#L719 assume !false; 4675#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5219#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4660#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5221#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5138#L616 assume !(0 != eval_~tmp~0); 5140#L734 start_simulation_~kernel_st~0 := 2; 5235#L504-1 start_simulation_~kernel_st~0 := 3; 5231#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5220#L744-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5092#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4757#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4758#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4509#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4510#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4653#L774-3 assume !(0 == ~T7_E~0); 4654#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4962#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4963#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4828#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4829#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5091#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4748#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4749#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5144#L351-24 assume 1 == ~m_pc~0; 5104#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5005#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5006#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5101#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5169#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5170#L370-24 assume !(1 == ~t1_pc~0); 5248#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 5199#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5200#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4558#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4559#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4513#L389-24 assume !(1 == ~t2_pc~0); 4514#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 4519#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4560#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4765#L936-24 assume !(0 != activate_threads_~tmp___1~0); 4850#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4831#L408-24 assume 1 == ~t3_pc~0; 4832#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4809#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4880#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4989#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5074#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5067#L427-24 assume !(1 == ~t4_pc~0); 4992#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 4993#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5051#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4695#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4696#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5230#L446-24 assume 1 == ~t5_pc~0; 5187#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4692#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4693#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4940#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4941#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4652#L465-24 assume !(1 == ~t6_pc~0); 4609#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 4608#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4605#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4606#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5100#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5088#L484-24 assume 1 == ~t7_pc~0; 4869#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4870#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4866#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4867#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5244#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 4826#L827-3 assume !(1 == ~T1_E~0); 4827#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5086#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4744#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4745#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4530#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4531#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4669#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4670#L867-3 assume !(1 == ~E_2~0); 4976#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4977#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4843#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4844#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5083#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4737#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4738#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4662#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5223#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 4881#L1157 assume !(0 == start_simulation_~tmp~3); 4848#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4849#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4618#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5225#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 5106#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5107#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 5201#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4942#L1170 assume !(0 != start_simulation_~tmp___0~1); 4565#L1138-1 [2018-11-28 11:38:37,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,308 INFO L82 PathProgramCache]: Analyzing trace with hash -1215154612, now seen corresponding path program 1 times [2018-11-28 11:38:37,308 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,308 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,309 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,369 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,369 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,370 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:37,370 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,370 INFO L82 PathProgramCache]: Analyzing trace with hash 124911521, now seen corresponding path program 1 times [2018-11-28 11:38:37,370 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,370 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,407 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,407 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,408 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:37,408 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:37,408 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:37,408 INFO L87 Difference]: Start difference. First operand 746 states and 1124 transitions. cyclomatic complexity: 379 Second operand 3 states. [2018-11-28 11:38:37,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:37,424 INFO L93 Difference]: Finished difference Result 746 states and 1123 transitions. [2018-11-28 11:38:37,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:37,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1123 transitions. [2018-11-28 11:38:37,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1123 transitions. [2018-11-28 11:38:37,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:37,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:37,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1123 transitions. [2018-11-28 11:38:37,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:37,430 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1123 transitions. [2018-11-28 11:38:37,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1123 transitions. [2018-11-28 11:38:37,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:37,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:37,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1123 transitions. [2018-11-28 11:38:37,438 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1123 transitions. [2018-11-28 11:38:37,438 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1123 transitions. [2018-11-28 11:38:37,438 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-28 11:38:37,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1123 transitions. [2018-11-28 11:38:37,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:37,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:37,441 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,441 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,442 INFO L794 eck$LassoCheckResult]: Stem: 6619#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6513#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6514#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6601#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 6271#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6272#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6120#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6121#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6455#L531-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6456#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6314#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6315#L546-1 assume !(0 == ~M_E~0); 6726#L744-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6587#L749-1 assume !(0 == ~T2_E~0); 6245#L754-1 assume !(0 == ~T3_E~0); 6246#L759-1 assume !(0 == ~T4_E~0); 6032#L764-1 assume !(0 == ~T5_E~0); 6033#L769-1 assume !(0 == ~T6_E~0); 6170#L774-1 assume !(0 == ~T7_E~0); 6171#L779-1 assume !(0 == ~E_1~0); 6478#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 6479#L789-1 assume !(0 == ~E_3~0); 6320#L794-1 assume !(0 == ~E_4~0); 6321#L799-1 assume !(0 == ~E_5~0); 6583#L804-1 assume !(0 == ~E_6~0); 6239#L809-1 assume !(0 == ~E_7~0); 6240#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6564#L351 assume 1 == ~m_pc~0; 6565#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6528#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6560#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6635#L920 assume !(0 != activate_threads_~tmp~1); 6731#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6705#L370 assume !(1 == ~t1_pc~0); 6706#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 6703#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6704#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6434#L928 assume !(0 != activate_threads_~tmp___0~0); 6162#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6140#L389 assume 1 == ~t2_pc~0; 6141#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6080#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6136#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6275#L936 assume !(0 != activate_threads_~tmp___1~0); 6592#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6394#L408 assume !(1 == ~t3_pc~0); 6282#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 6281#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6278#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6279#L944 assume !(0 != activate_threads_~tmp___2~0); 6739#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6736#L427 assume 1 == ~t4_pc~0; 6552#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6553#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6551#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6260#L952 assume !(0 != activate_threads_~tmp___3~0); 6261#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6205#L446 assume 1 == ~t5_pc~0; 6206#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6201#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6202#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6485#L960 assume !(0 != activate_threads_~tmp___4~0); 6470#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6457#L465 assume !(1 == ~t6_pc~0); 6126#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 6125#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6122#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6123#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6649#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6632#L484 assume 1 == ~t7_pc~0; 6423#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6424#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6421#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6422#L976 assume !(0 != activate_threads_~tmp___6~0); 6653#L976-2 assume !(1 == ~M_E~0); 6340#L827-1 assume !(1 == ~T1_E~0); 6341#L832-1 assume !(1 == ~T2_E~0); 6581#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6234#L842-1 assume !(1 == ~T4_E~0); 6235#L847-1 assume !(1 == ~T5_E~0); 6024#L852-1 assume !(1 == ~T6_E~0); 6025#L857-1 assume !(1 == ~T7_E~0); 6163#L862-1 assume !(1 == ~E_1~0); 6164#L867-1 assume !(1 == ~E_2~0); 6473#L872-1 assume !(1 == ~E_3~0); 6474#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6336#L882-1 assume !(1 == ~E_5~0); 6337#L887-1 assume !(1 == ~E_6~0); 6594#L892-1 assume !(1 == ~E_7~0); 6064#L1138-1 [2018-11-28 11:38:37,442 INFO L796 eck$LassoCheckResult]: Loop: 6064#L1138-1 assume !false; 6065#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 6173#L719 assume !false; 6174#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6718#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6159#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 6720#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6637#L616 assume !(0 != eval_~tmp~0); 6639#L734 start_simulation_~kernel_st~0 := 2; 6734#L504-1 start_simulation_~kernel_st~0 := 3; 6729#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6719#L744-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6591#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6255#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6256#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6008#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6009#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6152#L774-3 assume !(0 == ~T7_E~0); 6153#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6461#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6462#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6327#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6328#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6590#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6247#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6248#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6643#L351-24 assume 1 == ~m_pc~0; 6602#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6504#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6505#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6600#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6668#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6669#L370-24 assume 1 == ~t1_pc~0; 6746#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6698#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6699#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6057#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6058#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6015#L389-24 assume !(1 == ~t2_pc~0); 6016#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 6018#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6059#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6264#L936-24 assume !(0 != activate_threads_~tmp___1~0); 6349#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6330#L408-24 assume !(1 == ~t3_pc~0); 6307#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 6308#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6379#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6488#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6573#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6566#L427-24 assume 1 == ~t4_pc~0; 6492#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6494#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6550#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6194#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6195#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6730#L446-24 assume 1 == ~t5_pc~0; 6688#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6191#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6192#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6439#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6440#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6151#L465-24 assume 1 == ~t6_pc~0; 6107#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6108#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6104#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6105#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6599#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6588#L484-24 assume 1 == ~t7_pc~0; 6368#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6369#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6365#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6366#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 6743#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 6325#L827-3 assume !(1 == ~T1_E~0); 6326#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6586#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6243#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6244#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6030#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6031#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6168#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6169#L867-3 assume !(1 == ~E_2~0); 6475#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6476#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6342#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6343#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6582#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6236#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6237#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6161#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 6722#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6381#L1157 assume !(0 == start_simulation_~tmp~3); 6347#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6348#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6117#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 6724#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 6605#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6606#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 6701#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 6441#L1170 assume !(0 != start_simulation_~tmp___0~1); 6064#L1138-1 [2018-11-28 11:38:37,442 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,442 INFO L82 PathProgramCache]: Analyzing trace with hash 1513054734, now seen corresponding path program 1 times [2018-11-28 11:38:37,443 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,443 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,443 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,470 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,470 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,470 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:37,470 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,470 INFO L82 PathProgramCache]: Analyzing trace with hash -2009647713, now seen corresponding path program 1 times [2018-11-28 11:38:37,470 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,471 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,471 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,517 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,517 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,517 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:37,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:37,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:37,517 INFO L87 Difference]: Start difference. First operand 746 states and 1123 transitions. cyclomatic complexity: 378 Second operand 3 states. [2018-11-28 11:38:37,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:37,529 INFO L93 Difference]: Finished difference Result 746 states and 1122 transitions. [2018-11-28 11:38:37,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:37,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1122 transitions. [2018-11-28 11:38:37,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1122 transitions. [2018-11-28 11:38:37,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:37,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:37,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1122 transitions. [2018-11-28 11:38:37,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:37,539 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1122 transitions. [2018-11-28 11:38:37,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1122 transitions. [2018-11-28 11:38:37,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:37,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:37,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1122 transitions. [2018-11-28 11:38:37,550 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1122 transitions. [2018-11-28 11:38:37,550 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1122 transitions. [2018-11-28 11:38:37,550 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-28 11:38:37,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1122 transitions. [2018-11-28 11:38:37,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:37,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:37,555 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,555 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,555 INFO L794 eck$LassoCheckResult]: Stem: 8119#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8013#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8014#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8101#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 7770#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7771#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7619#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7620#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7954#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7955#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7813#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7814#L546-1 assume !(0 == ~M_E~0); 8225#L744-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8087#L749-1 assume !(0 == ~T2_E~0); 7744#L754-1 assume !(0 == ~T3_E~0); 7745#L759-1 assume !(0 == ~T4_E~0); 7531#L764-1 assume !(0 == ~T5_E~0); 7532#L769-1 assume !(0 == ~T6_E~0); 7669#L774-1 assume !(0 == ~T7_E~0); 7670#L779-1 assume !(0 == ~E_1~0); 7977#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7978#L789-1 assume !(0 == ~E_3~0); 7819#L794-1 assume !(0 == ~E_4~0); 7820#L799-1 assume !(0 == ~E_5~0); 8082#L804-1 assume !(0 == ~E_6~0); 7738#L809-1 assume !(0 == ~E_7~0); 7739#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8063#L351 assume 1 == ~m_pc~0; 8064#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8027#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8059#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8134#L920 assume !(0 != activate_threads_~tmp~1); 8230#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8204#L370 assume !(1 == ~t1_pc~0); 8205#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 8202#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8203#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7933#L928 assume !(0 != activate_threads_~tmp___0~0); 7661#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7639#L389 assume 1 == ~t2_pc~0; 7640#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7579#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7638#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7774#L936 assume !(0 != activate_threads_~tmp___1~0); 8091#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7893#L408 assume !(1 == ~t3_pc~0); 7781#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 7780#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7777#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7778#L944 assume !(0 != activate_threads_~tmp___2~0); 8238#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8235#L427 assume 1 == ~t4_pc~0; 8051#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8052#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8050#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7759#L952 assume !(0 != activate_threads_~tmp___3~0); 7760#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7704#L446 assume 1 == ~t5_pc~0; 7705#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7702#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7703#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7984#L960 assume !(0 != activate_threads_~tmp___4~0); 7969#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7958#L465 assume !(1 == ~t6_pc~0); 7625#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 7624#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7621#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7622#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8148#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8131#L484 assume 1 == ~t7_pc~0; 7922#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7923#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7920#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7921#L976 assume !(0 != activate_threads_~tmp___6~0); 8152#L976-2 assume !(1 == ~M_E~0); 7839#L827-1 assume !(1 == ~T1_E~0); 7840#L832-1 assume !(1 == ~T2_E~0); 8080#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7733#L842-1 assume !(1 == ~T4_E~0); 7734#L847-1 assume !(1 == ~T5_E~0); 7523#L852-1 assume !(1 == ~T6_E~0); 7524#L857-1 assume !(1 == ~T7_E~0); 7662#L862-1 assume !(1 == ~E_1~0); 7663#L867-1 assume !(1 == ~E_2~0); 7972#L872-1 assume !(1 == ~E_3~0); 7973#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7835#L882-1 assume !(1 == ~E_5~0); 7836#L887-1 assume !(1 == ~E_6~0); 8093#L892-1 assume !(1 == ~E_7~0); 7563#L1138-1 [2018-11-28 11:38:37,556 INFO L796 eck$LassoCheckResult]: Loop: 7563#L1138-1 assume !false; 7564#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 7672#L719 assume !false; 7673#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8217#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 7658#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8219#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 8136#L616 assume !(0 != eval_~tmp~0); 8138#L734 start_simulation_~kernel_st~0 := 2; 8233#L504-1 start_simulation_~kernel_st~0 := 3; 8229#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8218#L744-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8090#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7755#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7756#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7507#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7508#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7651#L774-3 assume !(0 == ~T7_E~0); 7652#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7960#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7961#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7826#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7827#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8089#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7746#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7747#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8142#L351-24 assume 1 == ~m_pc~0; 8102#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8003#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8004#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8099#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8167#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8168#L370-24 assume 1 == ~t1_pc~0; 8245#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8197#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8198#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7557#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7558#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7514#L389-24 assume !(1 == ~t2_pc~0); 7515#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 7517#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7556#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7763#L936-24 assume !(0 != activate_threads_~tmp___1~0); 7848#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7829#L408-24 assume 1 == ~t3_pc~0; 7830#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7807#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7878#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7987#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8072#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8065#L427-24 assume 1 == ~t4_pc~0; 7989#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7991#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8049#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7693#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7694#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8228#L446-24 assume 1 == ~t5_pc~0; 8185#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7690#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7691#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7938#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7939#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7650#L465-24 assume 1 == ~t6_pc~0; 7605#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7606#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7603#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7604#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8098#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8086#L484-24 assume 1 == ~t7_pc~0; 7866#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7867#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7864#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7865#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8242#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 7824#L827-3 assume !(1 == ~T1_E~0); 7825#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8084#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7742#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7743#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7528#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7529#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7667#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7668#L867-3 assume !(1 == ~E_2~0); 7974#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7975#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7841#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7842#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8081#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7735#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 7736#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 7660#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8221#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 7879#L1157 assume !(0 == start_simulation_~tmp~3); 7846#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 7847#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 7616#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8223#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 8104#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8105#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 8199#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7940#L1170 assume !(0 != start_simulation_~tmp___0~1); 7563#L1138-1 [2018-11-28 11:38:37,556 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,556 INFO L82 PathProgramCache]: Analyzing trace with hash -1724074484, now seen corresponding path program 1 times [2018-11-28 11:38:37,556 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,556 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,557 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,598 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,598 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,598 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:37,598 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,599 INFO L82 PathProgramCache]: Analyzing trace with hash 2045052254, now seen corresponding path program 2 times [2018-11-28 11:38:37,599 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,599 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,633 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,633 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,634 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:37,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:37,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:37,634 INFO L87 Difference]: Start difference. First operand 746 states and 1122 transitions. cyclomatic complexity: 377 Second operand 3 states. [2018-11-28 11:38:37,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:37,646 INFO L93 Difference]: Finished difference Result 746 states and 1121 transitions. [2018-11-28 11:38:37,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:37,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1121 transitions. [2018-11-28 11:38:37,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,654 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1121 transitions. [2018-11-28 11:38:37,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:37,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:37,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1121 transitions. [2018-11-28 11:38:37,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:37,656 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1121 transitions. [2018-11-28 11:38:37,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1121 transitions. [2018-11-28 11:38:37,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:37,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:37,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1121 transitions. [2018-11-28 11:38:37,666 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1121 transitions. [2018-11-28 11:38:37,666 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1121 transitions. [2018-11-28 11:38:37,666 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-28 11:38:37,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1121 transitions. [2018-11-28 11:38:37,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:37,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:37,671 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,671 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,671 INFO L794 eck$LassoCheckResult]: Stem: 9617#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 9511#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9512#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9599#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 9269#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9270#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9118#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9119#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9453#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9454#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9312#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9313#L546-1 assume !(0 == ~M_E~0); 9724#L744-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9585#L749-1 assume !(0 == ~T2_E~0); 9243#L754-1 assume !(0 == ~T3_E~0); 9244#L759-1 assume !(0 == ~T4_E~0); 9030#L764-1 assume !(0 == ~T5_E~0); 9031#L769-1 assume !(0 == ~T6_E~0); 9168#L774-1 assume !(0 == ~T7_E~0); 9169#L779-1 assume !(0 == ~E_1~0); 9476#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9477#L789-1 assume !(0 == ~E_3~0); 9318#L794-1 assume !(0 == ~E_4~0); 9319#L799-1 assume !(0 == ~E_5~0); 9581#L804-1 assume !(0 == ~E_6~0); 9237#L809-1 assume !(0 == ~E_7~0); 9238#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9562#L351 assume 1 == ~m_pc~0; 9563#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9526#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9558#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9633#L920 assume !(0 != activate_threads_~tmp~1); 9729#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9703#L370 assume !(1 == ~t1_pc~0); 9704#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 9701#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9702#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9432#L928 assume !(0 != activate_threads_~tmp___0~0); 9160#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9138#L389 assume 1 == ~t2_pc~0; 9139#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9078#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9134#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9273#L936 assume !(0 != activate_threads_~tmp___1~0); 9590#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9392#L408 assume !(1 == ~t3_pc~0); 9280#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 9279#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9276#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9277#L944 assume !(0 != activate_threads_~tmp___2~0); 9737#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9734#L427 assume 1 == ~t4_pc~0; 9550#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9551#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9549#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9258#L952 assume !(0 != activate_threads_~tmp___3~0); 9259#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9203#L446 assume 1 == ~t5_pc~0; 9204#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9199#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9200#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9483#L960 assume !(0 != activate_threads_~tmp___4~0); 9468#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9455#L465 assume !(1 == ~t6_pc~0); 9124#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 9123#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9120#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9121#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9647#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9630#L484 assume 1 == ~t7_pc~0; 9421#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9422#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9419#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9420#L976 assume !(0 != activate_threads_~tmp___6~0); 9651#L976-2 assume !(1 == ~M_E~0); 9338#L827-1 assume !(1 == ~T1_E~0); 9339#L832-1 assume !(1 == ~T2_E~0); 9579#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9232#L842-1 assume !(1 == ~T4_E~0); 9233#L847-1 assume !(1 == ~T5_E~0); 9022#L852-1 assume !(1 == ~T6_E~0); 9023#L857-1 assume !(1 == ~T7_E~0); 9161#L862-1 assume !(1 == ~E_1~0); 9162#L867-1 assume !(1 == ~E_2~0); 9471#L872-1 assume !(1 == ~E_3~0); 9472#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9334#L882-1 assume !(1 == ~E_5~0); 9335#L887-1 assume !(1 == ~E_6~0); 9592#L892-1 assume !(1 == ~E_7~0); 9062#L1138-1 [2018-11-28 11:38:37,671 INFO L796 eck$LassoCheckResult]: Loop: 9062#L1138-1 assume !false; 9063#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 9171#L719 assume !false; 9172#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9716#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9157#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9718#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9635#L616 assume !(0 != eval_~tmp~0); 9637#L734 start_simulation_~kernel_st~0 := 2; 9732#L504-1 start_simulation_~kernel_st~0 := 3; 9727#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9717#L744-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9589#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9253#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9254#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9006#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9007#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9150#L774-3 assume !(0 == ~T7_E~0); 9151#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9459#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9460#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9325#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9326#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9588#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9245#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9246#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9641#L351-24 assume 1 == ~m_pc~0; 9600#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9502#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9503#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9598#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9666#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9667#L370-24 assume 1 == ~t1_pc~0; 9744#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9696#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9697#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9055#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9056#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9013#L389-24 assume !(1 == ~t2_pc~0); 9014#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 9016#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9057#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9262#L936-24 assume !(0 != activate_threads_~tmp___1~0); 9347#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9328#L408-24 assume 1 == ~t3_pc~0; 9329#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9306#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9377#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9486#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9571#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9564#L427-24 assume 1 == ~t4_pc~0; 9490#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9492#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9548#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9192#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9193#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9728#L446-24 assume 1 == ~t5_pc~0; 9686#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9189#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9190#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9437#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9438#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9149#L465-24 assume 1 == ~t6_pc~0; 9105#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9106#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9102#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9103#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9597#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9586#L484-24 assume 1 == ~t7_pc~0; 9366#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9367#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9363#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9364#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9741#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 9323#L827-3 assume !(1 == ~T1_E~0); 9324#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9584#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9241#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9242#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9028#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9029#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9166#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9167#L867-3 assume !(1 == ~E_2~0); 9473#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9474#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9340#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9341#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9580#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9234#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9235#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9159#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9720#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 9379#L1157 assume !(0 == start_simulation_~tmp~3); 9345#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9346#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9115#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9722#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 9603#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9604#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 9699#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 9439#L1170 assume !(0 != start_simulation_~tmp___0~1); 9062#L1138-1 [2018-11-28 11:38:37,672 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,672 INFO L82 PathProgramCache]: Analyzing trace with hash -581572018, now seen corresponding path program 1 times [2018-11-28 11:38:37,672 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,672 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,673 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,673 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:37,673 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,699 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,699 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,699 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:37,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,699 INFO L82 PathProgramCache]: Analyzing trace with hash 2045052254, now seen corresponding path program 3 times [2018-11-28 11:38:37,700 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,700 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,700 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,752 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,752 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:37,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:37,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:37,753 INFO L87 Difference]: Start difference. First operand 746 states and 1121 transitions. cyclomatic complexity: 376 Second operand 3 states. [2018-11-28 11:38:37,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:37,765 INFO L93 Difference]: Finished difference Result 746 states and 1120 transitions. [2018-11-28 11:38:37,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:37,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1120 transitions. [2018-11-28 11:38:37,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1120 transitions. [2018-11-28 11:38:37,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:37,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:37,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1120 transitions. [2018-11-28 11:38:37,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:37,775 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1120 transitions. [2018-11-28 11:38:37,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1120 transitions. [2018-11-28 11:38:37,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:37,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:37,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1120 transitions. [2018-11-28 11:38:37,786 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1120 transitions. [2018-11-28 11:38:37,786 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1120 transitions. [2018-11-28 11:38:37,786 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-28 11:38:37,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1120 transitions. [2018-11-28 11:38:37,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:37,789 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:37,790 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,790 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,790 INFO L794 eck$LassoCheckResult]: Stem: 11117#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11010#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11011#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11099#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 10768#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10769#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10617#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10618#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10952#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10953#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10811#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 10812#L546-1 assume !(0 == ~M_E~0); 11223#L744-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11085#L749-1 assume !(0 == ~T2_E~0); 10742#L754-1 assume !(0 == ~T3_E~0); 10743#L759-1 assume !(0 == ~T4_E~0); 10529#L764-1 assume !(0 == ~T5_E~0); 10530#L769-1 assume !(0 == ~T6_E~0); 10667#L774-1 assume !(0 == ~T7_E~0); 10668#L779-1 assume !(0 == ~E_1~0); 10975#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10976#L789-1 assume !(0 == ~E_3~0); 10817#L794-1 assume !(0 == ~E_4~0); 10818#L799-1 assume !(0 == ~E_5~0); 11080#L804-1 assume !(0 == ~E_6~0); 10736#L809-1 assume !(0 == ~E_7~0); 10737#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11061#L351 assume 1 == ~m_pc~0; 11062#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11025#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11057#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11132#L920 assume !(0 != activate_threads_~tmp~1); 11228#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11202#L370 assume !(1 == ~t1_pc~0); 11203#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 11200#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11201#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10931#L928 assume !(0 != activate_threads_~tmp___0~0); 10659#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10637#L389 assume 1 == ~t2_pc~0; 10638#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10577#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10636#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10772#L936 assume !(0 != activate_threads_~tmp___1~0); 11089#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10891#L408 assume !(1 == ~t3_pc~0); 10779#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 10778#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10775#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10776#L944 assume !(0 != activate_threads_~tmp___2~0); 11236#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11233#L427 assume 1 == ~t4_pc~0; 11049#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11050#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11048#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10757#L952 assume !(0 != activate_threads_~tmp___3~0); 10758#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10702#L446 assume 1 == ~t5_pc~0; 10703#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10698#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10699#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10982#L960 assume !(0 != activate_threads_~tmp___4~0); 10967#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10956#L465 assume !(1 == ~t6_pc~0); 10623#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 10622#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10619#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10620#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11146#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11129#L484 assume 1 == ~t7_pc~0; 10920#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 10921#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10918#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10919#L976 assume !(0 != activate_threads_~tmp___6~0); 11150#L976-2 assume !(1 == ~M_E~0); 10837#L827-1 assume !(1 == ~T1_E~0); 10838#L832-1 assume !(1 == ~T2_E~0); 11078#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10731#L842-1 assume !(1 == ~T4_E~0); 10732#L847-1 assume !(1 == ~T5_E~0); 10521#L852-1 assume !(1 == ~T6_E~0); 10522#L857-1 assume !(1 == ~T7_E~0); 10660#L862-1 assume !(1 == ~E_1~0); 10661#L867-1 assume !(1 == ~E_2~0); 10970#L872-1 assume !(1 == ~E_3~0); 10971#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10833#L882-1 assume !(1 == ~E_5~0); 10834#L887-1 assume !(1 == ~E_6~0); 11091#L892-1 assume !(1 == ~E_7~0); 10561#L1138-1 [2018-11-28 11:38:37,791 INFO L796 eck$LassoCheckResult]: Loop: 10561#L1138-1 assume !false; 10562#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 10670#L719 assume !false; 10671#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11215#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10656#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11217#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 11134#L616 assume !(0 != eval_~tmp~0); 11136#L734 start_simulation_~kernel_st~0 := 2; 11231#L504-1 start_simulation_~kernel_st~0 := 3; 11227#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11216#L744-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11088#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10752#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10753#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10505#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10506#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10649#L774-3 assume !(0 == ~T7_E~0); 10650#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10958#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10959#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10824#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10825#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11087#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10744#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10745#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11140#L351-24 assume 1 == ~m_pc~0; 11100#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11001#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11002#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11097#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11165#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11166#L370-24 assume 1 == ~t1_pc~0; 11243#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11195#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11196#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10554#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10555#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10512#L389-24 assume !(1 == ~t2_pc~0); 10513#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 10515#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10556#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10761#L936-24 assume !(0 != activate_threads_~tmp___1~0); 10846#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10827#L408-24 assume !(1 == ~t3_pc~0); 10804#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 10805#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10876#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10985#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11070#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11063#L427-24 assume 1 == ~t4_pc~0; 10987#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10989#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11047#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10691#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10692#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11226#L446-24 assume !(1 == ~t5_pc~0); 11184#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 10687#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10688#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10936#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10937#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10648#L465-24 assume 1 == ~t6_pc~0; 10603#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10604#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10601#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10602#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11096#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11084#L484-24 assume 1 == ~t7_pc~0; 10864#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 10865#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10862#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10863#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11240#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 10822#L827-3 assume !(1 == ~T1_E~0); 10823#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11082#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10740#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10741#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10526#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10527#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10665#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10666#L867-3 assume !(1 == ~E_2~0); 10972#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10973#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10839#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10840#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11079#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10733#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10734#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10658#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11219#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10877#L1157 assume !(0 == start_simulation_~tmp~3); 10844#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10845#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10614#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11221#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 11102#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11103#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 11197#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 10938#L1170 assume !(0 != start_simulation_~tmp___0~1); 10561#L1138-1 [2018-11-28 11:38:37,791 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,791 INFO L82 PathProgramCache]: Analyzing trace with hash -821811764, now seen corresponding path program 1 times [2018-11-28 11:38:37,791 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,791 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,792 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:37,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,814 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:37,815 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:37,815 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,815 INFO L82 PathProgramCache]: Analyzing trace with hash 1411841888, now seen corresponding path program 1 times [2018-11-28 11:38:37,815 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,815 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,816 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,860 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,860 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,860 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:37,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:37,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:37,860 INFO L87 Difference]: Start difference. First operand 746 states and 1120 transitions. cyclomatic complexity: 375 Second operand 3 states. [2018-11-28 11:38:37,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:37,883 INFO L93 Difference]: Finished difference Result 746 states and 1115 transitions. [2018-11-28 11:38:37,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:37,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1115 transitions. [2018-11-28 11:38:37,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1115 transitions. [2018-11-28 11:38:37,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:37,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:37,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1115 transitions. [2018-11-28 11:38:37,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:37,892 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1115 transitions. [2018-11-28 11:38:37,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1115 transitions. [2018-11-28 11:38:37,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:37,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:37,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1115 transitions. [2018-11-28 11:38:37,902 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1115 transitions. [2018-11-28 11:38:37,902 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1115 transitions. [2018-11-28 11:38:37,902 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-28 11:38:37,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1115 transitions. [2018-11-28 11:38:37,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:37,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:37,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:37,906 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,906 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:37,906 INFO L794 eck$LassoCheckResult]: Stem: 12616#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 12510#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12511#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12600#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 12269#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12270#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12116#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12117#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12451#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12452#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12310#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12311#L546-1 assume !(0 == ~M_E~0); 12722#L744-1 assume !(0 == ~T1_E~0); 12583#L749-1 assume !(0 == ~T2_E~0); 12241#L754-1 assume !(0 == ~T3_E~0); 12242#L759-1 assume !(0 == ~T4_E~0); 12028#L764-1 assume !(0 == ~T5_E~0); 12029#L769-1 assume !(0 == ~T6_E~0); 12166#L774-1 assume !(0 == ~T7_E~0); 12167#L779-1 assume !(0 == ~E_1~0); 12474#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12475#L789-1 assume !(0 == ~E_3~0); 12316#L794-1 assume !(0 == ~E_4~0); 12317#L799-1 assume !(0 == ~E_5~0); 12579#L804-1 assume !(0 == ~E_6~0); 12235#L809-1 assume !(0 == ~E_7~0); 12236#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12560#L351 assume 1 == ~m_pc~0; 12561#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12524#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12556#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12631#L920 assume !(0 != activate_threads_~tmp~1); 12727#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12701#L370 assume !(1 == ~t1_pc~0); 12702#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 12699#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12700#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12430#L928 assume !(0 != activate_threads_~tmp___0~0); 12158#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12136#L389 assume 1 == ~t2_pc~0; 12137#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12076#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12132#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12271#L936 assume !(0 != activate_threads_~tmp___1~0); 12588#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12390#L408 assume !(1 == ~t3_pc~0); 12278#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 12277#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12274#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12275#L944 assume !(0 != activate_threads_~tmp___2~0); 12735#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12732#L427 assume 1 == ~t4_pc~0; 12548#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12549#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12547#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12256#L952 assume !(0 != activate_threads_~tmp___3~0); 12257#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12201#L446 assume 1 == ~t5_pc~0; 12202#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12197#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12198#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12481#L960 assume !(0 != activate_threads_~tmp___4~0); 12466#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12453#L465 assume !(1 == ~t6_pc~0); 12122#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 12121#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12118#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12119#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12645#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12628#L484 assume 1 == ~t7_pc~0; 12419#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12420#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12417#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12418#L976 assume !(0 != activate_threads_~tmp___6~0); 12649#L976-2 assume !(1 == ~M_E~0); 12336#L827-1 assume !(1 == ~T1_E~0); 12337#L832-1 assume !(1 == ~T2_E~0); 12577#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12230#L842-1 assume !(1 == ~T4_E~0); 12231#L847-1 assume !(1 == ~T5_E~0); 12020#L852-1 assume !(1 == ~T6_E~0); 12021#L857-1 assume !(1 == ~T7_E~0); 12159#L862-1 assume !(1 == ~E_1~0); 12160#L867-1 assume !(1 == ~E_2~0); 12469#L872-1 assume !(1 == ~E_3~0); 12470#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12332#L882-1 assume !(1 == ~E_5~0); 12333#L887-1 assume !(1 == ~E_6~0); 12590#L892-1 assume !(1 == ~E_7~0); 12060#L1138-1 [2018-11-28 11:38:37,906 INFO L796 eck$LassoCheckResult]: Loop: 12060#L1138-1 assume !false; 12061#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 12169#L719 assume !false; 12170#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12714#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 12155#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12716#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 12633#L616 assume !(0 != eval_~tmp~0); 12635#L734 start_simulation_~kernel_st~0 := 2; 12730#L504-1 start_simulation_~kernel_st~0 := 3; 12725#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12715#L744-4 assume !(0 == ~T1_E~0); 12587#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12251#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12252#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12004#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12005#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12148#L774-3 assume !(0 == ~T7_E~0); 12149#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12457#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12458#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12323#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12324#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12586#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12243#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12244#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12639#L351-24 assume 1 == ~m_pc~0; 12597#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12500#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12501#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12596#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12664#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12665#L370-24 assume 1 == ~t1_pc~0; 12742#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12694#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12695#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12053#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12054#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12011#L389-24 assume !(1 == ~t2_pc~0); 12012#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 12014#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12055#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12260#L936-24 assume !(0 != activate_threads_~tmp___1~0); 12345#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12326#L408-24 assume 1 == ~t3_pc~0; 12327#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12304#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12375#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12484#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12569#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12562#L427-24 assume 1 == ~t4_pc~0; 12488#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12490#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12546#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12190#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12191#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12726#L446-24 assume 1 == ~t5_pc~0; 12684#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12187#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12188#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12435#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12436#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12147#L465-24 assume 1 == ~t6_pc~0; 12103#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12104#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12100#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12101#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12595#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12584#L484-24 assume 1 == ~t7_pc~0; 12364#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12365#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12361#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12362#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12739#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 12321#L827-3 assume !(1 == ~T1_E~0); 12322#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12582#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12239#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12240#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12026#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12027#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12164#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12165#L867-3 assume !(1 == ~E_2~0); 12471#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12472#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12338#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12339#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12578#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12232#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12233#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 12157#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12718#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 12377#L1157 assume !(0 == start_simulation_~tmp~3); 12343#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12344#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 12113#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12720#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 12601#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12602#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 12697#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 12437#L1170 assume !(0 != start_simulation_~tmp___0~1); 12060#L1138-1 [2018-11-28 11:38:37,907 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,907 INFO L82 PathProgramCache]: Analyzing trace with hash -794746162, now seen corresponding path program 1 times [2018-11-28 11:38:37,907 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,907 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,938 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,939 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:37,939 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:37,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:37,939 INFO L82 PathProgramCache]: Analyzing trace with hash -372851812, now seen corresponding path program 1 times [2018-11-28 11:38:37,939 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:37,939 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:37,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,940 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:37,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:37,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:37,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:37,982 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:37,982 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:37,983 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:37,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:37,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:37,983 INFO L87 Difference]: Start difference. First operand 746 states and 1115 transitions. cyclomatic complexity: 370 Second operand 3 states. [2018-11-28 11:38:38,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:38,032 INFO L93 Difference]: Finished difference Result 746 states and 1101 transitions. [2018-11-28 11:38:38,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:38,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1101 transitions. [2018-11-28 11:38:38,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:38,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1101 transitions. [2018-11-28 11:38:38,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2018-11-28 11:38:38,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2018-11-28 11:38:38,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1101 transitions. [2018-11-28 11:38:38,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:38,044 INFO L705 BuchiCegarLoop]: Abstraction has 746 states and 1101 transitions. [2018-11-28 11:38:38,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1101 transitions. [2018-11-28 11:38:38,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2018-11-28 11:38:38,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 746 states. [2018-11-28 11:38:38,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1101 transitions. [2018-11-28 11:38:38,054 INFO L728 BuchiCegarLoop]: Abstraction has 746 states and 1101 transitions. [2018-11-28 11:38:38,054 INFO L608 BuchiCegarLoop]: Abstraction has 746 states and 1101 transitions. [2018-11-28 11:38:38,054 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-28 11:38:38,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1101 transitions. [2018-11-28 11:38:38,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 649 [2018-11-28 11:38:38,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:38,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:38,058 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:38,058 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:38,058 INFO L794 eck$LassoCheckResult]: Stem: 14115#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 14008#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14009#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14097#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 13766#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13767#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13615#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13616#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13950#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13951#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13809#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13810#L546-1 assume !(0 == ~M_E~0); 14221#L744-1 assume !(0 == ~T1_E~0); 14083#L749-1 assume !(0 == ~T2_E~0); 13740#L754-1 assume !(0 == ~T3_E~0); 13741#L759-1 assume !(0 == ~T4_E~0); 13527#L764-1 assume !(0 == ~T5_E~0); 13528#L769-1 assume !(0 == ~T6_E~0); 13665#L774-1 assume !(0 == ~T7_E~0); 13666#L779-1 assume !(0 == ~E_1~0); 13973#L784-1 assume !(0 == ~E_2~0); 13974#L789-1 assume !(0 == ~E_3~0); 13815#L794-1 assume !(0 == ~E_4~0); 13816#L799-1 assume !(0 == ~E_5~0); 14078#L804-1 assume !(0 == ~E_6~0); 13734#L809-1 assume !(0 == ~E_7~0); 13735#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14059#L351 assume 1 == ~m_pc~0; 14060#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 14023#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14055#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14130#L920 assume !(0 != activate_threads_~tmp~1); 14226#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14200#L370 assume !(1 == ~t1_pc~0); 14201#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 14198#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14199#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13929#L928 assume !(0 != activate_threads_~tmp___0~0); 13657#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13635#L389 assume !(1 == ~t2_pc~0); 13574#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 13575#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13631#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13770#L936 assume !(0 != activate_threads_~tmp___1~0); 14087#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13889#L408 assume !(1 == ~t3_pc~0); 13777#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 13776#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13773#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13774#L944 assume !(0 != activate_threads_~tmp___2~0); 14234#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14231#L427 assume 1 == ~t4_pc~0; 14047#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14048#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14046#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13755#L952 assume !(0 != activate_threads_~tmp___3~0); 13756#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13700#L446 assume 1 == ~t5_pc~0; 13701#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 13696#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13697#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13980#L960 assume !(0 != activate_threads_~tmp___4~0); 13965#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13952#L465 assume !(1 == ~t6_pc~0); 13621#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 13620#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13617#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13618#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14144#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14127#L484 assume 1 == ~t7_pc~0; 13918#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13919#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13916#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13917#L976 assume !(0 != activate_threads_~tmp___6~0); 14148#L976-2 assume !(1 == ~M_E~0); 13835#L827-1 assume !(1 == ~T1_E~0); 13836#L832-1 assume !(1 == ~T2_E~0); 14076#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13729#L842-1 assume !(1 == ~T4_E~0); 13730#L847-1 assume !(1 == ~T5_E~0); 13519#L852-1 assume !(1 == ~T6_E~0); 13520#L857-1 assume !(1 == ~T7_E~0); 13658#L862-1 assume !(1 == ~E_1~0); 13659#L867-1 assume !(1 == ~E_2~0); 13968#L872-1 assume !(1 == ~E_3~0); 13969#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13831#L882-1 assume !(1 == ~E_5~0); 13832#L887-1 assume !(1 == ~E_6~0); 14089#L892-1 assume !(1 == ~E_7~0); 13559#L1138-1 [2018-11-28 11:38:38,059 INFO L796 eck$LassoCheckResult]: Loop: 13559#L1138-1 assume !false; 13560#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 13668#L719 assume !false; 13669#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14213#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13654#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14215#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 14132#L616 assume !(0 != eval_~tmp~0); 14134#L734 start_simulation_~kernel_st~0 := 2; 14229#L504-1 start_simulation_~kernel_st~0 := 3; 14225#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14214#L744-4 assume !(0 == ~T1_E~0); 14086#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13750#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13751#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13503#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13504#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13647#L774-3 assume !(0 == ~T7_E~0); 13648#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13956#L784-3 assume !(0 == ~E_2~0); 13957#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13822#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13823#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14085#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13742#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13743#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14138#L351-24 assume 1 == ~m_pc~0; 14098#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 13999#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14000#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14095#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14163#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14164#L370-24 assume 1 == ~t1_pc~0; 14241#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14193#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14194#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13552#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13553#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13510#L389-24 assume !(1 == ~t2_pc~0); 13511#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 13513#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13554#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13759#L936-24 assume !(0 != activate_threads_~tmp___1~0); 13844#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13825#L408-24 assume 1 == ~t3_pc~0; 13826#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13803#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13874#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13983#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14068#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14061#L427-24 assume 1 == ~t4_pc~0; 13987#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13989#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14045#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13691#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13692#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14224#L446-24 assume 1 == ~t5_pc~0; 14181#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 13685#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13686#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13933#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13934#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13646#L465-24 assume 1 == ~t6_pc~0; 13601#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13602#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13599#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13600#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14094#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14082#L484-24 assume 1 == ~t7_pc~0; 13862#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13863#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13860#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13861#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14238#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 13820#L827-3 assume !(1 == ~T1_E~0); 13821#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14080#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13738#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13739#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13524#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13525#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13663#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13664#L867-3 assume !(1 == ~E_2~0); 13970#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13971#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13837#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13838#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14077#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13731#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13732#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13656#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14217#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 13875#L1157 assume !(0 == start_simulation_~tmp~3); 13842#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13843#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13612#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14219#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 14100#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14101#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 14195#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 13936#L1170 assume !(0 != start_simulation_~tmp___0~1); 13559#L1138-1 [2018-11-28 11:38:38,059 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:38,059 INFO L82 PathProgramCache]: Analyzing trace with hash 1277257903, now seen corresponding path program 1 times [2018-11-28 11:38:38,059 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:38,059 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:38,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,060 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:38,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:38,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:38,083 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:38,083 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:38,083 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:38,083 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:38,083 INFO L82 PathProgramCache]: Analyzing trace with hash 1193906138, now seen corresponding path program 1 times [2018-11-28 11:38:38,084 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:38,084 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:38,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,084 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:38,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:38,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:38,128 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:38,128 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:38,128 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:38,129 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:38,129 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:38,129 INFO L87 Difference]: Start difference. First operand 746 states and 1101 transitions. cyclomatic complexity: 356 Second operand 3 states. [2018-11-28 11:38:38,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:38,212 INFO L93 Difference]: Finished difference Result 1385 states and 2024 transitions. [2018-11-28 11:38:38,213 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:38,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1385 states and 2024 transitions. [2018-11-28 11:38:38,220 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1287 [2018-11-28 11:38:38,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1385 states to 1385 states and 2024 transitions. [2018-11-28 11:38:38,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1385 [2018-11-28 11:38:38,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1385 [2018-11-28 11:38:38,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1385 states and 2024 transitions. [2018-11-28 11:38:38,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:38,229 INFO L705 BuchiCegarLoop]: Abstraction has 1385 states and 2024 transitions. [2018-11-28 11:38:38,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1385 states and 2024 transitions. [2018-11-28 11:38:38,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1385 to 1329. [2018-11-28 11:38:38,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1329 states. [2018-11-28 11:38:38,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1329 states to 1329 states and 1947 transitions. [2018-11-28 11:38:38,249 INFO L728 BuchiCegarLoop]: Abstraction has 1329 states and 1947 transitions. [2018-11-28 11:38:38,249 INFO L608 BuchiCegarLoop]: Abstraction has 1329 states and 1947 transitions. [2018-11-28 11:38:38,249 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-28 11:38:38,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1329 states and 1947 transitions. [2018-11-28 11:38:38,254 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1231 [2018-11-28 11:38:38,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:38,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:38,256 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:38,256 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:38,256 INFO L794 eck$LassoCheckResult]: Stem: 16259#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16150#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16151#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16243#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 15908#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15909#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15755#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15756#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16091#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16092#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15949#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15950#L546-1 assume !(0 == ~M_E~0); 16370#L744-1 assume !(0 == ~T1_E~0); 16225#L749-1 assume !(0 == ~T2_E~0); 15880#L754-1 assume !(0 == ~T3_E~0); 15881#L759-1 assume !(0 == ~T4_E~0); 15667#L764-1 assume !(0 == ~T5_E~0); 15668#L769-1 assume !(0 == ~T6_E~0); 15805#L774-1 assume !(0 == ~T7_E~0); 15806#L779-1 assume !(0 == ~E_1~0); 16114#L784-1 assume !(0 == ~E_2~0); 16115#L789-1 assume !(0 == ~E_3~0); 15955#L794-1 assume !(0 == ~E_4~0); 15956#L799-1 assume !(0 == ~E_5~0); 16221#L804-1 assume !(0 == ~E_6~0); 15874#L809-1 assume !(0 == ~E_7~0); 15875#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16200#L351 assume !(1 == ~m_pc~0); 16163#L351-2 is_master_triggered_~__retres1~0 := 0; 16164#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16199#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16275#L920 assume !(0 != activate_threads_~tmp~1); 16376#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16349#L370 assume !(1 == ~t1_pc~0); 16350#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 16347#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16348#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16070#L928 assume !(0 != activate_threads_~tmp___0~0); 15797#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15775#L389 assume !(1 == ~t2_pc~0); 15714#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 15715#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15774#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15910#L936 assume !(0 != activate_threads_~tmp___1~0); 16229#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16030#L408 assume !(1 == ~t3_pc~0); 15917#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 15916#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15913#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15914#L944 assume !(0 != activate_threads_~tmp___2~0); 16384#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16381#L427 assume 1 == ~t4_pc~0; 16188#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16189#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16187#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15895#L952 assume !(0 != activate_threads_~tmp___3~0); 15896#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15840#L446 assume 1 == ~t5_pc~0; 15841#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15838#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15839#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16121#L960 assume !(0 != activate_threads_~tmp___4~0); 16106#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16095#L465 assume !(1 == ~t6_pc~0); 15761#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 15760#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15757#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15758#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16292#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16272#L484 assume 1 == ~t7_pc~0; 16059#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16060#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16057#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16058#L976 assume !(0 != activate_threads_~tmp___6~0); 16296#L976-2 assume !(1 == ~M_E~0); 15975#L827-1 assume !(1 == ~T1_E~0); 15976#L832-1 assume !(1 == ~T2_E~0); 16218#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15869#L842-1 assume !(1 == ~T4_E~0); 15870#L847-1 assume !(1 == ~T5_E~0); 15659#L852-1 assume !(1 == ~T6_E~0); 15660#L857-1 assume !(1 == ~T7_E~0); 15798#L862-1 assume !(1 == ~E_1~0); 15799#L867-1 assume !(1 == ~E_2~0); 16109#L872-1 assume !(1 == ~E_3~0); 16110#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15971#L882-1 assume !(1 == ~E_5~0); 15972#L887-1 assume !(1 == ~E_6~0); 16231#L892-1 assume !(1 == ~E_7~0); 16232#L1138-1 [2018-11-28 11:38:38,256 INFO L796 eck$LassoCheckResult]: Loop: 16232#L1138-1 assume !false; 16419#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 16418#L719 assume !false; 16417#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16416#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16408#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 16407#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 16405#L616 assume !(0 != eval_~tmp~0); 16406#L734 start_simulation_~kernel_st~0 := 2; 16924#L504-1 start_simulation_~kernel_st~0 := 3; 16923#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16922#L744-4 assume !(0 == ~T1_E~0); 16921#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16920#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16919#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16918#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16917#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16916#L774-3 assume !(0 == ~T7_E~0); 16915#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16914#L784-3 assume !(0 == ~E_2~0); 16913#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16912#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16886#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16227#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15882#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15883#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16284#L351-24 assume !(1 == ~m_pc~0); 16285#L351-26 is_master_triggered_~__retres1~0 := 0; 16140#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16141#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16238#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16311#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16312#L370-24 assume 1 == ~t1_pc~0; 16391#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16342#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16343#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15692#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15693#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15650#L389-24 assume !(1 == ~t2_pc~0); 15651#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 15653#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15694#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15899#L936-24 assume !(0 != activate_threads_~tmp___1~0); 15984#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15965#L408-24 assume !(1 == ~t3_pc~0); 15942#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 15943#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16014#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16124#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16209#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16201#L427-24 assume 1 == ~t4_pc~0; 16128#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16130#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16186#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15829#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15830#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16375#L446-24 assume 1 == ~t5_pc~0; 16332#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15826#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15827#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16329#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16910#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16909#L465-24 assume !(1 == ~t6_pc~0); 16907#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 16906#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16905#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16904#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16903#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16902#L484-24 assume 1 == ~t7_pc~0; 16900#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16899#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16882#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16881#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 16880#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 16879#L827-3 assume !(1 == ~T1_E~0); 16878#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16877#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16875#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16873#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16871#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16869#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16868#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16867#L867-3 assume !(1 == ~E_2~0); 16866#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16865#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16825#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16810#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16778#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16755#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16703#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16697#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 16695#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 16693#L1157 assume !(0 == start_simulation_~tmp~3); 16691#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16686#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16677#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 16675#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 16673#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16671#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 16669#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 16655#L1170 assume !(0 != start_simulation_~tmp___0~1); 16232#L1138-1 [2018-11-28 11:38:38,257 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:38,257 INFO L82 PathProgramCache]: Analyzing trace with hash -1197983474, now seen corresponding path program 1 times [2018-11-28 11:38:38,257 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:38,257 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:38,258 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,258 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:38,258 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:38,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:38,289 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:38,290 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:38,290 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:38,291 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:38,291 INFO L82 PathProgramCache]: Analyzing trace with hash 618344605, now seen corresponding path program 1 times [2018-11-28 11:38:38,291 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:38,291 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:38,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,292 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:38,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:38,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:38,344 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:38,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:38,344 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:38,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:38,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:38,345 INFO L87 Difference]: Start difference. First operand 1329 states and 1947 transitions. cyclomatic complexity: 620 Second operand 3 states. [2018-11-28 11:38:38,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:38,431 INFO L93 Difference]: Finished difference Result 2433 states and 3543 transitions. [2018-11-28 11:38:38,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:38,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2433 states and 3543 transitions. [2018-11-28 11:38:38,445 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2330 [2018-11-28 11:38:38,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2433 states to 2433 states and 3543 transitions. [2018-11-28 11:38:38,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2433 [2018-11-28 11:38:38,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2433 [2018-11-28 11:38:38,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2433 states and 3543 transitions. [2018-11-28 11:38:38,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:38,463 INFO L705 BuchiCegarLoop]: Abstraction has 2433 states and 3543 transitions. [2018-11-28 11:38:38,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2433 states and 3543 transitions. [2018-11-28 11:38:38,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2433 to 2429. [2018-11-28 11:38:38,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2429 states. [2018-11-28 11:38:38,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2429 states to 2429 states and 3539 transitions. [2018-11-28 11:38:38,505 INFO L728 BuchiCegarLoop]: Abstraction has 2429 states and 3539 transitions. [2018-11-28 11:38:38,505 INFO L608 BuchiCegarLoop]: Abstraction has 2429 states and 3539 transitions. [2018-11-28 11:38:38,505 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-28 11:38:38,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2429 states and 3539 transitions. [2018-11-28 11:38:38,513 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2326 [2018-11-28 11:38:38,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:38,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:38,515 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:38,515 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:38,515 INFO L794 eck$LassoCheckResult]: Stem: 20049#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 19924#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19925#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20026#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 19679#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19680#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19526#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19527#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19867#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19868#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19723#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19724#L546-1 assume !(0 == ~M_E~0); 20177#L744-1 assume !(0 == ~T1_E~0); 20011#L749-1 assume !(0 == ~T2_E~0); 19651#L754-1 assume !(0 == ~T3_E~0); 19652#L759-1 assume !(0 == ~T4_E~0); 19438#L764-1 assume !(0 == ~T5_E~0); 19439#L769-1 assume !(0 == ~T6_E~0); 19576#L774-1 assume !(0 == ~T7_E~0); 19577#L779-1 assume !(0 == ~E_1~0); 19891#L784-1 assume !(0 == ~E_2~0); 19892#L789-1 assume !(0 == ~E_3~0); 19729#L794-1 assume !(0 == ~E_4~0); 19730#L799-1 assume !(0 == ~E_5~0); 20006#L804-1 assume !(0 == ~E_6~0); 19645#L809-1 assume !(0 == ~E_7~0); 19646#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19973#L351 assume !(1 == ~m_pc~0); 19938#L351-2 is_master_triggered_~__retres1~0 := 0; 19939#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19969#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20071#L920 assume !(0 != activate_threads_~tmp~1); 20182#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20154#L370 assume !(1 == ~t1_pc~0); 20155#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 20152#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20153#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19845#L928 assume !(0 != activate_threads_~tmp___0~0); 19568#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19546#L389 assume !(1 == ~t2_pc~0); 19485#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 19486#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19542#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 19684#L936 assume !(0 != activate_threads_~tmp___1~0); 20016#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19805#L408 assume !(1 == ~t3_pc~0); 19691#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 19690#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19687#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 19688#L944 assume !(0 != activate_threads_~tmp___2~0); 20194#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20188#L427 assume !(1 == ~t4_pc~0); 19997#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 19998#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19963#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 19667#L952 assume !(0 != activate_threads_~tmp___3~0); 19668#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19611#L446 assume 1 == ~t5_pc~0; 19612#L447 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19607#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19608#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19898#L960 assume !(0 != activate_threads_~tmp___4~0); 19883#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19869#L465 assume !(1 == ~t6_pc~0); 19532#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 19531#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19528#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19529#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 20095#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20067#L484 assume 1 == ~t7_pc~0; 19834#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 19835#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19832#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 19833#L976 assume !(0 != activate_threads_~tmp___6~0); 20100#L976-2 assume !(1 == ~M_E~0); 19749#L827-1 assume !(1 == ~T1_E~0); 19750#L832-1 assume !(1 == ~T2_E~0); 20004#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19640#L842-1 assume !(1 == ~T4_E~0); 19641#L847-1 assume !(1 == ~T5_E~0); 19430#L852-1 assume !(1 == ~T6_E~0); 19431#L857-1 assume !(1 == ~T7_E~0); 19569#L862-1 assume !(1 == ~E_1~0); 19570#L867-1 assume !(1 == ~E_2~0); 19886#L872-1 assume !(1 == ~E_3~0); 19887#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19745#L882-1 assume !(1 == ~E_5~0); 19746#L887-1 assume !(1 == ~E_6~0); 20018#L892-1 assume !(1 == ~E_7~0); 19469#L1138-1 [2018-11-28 11:38:38,516 INFO L796 eck$LassoCheckResult]: Loop: 19469#L1138-1 assume !false; 19470#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 19579#L719 assume !false; 19580#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 20169#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 19565#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 20171#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 20076#L616 assume !(0 != eval_~tmp~0); 20078#L734 start_simulation_~kernel_st~0 := 2; 20186#L504-1 start_simulation_~kernel_st~0 := 3; 20180#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 20170#L744-4 assume !(0 == ~T1_E~0); 20015#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19661#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19662#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21569#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21568#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21567#L774-3 assume !(0 == ~T7_E~0); 21566#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21565#L784-3 assume !(0 == ~E_2~0); 21564#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21560#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21559#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21553#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21552#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20092#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20083#L351-24 assume !(1 == ~m_pc~0); 20084#L351-26 is_master_triggered_~__retres1~0 := 0; 19916#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19917#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20025#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 20116#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20117#L370-24 assume 1 == ~t1_pc~0; 20201#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 20147#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20148#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19462#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19463#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19421#L389-24 assume !(1 == ~t2_pc~0); 19422#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 19424#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19464#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 19672#L936-24 assume !(0 != activate_threads_~tmp___1~0); 19758#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19739#L408-24 assume !(1 == ~t3_pc~0); 19716#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 19717#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19790#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 19901#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 19991#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19976#L427-24 assume !(1 == ~t4_pc~0); 19977#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 19978#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19962#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 19600#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 19601#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20181#L446-24 assume 1 == ~t5_pc~0; 20137#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19597#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19598#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19850#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 19851#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19557#L465-24 assume 1 == ~t6_pc~0; 19513#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 19514#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19510#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19511#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 20024#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20012#L484-24 assume 1 == ~t7_pc~0; 19779#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 19780#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19776#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 19777#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 20198#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 19734#L827-3 assume !(1 == ~T1_E~0); 19735#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20010#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19649#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19650#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19436#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19437#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19574#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19575#L867-3 assume !(1 == ~E_2~0); 19888#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19889#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19751#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19752#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20005#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19642#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 19643#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 19567#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 20173#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 19792#L1157 assume !(0 == start_simulation_~tmp~3); 19756#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 19757#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 19523#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 20175#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 20031#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20032#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 20150#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 19852#L1170 assume !(0 != start_simulation_~tmp___0~1); 19469#L1138-1 [2018-11-28 11:38:38,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:38,516 INFO L82 PathProgramCache]: Analyzing trace with hash -674662803, now seen corresponding path program 1 times [2018-11-28 11:38:38,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:38,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:38,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,517 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:38,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:38,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:38,568 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:38,568 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:38,568 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:38,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:38,568 INFO L82 PathProgramCache]: Analyzing trace with hash -525568227, now seen corresponding path program 1 times [2018-11-28 11:38:38,568 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:38,569 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:38,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,569 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:38,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:38,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:38,607 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:38,607 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:38,607 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:38,607 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:38,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:38,607 INFO L87 Difference]: Start difference. First operand 2429 states and 3539 transitions. cyclomatic complexity: 1114 Second operand 3 states. [2018-11-28 11:38:38,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:38,675 INFO L93 Difference]: Finished difference Result 4510 states and 6538 transitions. [2018-11-28 11:38:38,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:38,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4510 states and 6538 transitions. [2018-11-28 11:38:38,688 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4392 [2018-11-28 11:38:38,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4510 states to 4510 states and 6538 transitions. [2018-11-28 11:38:38,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4510 [2018-11-28 11:38:38,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4510 [2018-11-28 11:38:38,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4510 states and 6538 transitions. [2018-11-28 11:38:38,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:38,707 INFO L705 BuchiCegarLoop]: Abstraction has 4510 states and 6538 transitions. [2018-11-28 11:38:38,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4510 states and 6538 transitions. [2018-11-28 11:38:38,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4510 to 4502. [2018-11-28 11:38:38,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4502 states. [2018-11-28 11:38:38,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4502 states to 4502 states and 6530 transitions. [2018-11-28 11:38:38,752 INFO L728 BuchiCegarLoop]: Abstraction has 4502 states and 6530 transitions. [2018-11-28 11:38:38,752 INFO L608 BuchiCegarLoop]: Abstraction has 4502 states and 6530 transitions. [2018-11-28 11:38:38,752 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-28 11:38:38,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4502 states and 6530 transitions. [2018-11-28 11:38:38,762 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4384 [2018-11-28 11:38:38,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:38,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:38,763 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:38,764 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:38,764 INFO L794 eck$LassoCheckResult]: Stem: 26996#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 26869#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 26870#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26977#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 26623#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26624#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26474#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26475#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26810#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26811#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26667#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26668#L546-1 assume !(0 == ~M_E~0); 27132#L744-1 assume !(0 == ~T1_E~0); 26960#L749-1 assume !(0 == ~T2_E~0); 26596#L754-1 assume !(0 == ~T3_E~0); 26597#L759-1 assume !(0 == ~T4_E~0); 26386#L764-1 assume !(0 == ~T5_E~0); 26387#L769-1 assume !(0 == ~T6_E~0); 26524#L774-1 assume !(0 == ~T7_E~0); 26525#L779-1 assume !(0 == ~E_1~0); 26833#L784-1 assume !(0 == ~E_2~0); 26834#L789-1 assume !(0 == ~E_3~0); 26673#L794-1 assume !(0 == ~E_4~0); 26674#L799-1 assume !(0 == ~E_5~0); 26954#L804-1 assume !(0 == ~E_6~0); 26590#L809-1 assume !(0 == ~E_7~0); 26591#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26919#L351 assume !(1 == ~m_pc~0); 26882#L351-2 is_master_triggered_~__retres1~0 := 0; 26883#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26918#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 27017#L920 assume !(0 != activate_threads_~tmp~1); 27139#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27103#L370 assume !(1 == ~t1_pc~0); 27104#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 27101#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27102#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 26789#L928 assume !(0 != activate_threads_~tmp___0~0); 26516#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26494#L389 assume !(1 == ~t2_pc~0); 26432#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 26433#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26493#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 26628#L936 assume !(0 != activate_threads_~tmp___1~0); 26965#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26748#L408 assume !(1 == ~t3_pc~0); 26635#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 26634#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26631#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26632#L944 assume !(0 != activate_threads_~tmp___2~0); 27156#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27149#L427 assume !(1 == ~t4_pc~0); 26945#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 26946#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26909#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26611#L952 assume !(0 != activate_threads_~tmp___3~0); 26612#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26557#L446 assume !(1 == ~t5_pc~0); 26558#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 26555#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 26556#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26840#L960 assume !(0 != activate_threads_~tmp___4~0); 26825#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 26814#L465 assume !(1 == ~t6_pc~0); 26480#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 26479#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26476#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26477#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 27037#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27014#L484 assume 1 == ~t7_pc~0; 26778#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 26779#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 26776#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26777#L976 assume !(0 != activate_threads_~tmp___6~0); 27042#L976-2 assume !(1 == ~M_E~0); 26694#L827-1 assume !(1 == ~T1_E~0); 26695#L832-1 assume !(1 == ~T2_E~0); 26952#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26585#L842-1 assume !(1 == ~T4_E~0); 26586#L847-1 assume !(1 == ~T5_E~0); 26381#L852-1 assume !(1 == ~T6_E~0); 26382#L857-1 assume !(1 == ~T7_E~0); 26517#L862-1 assume !(1 == ~E_1~0); 26518#L867-1 assume !(1 == ~E_2~0); 26828#L872-1 assume !(1 == ~E_3~0); 26829#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26689#L882-1 assume !(1 == ~E_5~0); 26690#L887-1 assume !(1 == ~E_6~0); 26967#L892-1 assume !(1 == ~E_7~0); 26420#L1138-1 [2018-11-28 11:38:38,764 INFO L796 eck$LassoCheckResult]: Loop: 26420#L1138-1 assume !false; 26421#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 26527#L719 assume !false; 26528#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 27123#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 29703#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 29701#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 29698#L616 assume !(0 != eval_~tmp~0); 29699#L734 start_simulation_~kernel_st~0 := 2; 30657#L504-1 start_simulation_~kernel_st~0 := 3; 30656#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 30655#L744-4 assume !(0 == ~T1_E~0); 30654#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30653#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30652#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30651#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30650#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30649#L774-3 assume !(0 == ~T7_E~0); 30648#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30647#L784-3 assume !(0 == ~E_2~0); 30646#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30645#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30644#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30643#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30642#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30641#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30640#L351-24 assume !(1 == ~m_pc~0); 30639#L351-26 is_master_triggered_~__retres1~0 := 0; 30638#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30637#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30636#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30635#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30634#L370-24 assume !(1 == ~t1_pc~0); 30632#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 30631#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30630#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30629#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30628#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30627#L389-24 assume !(1 == ~t2_pc~0); 30625#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 30624#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30623#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30622#L936-24 assume !(0 != activate_threads_~tmp___1~0); 30621#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30620#L408-24 assume 1 == ~t3_pc~0; 30618#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 30617#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30616#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30615#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 30614#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30613#L427-24 assume !(1 == ~t4_pc~0); 30612#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 30611#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30610#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30609#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 30608#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30607#L446-24 assume !(1 == ~t5_pc~0); 30606#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 30605#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30604#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30603#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 30602#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30601#L465-24 assume !(1 == ~t6_pc~0); 30599#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 30598#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30597#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30596#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 30595#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 30594#L484-24 assume 1 == ~t7_pc~0; 30592#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 30591#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 30590#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30589#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 30588#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 30587#L827-3 assume !(1 == ~T1_E~0); 30586#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30585#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30584#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30583#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30582#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30581#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30580#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30579#L867-3 assume !(1 == ~E_2~0); 30578#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30577#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30576#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30575#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30574#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30573#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 27146#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 26515#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 27128#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 26734#L1157 assume !(0 == start_simulation_~tmp~3); 26701#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 26702#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 26471#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 27130#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 26978#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 26979#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 27094#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 26796#L1170 assume !(0 != start_simulation_~tmp___0~1); 26420#L1138-1 [2018-11-28 11:38:38,764 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:38,765 INFO L82 PathProgramCache]: Analyzing trace with hash 244311820, now seen corresponding path program 1 times [2018-11-28 11:38:38,765 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:38,765 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:38,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,766 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:38,766 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:38,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:38,806 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:38,806 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:38,806 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:38,806 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:38,806 INFO L82 PathProgramCache]: Analyzing trace with hash -1458612769, now seen corresponding path program 1 times [2018-11-28 11:38:38,806 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:38,807 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:38,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,807 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:38,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:38,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:38,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:38,845 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:38,845 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:38,845 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:38,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:38,846 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:38,846 INFO L87 Difference]: Start difference. First operand 4502 states and 6530 transitions. cyclomatic complexity: 2036 Second operand 3 states. [2018-11-28 11:38:38,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:38,926 INFO L93 Difference]: Finished difference Result 8849 states and 12739 transitions. [2018-11-28 11:38:38,927 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:38,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8849 states and 12739 transitions. [2018-11-28 11:38:38,951 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8692 [2018-11-28 11:38:38,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8849 states to 8849 states and 12739 transitions. [2018-11-28 11:38:38,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8849 [2018-11-28 11:38:38,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8849 [2018-11-28 11:38:38,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8849 states and 12739 transitions. [2018-11-28 11:38:38,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:38,991 INFO L705 BuchiCegarLoop]: Abstraction has 8849 states and 12739 transitions. [2018-11-28 11:38:38,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8849 states and 12739 transitions. [2018-11-28 11:38:39,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8849 to 8817. [2018-11-28 11:38:39,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8817 states. [2018-11-28 11:38:39,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8817 states to 8817 states and 12699 transitions. [2018-11-28 11:38:39,075 INFO L728 BuchiCegarLoop]: Abstraction has 8817 states and 12699 transitions. [2018-11-28 11:38:39,075 INFO L608 BuchiCegarLoop]: Abstraction has 8817 states and 12699 transitions. [2018-11-28 11:38:39,075 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-28 11:38:39,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8817 states and 12699 transitions. [2018-11-28 11:38:39,096 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8676 [2018-11-28 11:38:39,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:39,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:39,098 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:39,098 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:39,099 INFO L794 eck$LassoCheckResult]: Stem: 40377#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 40240#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 40241#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 40356#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 39991#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39992#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39835#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39836#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40180#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40181#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40033#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40034#L546-1 assume !(0 == ~M_E~0); 40523#L744-1 assume !(0 == ~T1_E~0); 40333#L749-1 assume !(0 == ~T2_E~0); 39958#L754-1 assume !(0 == ~T3_E~0); 39959#L759-1 assume !(0 == ~T4_E~0); 39746#L764-1 assume !(0 == ~T5_E~0); 39747#L769-1 assume !(0 == ~T6_E~0); 39887#L774-1 assume !(0 == ~T7_E~0); 39888#L779-1 assume !(0 == ~E_1~0); 40203#L784-1 assume !(0 == ~E_2~0); 40204#L789-1 assume !(0 == ~E_3~0); 40039#L794-1 assume !(0 == ~E_4~0); 40040#L799-1 assume !(0 == ~E_5~0); 40326#L804-1 assume !(0 == ~E_6~0); 39952#L809-1 assume !(0 == ~E_7~0); 39953#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40289#L351 assume !(1 == ~m_pc~0); 40254#L351-2 is_master_triggered_~__retres1~0 := 0; 40255#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40288#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 40399#L920 assume !(0 != activate_threads_~tmp~1); 40530#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40493#L370 assume !(1 == ~t1_pc~0); 40494#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 40491#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40492#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 40155#L928 assume !(0 != activate_threads_~tmp___0~0); 39879#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39855#L389 assume !(1 == ~t2_pc~0); 39794#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 39795#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39854#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 39994#L936 assume !(0 != activate_threads_~tmp___1~0); 40340#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40116#L408 assume !(1 == ~t3_pc~0); 40001#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 40000#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39997#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 39998#L944 assume !(0 != activate_threads_~tmp___2~0); 40543#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40540#L427 assume !(1 == ~t4_pc~0); 40315#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 40316#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40279#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 39973#L952 assume !(0 != activate_threads_~tmp___3~0); 39974#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 39920#L446 assume !(1 == ~t5_pc~0); 39921#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 39918#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39919#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 40210#L960 assume !(0 != activate_threads_~tmp___4~0); 40195#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40184#L465 assume !(1 == ~t6_pc~0); 39841#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 39840#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 39837#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 39838#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 40424#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 40394#L484 assume !(1 == ~t7_pc~0); 40395#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 40397#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 40144#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 40145#L976 assume !(0 != activate_threads_~tmp___6~0); 40428#L976-2 assume !(1 == ~M_E~0); 40059#L827-1 assume !(1 == ~T1_E~0); 40060#L832-1 assume !(1 == ~T2_E~0); 40323#L837-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39947#L842-1 assume !(1 == ~T4_E~0); 39948#L847-1 assume !(1 == ~T5_E~0); 39741#L852-1 assume !(1 == ~T6_E~0); 39742#L857-1 assume !(1 == ~T7_E~0); 39880#L862-1 assume !(1 == ~E_1~0); 39881#L867-1 assume !(1 == ~E_2~0); 40198#L872-1 assume !(1 == ~E_3~0); 40199#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40055#L882-1 assume !(1 == ~E_5~0); 40056#L887-1 assume !(1 == ~E_6~0); 40343#L892-1 assume !(1 == ~E_7~0); 40344#L1138-1 [2018-11-28 11:38:39,099 INFO L796 eck$LassoCheckResult]: Loop: 40344#L1138-1 assume !false; 44897#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 44896#L719 assume !false; 44895#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 44894#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 44883#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 44881#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 44879#L616 assume !(0 != eval_~tmp~0); 44880#L734 start_simulation_~kernel_st~0 := 2; 45110#L504-1 start_simulation_~kernel_st~0 := 3; 45108#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 45106#L744-4 assume !(0 == ~T1_E~0); 45104#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45102#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45100#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45098#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45096#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45094#L774-3 assume !(0 == ~T7_E~0); 45092#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45090#L784-3 assume !(0 == ~E_2~0); 45088#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45086#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 45084#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45082#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45080#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45077#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45075#L351-24 assume !(1 == ~m_pc~0); 45073#L351-26 is_master_triggered_~__retres1~0 := 0; 45071#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45069#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 45067#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45065#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45063#L370-24 assume !(1 == ~t1_pc~0); 45060#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 45058#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45056#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 45054#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 45052#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45050#L389-24 assume !(1 == ~t2_pc~0); 45047#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 45045#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45043#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 45041#L936-24 assume !(0 != activate_threads_~tmp___1~0); 45039#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45037#L408-24 assume 1 == ~t3_pc~0; 45034#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 45032#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45030#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 45028#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 45027#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 45026#L427-24 assume !(1 == ~t4_pc~0); 45025#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 45024#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45023#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 45022#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 45020#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 45018#L446-24 assume !(1 == ~t5_pc~0); 45016#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 45014#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 45012#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 45010#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 45008#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 45005#L465-24 assume !(1 == ~t6_pc~0); 45002#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 45000#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 44998#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 44996#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 44993#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 44991#L484-24 assume !(1 == ~t7_pc~0); 44989#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 44987#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44985#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 44983#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 44981#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 44978#L827-3 assume !(1 == ~T1_E~0); 44976#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44974#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44972#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44970#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44968#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44966#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44964#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44962#L867-3 assume !(1 == ~E_2~0); 44960#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44958#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44956#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44954#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44952#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44950#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 44944#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 44938#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 44935#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 44932#L1157 assume !(0 == start_simulation_~tmp~3); 44929#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 44927#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 44918#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 44916#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 44914#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 44912#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 44910#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 44908#L1170 assume !(0 != start_simulation_~tmp___0~1); 40344#L1138-1 [2018-11-28 11:38:39,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:39,099 INFO L82 PathProgramCache]: Analyzing trace with hash 905645611, now seen corresponding path program 1 times [2018-11-28 11:38:39,099 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:39,099 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:39,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,100 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:39,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:39,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:39,146 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:39,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:39,147 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:39,147 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:39,147 INFO L82 PathProgramCache]: Analyzing trace with hash 1259796768, now seen corresponding path program 1 times [2018-11-28 11:38:39,147 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:39,147 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:39,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,148 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:39,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:39,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:39,194 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:39,194 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:39,194 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:39,194 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:39,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:39,195 INFO L87 Difference]: Start difference. First operand 8817 states and 12699 transitions. cyclomatic complexity: 3898 Second operand 3 states. [2018-11-28 11:38:39,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:39,237 INFO L93 Difference]: Finished difference Result 8817 states and 12649 transitions. [2018-11-28 11:38:39,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:39,238 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8817 states and 12649 transitions. [2018-11-28 11:38:39,260 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8676 [2018-11-28 11:38:39,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8817 states to 8817 states and 12649 transitions. [2018-11-28 11:38:39,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8817 [2018-11-28 11:38:39,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8817 [2018-11-28 11:38:39,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8817 states and 12649 transitions. [2018-11-28 11:38:39,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:39,294 INFO L705 BuchiCegarLoop]: Abstraction has 8817 states and 12649 transitions. [2018-11-28 11:38:39,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8817 states and 12649 transitions. [2018-11-28 11:38:39,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8817 to 8817. [2018-11-28 11:38:39,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8817 states. [2018-11-28 11:38:39,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8817 states to 8817 states and 12649 transitions. [2018-11-28 11:38:39,374 INFO L728 BuchiCegarLoop]: Abstraction has 8817 states and 12649 transitions. [2018-11-28 11:38:39,374 INFO L608 BuchiCegarLoop]: Abstraction has 8817 states and 12649 transitions. [2018-11-28 11:38:39,374 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-28 11:38:39,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8817 states and 12649 transitions. [2018-11-28 11:38:39,395 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8676 [2018-11-28 11:38:39,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:39,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:39,397 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:39,397 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:39,397 INFO L794 eck$LassoCheckResult]: Stem: 58019#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 57882#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 57883#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 57997#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 57631#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57632#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57476#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57477#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57823#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57824#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 57674#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57675#L546-1 assume !(0 == ~M_E~0); 58153#L744-1 assume !(0 == ~T1_E~0); 57970#L749-1 assume !(0 == ~T2_E~0); 57599#L754-1 assume !(0 == ~T3_E~0); 57600#L759-1 assume !(0 == ~T4_E~0); 57389#L764-1 assume !(0 == ~T5_E~0); 57390#L769-1 assume !(0 == ~T6_E~0); 57526#L774-1 assume !(0 == ~T7_E~0); 57527#L779-1 assume !(0 == ~E_1~0); 57847#L784-1 assume !(0 == ~E_2~0); 57848#L789-1 assume !(0 == ~E_3~0); 57680#L794-1 assume !(0 == ~E_4~0); 57681#L799-1 assume !(0 == ~E_5~0); 57963#L804-1 assume !(0 == ~E_6~0); 57593#L809-1 assume !(0 == ~E_7~0); 57594#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57931#L351 assume !(1 == ~m_pc~0); 57895#L351-2 is_master_triggered_~__retres1~0 := 0; 57896#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 57930#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 58042#L920 assume !(0 != activate_threads_~tmp~1); 58161#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 58125#L370 assume !(1 == ~t1_pc~0); 58126#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 58123#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58124#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 57800#L928 assume !(0 != activate_threads_~tmp___0~0); 57518#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 57496#L389 assume !(1 == ~t2_pc~0); 57435#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 57436#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57495#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 57635#L936 assume !(0 != activate_threads_~tmp___1~0); 57979#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57759#L408 assume !(1 == ~t3_pc~0); 57642#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 57641#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57638#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 57639#L944 assume !(0 != activate_threads_~tmp___2~0); 58176#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 58169#L427 assume !(1 == ~t4_pc~0); 57952#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 57953#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57921#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 57615#L952 assume !(0 != activate_threads_~tmp___3~0); 57616#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 57560#L446 assume !(1 == ~t5_pc~0); 57561#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 57558#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 57559#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 57854#L960 assume !(0 != activate_threads_~tmp___4~0); 57838#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 57827#L465 assume !(1 == ~t6_pc~0); 57482#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 57481#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 57478#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 57479#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 58064#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 58036#L484 assume !(1 == ~t7_pc~0); 58037#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 58039#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 57790#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 57791#L976 assume !(0 != activate_threads_~tmp___6~0); 58068#L976-2 assume !(1 == ~M_E~0); 57701#L827-1 assume !(1 == ~T1_E~0); 57702#L832-1 assume !(1 == ~T2_E~0); 57960#L837-1 assume !(1 == ~T3_E~0); 57588#L842-1 assume !(1 == ~T4_E~0); 57589#L847-1 assume !(1 == ~T5_E~0); 57384#L852-1 assume !(1 == ~T6_E~0); 57385#L857-1 assume !(1 == ~T7_E~0); 57521#L862-1 assume !(1 == ~E_1~0); 57522#L867-1 assume !(1 == ~E_2~0); 57841#L872-1 assume !(1 == ~E_3~0); 57842#L877-1 assume 1 == ~E_4~0;~E_4~0 := 2; 57697#L882-1 assume !(1 == ~E_5~0); 57698#L887-1 assume !(1 == ~E_6~0); 57982#L892-1 assume !(1 == ~E_7~0); 57983#L1138-1 [2018-11-28 11:38:39,397 INFO L796 eck$LassoCheckResult]: Loop: 57983#L1138-1 assume !false; 61279#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 61277#L719 assume !false; 61275#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 61273#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 61263#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 61261#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 61258#L616 assume !(0 != eval_~tmp~0); 61259#L734 start_simulation_~kernel_st~0 := 2; 61580#L504-1 start_simulation_~kernel_st~0 := 3; 61579#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 61578#L744-4 assume !(0 == ~T1_E~0); 61574#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61572#L754-3 assume !(0 == ~T3_E~0); 61571#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61570#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61569#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61568#L774-3 assume !(0 == ~T7_E~0); 61567#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61566#L784-3 assume !(0 == ~E_2~0); 61565#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61564#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61563#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 61562#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61561#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 61560#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 61559#L351-24 assume !(1 == ~m_pc~0); 61558#L351-26 is_master_triggered_~__retres1~0 := 0; 61557#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 61556#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 61555#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 61554#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 61553#L370-24 assume 1 == ~t1_pc~0; 61552#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 61550#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 61549#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 61547#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 61545#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 61543#L389-24 assume !(1 == ~t2_pc~0); 61540#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 61538#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 61536#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 61534#L936-24 assume !(0 != activate_threads_~tmp___1~0); 61531#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 61529#L408-24 assume 1 == ~t3_pc~0; 61526#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 61524#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 61522#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 61519#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 61517#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 61515#L427-24 assume !(1 == ~t4_pc~0); 61513#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 61511#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 61509#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 61507#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 61504#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 61502#L446-24 assume !(1 == ~t5_pc~0); 61500#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 61498#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 61496#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 61494#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 61492#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 61490#L465-24 assume 1 == ~t6_pc~0; 61488#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 61485#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 61483#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 61481#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 61479#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 61477#L484-24 assume !(1 == ~t7_pc~0); 61475#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 61473#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 61471#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 61469#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 61466#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 61464#L827-3 assume !(1 == ~T1_E~0); 61462#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61460#L837-3 assume !(1 == ~T3_E~0); 61458#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61456#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 61454#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61452#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61450#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61448#L867-3 assume !(1 == ~E_2~0); 61446#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61444#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61442#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61440#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61438#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61436#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 61426#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 61420#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 61418#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 61416#L1157 assume !(0 == start_simulation_~tmp~3); 61414#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 61413#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 61405#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 61404#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 61403#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 61402#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 61401#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 61400#L1170 assume !(0 != start_simulation_~tmp___0~1); 57983#L1138-1 [2018-11-28 11:38:39,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:39,398 INFO L82 PathProgramCache]: Analyzing trace with hash 1163811049, now seen corresponding path program 1 times [2018-11-28 11:38:39,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:39,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:39,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:39,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:39,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:39,434 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:39,434 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:38:39,435 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:39,435 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:39,435 INFO L82 PathProgramCache]: Analyzing trace with hash 224951198, now seen corresponding path program 1 times [2018-11-28 11:38:39,435 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:39,435 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:39,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,436 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:39,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:39,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:39,477 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:39,477 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:39,478 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:39,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:39,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:39,478 INFO L87 Difference]: Start difference. First operand 8817 states and 12649 transitions. cyclomatic complexity: 3848 Second operand 3 states. [2018-11-28 11:38:39,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:39,570 INFO L93 Difference]: Finished difference Result 8817 states and 12543 transitions. [2018-11-28 11:38:39,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:39,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8817 states and 12543 transitions. [2018-11-28 11:38:39,596 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8676 [2018-11-28 11:38:39,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8817 states to 8817 states and 12543 transitions. [2018-11-28 11:38:39,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8817 [2018-11-28 11:38:39,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8817 [2018-11-28 11:38:39,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8817 states and 12543 transitions. [2018-11-28 11:38:39,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:39,627 INFO L705 BuchiCegarLoop]: Abstraction has 8817 states and 12543 transitions. [2018-11-28 11:38:39,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8817 states and 12543 transitions. [2018-11-28 11:38:39,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8817 to 8817. [2018-11-28 11:38:39,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8817 states. [2018-11-28 11:38:39,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8817 states to 8817 states and 12543 transitions. [2018-11-28 11:38:39,721 INFO L728 BuchiCegarLoop]: Abstraction has 8817 states and 12543 transitions. [2018-11-28 11:38:39,721 INFO L608 BuchiCegarLoop]: Abstraction has 8817 states and 12543 transitions. [2018-11-28 11:38:39,721 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-28 11:38:39,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8817 states and 12543 transitions. [2018-11-28 11:38:39,743 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8676 [2018-11-28 11:38:39,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:39,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:39,745 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:39,745 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:39,746 INFO L794 eck$LassoCheckResult]: Stem: 75660#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 75522#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 75523#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 75639#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 75272#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75273#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75122#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75123#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75465#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75466#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75316#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75317#L546-1 assume !(0 == ~M_E~0); 75800#L744-1 assume !(0 == ~T1_E~0); 75610#L749-1 assume !(0 == ~T2_E~0); 75245#L754-1 assume !(0 == ~T3_E~0); 75246#L759-1 assume !(0 == ~T4_E~0); 75032#L764-1 assume !(0 == ~T5_E~0); 75033#L769-1 assume !(0 == ~T6_E~0); 75172#L774-1 assume !(0 == ~T7_E~0); 75173#L779-1 assume !(0 == ~E_1~0); 75488#L784-1 assume !(0 == ~E_2~0); 75489#L789-1 assume !(0 == ~E_3~0); 75322#L794-1 assume !(0 == ~E_4~0); 75323#L799-1 assume !(0 == ~E_5~0); 75604#L804-1 assume !(0 == ~E_6~0); 75239#L809-1 assume !(0 == ~E_7~0); 75240#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 75566#L351 assume !(1 == ~m_pc~0); 75536#L351-2 is_master_triggered_~__retres1~0 := 0; 75537#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 75563#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 75689#L920 assume !(0 != activate_threads_~tmp~1); 75811#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 75775#L370 assume !(1 == ~t1_pc~0); 75776#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 75773#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 75774#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 75443#L928 assume !(0 != activate_threads_~tmp___0~0); 75164#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 75142#L389 assume !(1 == ~t2_pc~0); 75081#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 75082#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 75138#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 75277#L936 assume !(0 != activate_threads_~tmp___1~0); 75623#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 75401#L408 assume !(1 == ~t3_pc~0); 75284#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 75283#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 75280#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 75281#L944 assume !(0 != activate_threads_~tmp___2~0); 75827#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 75820#L427 assume !(1 == ~t4_pc~0); 75591#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 75592#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 75558#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 75260#L952 assume !(0 != activate_threads_~tmp___3~0); 75261#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 75207#L446 assume !(1 == ~t5_pc~0); 75208#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 75203#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 75204#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 75496#L960 assume !(0 != activate_threads_~tmp___4~0); 75480#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 75467#L465 assume !(1 == ~t6_pc~0); 75128#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 75127#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 75124#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 75125#L968 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 75713#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 75681#L484 assume !(1 == ~t7_pc~0); 75682#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 75686#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 75431#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 75432#L976 assume !(0 != activate_threads_~tmp___6~0); 75717#L976-2 assume !(1 == ~M_E~0); 75342#L827-1 assume !(1 == ~T1_E~0); 75343#L832-1 assume !(1 == ~T2_E~0); 75602#L837-1 assume !(1 == ~T3_E~0); 75234#L842-1 assume !(1 == ~T4_E~0); 75235#L847-1 assume !(1 == ~T5_E~0); 75024#L852-1 assume !(1 == ~T6_E~0); 75025#L857-1 assume !(1 == ~T7_E~0); 75165#L862-1 assume !(1 == ~E_1~0); 75166#L867-1 assume !(1 == ~E_2~0); 75483#L872-1 assume !(1 == ~E_3~0); 75484#L877-1 assume !(1 == ~E_4~0); 75338#L882-1 assume !(1 == ~E_5~0); 75339#L887-1 assume !(1 == ~E_6~0); 75626#L892-1 assume !(1 == ~E_7~0); 75627#L1138-1 [2018-11-28 11:38:39,746 INFO L796 eck$LassoCheckResult]: Loop: 75627#L1138-1 assume !false; 77486#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 77481#L719 assume !false; 77477#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 77406#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 77394#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 77388#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77382#L616 assume !(0 != eval_~tmp~0); 77383#L734 start_simulation_~kernel_st~0 := 2; 80223#L504-1 start_simulation_~kernel_st~0 := 3; 80221#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 80219#L744-4 assume !(0 == ~T1_E~0); 80217#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 80215#L754-3 assume !(0 == ~T3_E~0); 80213#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 80211#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 80209#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 80207#L774-3 assume !(0 == ~T7_E~0); 80205#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 80203#L784-3 assume !(0 == ~E_2~0); 80200#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80198#L794-3 assume !(0 == ~E_4~0); 80196#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 80194#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 80192#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 80190#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 80187#L351-24 assume !(1 == ~m_pc~0); 80185#L351-26 is_master_triggered_~__retres1~0 := 0; 80183#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 80181#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 80180#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 80179#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 80175#L370-24 assume !(1 == ~t1_pc~0); 80167#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 80164#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 80162#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 80160#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 80158#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 80155#L389-24 assume !(1 == ~t2_pc~0); 80150#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 80145#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 80141#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 80137#L936-24 assume !(0 != activate_threads_~tmp___1~0); 80008#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 80007#L408-24 assume 1 == ~t3_pc~0; 79939#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 79853#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 79846#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 79837#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 79836#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78826#L427-24 assume !(1 == ~t4_pc~0); 78825#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 78824#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78823#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 78822#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 77991#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 77987#L446-24 assume !(1 == ~t5_pc~0); 77978#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 77976#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 77974#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 77970#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 77968#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 77967#L465-24 assume !(1 == ~t6_pc~0); 77769#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 77767#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 77765#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 77763#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 77761#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 77759#L484-24 assume !(1 == ~t7_pc~0); 77757#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 77755#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 77753#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 77750#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 77748#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 77746#L827-3 assume !(1 == ~T1_E~0); 77745#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77736#L837-3 assume !(1 == ~T3_E~0); 77677#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77676#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77674#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77672#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77671#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77670#L867-3 assume !(1 == ~E_2~0); 77668#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77663#L877-3 assume !(1 == ~E_4~0); 77660#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77657#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77654#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77652#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 77606#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 77599#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 77597#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 77546#L1157 assume !(0 == start_simulation_~tmp~3); 77543#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 77541#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 77529#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 77524#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 77518#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 77513#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 77506#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 77501#L1170 assume !(0 != start_simulation_~tmp___0~1); 75627#L1138-1 [2018-11-28 11:38:39,746 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:39,747 INFO L82 PathProgramCache]: Analyzing trace with hash 1163870631, now seen corresponding path program 1 times [2018-11-28 11:38:39,747 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:39,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:39,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:39,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:39,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:39,864 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:39,864 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:39,864 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:39,864 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:39,865 INFO L82 PathProgramCache]: Analyzing trace with hash 1969768608, now seen corresponding path program 1 times [2018-11-28 11:38:39,865 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:39,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:39,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,866 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:39,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:39,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:39,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:39,902 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:39,902 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:39,902 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:39,902 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:38:39,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:38:39,903 INFO L87 Difference]: Start difference. First operand 8817 states and 12543 transitions. cyclomatic complexity: 3742 Second operand 5 states. [2018-11-28 11:38:40,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:40,123 INFO L93 Difference]: Finished difference Result 20350 states and 29092 transitions. [2018-11-28 11:38:40,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:38:40,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20350 states and 29092 transitions. [2018-11-28 11:38:40,184 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20068 [2018-11-28 11:38:40,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20350 states to 20350 states and 29092 transitions. [2018-11-28 11:38:40,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20350 [2018-11-28 11:38:40,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20350 [2018-11-28 11:38:40,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20350 states and 29092 transitions. [2018-11-28 11:38:40,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:40,249 INFO L705 BuchiCegarLoop]: Abstraction has 20350 states and 29092 transitions. [2018-11-28 11:38:40,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20350 states and 29092 transitions. [2018-11-28 11:38:40,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20350 to 9180. [2018-11-28 11:38:40,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9180 states. [2018-11-28 11:38:40,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9180 states to 9180 states and 12906 transitions. [2018-11-28 11:38:40,365 INFO L728 BuchiCegarLoop]: Abstraction has 9180 states and 12906 transitions. [2018-11-28 11:38:40,365 INFO L608 BuchiCegarLoop]: Abstraction has 9180 states and 12906 transitions. [2018-11-28 11:38:40,365 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-28 11:38:40,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9180 states and 12906 transitions. [2018-11-28 11:38:40,384 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9036 [2018-11-28 11:38:40,384 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:40,384 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:40,385 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:40,386 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:40,386 INFO L794 eck$LassoCheckResult]: Stem: 104862#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 104734#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 104735#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 104843#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 104465#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104466#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104303#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104304#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104668#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 104669#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 104510#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104511#L546-1 assume !(0 == ~M_E~0); 104987#L744-1 assume !(0 == ~T1_E~0); 104822#L749-1 assume !(0 == ~T2_E~0); 104437#L754-1 assume !(0 == ~T3_E~0); 104438#L759-1 assume !(0 == ~T4_E~0); 104215#L764-1 assume !(0 == ~T5_E~0); 104216#L769-1 assume !(0 == ~T6_E~0); 104362#L774-1 assume !(0 == ~T7_E~0); 104363#L779-1 assume !(0 == ~E_1~0); 104698#L784-1 assume !(0 == ~E_2~0); 104699#L789-1 assume !(0 == ~E_3~0); 104516#L794-1 assume !(0 == ~E_4~0); 104517#L799-1 assume !(0 == ~E_5~0); 104814#L804-1 assume !(0 == ~E_6~0); 104431#L809-1 assume !(0 == ~E_7~0); 104432#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 104775#L351 assume !(1 == ~m_pc~0); 104746#L351-2 is_master_triggered_~__retres1~0 := 0; 104747#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 104774#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 104883#L920 assume !(0 != activate_threads_~tmp~1); 104993#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 104964#L370 assume !(1 == ~t1_pc~0); 104965#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 104962#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 104963#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 104632#L928 assume !(0 != activate_threads_~tmp___0~0); 104350#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 104323#L389 assume !(1 == ~t2_pc~0); 104261#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 104262#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 104322#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 104470#L936 assume !(0 != activate_threads_~tmp___1~0); 104830#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 104590#L408 assume !(1 == ~t3_pc~0); 104478#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 104477#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 104474#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 104475#L944 assume !(0 != activate_threads_~tmp___2~0); 105010#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 105005#L427 assume !(1 == ~t4_pc~0); 104802#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 104803#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 104767#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 104453#L952 assume !(0 != activate_threads_~tmp___3~0); 104454#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 104398#L446 assume !(1 == ~t5_pc~0); 104399#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 104396#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 104397#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 104706#L960 assume !(0 != activate_threads_~tmp___4~0); 104689#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 104674#L465 assume !(1 == ~t6_pc~0); 104309#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 104670#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 104671#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 104903#L968 assume !(0 != activate_threads_~tmp___5~0); 104904#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 104876#L484 assume !(1 == ~t7_pc~0); 104877#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 104880#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 104617#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 104618#L976 assume !(0 != activate_threads_~tmp___6~0); 104909#L976-2 assume !(1 == ~M_E~0); 104536#L827-1 assume !(1 == ~T1_E~0); 104537#L832-1 assume !(1 == ~T2_E~0); 104812#L837-1 assume !(1 == ~T3_E~0); 104426#L842-1 assume !(1 == ~T4_E~0); 104427#L847-1 assume !(1 == ~T5_E~0); 104206#L852-1 assume !(1 == ~T6_E~0); 104207#L857-1 assume !(1 == ~T7_E~0); 104352#L862-1 assume !(1 == ~E_1~0); 104353#L867-1 assume !(1 == ~E_2~0); 104692#L872-1 assume !(1 == ~E_3~0); 104693#L877-1 assume !(1 == ~E_4~0); 104532#L882-1 assume !(1 == ~E_5~0); 104533#L887-1 assume !(1 == ~E_6~0); 104833#L892-1 assume !(1 == ~E_7~0); 104834#L1138-1 [2018-11-28 11:38:40,386 INFO L796 eck$LassoCheckResult]: Loop: 104834#L1138-1 assume !false; 107975#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 107970#L719 assume !false; 107783#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 106603#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 106595#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 106586#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 106583#L616 assume !(0 != eval_~tmp~0); 106584#L734 start_simulation_~kernel_st~0 := 2; 109092#L504-1 start_simulation_~kernel_st~0 := 3; 109090#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 109088#L744-4 assume !(0 == ~T1_E~0); 109086#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 109035#L754-3 assume !(0 == ~T3_E~0); 109032#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 109029#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 109025#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 109022#L774-3 assume !(0 == ~T7_E~0); 108970#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 108966#L784-3 assume !(0 == ~E_2~0); 108962#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108958#L794-3 assume !(0 == ~E_4~0); 108905#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108901#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 108897#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 108844#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 108843#L351-24 assume !(1 == ~m_pc~0); 108842#L351-26 is_master_triggered_~__retres1~0 := 0; 108841#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 108840#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 108839#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 108838#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 108837#L370-24 assume !(1 == ~t1_pc~0); 108835#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 108834#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 108833#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 108832#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 108831#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 108830#L389-24 assume !(1 == ~t2_pc~0); 108828#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 108827#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 108826#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 108825#L936-24 assume !(0 != activate_threads_~tmp___1~0); 108824#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 108823#L408-24 assume 1 == ~t3_pc~0; 108821#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 108820#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 108819#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 108818#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 108817#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 108816#L427-24 assume !(1 == ~t4_pc~0); 108815#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 108814#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 108813#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 108812#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 108811#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 108810#L446-24 assume !(1 == ~t5_pc~0); 108809#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 108808#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 108807#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 108806#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 108805#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 108804#L465-24 assume !(1 == ~t6_pc~0); 108803#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 108801#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 108799#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 108797#L968-24 assume !(0 != activate_threads_~tmp___5~0); 108792#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 108789#L484-24 assume !(1 == ~t7_pc~0); 108659#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 108657#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 108655#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 108652#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 108650#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 108648#L827-3 assume !(1 == ~T1_E~0); 108646#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108644#L837-3 assume !(1 == ~T3_E~0); 108642#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 108640#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 108638#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108636#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 108634#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 108632#L867-3 assume !(1 == ~E_2~0); 108630#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108628#L877-3 assume !(1 == ~E_4~0); 108626#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 108624#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 108622#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 108620#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 108610#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 108604#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 108602#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 108600#L1157 assume !(0 == start_simulation_~tmp~3); 108598#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 108597#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 108392#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 108384#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 108330#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 108329#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 108328#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 108327#L1170 assume !(0 != start_simulation_~tmp___0~1); 104834#L1138-1 [2018-11-28 11:38:40,386 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:40,387 INFO L82 PathProgramCache]: Analyzing trace with hash 1382725349, now seen corresponding path program 1 times [2018-11-28 11:38:40,387 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:40,387 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:40,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:40,388 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:40,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:40,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:40,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:40,432 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:40,432 INFO L82 PathProgramCache]: Analyzing trace with hash 1125763106, now seen corresponding path program 1 times [2018-11-28 11:38:40,432 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:40,432 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:40,433 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:40,433 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:40,433 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:40,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:40,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:40,474 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:40,474 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:40,474 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:40,474 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:38:40,474 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:38:40,475 INFO L87 Difference]: Start difference. First operand 9180 states and 12906 transitions. cyclomatic complexity: 3742 Second operand 5 states. [2018-11-28 11:38:40,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:40,608 INFO L93 Difference]: Finished difference Result 16664 states and 23158 transitions. [2018-11-28 11:38:40,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-28 11:38:40,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16664 states and 23158 transitions. [2018-11-28 11:38:40,655 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16472 [2018-11-28 11:38:40,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16664 states to 16664 states and 23158 transitions. [2018-11-28 11:38:40,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16664 [2018-11-28 11:38:40,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16664 [2018-11-28 11:38:40,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16664 states and 23158 transitions. [2018-11-28 11:38:40,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:40,709 INFO L705 BuchiCegarLoop]: Abstraction has 16664 states and 23158 transitions. [2018-11-28 11:38:40,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16664 states and 23158 transitions. [2018-11-28 11:38:40,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16664 to 9228. [2018-11-28 11:38:40,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9228 states. [2018-11-28 11:38:40,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9228 states to 9228 states and 12954 transitions. [2018-11-28 11:38:40,806 INFO L728 BuchiCegarLoop]: Abstraction has 9228 states and 12954 transitions. [2018-11-28 11:38:40,807 INFO L608 BuchiCegarLoop]: Abstraction has 9228 states and 12954 transitions. [2018-11-28 11:38:40,807 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-28 11:38:40,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9228 states and 12954 transitions. [2018-11-28 11:38:40,825 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9084 [2018-11-28 11:38:40,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:40,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:40,827 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:40,827 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:40,827 INFO L794 eck$LassoCheckResult]: Stem: 130715#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 130576#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 130577#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 130689#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 130320#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130321#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 130166#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130167#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130517#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 130518#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 130363#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 130364#L546-1 assume !(0 == ~M_E~0); 130862#L744-1 assume !(0 == ~T1_E~0); 130665#L749-1 assume !(0 == ~T2_E~0); 130292#L754-1 assume !(0 == ~T3_E~0); 130293#L759-1 assume !(0 == ~T4_E~0); 130075#L764-1 assume !(0 == ~T5_E~0); 130076#L769-1 assume !(0 == ~T6_E~0); 130219#L774-1 assume !(0 == ~T7_E~0); 130220#L779-1 assume !(0 == ~E_1~0); 130542#L784-1 assume !(0 == ~E_2~0); 130543#L789-1 assume !(0 == ~E_3~0); 130369#L794-1 assume !(0 == ~E_4~0); 130370#L799-1 assume !(0 == ~E_5~0); 130658#L804-1 assume !(0 == ~E_6~0); 130286#L809-1 assume !(0 == ~E_7~0); 130287#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 130620#L351 assume !(1 == ~m_pc~0); 130590#L351-2 is_master_triggered_~__retres1~0 := 0; 130591#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 130617#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 130742#L920 assume !(0 != activate_threads_~tmp~1); 130873#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 130835#L370 assume !(1 == ~t1_pc~0); 130836#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 130830#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 130831#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 130488#L928 assume !(0 != activate_threads_~tmp___0~0); 130210#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 130186#L389 assume !(1 == ~t2_pc~0); 130124#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 130125#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 130182#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 130324#L936 assume !(0 != activate_threads_~tmp___1~0); 130674#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 130448#L408 assume !(1 == ~t3_pc~0); 130331#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 130330#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 130327#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 130328#L944 assume !(0 != activate_threads_~tmp___2~0); 130892#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 130886#L427 assume !(1 == ~t4_pc~0); 130647#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 130648#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 130612#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 130307#L952 assume !(0 != activate_threads_~tmp___3~0); 130308#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 130254#L446 assume !(1 == ~t5_pc~0); 130255#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 130250#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 130251#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 130549#L960 assume !(0 != activate_threads_~tmp___4~0); 130534#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 130519#L465 assume !(1 == ~t6_pc~0); 130172#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 130523#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 130925#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 130765#L968 assume !(0 != activate_threads_~tmp___5~0); 130766#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 130733#L484 assume !(1 == ~t7_pc~0); 130734#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 130738#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 130476#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 130477#L976 assume !(0 != activate_threads_~tmp___6~0); 130771#L976-2 assume !(1 == ~M_E~0); 130390#L827-1 assume !(1 == ~T1_E~0); 130391#L832-1 assume !(1 == ~T2_E~0); 130656#L837-1 assume !(1 == ~T3_E~0); 130281#L842-1 assume !(1 == ~T4_E~0); 130282#L847-1 assume !(1 == ~T5_E~0); 130067#L852-1 assume !(1 == ~T6_E~0); 130068#L857-1 assume !(1 == ~T7_E~0); 130211#L862-1 assume !(1 == ~E_1~0); 130212#L867-1 assume !(1 == ~E_2~0); 130537#L872-1 assume !(1 == ~E_3~0); 130538#L877-1 assume !(1 == ~E_4~0); 130386#L882-1 assume !(1 == ~E_5~0); 130387#L887-1 assume !(1 == ~E_6~0); 130677#L892-1 assume !(1 == ~E_7~0); 130678#L1138-1 [2018-11-28 11:38:40,828 INFO L796 eck$LassoCheckResult]: Loop: 130678#L1138-1 assume !false; 138522#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 130668#L719 assume !false; 130853#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 130854#L559 assume !(0 == ~m_st~0); 130358#L563 assume !(0 == ~t1_st~0); 130272#L567 assume !(0 == ~t2_st~0); 130273#L571 assume !(0 == ~t3_st~0); 130532#L575 assume !(0 == ~t4_st~0); 130533#L579 assume !(0 == ~t5_st~0); 130752#L583 assume !(0 == ~t6_st~0); 130205#L587 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 130207#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 139173#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 138919#L616 assume !(0 != eval_~tmp~0); 130916#L734 start_simulation_~kernel_st~0 := 2; 130883#L504-1 start_simulation_~kernel_st~0 := 3; 130884#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 138644#L744-4 assume !(0 == ~T1_E~0); 138643#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 138642#L754-3 assume !(0 == ~T3_E~0); 138641#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 138640#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 138639#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 138638#L774-3 assume !(0 == ~T7_E~0); 130889#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 130525#L784-3 assume !(0 == ~E_2~0); 130526#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 130376#L794-3 assume !(0 == ~E_4~0); 130377#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 138636#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 138635#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 138634#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 138633#L351-24 assume !(1 == ~m_pc~0); 138632#L351-26 is_master_triggered_~__retres1~0 := 0; 138631#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 138630#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 138629#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 138628#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 138627#L370-24 assume 1 == ~t1_pc~0; 138626#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 138624#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 138623#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 138622#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 138621#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 138620#L389-24 assume !(1 == ~t2_pc~0); 138618#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 138617#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 138616#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 138615#L936-24 assume !(0 != activate_threads_~tmp___1~0); 138614#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 138613#L408-24 assume 1 == ~t3_pc~0; 138611#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 138610#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 138609#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 138608#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 138607#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 138606#L427-24 assume !(1 == ~t4_pc~0); 138605#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 138604#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 138603#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 138602#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 138601#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 138600#L446-24 assume !(1 == ~t5_pc~0); 138599#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 138598#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 138597#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 138596#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 138595#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 138594#L465-24 assume 1 == ~t6_pc~0; 138592#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 138590#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 138588#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 138586#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 138585#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 138584#L484-24 assume !(1 == ~t7_pc~0); 138583#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 138582#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 138581#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 138580#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 138579#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 138578#L827-3 assume !(1 == ~T1_E~0); 138577#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 138576#L837-3 assume !(1 == ~T3_E~0); 138575#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 138574#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 138573#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 138572#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 138571#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 138570#L867-3 assume !(1 == ~E_2~0); 138569#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 138568#L877-3 assume !(1 == ~E_4~0); 138567#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 138566#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 138565#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 138564#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 138560#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 138553#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 138551#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 138548#L1157 assume !(0 == start_simulation_~tmp~3); 138546#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 138545#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 138535#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 138533#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 138531#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 138529#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 138528#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 138524#L1170 assume !(0 != start_simulation_~tmp___0~1); 130678#L1138-1 [2018-11-28 11:38:40,828 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:40,828 INFO L82 PathProgramCache]: Analyzing trace with hash 1382725349, now seen corresponding path program 2 times [2018-11-28 11:38:40,828 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:40,828 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:40,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:40,829 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:40,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:40,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:40,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:40,863 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:40,863 INFO L82 PathProgramCache]: Analyzing trace with hash 970940382, now seen corresponding path program 1 times [2018-11-28 11:38:40,863 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:40,863 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:40,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:40,864 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:40,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:40,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:40,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:40,931 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:40,931 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-28 11:38:40,931 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:40,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-28 11:38:40,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-28 11:38:40,932 INFO L87 Difference]: Start difference. First operand 9228 states and 12954 transitions. cyclomatic complexity: 3742 Second operand 5 states. [2018-11-28 11:38:41,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:41,119 INFO L93 Difference]: Finished difference Result 18340 states and 25589 transitions. [2018-11-28 11:38:41,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-28 11:38:41,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18340 states and 25589 transitions. [2018-11-28 11:38:41,241 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18164 [2018-11-28 11:38:41,272 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18340 states to 18340 states and 25589 transitions. [2018-11-28 11:38:41,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18340 [2018-11-28 11:38:41,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18340 [2018-11-28 11:38:41,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18340 states and 25589 transitions. [2018-11-28 11:38:41,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:41,289 INFO L705 BuchiCegarLoop]: Abstraction has 18340 states and 25589 transitions. [2018-11-28 11:38:41,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18340 states and 25589 transitions. [2018-11-28 11:38:41,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18340 to 9420. [2018-11-28 11:38:41,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9420 states. [2018-11-28 11:38:41,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9420 states to 9420 states and 13089 transitions. [2018-11-28 11:38:41,378 INFO L728 BuchiCegarLoop]: Abstraction has 9420 states and 13089 transitions. [2018-11-28 11:38:41,378 INFO L608 BuchiCegarLoop]: Abstraction has 9420 states and 13089 transitions. [2018-11-28 11:38:41,378 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-28 11:38:41,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9420 states and 13089 transitions. [2018-11-28 11:38:41,397 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9276 [2018-11-28 11:38:41,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:41,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:41,399 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:41,399 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:41,399 INFO L794 eck$LassoCheckResult]: Stem: 158301#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 158162#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 158163#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 158275#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 157903#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157904#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157744#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157745#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158100#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 158101#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 157948#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 157949#L546-1 assume !(0 == ~M_E~0); 158450#L744-1 assume !(0 == ~T1_E~0); 158252#L749-1 assume !(0 == ~T2_E~0); 157874#L754-1 assume !(0 == ~T3_E~0); 157875#L759-1 assume !(0 == ~T4_E~0); 157655#L764-1 assume !(0 == ~T5_E~0); 157656#L769-1 assume !(0 == ~T6_E~0); 157798#L774-1 assume !(0 == ~T7_E~0); 157799#L779-1 assume !(0 == ~E_1~0); 158127#L784-1 assume !(0 == ~E_2~0); 158128#L789-1 assume !(0 == ~E_3~0); 157954#L794-1 assume !(0 == ~E_4~0); 157955#L799-1 assume !(0 == ~E_5~0); 158246#L804-1 assume !(0 == ~E_6~0); 157868#L809-1 assume !(0 == ~E_7~0); 157869#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 158207#L351 assume !(1 == ~m_pc~0); 158176#L351-2 is_master_triggered_~__retres1~0 := 0; 158177#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 158204#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 158328#L920 assume !(0 != activate_threads_~tmp~1); 158459#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 158420#L370 assume !(1 == ~t1_pc~0); 158421#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 158418#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 158419#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 158072#L928 assume !(0 != activate_threads_~tmp___0~0); 157788#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 157764#L389 assume !(1 == ~t2_pc~0); 157702#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 157703#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 157760#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 157909#L936 assume !(0 != activate_threads_~tmp___1~0); 158261#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 158029#L408 assume !(1 == ~t3_pc~0); 157916#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 157915#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 157912#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 157913#L944 assume !(0 != activate_threads_~tmp___2~0); 158472#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 158469#L427 assume !(1 == ~t4_pc~0); 158235#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 158236#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 158199#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 157890#L952 assume !(0 != activate_threads_~tmp___3~0); 157891#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157834#L446 assume !(1 == ~t5_pc~0); 157835#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 157830#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157831#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 158137#L960 assume !(0 != activate_threads_~tmp___4~0); 158119#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 158102#L465 assume !(1 == ~t6_pc~0); 157750#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 158106#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 158491#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 158356#L968 assume !(0 != activate_threads_~tmp___5~0); 158357#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 158321#L484 assume !(1 == ~t7_pc~0); 158322#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 158325#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 158058#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 158059#L976 assume !(0 != activate_threads_~tmp___6~0); 158362#L976-2 assume !(1 == ~M_E~0); 157974#L827-1 assume !(1 == ~T1_E~0); 157975#L832-1 assume !(1 == ~T2_E~0); 158244#L837-1 assume !(1 == ~T3_E~0); 157863#L842-1 assume !(1 == ~T4_E~0); 157864#L847-1 assume !(1 == ~T5_E~0); 157647#L852-1 assume !(1 == ~T6_E~0); 157648#L857-1 assume !(1 == ~T7_E~0); 157789#L862-1 assume !(1 == ~E_1~0); 157790#L867-1 assume !(1 == ~E_2~0); 158122#L872-1 assume !(1 == ~E_3~0); 158123#L877-1 assume !(1 == ~E_4~0); 157970#L882-1 assume !(1 == ~E_5~0); 157971#L887-1 assume !(1 == ~E_6~0); 158264#L892-1 assume !(1 == ~E_7~0); 158265#L1138-1 [2018-11-28 11:38:41,399 INFO L796 eck$LassoCheckResult]: Loop: 158265#L1138-1 assume !false; 162275#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 161835#L719 assume !false; 162212#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 162202#L559 assume !(0 == ~m_st~0); 162198#L563 assume !(0 == ~t1_st~0); 162199#L567 assume !(0 == ~t2_st~0); 162201#L571 assume !(0 == ~t3_st~0); 162196#L575 assume !(0 == ~t4_st~0); 162197#L579 assume !(0 == ~t5_st~0); 162200#L583 assume !(0 == ~t6_st~0); 162194#L587 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 162195#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 161745#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 161746#L616 assume !(0 != eval_~tmp~0); 162781#L734 start_simulation_~kernel_st~0 := 2; 162778#L504-1 start_simulation_~kernel_st~0 := 3; 162775#L744-2 assume 0 == ~M_E~0;~M_E~0 := 1; 162772#L744-4 assume !(0 == ~T1_E~0); 162769#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 162765#L754-3 assume !(0 == ~T3_E~0); 162761#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 162757#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 162752#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 162747#L774-3 assume !(0 == ~T7_E~0); 162742#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 162737#L784-3 assume !(0 == ~E_2~0); 162732#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 162727#L794-3 assume !(0 == ~E_4~0); 162721#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 162716#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 162711#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 162706#L814-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 162702#L351-24 assume !(1 == ~m_pc~0); 162697#L351-26 is_master_triggered_~__retres1~0 := 0; 162693#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 162689#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 162685#L920-24 assume !(0 != activate_threads_~tmp~1); 162680#L920-26 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 162674#L370-24 assume !(1 == ~t1_pc~0); 162668#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 162663#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 162658#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 162652#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 162647#L928-26 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 162642#L389-24 assume !(1 == ~t2_pc~0); 162635#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 162629#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 162626#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 162625#L936-24 assume !(0 != activate_threads_~tmp___1~0); 162624#L936-26 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 162623#L408-24 assume 1 == ~t3_pc~0; 162620#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 162618#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 162617#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 162616#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 162615#L944-26 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 162614#L427-24 assume !(1 == ~t4_pc~0); 162612#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 162610#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 162608#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 162606#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 162604#L952-26 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 162602#L446-24 assume !(1 == ~t5_pc~0); 162600#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 162597#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 162595#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 162593#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 162591#L960-26 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 162589#L465-24 assume !(1 == ~t6_pc~0); 162586#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 162638#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 162632#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 162557#L968-24 assume !(0 != activate_threads_~tmp___5~0); 162554#L968-26 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 162552#L484-24 assume !(1 == ~t7_pc~0); 162550#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 162548#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 162546#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 162544#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 162542#L976-26 assume 1 == ~M_E~0;~M_E~0 := 2; 162540#L827-3 assume !(1 == ~T1_E~0); 162537#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 162535#L837-3 assume !(1 == ~T3_E~0); 162533#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 162530#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 162528#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 162526#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 162511#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 162505#L867-3 assume !(1 == ~E_2~0); 162499#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 162493#L877-3 assume !(1 == ~E_4~0); 162489#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 162487#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 162485#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 162483#L897-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 162401#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 162390#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 162384#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 162377#L1157 assume !(0 == start_simulation_~tmp~3); 162374#L1157-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 162333#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 162319#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 162313#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 162308#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 162303#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 162296#L1120 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 162290#L1170 assume !(0 != start_simulation_~tmp___0~1); 158265#L1138-1 [2018-11-28 11:38:41,400 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:41,400 INFO L82 PathProgramCache]: Analyzing trace with hash 1382725349, now seen corresponding path program 3 times [2018-11-28 11:38:41,400 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:41,400 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:41,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,401 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:41,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:41,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:41,433 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:41,433 INFO L82 PathProgramCache]: Analyzing trace with hash -659715292, now seen corresponding path program 1 times [2018-11-28 11:38:41,434 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:41,434 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:41,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,434 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:41,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:41,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:41,473 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:41,473 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:41,473 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-28 11:38:41,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:41,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:41,474 INFO L87 Difference]: Start difference. First operand 9420 states and 13089 transitions. cyclomatic complexity: 3685 Second operand 3 states. [2018-11-28 11:38:41,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:41,593 INFO L93 Difference]: Finished difference Result 16586 states and 22735 transitions. [2018-11-28 11:38:41,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:41,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16586 states and 22735 transitions. [2018-11-28 11:38:41,655 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 16408 [2018-11-28 11:38:41,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16586 states to 16586 states and 22735 transitions. [2018-11-28 11:38:41,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16586 [2018-11-28 11:38:41,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16586 [2018-11-28 11:38:41,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16586 states and 22735 transitions. [2018-11-28 11:38:41,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:41,722 INFO L705 BuchiCegarLoop]: Abstraction has 16586 states and 22735 transitions. [2018-11-28 11:38:41,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16586 states and 22735 transitions. [2018-11-28 11:38:41,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16586 to 16158. [2018-11-28 11:38:41,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16158 states. [2018-11-28 11:38:41,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16158 states to 16158 states and 22175 transitions. [2018-11-28 11:38:41,872 INFO L728 BuchiCegarLoop]: Abstraction has 16158 states and 22175 transitions. [2018-11-28 11:38:41,872 INFO L608 BuchiCegarLoop]: Abstraction has 16158 states and 22175 transitions. [2018-11-28 11:38:41,872 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-28 11:38:41,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16158 states and 22175 transitions. [2018-11-28 11:38:41,914 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15980 [2018-11-28 11:38:41,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:41,915 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:41,915 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:41,916 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:41,916 INFO L794 eck$LassoCheckResult]: Stem: 184304#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 184162#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 184163#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 184276#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 183913#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 183914#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 183758#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 183759#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 184103#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 184104#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 183957#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 183958#L546-1 assume !(0 == ~M_E~0); 184452#L744-1 assume !(0 == ~T1_E~0); 184249#L749-1 assume !(0 == ~T2_E~0); 183885#L754-1 assume !(0 == ~T3_E~0); 183886#L759-1 assume !(0 == ~T4_E~0); 183668#L764-1 assume !(0 == ~T5_E~0); 183669#L769-1 assume !(0 == ~T6_E~0); 183811#L774-1 assume !(0 == ~T7_E~0); 183812#L779-1 assume !(0 == ~E_1~0); 184127#L784-1 assume !(0 == ~E_2~0); 184128#L789-1 assume !(0 == ~E_3~0); 183963#L794-1 assume !(0 == ~E_4~0); 183964#L799-1 assume !(0 == ~E_5~0); 184245#L804-1 assume !(0 == ~E_6~0); 183879#L809-1 assume !(0 == ~E_7~0); 183880#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 184209#L351 assume !(1 == ~m_pc~0); 184175#L351-2 is_master_triggered_~__retres1~0 := 0; 184176#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 184206#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 184335#L920 assume !(0 != activate_threads_~tmp~1); 184461#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 184425#L370 assume !(1 == ~t1_pc~0); 184426#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 184420#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 184421#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 184078#L928 assume !(0 != activate_threads_~tmp___0~0); 183802#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 183778#L389 assume !(1 == ~t2_pc~0); 183715#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 183716#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 183774#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 183918#L936 assume !(0 != activate_threads_~tmp___1~0); 184259#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 184038#L408 assume !(1 == ~t3_pc~0); 183925#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 183924#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 183921#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 183922#L944 assume !(0 != activate_threads_~tmp___2~0); 184477#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 184472#L427 assume !(1 == ~t4_pc~0); 184235#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 184236#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 184201#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 183900#L952 assume !(0 != activate_threads_~tmp___3~0); 183901#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 183846#L446 assume !(1 == ~t5_pc~0); 183847#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 183842#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 183843#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 184135#L960 assume !(0 != activate_threads_~tmp___4~0); 184119#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 184105#L465 assume !(1 == ~t6_pc~0); 183764#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 184108#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 184503#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 184357#L968 assume !(0 != activate_threads_~tmp___5~0); 184358#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 184326#L484 assume !(1 == ~t7_pc~0); 184327#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 184332#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 184067#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 184068#L976 assume !(0 != activate_threads_~tmp___6~0); 184362#L976-2 assume !(1 == ~M_E~0); 183984#L827-1 assume !(1 == ~T1_E~0); 183985#L832-1 assume !(1 == ~T2_E~0); 184243#L837-1 assume !(1 == ~T3_E~0); 183874#L842-1 assume !(1 == ~T4_E~0); 183875#L847-1 assume !(1 == ~T5_E~0); 183659#L852-1 assume !(1 == ~T6_E~0); 183660#L857-1 assume !(1 == ~T7_E~0); 183803#L862-1 assume !(1 == ~E_1~0); 183804#L867-1 assume !(1 == ~E_2~0); 184122#L872-1 assume !(1 == ~E_3~0); 184123#L877-1 assume !(1 == ~E_4~0); 183979#L882-1 assume !(1 == ~E_5~0); 183980#L887-1 assume !(1 == ~E_6~0); 184262#L892-1 assume !(1 == ~E_7~0); 184263#L1138-1 assume !false; 193738#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 193736#L719 [2018-11-28 11:38:41,916 INFO L796 eck$LassoCheckResult]: Loop: 193736#L719 assume !false; 193734#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 193732#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 193730#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 193728#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 193727#L616 assume 0 != eval_~tmp~0; 193726#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 193657#L624 assume !(0 != eval_~tmp_ndt_1~0); 193649#L621 assume !(0 == ~t1_st~0); 193639#L635 assume !(0 == ~t2_st~0); 193632#L649 assume !(0 == ~t3_st~0); 193626#L663 assume !(0 == ~t4_st~0); 193621#L677 assume !(0 == ~t5_st~0); 193618#L691 assume !(0 == ~t6_st~0); 193741#L705 assume !(0 == ~t7_st~0); 193736#L719 [2018-11-28 11:38:41,916 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:41,916 INFO L82 PathProgramCache]: Analyzing trace with hash 1654179687, now seen corresponding path program 1 times [2018-11-28 11:38:41,917 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:41,917 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:41,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,917 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:41,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:41,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:41,950 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:41,950 INFO L82 PathProgramCache]: Analyzing trace with hash 1084831058, now seen corresponding path program 1 times [2018-11-28 11:38:41,950 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:41,950 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:41,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,951 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:41,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:41,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:41,957 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:41,957 INFO L82 PathProgramCache]: Analyzing trace with hash -1633159892, now seen corresponding path program 1 times [2018-11-28 11:38:41,957 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:41,957 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:41,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,958 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:41,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:41,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:41,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:41,995 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:41,995 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:42,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:42,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:42,095 INFO L87 Difference]: Start difference. First operand 16158 states and 22175 transitions. cyclomatic complexity: 6041 Second operand 3 states. [2018-11-28 11:38:42,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:42,349 INFO L93 Difference]: Finished difference Result 30831 states and 41968 transitions. [2018-11-28 11:38:42,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:42,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30831 states and 41968 transitions. [2018-11-28 11:38:42,465 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 30480 [2018-11-28 11:38:42,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30831 states to 30831 states and 41968 transitions. [2018-11-28 11:38:42,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30831 [2018-11-28 11:38:42,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30831 [2018-11-28 11:38:42,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30831 states and 41968 transitions. [2018-11-28 11:38:42,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:42,580 INFO L705 BuchiCegarLoop]: Abstraction has 30831 states and 41968 transitions. [2018-11-28 11:38:42,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30831 states and 41968 transitions. [2018-11-28 11:38:42,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30831 to 29343. [2018-11-28 11:38:42,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29343 states. [2018-11-28 11:38:42,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29343 states to 29343 states and 40016 transitions. [2018-11-28 11:38:42,912 INFO L728 BuchiCegarLoop]: Abstraction has 29343 states and 40016 transitions. [2018-11-28 11:38:42,912 INFO L608 BuchiCegarLoop]: Abstraction has 29343 states and 40016 transitions. [2018-11-28 11:38:42,913 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-28 11:38:42,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29343 states and 40016 transitions. [2018-11-28 11:38:43,008 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28992 [2018-11-28 11:38:43,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:43,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:43,010 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:43,010 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:43,010 INFO L794 eck$LassoCheckResult]: Stem: 231315#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 231174#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 231175#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 231287#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 230912#L511-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 230913#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 235499#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 235498#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 235497#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 235496#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 235495#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 235494#L546-1 assume !(0 == ~M_E~0); 235493#L744-1 assume !(0 == ~T1_E~0); 235492#L749-1 assume !(0 == ~T2_E~0); 235491#L754-1 assume !(0 == ~T3_E~0); 235490#L759-1 assume !(0 == ~T4_E~0); 235489#L764-1 assume !(0 == ~T5_E~0); 235488#L769-1 assume !(0 == ~T6_E~0); 235487#L774-1 assume !(0 == ~T7_E~0); 235486#L779-1 assume !(0 == ~E_1~0); 235485#L784-1 assume !(0 == ~E_2~0); 235484#L789-1 assume !(0 == ~E_3~0); 235483#L794-1 assume !(0 == ~E_4~0); 235482#L799-1 assume !(0 == ~E_5~0); 235481#L804-1 assume !(0 == ~E_6~0); 235480#L809-1 assume !(0 == ~E_7~0); 235479#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 235478#L351 assume !(1 == ~m_pc~0); 235477#L351-2 is_master_triggered_~__retres1~0 := 0; 235476#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 235475#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 235474#L920 assume !(0 != activate_threads_~tmp~1); 235473#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 235472#L370 assume !(1 == ~t1_pc~0); 235470#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 235469#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 235468#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 235467#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 230799#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 230772#L389 assume !(1 == ~t2_pc~0); 230710#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 230711#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 230768#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 230920#L936 assume !(0 != activate_threads_~tmp___1~0); 231272#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 231044#L408 assume !(1 == ~t3_pc~0); 230927#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 230926#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 230923#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 230924#L944 assume !(0 != activate_threads_~tmp___2~0); 231477#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 231472#L427 assume !(1 == ~t4_pc~0); 231241#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 231242#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 231211#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 230899#L952 assume !(0 != activate_threads_~tmp___3~0); 230900#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 230844#L446 assume !(1 == ~t5_pc~0); 230845#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 230840#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 230841#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 231150#L960 assume !(0 != activate_threads_~tmp___4~0); 231132#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 231116#L465 assume !(1 == ~t6_pc~0); 230758#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 231119#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 231504#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 231367#L968 assume !(0 != activate_threads_~tmp___5~0); 231368#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 231334#L484 assume !(1 == ~t7_pc~0); 231335#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 231338#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 231075#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 231076#L976 assume !(0 != activate_threads_~tmp___6~0); 231372#L976-2 assume !(1 == ~M_E~0); 230988#L827-1 assume !(1 == ~T1_E~0); 230989#L832-1 assume !(1 == ~T2_E~0); 231251#L837-1 assume !(1 == ~T3_E~0); 230873#L842-1 assume !(1 == ~T4_E~0); 230874#L847-1 assume !(1 == ~T5_E~0); 230655#L852-1 assume !(1 == ~T6_E~0); 230656#L857-1 assume !(1 == ~T7_E~0); 231227#L862-1 assume !(1 == ~E_1~0); 234122#L867-1 assume !(1 == ~E_2~0); 234120#L872-1 assume !(1 == ~E_3~0); 234118#L877-1 assume !(1 == ~E_4~0); 234116#L882-1 assume !(1 == ~E_5~0); 234113#L887-1 assume !(1 == ~E_6~0); 234111#L892-1 assume !(1 == ~E_7~0); 234109#L1138-1 assume !false; 233998#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 233994#L719 [2018-11-28 11:38:43,011 INFO L796 eck$LassoCheckResult]: Loop: 233994#L719 assume !false; 233992#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 233989#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 233987#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 233984#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 233982#L616 assume 0 != eval_~tmp~0; 233979#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 233976#L624 assume !(0 != eval_~tmp_ndt_1~0); 233974#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 233961#L638 assume !(0 != eval_~tmp_ndt_2~0); 233972#L635 assume !(0 == ~t2_st~0); 234017#L649 assume !(0 == ~t3_st~0); 234013#L663 assume !(0 == ~t4_st~0); 234010#L677 assume !(0 == ~t5_st~0); 234003#L691 assume !(0 == ~t6_st~0); 234001#L705 assume !(0 == ~t7_st~0); 233994#L719 [2018-11-28 11:38:43,116 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:43,116 INFO L82 PathProgramCache]: Analyzing trace with hash 191884459, now seen corresponding path program 1 times [2018-11-28 11:38:43,116 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:43,116 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:43,117 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:43,117 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:43,117 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:43,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:43,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:43,138 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:43,138 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:43,138 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-28 11:38:43,138 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:43,138 INFO L82 PathProgramCache]: Analyzing trace with hash 2102285721, now seen corresponding path program 1 times [2018-11-28 11:38:43,138 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:43,139 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:43,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:43,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:43,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:43,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:43,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:43,292 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2018-11-28 11:38:43,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:43,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:43,341 INFO L87 Difference]: Start difference. First operand 29343 states and 40016 transitions. cyclomatic complexity: 10697 Second operand 3 states. [2018-11-28 11:38:43,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:43,422 INFO L93 Difference]: Finished difference Result 29250 states and 39886 transitions. [2018-11-28 11:38:43,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:43,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29250 states and 39886 transitions. [2018-11-28 11:38:43,541 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28992 [2018-11-28 11:38:43,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29250 states to 29250 states and 39886 transitions. [2018-11-28 11:38:43,611 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29250 [2018-11-28 11:38:43,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29250 [2018-11-28 11:38:43,629 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29250 states and 39886 transitions. [2018-11-28 11:38:43,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:43,648 INFO L705 BuchiCegarLoop]: Abstraction has 29250 states and 39886 transitions. [2018-11-28 11:38:43,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29250 states and 39886 transitions. [2018-11-28 11:38:43,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29250 to 29250. [2018-11-28 11:38:43,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29250 states. [2018-11-28 11:38:43,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29250 states to 29250 states and 39886 transitions. [2018-11-28 11:38:43,927 INFO L728 BuchiCegarLoop]: Abstraction has 29250 states and 39886 transitions. [2018-11-28 11:38:43,927 INFO L608 BuchiCegarLoop]: Abstraction has 29250 states and 39886 transitions. [2018-11-28 11:38:43,927 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-28 11:38:43,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29250 states and 39886 transitions. [2018-11-28 11:38:44,011 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28992 [2018-11-28 11:38:44,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:44,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:44,012 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:44,013 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:44,013 INFO L794 eck$LassoCheckResult]: Stem: 289918#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 289781#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 289782#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 289893#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 289516#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 289517#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 289353#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 289354#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 289717#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 289718#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 289559#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 289560#L546-1 assume !(0 == ~M_E~0); 290069#L744-1 assume !(0 == ~T1_E~0); 289869#L749-1 assume !(0 == ~T2_E~0); 289485#L754-1 assume !(0 == ~T3_E~0); 289486#L759-1 assume !(0 == ~T4_E~0); 289262#L764-1 assume !(0 == ~T5_E~0); 289263#L769-1 assume !(0 == ~T6_E~0); 289409#L774-1 assume !(0 == ~T7_E~0); 289410#L779-1 assume !(0 == ~E_1~0); 289743#L784-1 assume !(0 == ~E_2~0); 289744#L789-1 assume !(0 == ~E_3~0); 289566#L794-1 assume !(0 == ~E_4~0); 289567#L799-1 assume !(0 == ~E_5~0); 289864#L804-1 assume !(0 == ~E_6~0); 289479#L809-1 assume !(0 == ~E_7~0); 289480#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 289826#L351 assume !(1 == ~m_pc~0); 289793#L351-2 is_master_triggered_~__retres1~0 := 0; 289794#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 289825#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 289949#L920 assume !(0 != activate_threads_~tmp~1); 290077#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 290043#L370 assume !(1 == ~t1_pc~0); 290044#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 290041#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 290042#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 289687#L928 assume !(0 != activate_threads_~tmp___0~0); 289400#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 289374#L389 assume !(1 == ~t2_pc~0); 289310#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 289311#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 289373#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 289518#L936 assume !(0 != activate_threads_~tmp___1~0); 289876#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 289642#L408 assume !(1 == ~t3_pc~0); 289525#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 289524#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 289521#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 289522#L944 assume !(0 != activate_threads_~tmp___2~0); 290094#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 290089#L427 assume !(1 == ~t4_pc~0); 289846#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 289847#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 289817#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 289500#L952 assume !(0 != activate_threads_~tmp___3~0); 289501#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 289444#L446 assume !(1 == ~t5_pc~0); 289445#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 289442#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 289443#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 289753#L960 assume !(0 != activate_threads_~tmp___4~0); 289734#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 289721#L465 assume !(1 == ~t6_pc~0); 289359#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 289722#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 290123#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 289978#L968 assume !(0 != activate_threads_~tmp___5~0); 289979#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 289941#L484 assume !(1 == ~t7_pc~0); 289942#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 289944#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 289672#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 289673#L976 assume !(0 != activate_threads_~tmp___6~0); 289983#L976-2 assume !(1 == ~M_E~0); 289587#L827-1 assume !(1 == ~T1_E~0); 289588#L832-1 assume !(1 == ~T2_E~0); 289860#L837-1 assume !(1 == ~T3_E~0); 289473#L842-1 assume !(1 == ~T4_E~0); 289474#L847-1 assume !(1 == ~T5_E~0); 289257#L852-1 assume !(1 == ~T6_E~0); 289258#L857-1 assume !(1 == ~T7_E~0); 289404#L862-1 assume !(1 == ~E_1~0); 289405#L867-1 assume !(1 == ~E_2~0); 289737#L872-1 assume !(1 == ~E_3~0); 289738#L877-1 assume !(1 == ~E_4~0); 289583#L882-1 assume !(1 == ~E_5~0); 289584#L887-1 assume !(1 == ~E_6~0); 289879#L892-1 assume !(1 == ~E_7~0); 289880#L1138-1 assume !false; 292841#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 292838#L719 [2018-11-28 11:38:44,013 INFO L796 eck$LassoCheckResult]: Loop: 292838#L719 assume !false; 292836#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 292833#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 292831#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 292829#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 292827#L616 assume 0 != eval_~tmp~0; 292824#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 292820#L624 assume !(0 != eval_~tmp_ndt_1~0); 292818#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 292805#L638 assume !(0 != eval_~tmp_ndt_2~0); 292816#L635 assume !(0 == ~t2_st~0); 292873#L649 assume !(0 == ~t3_st~0); 292868#L663 assume !(0 == ~t4_st~0); 292864#L677 assume !(0 == ~t5_st~0); 292846#L691 assume !(0 == ~t6_st~0); 292844#L705 assume !(0 == ~t7_st~0); 292838#L719 [2018-11-28 11:38:44,013 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:44,013 INFO L82 PathProgramCache]: Analyzing trace with hash 1654179687, now seen corresponding path program 2 times [2018-11-28 11:38:44,013 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:44,014 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:44,014 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:44,014 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:44,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:44,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:44,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:44,048 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:44,048 INFO L82 PathProgramCache]: Analyzing trace with hash 2102285721, now seen corresponding path program 2 times [2018-11-28 11:38:44,048 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:44,048 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:44,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:44,049 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:44,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:44,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:44,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:44,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:44,055 INFO L82 PathProgramCache]: Analyzing trace with hash -551055105, now seen corresponding path program 1 times [2018-11-28 11:38:44,055 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:44,055 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:44,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:44,056 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:44,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:44,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:44,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:44,106 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:44,106 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:44,209 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2018-11-28 11:38:44,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:44,263 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:44,263 INFO L87 Difference]: Start difference. First operand 29250 states and 39886 transitions. cyclomatic complexity: 10660 Second operand 3 states. [2018-11-28 11:38:44,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:44,470 INFO L93 Difference]: Finished difference Result 55610 states and 75502 transitions. [2018-11-28 11:38:44,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:44,472 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55610 states and 75502 transitions. [2018-11-28 11:38:44,671 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 55192 [2018-11-28 11:38:44,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55610 states to 55610 states and 75502 transitions. [2018-11-28 11:38:44,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55610 [2018-11-28 11:38:44,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55610 [2018-11-28 11:38:44,841 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55610 states and 75502 transitions. [2018-11-28 11:38:44,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:44,885 INFO L705 BuchiCegarLoop]: Abstraction has 55610 states and 75502 transitions. [2018-11-28 11:38:44,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55610 states and 75502 transitions. [2018-11-28 11:38:45,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55610 to 53082. [2018-11-28 11:38:45,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53082 states. [2018-11-28 11:38:45,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53082 states to 53082 states and 72238 transitions. [2018-11-28 11:38:45,456 INFO L728 BuchiCegarLoop]: Abstraction has 53082 states and 72238 transitions. [2018-11-28 11:38:45,456 INFO L608 BuchiCegarLoop]: Abstraction has 53082 states and 72238 transitions. [2018-11-28 11:38:45,456 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-28 11:38:45,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53082 states and 72238 transitions. [2018-11-28 11:38:45,561 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 52664 [2018-11-28 11:38:45,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:45,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:45,562 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:45,562 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:45,562 INFO L794 eck$LassoCheckResult]: Stem: 374801#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 374662#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 374663#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 374776#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 374385#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 374386#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 374225#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 374226#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 374596#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 374597#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 374432#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 374433#L546-1 assume !(0 == ~M_E~0); 374972#L744-1 assume !(0 == ~T1_E~0); 374756#L749-1 assume !(0 == ~T2_E~0); 374355#L754-1 assume !(0 == ~T3_E~0); 374356#L759-1 assume !(0 == ~T4_E~0); 374130#L764-1 assume !(0 == ~T5_E~0); 374131#L769-1 assume !(0 == ~T6_E~0); 374283#L774-1 assume !(0 == ~T7_E~0); 374284#L779-1 assume !(0 == ~E_1~0); 374622#L784-1 assume !(0 == ~E_2~0); 374623#L789-1 assume !(0 == ~E_3~0); 374440#L794-1 assume !(0 == ~E_4~0); 374441#L799-1 assume !(0 == ~E_5~0); 374752#L804-1 assume !(0 == ~E_6~0); 374349#L809-1 assume !(0 == ~E_7~0); 374350#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 374710#L351 assume !(1 == ~m_pc~0); 374675#L351-2 is_master_triggered_~__retres1~0 := 0; 374676#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 374707#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 374835#L920 assume !(0 != activate_threads_~tmp~1); 374988#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 374939#L370 assume !(1 == ~t1_pc~0); 374940#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 374934#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 374935#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 374565#L928 assume !(0 != activate_threads_~tmp___0~0); 374273#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 374245#L389 assume !(1 == ~t2_pc~0); 374181#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 374182#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 374241#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 374391#L936 assume !(0 != activate_threads_~tmp___1~0); 374762#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 374521#L408 assume !(1 == ~t3_pc~0); 374398#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 374397#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 374394#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 374395#L944 assume !(0 != activate_threads_~tmp___2~0); 375009#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 375000#L427 assume !(1 == ~t4_pc~0); 374738#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 374739#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 374702#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 374370#L952 assume !(0 != activate_threads_~tmp___3~0); 374371#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 374317#L446 assume !(1 == ~t5_pc~0); 374318#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 374313#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 374314#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 374631#L960 assume !(0 != activate_threads_~tmp___4~0); 374614#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 374599#L465 assume !(1 == ~t6_pc~0); 374231#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 374602#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 375052#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 374861#L968 assume !(0 != activate_threads_~tmp___5~0); 374862#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 374827#L484 assume !(1 == ~t7_pc~0); 374828#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 374830#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 374552#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 374553#L976 assume !(0 != activate_threads_~tmp___6~0); 374868#L976-2 assume !(1 == ~M_E~0); 374460#L827-1 assume !(1 == ~T1_E~0); 374461#L832-1 assume !(1 == ~T2_E~0); 374750#L837-1 assume !(1 == ~T3_E~0); 374344#L842-1 assume !(1 == ~T4_E~0); 374345#L847-1 assume !(1 == ~T5_E~0); 374122#L852-1 assume !(1 == ~T6_E~0); 374123#L857-1 assume !(1 == ~T7_E~0); 374274#L862-1 assume !(1 == ~E_1~0); 374275#L867-1 assume !(1 == ~E_2~0); 374617#L872-1 assume !(1 == ~E_3~0); 374618#L877-1 assume !(1 == ~E_4~0); 374456#L882-1 assume !(1 == ~E_5~0); 374457#L887-1 assume !(1 == ~E_6~0); 374764#L892-1 assume !(1 == ~E_7~0); 374765#L1138-1 assume !false; 376960#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 376952#L719 [2018-11-28 11:38:45,562 INFO L796 eck$LassoCheckResult]: Loop: 376952#L719 assume !false; 376945#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 376937#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 376931#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 376927#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 376924#L616 assume 0 != eval_~tmp~0; 376919#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 376915#L624 assume !(0 != eval_~tmp_ndt_1~0); 376912#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 376898#L638 assume !(0 != eval_~tmp_ndt_2~0); 376909#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 376762#L652 assume !(0 != eval_~tmp_ndt_3~0); 376998#L649 assume !(0 == ~t3_st~0); 376987#L663 assume !(0 == ~t4_st~0); 376978#L677 assume !(0 == ~t5_st~0); 376969#L691 assume !(0 == ~t6_st~0); 376963#L705 assume !(0 == ~t7_st~0); 376952#L719 [2018-11-28 11:38:45,562 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:45,563 INFO L82 PathProgramCache]: Analyzing trace with hash 1654179687, now seen corresponding path program 3 times [2018-11-28 11:38:45,563 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:45,563 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:45,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:45,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:45,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:45,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:45,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:45,595 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:45,595 INFO L82 PathProgramCache]: Analyzing trace with hash -270659681, now seen corresponding path program 1 times [2018-11-28 11:38:45,596 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:45,596 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:45,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:45,596 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:45,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:45,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:45,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:45,602 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:45,602 INFO L82 PathProgramCache]: Analyzing trace with hash -919846663, now seen corresponding path program 1 times [2018-11-28 11:38:45,602 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:45,602 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:45,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:45,603 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:45,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:45,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:45,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:45,643 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:45,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:45,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:45,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:45,724 INFO L87 Difference]: Start difference. First operand 53082 states and 72238 transitions. cyclomatic complexity: 19180 Second operand 3 states. [2018-11-28 11:38:45,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:45,983 INFO L93 Difference]: Finished difference Result 100154 states and 135790 transitions. [2018-11-28 11:38:45,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:45,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100154 states and 135790 transitions. [2018-11-28 11:38:46,265 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 99416 [2018-11-28 11:38:46,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100154 states to 100154 states and 135790 transitions. [2018-11-28 11:38:46,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100154 [2018-11-28 11:38:46,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100154 [2018-11-28 11:38:46,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100154 states and 135790 transitions. [2018-11-28 11:38:46,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:46,509 INFO L705 BuchiCegarLoop]: Abstraction has 100154 states and 135790 transitions. [2018-11-28 11:38:46,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100154 states and 135790 transitions. [2018-11-28 11:38:47,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100154 to 95994. [2018-11-28 11:38:47,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95994 states. [2018-11-28 11:38:47,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95994 states to 95994 states and 130478 transitions. [2018-11-28 11:38:47,493 INFO L728 BuchiCegarLoop]: Abstraction has 95994 states and 130478 transitions. [2018-11-28 11:38:47,493 INFO L608 BuchiCegarLoop]: Abstraction has 95994 states and 130478 transitions. [2018-11-28 11:38:47,493 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-28 11:38:47,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95994 states and 130478 transitions. [2018-11-28 11:38:47,673 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 95256 [2018-11-28 11:38:47,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:47,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:47,673 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:47,673 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:47,674 INFO L794 eck$LassoCheckResult]: Stem: 528065#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 527912#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 527913#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 528041#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 527634#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 527635#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 527469#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 527470#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 527846#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 527847#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 527679#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 527680#L546-1 assume !(0 == ~M_E~0); 528233#L744-1 assume !(0 == ~T1_E~0); 528019#L749-1 assume !(0 == ~T2_E~0); 527605#L754-1 assume !(0 == ~T3_E~0); 527606#L759-1 assume !(0 == ~T4_E~0); 527374#L764-1 assume !(0 == ~T5_E~0); 527375#L769-1 assume !(0 == ~T6_E~0); 527529#L774-1 assume !(0 == ~T7_E~0); 527530#L779-1 assume !(0 == ~E_1~0); 527874#L784-1 assume !(0 == ~E_2~0); 527875#L789-1 assume !(0 == ~E_3~0); 527686#L794-1 assume !(0 == ~E_4~0); 527687#L799-1 assume !(0 == ~E_5~0); 528015#L804-1 assume !(0 == ~E_6~0); 527599#L809-1 assume !(0 == ~E_7~0); 527600#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 527962#L351 assume !(1 == ~m_pc~0); 527926#L351-2 is_master_triggered_~__retres1~0 := 0; 527927#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 527959#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 528102#L920 assume !(0 != activate_threads_~tmp~1); 528245#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 528203#L370 assume !(1 == ~t1_pc~0); 528204#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 528200#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 528201#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 527812#L928 assume !(0 != activate_threads_~tmp___0~0); 527519#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 527492#L389 assume !(1 == ~t2_pc~0); 527423#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 527424#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 527488#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 527638#L936 assume !(0 != activate_threads_~tmp___1~0); 528029#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 527766#L408 assume !(1 == ~t3_pc~0); 527645#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 527644#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 527641#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 527642#L944 assume !(0 != activate_threads_~tmp___2~0); 528269#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 528261#L427 assume !(1 == ~t4_pc~0); 527995#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 527996#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 527954#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 527620#L952 assume !(0 != activate_threads_~tmp___3~0); 527621#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 527565#L446 assume !(1 == ~t5_pc~0); 527566#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 527561#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 527562#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 527884#L960 assume !(0 != activate_threads_~tmp___4~0); 527866#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 527848#L465 assume !(1 == ~t6_pc~0); 527475#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 527852#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 528306#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 528135#L968 assume !(0 != activate_threads_~tmp___5~0); 528136#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 528089#L484 assume !(1 == ~t7_pc~0); 528090#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 528098#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 527799#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 527800#L976 assume !(0 != activate_threads_~tmp___6~0); 528140#L976-2 assume !(1 == ~M_E~0); 527706#L827-1 assume !(1 == ~T1_E~0); 527707#L832-1 assume !(1 == ~T2_E~0); 528012#L837-1 assume !(1 == ~T3_E~0); 527594#L842-1 assume !(1 == ~T4_E~0); 527595#L847-1 assume !(1 == ~T5_E~0); 527366#L852-1 assume !(1 == ~T6_E~0); 527367#L857-1 assume !(1 == ~T7_E~0); 527520#L862-1 assume !(1 == ~E_1~0); 527521#L867-1 assume !(1 == ~E_2~0); 527869#L872-1 assume !(1 == ~E_3~0); 527870#L877-1 assume !(1 == ~E_4~0); 527702#L882-1 assume !(1 == ~E_5~0); 527703#L887-1 assume !(1 == ~E_6~0); 528031#L892-1 assume !(1 == ~E_7~0); 528032#L1138-1 assume !false; 535959#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 535956#L719 [2018-11-28 11:38:47,674 INFO L796 eck$LassoCheckResult]: Loop: 535956#L719 assume !false; 535953#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 535950#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 535949#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 535947#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 535945#L616 assume 0 != eval_~tmp~0; 535943#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 535941#L624 assume !(0 != eval_~tmp_ndt_1~0); 535396#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 535393#L638 assume !(0 != eval_~tmp_ndt_2~0); 535391#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 535361#L652 assume !(0 != eval_~tmp_ndt_3~0); 535389#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 532041#L666 assume !(0 != eval_~tmp_ndt_4~0); 535658#L663 assume !(0 == ~t4_st~0); 535653#L677 assume !(0 == ~t5_st~0); 535627#L691 assume !(0 == ~t6_st~0); 535628#L705 assume !(0 == ~t7_st~0); 535956#L719 [2018-11-28 11:38:47,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:47,674 INFO L82 PathProgramCache]: Analyzing trace with hash 1654179687, now seen corresponding path program 4 times [2018-11-28 11:38:47,674 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:47,675 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:47,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:47,675 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:47,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:47,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:47,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:47,707 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:47,707 INFO L82 PathProgramCache]: Analyzing trace with hash -2050071732, now seen corresponding path program 1 times [2018-11-28 11:38:47,707 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:47,707 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:47,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:47,708 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:47,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:47,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:47,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:47,713 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:47,713 INFO L82 PathProgramCache]: Analyzing trace with hash -700031694, now seen corresponding path program 1 times [2018-11-28 11:38:47,713 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:47,713 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:47,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:47,714 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:47,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:47,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:47,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:47,744 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:47,744 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:47,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:47,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:47,837 INFO L87 Difference]: Start difference. First operand 95994 states and 130478 transitions. cyclomatic complexity: 34508 Second operand 3 states. [2018-11-28 11:38:48,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:48,139 INFO L93 Difference]: Finished difference Result 127806 states and 172954 transitions. [2018-11-28 11:38:48,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:48,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127806 states and 172954 transitions. [2018-11-28 11:38:48,485 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 126876 [2018-11-28 11:38:48,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127806 states to 127806 states and 172954 transitions. [2018-11-28 11:38:48,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127806 [2018-11-28 11:38:48,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127806 [2018-11-28 11:38:48,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127806 states and 172954 transitions. [2018-11-28 11:38:48,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:48,798 INFO L705 BuchiCegarLoop]: Abstraction has 127806 states and 172954 transitions. [2018-11-28 11:38:48,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127806 states and 172954 transitions. [2018-11-28 11:38:51,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127806 to 124478. [2018-11-28 11:38:51,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124478 states. [2018-11-28 11:38:51,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124478 states to 124478 states and 168730 transitions. [2018-11-28 11:38:51,742 INFO L728 BuchiCegarLoop]: Abstraction has 124478 states and 168730 transitions. [2018-11-28 11:38:51,742 INFO L608 BuchiCegarLoop]: Abstraction has 124478 states and 168730 transitions. [2018-11-28 11:38:51,742 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-28 11:38:51,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124478 states and 168730 transitions. [2018-11-28 11:38:51,995 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 123548 [2018-11-28 11:38:51,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:51,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:51,996 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:51,996 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:51,996 INFO L794 eck$LassoCheckResult]: Stem: 751878#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 751718#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 751719#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 751848#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 751441#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 751442#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 751274#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 751275#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 751655#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 751656#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 751488#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 751489#L546-1 assume !(0 == ~M_E~0); 752036#L744-1 assume !(0 == ~T1_E~0); 751818#L749-1 assume !(0 == ~T2_E~0); 751412#L754-1 assume !(0 == ~T3_E~0); 751413#L759-1 assume !(0 == ~T4_E~0); 751182#L764-1 assume !(0 == ~T5_E~0); 751183#L769-1 assume !(0 == ~T6_E~0); 751331#L774-1 assume !(0 == ~T7_E~0); 751332#L779-1 assume !(0 == ~E_1~0); 751683#L784-1 assume !(0 == ~E_2~0); 751684#L789-1 assume !(0 == ~E_3~0); 751495#L794-1 assume !(0 == ~E_4~0); 751496#L799-1 assume !(0 == ~E_5~0); 751814#L804-1 assume !(0 == ~E_6~0); 751406#L809-1 assume !(0 == ~E_7~0); 751407#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 751768#L351 assume !(1 == ~m_pc~0); 751731#L351-2 is_master_triggered_~__retres1~0 := 0; 751732#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 751765#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 751910#L920 assume !(0 != activate_threads_~tmp~1); 752050#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 752006#L370 assume !(1 == ~t1_pc~0); 752007#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 752003#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 752004#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 751623#L928 assume !(0 != activate_threads_~tmp___0~0); 751322#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 751296#L389 assume !(1 == ~t2_pc~0); 751232#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 751233#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 751292#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 751447#L936 assume !(0 != activate_threads_~tmp___1~0); 751829#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 751578#L408 assume !(1 == ~t3_pc~0); 751454#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 751453#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 751450#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 751451#L944 assume !(0 != activate_threads_~tmp___2~0); 752074#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 752063#L427 assume !(1 == ~t4_pc~0); 751799#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 751800#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 751760#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 751427#L952 assume !(0 != activate_threads_~tmp___3~0); 751428#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 751370#L446 assume !(1 == ~t5_pc~0); 751371#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 751366#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 751367#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 751691#L960 assume !(0 != activate_threads_~tmp___4~0); 751675#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 751657#L465 assume !(1 == ~t6_pc~0); 751280#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 751662#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 752105#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 751941#L968 assume !(0 != activate_threads_~tmp___5~0); 751942#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 751902#L484 assume !(1 == ~t7_pc~0); 751903#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 751907#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 751610#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 751611#L976 assume !(0 != activate_threads_~tmp___6~0); 751947#L976-2 assume !(1 == ~M_E~0); 751516#L827-1 assume !(1 == ~T1_E~0); 751517#L832-1 assume !(1 == ~T2_E~0); 751812#L837-1 assume !(1 == ~T3_E~0); 751401#L842-1 assume !(1 == ~T4_E~0); 751402#L847-1 assume !(1 == ~T5_E~0); 751174#L852-1 assume !(1 == ~T6_E~0); 751175#L857-1 assume !(1 == ~T7_E~0); 751323#L862-1 assume !(1 == ~E_1~0); 751324#L867-1 assume !(1 == ~E_2~0); 751678#L872-1 assume !(1 == ~E_3~0); 751679#L877-1 assume !(1 == ~E_4~0); 751512#L882-1 assume !(1 == ~E_5~0); 751513#L887-1 assume !(1 == ~E_6~0); 751832#L892-1 assume !(1 == ~E_7~0); 751833#L1138-1 assume !false; 788182#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 779245#L719 [2018-11-28 11:38:51,996 INFO L796 eck$LassoCheckResult]: Loop: 779245#L719 assume !false; 788170#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 788162#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 788154#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 788146#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 788139#L616 assume 0 != eval_~tmp~0; 788129#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 788120#L624 assume !(0 != eval_~tmp_ndt_1~0); 788112#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 788085#L638 assume !(0 != eval_~tmp_ndt_2~0); 767062#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 767059#L652 assume !(0 != eval_~tmp_ndt_3~0); 767057#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 767028#L666 assume !(0 != eval_~tmp_ndt_4~0); 770045#L663 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 779575#L680 assume !(0 != eval_~tmp_ndt_5~0); 779574#L677 assume !(0 == ~t5_st~0); 779249#L691 assume !(0 == ~t6_st~0); 779247#L705 assume !(0 == ~t7_st~0); 779245#L719 [2018-11-28 11:38:51,997 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:51,997 INFO L82 PathProgramCache]: Analyzing trace with hash 1654179687, now seen corresponding path program 5 times [2018-11-28 11:38:51,997 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:51,997 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:51,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:51,998 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:51,998 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:52,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:52,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:52,030 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:52,030 INFO L82 PathProgramCache]: Analyzing trace with hash 661179884, now seen corresponding path program 1 times [2018-11-28 11:38:52,030 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:52,030 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:52,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:52,031 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:52,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:52,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:52,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:52,036 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:52,036 INFO L82 PathProgramCache]: Analyzing trace with hash -437251898, now seen corresponding path program 1 times [2018-11-28 11:38:52,036 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:52,036 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:52,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:52,037 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:52,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:52,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:52,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:52,083 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:52,083 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:52,223 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 48 [2018-11-28 11:38:52,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:52,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:52,276 INFO L87 Difference]: Start difference. First operand 124478 states and 168730 transitions. cyclomatic complexity: 44276 Second operand 3 states. [2018-11-28 11:38:52,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:52,655 INFO L93 Difference]: Finished difference Result 169648 states and 229368 transitions. [2018-11-28 11:38:52,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:52,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 169648 states and 229368 transitions. [2018-11-28 11:38:53,131 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 168494 [2018-11-28 11:38:53,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 169648 states to 169648 states and 229368 transitions. [2018-11-28 11:38:53,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 169648 [2018-11-28 11:38:53,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 169648 [2018-11-28 11:38:53,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 169648 states and 229368 transitions. [2018-11-28 11:38:53,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:53,937 INFO L705 BuchiCegarLoop]: Abstraction has 169648 states and 229368 transitions. [2018-11-28 11:38:53,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169648 states and 229368 transitions. [2018-11-28 11:38:54,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169648 to 165904. [2018-11-28 11:38:54,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165904 states. [2018-11-28 11:38:54,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165904 states to 165904 states and 224664 transitions. [2018-11-28 11:38:54,986 INFO L728 BuchiCegarLoop]: Abstraction has 165904 states and 224664 transitions. [2018-11-28 11:38:54,986 INFO L608 BuchiCegarLoop]: Abstraction has 165904 states and 224664 transitions. [2018-11-28 11:38:54,986 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-28 11:38:54,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 165904 states and 224664 transitions. [2018-11-28 11:38:55,326 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 164750 [2018-11-28 11:38:55,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:38:55,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:38:55,327 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:55,327 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:38:55,327 INFO L794 eck$LassoCheckResult]: Stem: 1046010#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1045851#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1045852#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1045984#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 1045570#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1045571#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1045409#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1045410#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1045784#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1045785#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1045618#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1045619#L546-1 assume !(0 == ~M_E~0); 1046177#L744-1 assume !(0 == ~T1_E~0); 1045955#L749-1 assume !(0 == ~T2_E~0); 1045541#L754-1 assume !(0 == ~T3_E~0); 1045542#L759-1 assume !(0 == ~T4_E~0); 1045317#L764-1 assume !(0 == ~T5_E~0); 1045318#L769-1 assume !(0 == ~T6_E~0); 1045464#L774-1 assume !(0 == ~T7_E~0); 1045465#L779-1 assume !(0 == ~E_1~0); 1045813#L784-1 assume !(0 == ~E_2~0); 1045814#L789-1 assume !(0 == ~E_3~0); 1045625#L794-1 assume !(0 == ~E_4~0); 1045626#L799-1 assume !(0 == ~E_5~0); 1045950#L804-1 assume !(0 == ~E_6~0); 1045535#L809-1 assume !(0 == ~E_7~0); 1045536#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1045900#L351 assume !(1 == ~m_pc~0); 1045864#L351-2 is_master_triggered_~__retres1~0 := 0; 1045865#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1045897#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1046039#L920 assume !(0 != activate_threads_~tmp~1); 1046194#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1046145#L370 assume !(1 == ~t1_pc~0); 1046146#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 1046140#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1046141#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1045747#L928 assume !(0 != activate_threads_~tmp___0~0); 1045455#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1045430#L389 assume !(1 == ~t2_pc~0); 1045366#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 1045367#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1045426#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1045577#L936 assume !(0 != activate_threads_~tmp___1~0); 1045970#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1045704#L408 assume !(1 == ~t3_pc~0); 1045584#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 1045583#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1045580#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1045581#L944 assume !(0 != activate_threads_~tmp___2~0); 1046221#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1046210#L427 assume !(1 == ~t4_pc~0); 1045935#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 1045936#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1045891#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1045556#L952 assume !(0 != activate_threads_~tmp___3~0); 1045557#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1045501#L446 assume !(1 == ~t5_pc~0); 1045502#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 1045497#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1045498#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1045824#L960 assume !(0 != activate_threads_~tmp___4~0); 1045803#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1045786#L465 assume !(1 == ~t6_pc~0); 1045415#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 1045789#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1046255#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1046068#L968 assume !(0 != activate_threads_~tmp___5~0); 1046069#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1046031#L484 assume !(1 == ~t7_pc~0); 1046032#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 1046035#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1045734#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1045735#L976 assume !(0 != activate_threads_~tmp___6~0); 1046076#L976-2 assume !(1 == ~M_E~0); 1045645#L827-1 assume !(1 == ~T1_E~0); 1045646#L832-1 assume !(1 == ~T2_E~0); 1045947#L837-1 assume !(1 == ~T3_E~0); 1045530#L842-1 assume !(1 == ~T4_E~0); 1045531#L847-1 assume !(1 == ~T5_E~0); 1045308#L852-1 assume !(1 == ~T6_E~0); 1045309#L857-1 assume !(1 == ~T7_E~0); 1045456#L862-1 assume !(1 == ~E_1~0); 1045457#L867-1 assume !(1 == ~E_2~0); 1045806#L872-1 assume !(1 == ~E_3~0); 1045807#L877-1 assume !(1 == ~E_4~0); 1045641#L882-1 assume !(1 == ~E_5~0); 1045642#L887-1 assume !(1 == ~E_6~0); 1045973#L892-1 assume !(1 == ~E_7~0); 1045974#L1138-1 assume !false; 1066665#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1066663#L719 [2018-11-28 11:38:55,327 INFO L796 eck$LassoCheckResult]: Loop: 1066663#L719 assume !false; 1066660#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1066657#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1066653#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1066651#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1066649#L616 assume 0 != eval_~tmp~0; 1066646#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1066642#L624 assume !(0 != eval_~tmp_ndt_1~0); 1066640#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1060456#L638 assume !(0 != eval_~tmp_ndt_2~0); 1057952#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1057950#L652 assume !(0 != eval_~tmp_ndt_3~0); 1057939#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1057900#L666 assume !(0 != eval_~tmp_ndt_4~0); 1057933#L663 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1060529#L680 assume !(0 != eval_~tmp_ndt_5~0); 1060530#L677 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1066791#L694 assume !(0 != eval_~tmp_ndt_6~0); 1066670#L691 assume !(0 == ~t6_st~0); 1066668#L705 assume !(0 == ~t7_st~0); 1066663#L719 [2018-11-28 11:38:55,327 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:55,328 INFO L82 PathProgramCache]: Analyzing trace with hash 1654179687, now seen corresponding path program 6 times [2018-11-28 11:38:55,328 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:55,328 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:55,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:55,329 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:55,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:55,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:55,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:55,356 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:55,356 INFO L82 PathProgramCache]: Analyzing trace with hash -985062145, now seen corresponding path program 1 times [2018-11-28 11:38:55,356 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:55,357 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:55,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:55,357 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:38:55,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:55,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:55,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:38:55,362 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:38:55,362 INFO L82 PathProgramCache]: Analyzing trace with hash -676709019, now seen corresponding path program 1 times [2018-11-28 11:38:55,362 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:38:55,362 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:38:55,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:55,363 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:38:55,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:38:55,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:38:55,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:38:55,392 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:38:55,392 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-28 11:38:55,499 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:38:55,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:38:55,499 INFO L87 Difference]: Start difference. First operand 165904 states and 224664 transitions. cyclomatic complexity: 58784 Second operand 3 states. [2018-11-28 11:38:56,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:38:56,660 INFO L93 Difference]: Finished difference Result 296492 states and 401016 transitions. [2018-11-28 11:38:56,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:38:56,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 296492 states and 401016 transitions. [2018-11-28 11:38:57,493 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 294282 [2018-11-28 11:38:57,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 296492 states to 296492 states and 401016 transitions. [2018-11-28 11:38:57,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 296492 [2018-11-28 11:38:58,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 296492 [2018-11-28 11:38:58,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 296492 states and 401016 transitions. [2018-11-28 11:38:58,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:38:58,230 INFO L705 BuchiCegarLoop]: Abstraction has 296492 states and 401016 transitions. [2018-11-28 11:38:58,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 296492 states and 401016 transitions. [2018-11-28 11:39:03,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 296492 to 291020. [2018-11-28 11:39:03,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291020 states. [2018-11-28 11:39:03,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291020 states to 291020 states and 394392 transitions. [2018-11-28 11:39:03,884 INFO L728 BuchiCegarLoop]: Abstraction has 291020 states and 394392 transitions. [2018-11-28 11:39:03,884 INFO L608 BuchiCegarLoop]: Abstraction has 291020 states and 394392 transitions. [2018-11-28 11:39:03,885 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-28 11:39:03,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291020 states and 394392 transitions. [2018-11-28 11:39:04,518 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 288810 [2018-11-28 11:39:04,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:39:04,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:39:04,519 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:39:04,519 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:39:04,519 INFO L794 eck$LassoCheckResult]: Stem: 1508437#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1508274#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1508275#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1508409#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 1507988#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1507989#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1507814#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1507815#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1508202#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1508203#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1508035#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1508036#L546-1 assume !(0 == ~M_E~0); 1508606#L744-1 assume !(0 == ~T1_E~0); 1508381#L749-1 assume !(0 == ~T2_E~0); 1507957#L754-1 assume !(0 == ~T3_E~0); 1507958#L759-1 assume !(0 == ~T4_E~0); 1507721#L764-1 assume !(0 == ~T5_E~0); 1507722#L769-1 assume !(0 == ~T6_E~0); 1507876#L774-1 assume !(0 == ~T7_E~0); 1507877#L779-1 assume !(0 == ~E_1~0); 1508235#L784-1 assume !(0 == ~E_2~0); 1508236#L789-1 assume !(0 == ~E_3~0); 1508042#L794-1 assume !(0 == ~E_4~0); 1508043#L799-1 assume !(0 == ~E_5~0); 1508376#L804-1 assume !(0 == ~E_6~0); 1507951#L809-1 assume !(0 == ~E_7~0); 1507952#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1508323#L351 assume !(1 == ~m_pc~0); 1508287#L351-2 is_master_triggered_~__retres1~0 := 0; 1508288#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1508320#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1508468#L920 assume !(0 != activate_threads_~tmp~1); 1508622#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1508573#L370 assume !(1 == ~t1_pc~0); 1508574#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 1508568#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1508569#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1508163#L928 assume !(0 != activate_threads_~tmp___0~0); 1507863#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1507834#L389 assume !(1 == ~t2_pc~0); 1507769#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 1507770#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1507830#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1507994#L936 assume !(0 != activate_threads_~tmp___1~0); 1508393#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1508122#L408 assume !(1 == ~t3_pc~0); 1508001#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 1508000#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1507997#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1507998#L944 assume !(0 != activate_threads_~tmp___2~0); 1508647#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1508635#L427 assume !(1 == ~t4_pc~0); 1508358#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 1508359#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1508314#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1507972#L952 assume !(0 != activate_threads_~tmp___3~0); 1507973#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1507914#L446 assume !(1 == ~t5_pc~0); 1507915#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 1507910#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1507911#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1508247#L960 assume !(0 != activate_threads_~tmp___4~0); 1508226#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1508206#L465 assume !(1 == ~t6_pc~0); 1507820#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 1508210#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1508690#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1508504#L968 assume !(0 != activate_threads_~tmp___5~0); 1508505#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1508460#L484 assume !(1 == ~t7_pc~0); 1508461#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 1508463#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1508151#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1508152#L976 assume !(0 != activate_threads_~tmp___6~0); 1508509#L976-2 assume !(1 == ~M_E~0); 1508062#L827-1 assume !(1 == ~T1_E~0); 1508063#L832-1 assume !(1 == ~T2_E~0); 1508374#L837-1 assume !(1 == ~T3_E~0); 1507946#L842-1 assume !(1 == ~T4_E~0); 1507947#L847-1 assume !(1 == ~T5_E~0); 1507712#L852-1 assume !(1 == ~T6_E~0); 1507713#L857-1 assume !(1 == ~T7_E~0); 1507864#L862-1 assume !(1 == ~E_1~0); 1507865#L867-1 assume !(1 == ~E_2~0); 1508229#L872-1 assume !(1 == ~E_3~0); 1508230#L877-1 assume !(1 == ~E_4~0); 1508058#L882-1 assume !(1 == ~E_5~0); 1508059#L887-1 assume !(1 == ~E_6~0); 1508396#L892-1 assume !(1 == ~E_7~0); 1508397#L1138-1 assume !false; 1549264#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1549265#L719 [2018-11-28 11:39:04,519 INFO L796 eck$LassoCheckResult]: Loop: 1549265#L719 assume !false; 1551166#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1551164#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1551163#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1551162#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1551160#L616 assume 0 != eval_~tmp~0; 1551155#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1551156#L624 assume !(0 != eval_~tmp_ndt_1~0); 1553176#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1553167#L638 assume !(0 != eval_~tmp_ndt_2~0); 1553175#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1554700#L652 assume !(0 != eval_~tmp_ndt_3~0); 1554709#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1556021#L666 assume !(0 != eval_~tmp_ndt_4~0); 1556019#L663 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1556016#L680 assume !(0 != eval_~tmp_ndt_5~0); 1556012#L677 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1556009#L694 assume !(0 != eval_~tmp_ndt_6~0); 1551172#L691 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 1551170#L708 assume !(0 != eval_~tmp_ndt_7~0); 1551169#L705 assume !(0 == ~t7_st~0); 1549265#L719 [2018-11-28 11:39:04,519 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:39:04,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1654179687, now seen corresponding path program 7 times [2018-11-28 11:39:04,520 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:39:04,520 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:39:04,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:04,520 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:39:04,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:04,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:04,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:04,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:39:04,549 INFO L82 PathProgramCache]: Analyzing trace with hash -472367047, now seen corresponding path program 1 times [2018-11-28 11:39:04,549 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:39:04,550 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:39:04,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:04,550 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:39:04,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:04,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:04,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:04,555 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:39:04,556 INFO L82 PathProgramCache]: Analyzing trace with hash 496645267, now seen corresponding path program 1 times [2018-11-28 11:39:04,556 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:39:04,556 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:39:04,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:04,557 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:39:04,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:04,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-28 11:39:04,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-28 11:39:04,611 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-28 11:39:04,612 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-28 11:39:04,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-28 11:39:04,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-28 11:39:04,741 INFO L87 Difference]: Start difference. First operand 291020 states and 394392 transitions. cyclomatic complexity: 103396 Second operand 3 states. [2018-11-28 11:39:06,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-28 11:39:06,167 INFO L93 Difference]: Finished difference Result 409345 states and 553889 transitions. [2018-11-28 11:39:06,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-28 11:39:06,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 409345 states and 553889 transitions. [2018-11-28 11:39:07,448 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 406079 [2018-11-28 11:39:08,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 409345 states to 409345 states and 553889 transitions. [2018-11-28 11:39:08,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 409345 [2018-11-28 11:39:08,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 409345 [2018-11-28 11:39:08,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 409345 states and 553889 transitions. [2018-11-28 11:39:08,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-28 11:39:08,556 INFO L705 BuchiCegarLoop]: Abstraction has 409345 states and 553889 transitions. [2018-11-28 11:39:08,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 409345 states and 553889 transitions. [2018-11-28 11:39:11,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 409345 to 409345. [2018-11-28 11:39:11,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 409345 states. [2018-11-28 11:39:12,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409345 states to 409345 states and 553889 transitions. [2018-11-28 11:39:12,493 INFO L728 BuchiCegarLoop]: Abstraction has 409345 states and 553889 transitions. [2018-11-28 11:39:12,493 INFO L608 BuchiCegarLoop]: Abstraction has 409345 states and 553889 transitions. [2018-11-28 11:39:12,493 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-28 11:39:12,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 409345 states and 553889 transitions. [2018-11-28 11:39:13,438 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 406079 [2018-11-28 11:39:13,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-28 11:39:13,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-28 11:39:13,439 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:39:13,439 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-28 11:39:13,439 INFO L794 eck$LassoCheckResult]: Stem: 2208793#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2208631#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2208632#L1101 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2208766#L504 assume 1 == ~m_i~0;~m_st~0 := 0; 2208359#L511-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2208360#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2208188#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2208189#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2208568#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2208569#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2208405#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2208406#L546-1 assume !(0 == ~M_E~0); 2208965#L744-1 assume !(0 == ~T1_E~0); 2208736#L749-1 assume !(0 == ~T2_E~0); 2208325#L754-1 assume !(0 == ~T3_E~0); 2208326#L759-1 assume !(0 == ~T4_E~0); 2208093#L764-1 assume !(0 == ~T5_E~0); 2208094#L769-1 assume !(0 == ~T6_E~0); 2208248#L774-1 assume !(0 == ~T7_E~0); 2208249#L779-1 assume !(0 == ~E_1~0); 2208597#L784-1 assume !(0 == ~E_2~0); 2208598#L789-1 assume !(0 == ~E_3~0); 2208412#L794-1 assume !(0 == ~E_4~0); 2208413#L799-1 assume !(0 == ~E_5~0); 2208729#L804-1 assume !(0 == ~E_6~0); 2208319#L809-1 assume !(0 == ~E_7~0); 2208320#L814-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2208680#L351 assume !(1 == ~m_pc~0); 2208644#L351-2 is_master_triggered_~__retres1~0 := 0; 2208645#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2208677#L363 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2208828#L920 assume !(0 != activate_threads_~tmp~1); 2208978#L920-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2208933#L370 assume !(1 == ~t1_pc~0); 2208934#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 2208931#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2208932#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2208533#L928 assume !(0 != activate_threads_~tmp___0~0); 2208238#L928-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2208209#L389 assume !(1 == ~t2_pc~0); 2208143#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 2208144#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2208208#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2208363#L936 assume !(0 != activate_threads_~tmp___1~0); 2208747#L936-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2208491#L408 assume !(1 == ~t3_pc~0); 2208371#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 2208370#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2208367#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2208368#L944 assume !(0 != activate_threads_~tmp___2~0); 2209005#L944-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2208992#L427 assume !(1 == ~t4_pc~0); 2208715#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 2208716#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2208671#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2208341#L952 assume !(0 != activate_threads_~tmp___3~0); 2208342#L952-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2208283#L446 assume !(1 == ~t5_pc~0); 2208284#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 2208281#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2208282#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2208606#L960 assume !(0 != activate_threads_~tmp___4~0); 2208588#L960-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2208573#L465 assume !(1 == ~t6_pc~0); 2208194#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 2208570#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2208190#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2208191#L968 assume !(0 != activate_threads_~tmp___5~0); 2208860#L968-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2208819#L484 assume !(1 == ~t7_pc~0); 2208820#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 2208825#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2208520#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2208521#L976 assume !(0 != activate_threads_~tmp___6~0); 2208866#L976-2 assume !(1 == ~M_E~0); 2208432#L827-1 assume !(1 == ~T1_E~0); 2208433#L832-1 assume !(1 == ~T2_E~0); 2208727#L837-1 assume !(1 == ~T3_E~0); 2208313#L842-1 assume !(1 == ~T4_E~0); 2208314#L847-1 assume !(1 == ~T5_E~0); 2208085#L852-1 assume !(1 == ~T6_E~0); 2208086#L857-1 assume !(1 == ~T7_E~0); 2208240#L862-1 assume !(1 == ~E_1~0); 2208241#L867-1 assume !(1 == ~E_2~0); 2208591#L872-1 assume !(1 == ~E_3~0); 2208592#L877-1 assume !(1 == ~E_4~0); 2208428#L882-1 assume !(1 == ~E_5~0); 2208429#L887-1 assume !(1 == ~E_6~0); 2208750#L892-1 assume !(1 == ~E_7~0); 2208751#L1138-1 assume !false; 2350844#L1139 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 2350842#L719 [2018-11-28 11:39:13,439 INFO L796 eck$LassoCheckResult]: Loop: 2350842#L719 assume !false; 2350841#L612 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2350839#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 2350836#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2350834#L602 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2350832#L616 assume 0 != eval_~tmp~0; 2350829#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2350826#L624 assume !(0 != eval_~tmp_ndt_1~0); 2350824#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2350508#L638 assume !(0 != eval_~tmp_ndt_2~0); 2350822#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2351859#L652 assume !(0 != eval_~tmp_ndt_3~0); 2351873#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2352212#L666 assume !(0 != eval_~tmp_ndt_4~0); 2352220#L663 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2457466#L680 assume !(0 != eval_~tmp_ndt_5~0); 2457467#L677 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2568654#L694 assume !(0 != eval_~tmp_ndt_6~0); 2350852#L691 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 2350849#L708 assume !(0 != eval_~tmp_ndt_7~0); 2350847#L705 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 2350845#L722 assume !(0 != eval_~tmp_ndt_8~0); 2350842#L719 [2018-11-28 11:39:13,439 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:39:13,440 INFO L82 PathProgramCache]: Analyzing trace with hash 1654179687, now seen corresponding path program 8 times [2018-11-28 11:39:13,440 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:39:13,440 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:39:13,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:13,441 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:39:13,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:13,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:13,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:13,467 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:39:13,467 INFO L82 PathProgramCache]: Analyzing trace with hash -1758475598, now seen corresponding path program 1 times [2018-11-28 11:39:13,467 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:39:13,467 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:39:13,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:13,468 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-28 11:39:13,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:13,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:13,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:13,475 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-28 11:39:13,476 INFO L82 PathProgramCache]: Analyzing trace with hash -1783864936, now seen corresponding path program 1 times [2018-11-28 11:39:13,476 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-28 11:39:13,476 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-28 11:39:13,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:13,477 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-28 11:39:13,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-28 11:39:13,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:13,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-28 11:39:14,128 WARN L180 SmtUtils]: Spent 490.00 ms on a formula simplification. DAG size of input: 250 DAG size of output: 166 [2018-11-28 11:39:14,276 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification that was a NOOP. DAG size: 132 [2018-11-28 11:39:14,307 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 11:39:14 BoogieIcfgContainer [2018-11-28 11:39:14,307 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-28 11:39:14,307 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-28 11:39:14,307 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-28 11:39:14,308 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-28 11:39:14,308 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:38:36" (3/4) ... [2018-11-28 11:39:14,310 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-28 11:39:14,366 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_f0bb4598-418c-44b4-b9d0-2d3fe206d52f/bin-2019/uautomizer/witness.graphml [2018-11-28 11:39:14,366 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-28 11:39:14,367 INFO L168 Benchmark]: Toolchain (without parser) took 39564.85 ms. Allocated memory was 1.0 GB in the beginning and 5.4 GB in the end (delta: 4.3 GB). Free memory was 953.3 MB in the beginning and 1.2 GB in the end (delta: -210.0 MB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. [2018-11-28 11:39:14,367 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:39:14,367 INFO L168 Benchmark]: CACSL2BoogieTranslator took 297.10 ms. Allocated memory is still 1.0 GB. Free memory was 950.6 MB in the beginning and 931.8 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-28 11:39:14,368 INFO L168 Benchmark]: Boogie Procedure Inliner took 92.12 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 118.0 MB). Free memory was 931.8 MB in the beginning and 1.1 GB in the end (delta: -177.7 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. [2018-11-28 11:39:14,368 INFO L168 Benchmark]: Boogie Preprocessor took 61.92 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. [2018-11-28 11:39:14,368 INFO L168 Benchmark]: RCFGBuilder took 1245.54 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 941.5 MB in the end (delta: 161.3 MB). Peak memory consumption was 161.3 MB. Max. memory is 11.5 GB. [2018-11-28 11:39:14,368 INFO L168 Benchmark]: BuchiAutomizer took 37806.20 ms. Allocated memory was 1.1 GB in the beginning and 5.4 GB in the end (delta: 4.2 GB). Free memory was 941.5 MB in the beginning and 1.2 GB in the end (delta: -221.9 MB). Peak memory consumption was 4.0 GB. Max. memory is 11.5 GB. [2018-11-28 11:39:14,368 INFO L168 Benchmark]: Witness Printer took 58.41 ms. Allocated memory is still 5.4 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-28 11:39:14,370 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 297.10 ms. Allocated memory is still 1.0 GB. Free memory was 950.6 MB in the beginning and 931.8 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 92.12 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 118.0 MB). Free memory was 931.8 MB in the beginning and 1.1 GB in the end (delta: -177.7 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 61.92 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1245.54 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 941.5 MB in the end (delta: 161.3 MB). Peak memory consumption was 161.3 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 37806.20 ms. Allocated memory was 1.1 GB in the beginning and 5.4 GB in the end (delta: 4.2 GB). Free memory was 941.5 MB in the beginning and 1.2 GB in the end (delta: -221.9 MB). Peak memory consumption was 4.0 GB. Max. memory is 11.5 GB. * Witness Printer took 58.41 ms. Allocated memory is still 5.4 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 27 terminating modules (27 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.27 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 409345 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 37.7s and 28 iterations. TraceHistogramMax:1. Analysis of lassos took 4.4s. Construction of modules took 1.0s. Büchi inclusion checks took 4.3s. Highest rank in rank-based complementation 0. Minimization of det autom 27. Minimization of nondet autom 0. Automata minimization 16.6s AutomataMinimizationTime, 27 MinimizatonAttempts, 48774 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 6.9s Buchi closure took 0.6s. Biggest automaton had 409345 states and ocurred in iteration 27. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 30029 SDtfs, 31727 SDslu, 22286 SDs, 0 SdLazy, 591 SolverSat, 370 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc7 concLT0 SILN1 SILU0 SILI16 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 611]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, \result=0, tmp_ndt_4=0, m_st=0, t6_pc=0, tmp___2=0, __retres1=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t5_st=0, __retres1=1, E_2=2, t7_pc=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7409e809=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@67e9fc7a=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5c9b0e40=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3cc65c3f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2764a27d=0, t7_st=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6f58b8a0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6bb54298=0, \result=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@659cddb0=0, tmp___3=0, t1_i=1, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d5c0c8f=0, T7_E=2, tmp=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2f06313f=0, t4_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@36a15f7f=0, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, tmp___0=0, tmp=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@65dbcfa2=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7e90a738=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d856a53=0, tmp___0=0, t1_pc=0, E_4=2, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, m_i=1, t1_st=0, tmp_ndt_5=0, __retres1=0, t2_pc=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@739f06b8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d273b38=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@781f1782=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2386210f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d9d6c1a=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 611]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int m_st ; [L24] int t1_st ; [L25] int t2_st ; [L26] int t3_st ; [L27] int t4_st ; [L28] int t5_st ; [L29] int t6_st ; [L30] int t7_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int t3_i ; [L35] int t4_i ; [L36] int t5_i ; [L37] int t6_i ; [L38] int t7_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int T5_E = 2; [L45] int T6_E = 2; [L46] int T7_E = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L1183] int __retres1 ; [L1092] m_i = 1 [L1093] t1_i = 1 [L1094] t2_i = 1 [L1095] t3_i = 1 [L1096] t4_i = 1 [L1097] t5_i = 1 [L1098] t6_i = 1 [L1099] t7_i = 1 [L1124] int kernel_st ; [L1125] int tmp ; [L1126] int tmp___0 ; [L1130] kernel_st = 0 [L511] COND TRUE m_i == 1 [L512] m_st = 0 [L516] COND TRUE t1_i == 1 [L517] t1_st = 0 [L521] COND TRUE t2_i == 1 [L522] t2_st = 0 [L526] COND TRUE t3_i == 1 [L527] t3_st = 0 [L531] COND TRUE t4_i == 1 [L532] t4_st = 0 [L536] COND TRUE t5_i == 1 [L537] t5_st = 0 [L541] COND TRUE t6_i == 1 [L542] t6_st = 0 [L546] COND TRUE t7_i == 1 [L547] t7_st = 0 [L744] COND FALSE !(M_E == 0) [L749] COND FALSE !(T1_E == 0) [L754] COND FALSE !(T2_E == 0) [L759] COND FALSE !(T3_E == 0) [L764] COND FALSE !(T4_E == 0) [L769] COND FALSE !(T5_E == 0) [L774] COND FALSE !(T6_E == 0) [L779] COND FALSE !(T7_E == 0) [L784] COND FALSE !(E_1 == 0) [L789] COND FALSE !(E_2 == 0) [L794] COND FALSE !(E_3 == 0) [L799] COND FALSE !(E_4 == 0) [L804] COND FALSE !(E_5 == 0) [L809] COND FALSE !(E_6 == 0) [L814] COND FALSE !(E_7 == 0) [L907] int tmp ; [L908] int tmp___0 ; [L909] int tmp___1 ; [L910] int tmp___2 ; [L911] int tmp___3 ; [L912] int tmp___4 ; [L913] int tmp___5 ; [L914] int tmp___6 ; [L348] int __retres1 ; [L351] COND FALSE !(m_pc == 1) [L361] __retres1 = 0 [L363] return (__retres1); [L918] tmp = is_master_triggered() [L920] COND FALSE !(\read(tmp)) [L367] int __retres1 ; [L370] COND FALSE !(t1_pc == 1) [L380] __retres1 = 0 [L382] return (__retres1); [L926] tmp___0 = is_transmit1_triggered() [L928] COND FALSE !(\read(tmp___0)) [L386] int __retres1 ; [L389] COND FALSE !(t2_pc == 1) [L399] __retres1 = 0 [L401] return (__retres1); [L934] tmp___1 = is_transmit2_triggered() [L936] COND FALSE !(\read(tmp___1)) [L405] int __retres1 ; [L408] COND FALSE !(t3_pc == 1) [L418] __retres1 = 0 [L420] return (__retres1); [L942] tmp___2 = is_transmit3_triggered() [L944] COND FALSE !(\read(tmp___2)) [L424] int __retres1 ; [L427] COND FALSE !(t4_pc == 1) [L437] __retres1 = 0 [L439] return (__retres1); [L950] tmp___3 = is_transmit4_triggered() [L952] COND FALSE !(\read(tmp___3)) [L443] int __retres1 ; [L446] COND FALSE !(t5_pc == 1) [L456] __retres1 = 0 [L458] return (__retres1); [L958] tmp___4 = is_transmit5_triggered() [L960] COND FALSE !(\read(tmp___4)) [L462] int __retres1 ; [L465] COND FALSE !(t6_pc == 1) [L475] __retres1 = 0 [L477] return (__retres1); [L966] tmp___5 = is_transmit6_triggered() [L968] COND FALSE !(\read(tmp___5)) [L481] int __retres1 ; [L484] COND FALSE !(t7_pc == 1) [L494] __retres1 = 0 [L496] return (__retres1); [L974] tmp___6 = is_transmit7_triggered() [L976] COND FALSE !(\read(tmp___6)) [L827] COND FALSE !(M_E == 1) [L832] COND FALSE !(T1_E == 1) [L837] COND FALSE !(T2_E == 1) [L842] COND FALSE !(T3_E == 1) [L847] COND FALSE !(T4_E == 1) [L852] COND FALSE !(T5_E == 1) [L857] COND FALSE !(T6_E == 1) [L862] COND FALSE !(T7_E == 1) [L867] COND FALSE !(E_1 == 1) [L872] COND FALSE !(E_2 == 1) [L877] COND FALSE !(E_3 == 1) [L882] COND FALSE !(E_4 == 1) [L887] COND FALSE !(E_5 == 1) [L892] COND FALSE !(E_6 == 1) [L897] COND FALSE !(E_7 == 1) [L1138] COND TRUE 1 [L1141] kernel_st = 1 [L607] int tmp ; Loop: [L611] COND TRUE 1 [L556] int __retres1 ; [L559] COND TRUE m_st == 0 [L560] __retres1 = 1 [L602] return (__retres1); [L614] tmp = exists_runnable_thread() [L616] COND TRUE \read(tmp) [L621] COND TRUE m_st == 0 [L622] int tmp_ndt_1; [L623] tmp_ndt_1 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_1)) [L635] COND TRUE t1_st == 0 [L636] int tmp_ndt_2; [L637] tmp_ndt_2 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_2)) [L649] COND TRUE t2_st == 0 [L650] int tmp_ndt_3; [L651] tmp_ndt_3 = __VERIFIER_nondet_int() [L652] COND FALSE !(\read(tmp_ndt_3)) [L663] COND TRUE t3_st == 0 [L664] int tmp_ndt_4; [L665] tmp_ndt_4 = __VERIFIER_nondet_int() [L666] COND FALSE !(\read(tmp_ndt_4)) [L677] COND TRUE t4_st == 0 [L678] int tmp_ndt_5; [L679] tmp_ndt_5 = __VERIFIER_nondet_int() [L680] COND FALSE !(\read(tmp_ndt_5)) [L691] COND TRUE t5_st == 0 [L692] int tmp_ndt_6; [L693] tmp_ndt_6 = __VERIFIER_nondet_int() [L694] COND FALSE !(\read(tmp_ndt_6)) [L705] COND TRUE t6_st == 0 [L706] int tmp_ndt_7; [L707] tmp_ndt_7 = __VERIFIER_nondet_int() [L708] COND FALSE !(\read(tmp_ndt_7)) [L719] COND TRUE t7_st == 0 [L720] int tmp_ndt_8; [L721] tmp_ndt_8 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...