./Ultimate.py --spec ../../sv-benchmarks/c/properties/no-overflow.prp --file ../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for overflows Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i -s /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! overflow) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash c57ebc44b313bf301635c00d4458ecfdd41286b1 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis No suitable file found in config dir /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/config using search string *Overflow*64bit*_Bitvector*.epf No suitable settings file found using Overflow*64bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-02 14:09:13,747 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-02 14:09:13,748 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-02 14:09:13,756 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-02 14:09:13,757 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-02 14:09:13,757 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-02 14:09:13,758 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-02 14:09:13,758 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-02 14:09:13,759 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-02 14:09:13,760 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-02 14:09:13,760 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-02 14:09:13,760 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-02 14:09:13,761 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-02 14:09:13,761 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-02 14:09:13,762 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-02 14:09:13,762 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-02 14:09:13,762 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-02 14:09:13,763 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-02 14:09:13,764 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-02 14:09:13,765 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-02 14:09:13,765 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-02 14:09:13,766 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-02 14:09:13,768 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-02 14:09:13,768 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 14:09:13,768 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 14:09:13,769 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 14:09:13,769 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 14:09:13,769 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 14:09:13,770 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 14:09:13,770 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 14:09:13,770 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 14:09:13,771 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 14:09:13,771 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 14:09:13,771 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 14:09:13,771 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 14:09:13,772 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 14:09:13,772 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf [2018-12-02 14:09:13,779 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 14:09:13,779 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 14:09:13,779 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 14:09:13,779 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 14:09:13,780 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-02 14:09:13,780 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-02 14:09:13,780 INFO L133 SettingsManager]: * Use SBE=true [2018-12-02 14:09:13,780 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 14:09:13,780 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-12-02 14:09:13,780 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-02 14:09:13,780 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 14:09:13,780 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * Check absence of signed integer overflows=true [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-02 14:09:13,781 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 14:09:13,781 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 14:09:13,782 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 14:09:13,782 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 14:09:13,782 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-02 14:09:13,782 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-02 14:09:13,782 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 14:09:13,782 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-02 14:09:13,782 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! overflow) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c57ebc44b313bf301635c00d4458ecfdd41286b1 [2018-12-02 14:09:13,805 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 14:09:13,812 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 14:09:13,814 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 14:09:13,815 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 14:09:13,815 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 14:09:13,815 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-12-02 14:09:13,849 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/data/1187e4f94/4fae3e4c1a4849b89270ebd97ee2830a/FLAG7b6485da0 [2018-12-02 14:09:14,287 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 14:09:14,288 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-12-02 14:09:14,298 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/data/1187e4f94/4fae3e4c1a4849b89270ebd97ee2830a/FLAG7b6485da0 [2018-12-02 14:09:14,306 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/data/1187e4f94/4fae3e4c1a4849b89270ebd97ee2830a [2018-12-02 14:09:14,308 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 14:09:14,309 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 14:09:14,309 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 14:09:14,309 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 14:09:14,312 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 14:09:14,312 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,314 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@33416e95 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14, skipping insertion in model container [2018-12-02 14:09:14,314 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,318 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 14:09:14,343 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 14:09:14,750 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 14:09:14,765 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 14:09:14,818 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 14:09:14,900 INFO L195 MainTranslator]: Completed translation [2018-12-02 14:09:14,900 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14 WrapperNode [2018-12-02 14:09:14,900 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 14:09:14,901 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 14:09:14,901 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 14:09:14,901 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 14:09:14,906 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,922 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,929 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 14:09:14,929 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 14:09:14,929 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 14:09:14,929 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 14:09:14,935 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,935 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,939 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,940 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,955 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,959 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,964 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... [2018-12-02 14:09:14,969 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 14:09:14,970 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 14:09:14,970 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 14:09:14,970 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 14:09:14,971 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 14:09:15,013 INFO L130 BoogieDeclarations]: Found specification of procedure __main [2018-12-02 14:09:15,013 INFO L138 BoogieDeclarations]: Found implementation of procedure __main [2018-12-02 14:09:15,014 INFO L130 BoogieDeclarations]: Found specification of procedure last_char_is [2018-12-02 14:09:15,014 INFO L138 BoogieDeclarations]: Found implementation of procedure last_char_is [2018-12-02 14:09:15,014 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 14:09:15,014 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 14:09:15,014 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-12-02 14:09:15,014 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-02 14:09:15,014 INFO L130 BoogieDeclarations]: Found specification of procedure safe_write [2018-12-02 14:09:15,014 INFO L138 BoogieDeclarations]: Found implementation of procedure safe_write [2018-12-02 14:09:15,015 INFO L130 BoogieDeclarations]: Found specification of procedure bb_get_last_path_component_nostrip [2018-12-02 14:09:15,015 INFO L138 BoogieDeclarations]: Found implementation of procedure bb_get_last_path_component_nostrip [2018-12-02 14:09:15,015 INFO L130 BoogieDeclarations]: Found specification of procedure bb_get_last_path_component_strip [2018-12-02 14:09:15,015 INFO L138 BoogieDeclarations]: Found implementation of procedure bb_get_last_path_component_strip [2018-12-02 14:09:15,015 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-02 14:09:15,015 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-02 14:09:15,015 INFO L130 BoogieDeclarations]: Found specification of procedure write [2018-12-02 14:09:15,015 INFO L138 BoogieDeclarations]: Found implementation of procedure write [2018-12-02 14:09:15,015 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-02 14:09:15,016 INFO L130 BoogieDeclarations]: Found specification of procedure strrchr [2018-12-02 14:09:15,016 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 14:09:15,016 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 14:09:15,016 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-12-02 14:09:15,016 INFO L130 BoogieDeclarations]: Found specification of procedure full_write [2018-12-02 14:09:15,016 INFO L138 BoogieDeclarations]: Found implementation of procedure full_write [2018-12-02 14:09:15,016 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-12-02 14:09:15,016 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 14:09:15,016 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 14:09:15,556 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 14:09:15,556 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-12-02 14:09:15,557 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 02:09:15 BoogieIcfgContainer [2018-12-02 14:09:15,557 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 14:09:15,557 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 14:09:15,558 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 14:09:15,560 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 14:09:15,561 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 02:09:14" (1/3) ... [2018-12-02 14:09:15,561 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4bce019e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 02:09:15, skipping insertion in model container [2018-12-02 14:09:15,561 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 02:09:14" (2/3) ... [2018-12-02 14:09:15,562 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4bce019e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 02:09:15, skipping insertion in model container [2018-12-02 14:09:15,562 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 02:09:15" (3/3) ... [2018-12-02 14:09:15,563 INFO L112 eAbstractionObserver]: Analyzing ICFG basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-12-02 14:09:15,570 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 14:09:15,575 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 28 error locations. [2018-12-02 14:09:15,584 INFO L257 AbstractCegarLoop]: Starting to check reachability of 28 error locations. [2018-12-02 14:09:15,604 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-02 14:09:15,604 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 14:09:15,604 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-02 14:09:15,604 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 14:09:15,605 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 14:09:15,605 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 14:09:15,605 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 14:09:15,605 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 14:09:15,605 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 14:09:15,622 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states. [2018-12-02 14:09:15,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-12-02 14:09:15,626 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:15,627 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:15,628 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:15,631 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:15,632 INFO L82 PathProgramCache]: Analyzing trace with hash -51273939, now seen corresponding path program 1 times [2018-12-02 14:09:15,633 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:15,633 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:15,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:15,701 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:15,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:15,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:15,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:09:15,826 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:15,826 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:15,828 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:15,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:15,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:15,838 INFO L87 Difference]: Start difference. First operand 154 states. Second operand 3 states. [2018-12-02 14:09:15,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:15,879 INFO L93 Difference]: Finished difference Result 298 states and 388 transitions. [2018-12-02 14:09:15,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:15,881 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-12-02 14:09:15,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:15,888 INFO L225 Difference]: With dead ends: 298 [2018-12-02 14:09:15,888 INFO L226 Difference]: Without dead ends: 149 [2018-12-02 14:09:15,891 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:15,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-12-02 14:09:15,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-12-02 14:09:15,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-12-02 14:09:15,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 183 transitions. [2018-12-02 14:09:15,922 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 183 transitions. Word has length 8 [2018-12-02 14:09:15,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:15,923 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 183 transitions. [2018-12-02 14:09:15,923 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:15,923 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 183 transitions. [2018-12-02 14:09:15,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2018-12-02 14:09:15,923 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:15,923 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:15,924 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:15,924 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:15,924 INFO L82 PathProgramCache]: Analyzing trace with hash -1589491972, now seen corresponding path program 1 times [2018-12-02 14:09:15,924 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:15,924 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:15,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:15,934 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:15,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:15,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:15,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:09:15,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:15,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:15,980 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:15,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:15,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:15,981 INFO L87 Difference]: Start difference. First operand 149 states and 183 transitions. Second operand 3 states. [2018-12-02 14:09:16,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,004 INFO L93 Difference]: Finished difference Result 152 states and 186 transitions. [2018-12-02 14:09:16,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:16,005 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2018-12-02 14:09:16,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,006 INFO L225 Difference]: With dead ends: 152 [2018-12-02 14:09:16,006 INFO L226 Difference]: Without dead ends: 151 [2018-12-02 14:09:16,007 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-12-02 14:09:16,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-12-02 14:09:16,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-12-02 14:09:16,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 185 transitions. [2018-12-02 14:09:16,017 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 185 transitions. Word has length 9 [2018-12-02 14:09:16,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,017 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 185 transitions. [2018-12-02 14:09:16,017 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:16,018 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 185 transitions. [2018-12-02 14:09:16,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-02 14:09:16,018 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,018 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,019 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,019 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,019 INFO L82 PathProgramCache]: Analyzing trace with hash -540770008, now seen corresponding path program 1 times [2018-12-02 14:09:16,019 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,019 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,070 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-12-02 14:09:16,070 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:16,071 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:16,071 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:16,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:16,071 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,071 INFO L87 Difference]: Start difference. First operand 151 states and 185 transitions. Second operand 3 states. [2018-12-02 14:09:16,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,113 INFO L93 Difference]: Finished difference Result 151 states and 185 transitions. [2018-12-02 14:09:16,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:16,114 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-12-02 14:09:16,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,115 INFO L225 Difference]: With dead ends: 151 [2018-12-02 14:09:16,115 INFO L226 Difference]: Without dead ends: 147 [2018-12-02 14:09:16,115 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-12-02 14:09:16,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2018-12-02 14:09:16,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-12-02 14:09:16,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 181 transitions. [2018-12-02 14:09:16,124 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 181 transitions. Word has length 12 [2018-12-02 14:09:16,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,124 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 181 transitions. [2018-12-02 14:09:16,124 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:16,124 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 181 transitions. [2018-12-02 14:09:16,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-02 14:09:16,124 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,125 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,125 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,125 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,126 INFO L82 PathProgramCache]: Analyzing trace with hash -540768278, now seen corresponding path program 1 times [2018-12-02 14:09:16,126 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,126 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,136 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,186 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:09:16,186 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:16,186 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:16,186 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:16,187 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:16,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,187 INFO L87 Difference]: Start difference. First operand 147 states and 181 transitions. Second operand 3 states. [2018-12-02 14:09:16,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,202 INFO L93 Difference]: Finished difference Result 147 states and 181 transitions. [2018-12-02 14:09:16,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:16,203 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-12-02 14:09:16,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,204 INFO L225 Difference]: With dead ends: 147 [2018-12-02 14:09:16,204 INFO L226 Difference]: Without dead ends: 146 [2018-12-02 14:09:16,204 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-12-02 14:09:16,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-12-02 14:09:16,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-12-02 14:09:16,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 178 transitions. [2018-12-02 14:09:16,212 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 178 transitions. Word has length 12 [2018-12-02 14:09:16,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,213 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 178 transitions. [2018-12-02 14:09:16,213 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:16,213 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 178 transitions. [2018-12-02 14:09:16,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-12-02 14:09:16,213 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,213 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,214 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,214 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,214 INFO L82 PathProgramCache]: Analyzing trace with hash 415999081, now seen corresponding path program 1 times [2018-12-02 14:09:16,214 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,215 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,223 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,264 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-12-02 14:09:16,265 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:16,265 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:16,265 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:16,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:16,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,274 INFO L87 Difference]: Start difference. First operand 144 states and 178 transitions. Second operand 3 states. [2018-12-02 14:09:16,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,311 INFO L93 Difference]: Finished difference Result 144 states and 178 transitions. [2018-12-02 14:09:16,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:16,311 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2018-12-02 14:09:16,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,312 INFO L225 Difference]: With dead ends: 144 [2018-12-02 14:09:16,312 INFO L226 Difference]: Without dead ends: 142 [2018-12-02 14:09:16,313 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-12-02 14:09:16,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2018-12-02 14:09:16,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-12-02 14:09:16,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 176 transitions. [2018-12-02 14:09:16,319 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 176 transitions. Word has length 13 [2018-12-02 14:09:16,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,319 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 176 transitions. [2018-12-02 14:09:16,319 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:16,319 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 176 transitions. [2018-12-02 14:09:16,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-12-02 14:09:16,320 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,320 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,320 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,321 INFO L82 PathProgramCache]: Analyzing trace with hash 343163019, now seen corresponding path program 1 times [2018-12-02 14:09:16,321 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,321 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,331 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,375 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-12-02 14:09:16,375 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:16,375 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:16,375 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:16,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:16,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,376 INFO L87 Difference]: Start difference. First operand 142 states and 176 transitions. Second operand 3 states. [2018-12-02 14:09:16,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,406 INFO L93 Difference]: Finished difference Result 142 states and 176 transitions. [2018-12-02 14:09:16,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:16,406 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-12-02 14:09:16,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,407 INFO L225 Difference]: With dead ends: 142 [2018-12-02 14:09:16,407 INFO L226 Difference]: Without dead ends: 140 [2018-12-02 14:09:16,408 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-12-02 14:09:16,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-12-02 14:09:16,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-12-02 14:09:16,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 174 transitions. [2018-12-02 14:09:16,413 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 174 transitions. Word has length 15 [2018-12-02 14:09:16,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,413 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 174 transitions. [2018-12-02 14:09:16,414 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:16,414 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 174 transitions. [2018-12-02 14:09:16,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-12-02 14:09:16,414 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,414 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,415 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1254383198, now seen corresponding path program 1 times [2018-12-02 14:09:16,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,423 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,457 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-12-02 14:09:16,458 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:16,458 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:09:16,458 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:16,458 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:16,458 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,458 INFO L87 Difference]: Start difference. First operand 140 states and 174 transitions. Second operand 3 states. [2018-12-02 14:09:16,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,482 INFO L93 Difference]: Finished difference Result 264 states and 334 transitions. [2018-12-02 14:09:16,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:16,482 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-12-02 14:09:16,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,483 INFO L225 Difference]: With dead ends: 264 [2018-12-02 14:09:16,483 INFO L226 Difference]: Without dead ends: 143 [2018-12-02 14:09:16,484 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-12-02 14:09:16,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2018-12-02 14:09:16,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-12-02 14:09:16,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 177 transitions. [2018-12-02 14:09:16,489 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 177 transitions. Word has length 22 [2018-12-02 14:09:16,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,489 INFO L480 AbstractCegarLoop]: Abstraction has 143 states and 177 transitions. [2018-12-02 14:09:16,489 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:16,490 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 177 transitions. [2018-12-02 14:09:16,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-02 14:09:16,490 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,490 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,491 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,491 INFO L82 PathProgramCache]: Analyzing trace with hash 1182405925, now seen corresponding path program 1 times [2018-12-02 14:09:16,491 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,491 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,497 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,550 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-02 14:09:16,550 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:16,550 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:09:16,550 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:09:16,551 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:09:16,551 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:09:16,551 INFO L87 Difference]: Start difference. First operand 143 states and 177 transitions. Second operand 4 states. [2018-12-02 14:09:16,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,605 INFO L93 Difference]: Finished difference Result 151 states and 187 transitions. [2018-12-02 14:09:16,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 14:09:16,605 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-12-02 14:09:16,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,607 INFO L225 Difference]: With dead ends: 151 [2018-12-02 14:09:16,607 INFO L226 Difference]: Without dead ends: 150 [2018-12-02 14:09:16,608 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:09:16,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-12-02 14:09:16,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 142. [2018-12-02 14:09:16,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-12-02 14:09:16,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 176 transitions. [2018-12-02 14:09:16,616 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 176 transitions. Word has length 25 [2018-12-02 14:09:16,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,617 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 176 transitions. [2018-12-02 14:09:16,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:09:16,617 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 176 transitions. [2018-12-02 14:09:16,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-02 14:09:16,618 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,618 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,618 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,619 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,619 INFO L82 PathProgramCache]: Analyzing trace with hash 1182405980, now seen corresponding path program 1 times [2018-12-02 14:09:16,619 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,619 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,626 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,669 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-02 14:09:16,669 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:16,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:16,670 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:16,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:16,670 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,670 INFO L87 Difference]: Start difference. First operand 142 states and 176 transitions. Second operand 3 states. [2018-12-02 14:09:16,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,685 INFO L93 Difference]: Finished difference Result 142 states and 176 transitions. [2018-12-02 14:09:16,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:16,686 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-12-02 14:09:16,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,686 INFO L225 Difference]: With dead ends: 142 [2018-12-02 14:09:16,686 INFO L226 Difference]: Without dead ends: 141 [2018-12-02 14:09:16,686 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:16,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-12-02 14:09:16,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2018-12-02 14:09:16,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-12-02 14:09:16,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 175 transitions. [2018-12-02 14:09:16,690 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 175 transitions. Word has length 25 [2018-12-02 14:09:16,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,690 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 175 transitions. [2018-12-02 14:09:16,690 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:16,690 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 175 transitions. [2018-12-02 14:09:16,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-12-02 14:09:16,690 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,690 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,691 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,691 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,691 INFO L82 PathProgramCache]: Analyzing trace with hash -1458323352, now seen corresponding path program 1 times [2018-12-02 14:09:16,691 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,691 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,695 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,733 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:09:16,734 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:16,734 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:16,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,795 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:16,814 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:09:16,831 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:16,831 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-12-02 14:09:16,831 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 14:09:16,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 14:09:16,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:09:16,832 INFO L87 Difference]: Start difference. First operand 141 states and 175 transitions. Second operand 5 states. [2018-12-02 14:09:16,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:16,858 INFO L93 Difference]: Finished difference Result 277 states and 345 transitions. [2018-12-02 14:09:16,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 14:09:16,859 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-12-02 14:09:16,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:16,860 INFO L225 Difference]: With dead ends: 277 [2018-12-02 14:09:16,860 INFO L226 Difference]: Without dead ends: 146 [2018-12-02 14:09:16,860 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:09:16,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-12-02 14:09:16,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-12-02 14:09:16,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-12-02 14:09:16,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 178 transitions. [2018-12-02 14:09:16,866 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 178 transitions. Word has length 27 [2018-12-02 14:09:16,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:16,866 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 178 transitions. [2018-12-02 14:09:16,866 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 14:09:16,866 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 178 transitions. [2018-12-02 14:09:16,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-12-02 14:09:16,867 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:16,867 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:16,868 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:16,868 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:16,868 INFO L82 PathProgramCache]: Analyzing trace with hash -672341546, now seen corresponding path program 2 times [2018-12-02 14:09:16,868 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:16,868 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:16,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,877 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:16,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:16,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:16,930 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:09:16,930 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:16,930 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:16,956 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-02 14:09:16,997 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-12-02 14:09:16,997 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:09:17,000 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:17,032 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-02 14:09:17,057 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 14:09:17,057 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5] total 7 [2018-12-02 14:09:17,058 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-02 14:09:17,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-02 14:09:17,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:09:17,058 INFO L87 Difference]: Start difference. First operand 144 states and 178 transitions. Second operand 7 states. [2018-12-02 14:09:17,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:17,209 INFO L93 Difference]: Finished difference Result 290 states and 361 transitions. [2018-12-02 14:09:17,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 14:09:17,210 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 30 [2018-12-02 14:09:17,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:17,210 INFO L225 Difference]: With dead ends: 290 [2018-12-02 14:09:17,210 INFO L226 Difference]: Without dead ends: 159 [2018-12-02 14:09:17,211 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-02 14:09:17,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-12-02 14:09:17,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 148. [2018-12-02 14:09:17,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-12-02 14:09:17,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 182 transitions. [2018-12-02 14:09:17,216 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 182 transitions. Word has length 30 [2018-12-02 14:09:17,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:17,217 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 182 transitions. [2018-12-02 14:09:17,217 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-02 14:09:17,217 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 182 transitions. [2018-12-02 14:09:17,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-12-02 14:09:17,217 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:17,218 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:17,218 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:17,218 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:17,218 INFO L82 PathProgramCache]: Analyzing trace with hash -205191436, now seen corresponding path program 1 times [2018-12-02 14:09:17,218 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:17,219 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:17,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,225 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:09:17,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:17,271 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-02 14:09:17,271 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:17,271 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:17,271 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:17,272 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:17,272 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:17,272 INFO L87 Difference]: Start difference. First operand 148 states and 182 transitions. Second operand 3 states. [2018-12-02 14:09:17,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:17,296 INFO L93 Difference]: Finished difference Result 158 states and 193 transitions. [2018-12-02 14:09:17,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:17,296 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-12-02 14:09:17,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:17,297 INFO L225 Difference]: With dead ends: 158 [2018-12-02 14:09:17,297 INFO L226 Difference]: Without dead ends: 157 [2018-12-02 14:09:17,298 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:17,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-12-02 14:09:17,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 156. [2018-12-02 14:09:17,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-12-02 14:09:17,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 192 transitions. [2018-12-02 14:09:17,304 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 192 transitions. Word has length 32 [2018-12-02 14:09:17,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:17,304 INFO L480 AbstractCegarLoop]: Abstraction has 156 states and 192 transitions. [2018-12-02 14:09:17,304 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:17,304 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 192 transitions. [2018-12-02 14:09:17,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-12-02 14:09:17,305 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:17,305 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:17,306 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:17,306 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:17,306 INFO L82 PathProgramCache]: Analyzing trace with hash -205189738, now seen corresponding path program 1 times [2018-12-02 14:09:17,306 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:17,306 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:17,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,313 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:17,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:17,359 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-02 14:09:17,359 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:09:17,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:09:17,359 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:09:17,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:09:17,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:17,360 INFO L87 Difference]: Start difference. First operand 156 states and 192 transitions. Second operand 3 states. [2018-12-02 14:09:17,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:17,371 INFO L93 Difference]: Finished difference Result 156 states and 192 transitions. [2018-12-02 14:09:17,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:09:17,372 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-12-02 14:09:17,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:17,372 INFO L225 Difference]: With dead ends: 156 [2018-12-02 14:09:17,372 INFO L226 Difference]: Without dead ends: 155 [2018-12-02 14:09:17,373 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:09:17,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-12-02 14:09:17,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 151. [2018-12-02 14:09:17,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-12-02 14:09:17,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 186 transitions. [2018-12-02 14:09:17,377 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 186 transitions. Word has length 32 [2018-12-02 14:09:17,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:17,377 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 186 transitions. [2018-12-02 14:09:17,377 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:09:17,377 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 186 transitions. [2018-12-02 14:09:17,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-12-02 14:09:17,378 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:17,378 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:17,379 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:17,379 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:17,379 INFO L82 PathProgramCache]: Analyzing trace with hash 1301076365, now seen corresponding path program 1 times [2018-12-02 14:09:17,379 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:17,379 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:17,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:17,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:17,429 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-02 14:09:17,429 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:17,429 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:17,447 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:17,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:17,485 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:17,533 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-02 14:09:17,558 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:17,558 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6] total 8 [2018-12-02 14:09:17,559 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-02 14:09:17,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-02 14:09:17,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-12-02 14:09:17,559 INFO L87 Difference]: Start difference. First operand 151 states and 186 transitions. Second operand 8 states. [2018-12-02 14:09:17,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:17,624 INFO L93 Difference]: Finished difference Result 301 states and 373 transitions. [2018-12-02 14:09:17,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-02 14:09:17,624 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2018-12-02 14:09:17,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:17,625 INFO L225 Difference]: With dead ends: 301 [2018-12-02 14:09:17,625 INFO L226 Difference]: Without dead ends: 166 [2018-12-02 14:09:17,626 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-12-02 14:09:17,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-12-02 14:09:17,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 160. [2018-12-02 14:09:17,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-02 14:09:17,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 195 transitions. [2018-12-02 14:09:17,632 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 195 transitions. Word has length 40 [2018-12-02 14:09:17,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:17,632 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 195 transitions. [2018-12-02 14:09:17,633 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-02 14:09:17,633 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 195 transitions. [2018-12-02 14:09:17,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-02 14:09:17,633 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:17,633 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:17,634 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:17,634 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:17,634 INFO L82 PathProgramCache]: Analyzing trace with hash 532136062, now seen corresponding path program 2 times [2018-12-02 14:09:17,634 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:17,634 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:17,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,641 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:17,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:17,691 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-12-02 14:09:17,692 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:17,692 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:17,710 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-02 14:09:17,749 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-12-02 14:09:17,749 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:09:17,752 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:17,763 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-12-02 14:09:17,779 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 14:09:17,780 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-02 14:09:17,780 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 14:09:17,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 14:09:17,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:09:17,780 INFO L87 Difference]: Start difference. First operand 160 states and 195 transitions. Second operand 6 states. [2018-12-02 14:09:17,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:17,835 INFO L93 Difference]: Finished difference Result 312 states and 391 transitions. [2018-12-02 14:09:17,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 14:09:17,836 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-12-02 14:09:17,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:17,838 INFO L225 Difference]: With dead ends: 312 [2018-12-02 14:09:17,838 INFO L226 Difference]: Without dead ends: 188 [2018-12-02 14:09:17,839 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-12-02 14:09:17,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-12-02 14:09:17,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 167. [2018-12-02 14:09:17,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-12-02 14:09:17,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 202 transitions. [2018-12-02 14:09:17,845 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 202 transitions. Word has length 46 [2018-12-02 14:09:17,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:17,846 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 202 transitions. [2018-12-02 14:09:17,846 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 14:09:17,846 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 202 transitions. [2018-12-02 14:09:17,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-12-02 14:09:17,846 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:17,846 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:17,847 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:17,847 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:17,847 INFO L82 PathProgramCache]: Analyzing trace with hash -1211589613, now seen corresponding path program 1 times [2018-12-02 14:09:17,847 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:17,847 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:17,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,854 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:09:17,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:17,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:17,926 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-12-02 14:09:17,926 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:17,926 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:17,948 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:17,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:18,001 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:18,067 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-02 14:09:18,091 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:18,091 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 7] total 11 [2018-12-02 14:09:18,091 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-12-02 14:09:18,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-12-02 14:09:18,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-12-02 14:09:18,092 INFO L87 Difference]: Start difference. First operand 167 states and 202 transitions. Second operand 11 states. [2018-12-02 14:09:18,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:18,181 INFO L93 Difference]: Finished difference Result 330 states and 402 transitions. [2018-12-02 14:09:18,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-02 14:09:18,182 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 50 [2018-12-02 14:09:18,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:18,182 INFO L225 Difference]: With dead ends: 330 [2018-12-02 14:09:18,182 INFO L226 Difference]: Without dead ends: 182 [2018-12-02 14:09:18,183 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-12-02 14:09:18,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-12-02 14:09:18,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 176. [2018-12-02 14:09:18,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-12-02 14:09:18,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 211 transitions. [2018-12-02 14:09:18,187 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 211 transitions. Word has length 50 [2018-12-02 14:09:18,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:18,188 INFO L480 AbstractCegarLoop]: Abstraction has 176 states and 211 transitions. [2018-12-02 14:09:18,188 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-12-02 14:09:18,188 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 211 transitions. [2018-12-02 14:09:18,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-12-02 14:09:18,188 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:18,188 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:18,188 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:18,188 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:18,189 INFO L82 PathProgramCache]: Analyzing trace with hash -1484183166, now seen corresponding path program 2 times [2018-12-02 14:09:18,189 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:18,189 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:18,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:18,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:18,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:18,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:18,259 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-12-02 14:09:18,259 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:18,259 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:18,278 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-02 14:09:18,333 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-02 14:09:18,333 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:09:18,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:18,413 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-12-02 14:09:18,439 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:18,439 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2018-12-02 14:09:18,439 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-12-02 14:09:18,439 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-12-02 14:09:18,439 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-12-02 14:09:18,440 INFO L87 Difference]: Start difference. First operand 176 states and 211 transitions. Second operand 13 states. [2018-12-02 14:09:18,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:18,542 INFO L93 Difference]: Finished difference Result 345 states and 417 transitions. [2018-12-02 14:09:18,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-12-02 14:09:18,543 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2018-12-02 14:09:18,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:18,544 INFO L225 Difference]: With dead ends: 345 [2018-12-02 14:09:18,544 INFO L226 Difference]: Without dead ends: 191 [2018-12-02 14:09:18,544 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-12-02 14:09:18,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2018-12-02 14:09:18,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 185. [2018-12-02 14:09:18,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-12-02 14:09:18,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 220 transitions. [2018-12-02 14:09:18,552 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 220 transitions. Word has length 56 [2018-12-02 14:09:18,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:18,552 INFO L480 AbstractCegarLoop]: Abstraction has 185 states and 220 transitions. [2018-12-02 14:09:18,553 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-12-02 14:09:18,553 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 220 transitions. [2018-12-02 14:09:18,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-12-02 14:09:18,553 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:18,553 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:18,554 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:18,554 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:18,554 INFO L82 PathProgramCache]: Analyzing trace with hash 1464125235, now seen corresponding path program 3 times [2018-12-02 14:09:18,554 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:18,554 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:18,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:18,559 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:09:18,560 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:18,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:18,650 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-12-02 14:09:18,650 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:18,650 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:18,673 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 14:09:19,635 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-12-02 14:09:19,635 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:09:19,637 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:19,663 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-12-02 14:09:19,681 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:19,681 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-12-02 14:09:19,681 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-02 14:09:19,681 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-02 14:09:19,681 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-12-02 14:09:19,681 INFO L87 Difference]: Start difference. First operand 185 states and 220 transitions. Second operand 9 states. [2018-12-02 14:09:19,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:19,724 INFO L93 Difference]: Finished difference Result 329 states and 399 transitions. [2018-12-02 14:09:19,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-02 14:09:19,725 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 62 [2018-12-02 14:09:19,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:19,726 INFO L225 Difference]: With dead ends: 329 [2018-12-02 14:09:19,726 INFO L226 Difference]: Without dead ends: 195 [2018-12-02 14:09:19,726 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-12-02 14:09:19,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-12-02 14:09:19,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 191. [2018-12-02 14:09:19,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191 states. [2018-12-02 14:09:19,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 226 transitions. [2018-12-02 14:09:19,734 INFO L78 Accepts]: Start accepts. Automaton has 191 states and 226 transitions. Word has length 62 [2018-12-02 14:09:19,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:19,734 INFO L480 AbstractCegarLoop]: Abstraction has 191 states and 226 transitions. [2018-12-02 14:09:19,734 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-02 14:09:19,735 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 226 transitions. [2018-12-02 14:09:19,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-12-02 14:09:19,735 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:19,735 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:19,736 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:19,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:19,736 INFO L82 PathProgramCache]: Analyzing trace with hash 613455476, now seen corresponding path program 4 times [2018-12-02 14:09:19,736 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:19,736 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:19,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:19,741 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:09:19,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:19,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:19,837 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 14:09:19,837 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:19,837 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:19,856 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 14:09:19,916 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 14:09:19,916 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:09:19,919 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:19,934 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 14:09:19,950 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:19,950 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-12-02 14:09:19,951 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-02 14:09:19,951 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-02 14:09:19,951 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-12-02 14:09:19,951 INFO L87 Difference]: Start difference. First operand 191 states and 226 transitions. Second operand 10 states. [2018-12-02 14:09:20,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:20,007 INFO L93 Difference]: Finished difference Result 362 states and 432 transitions. [2018-12-02 14:09:20,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-02 14:09:20,007 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2018-12-02 14:09:20,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:20,008 INFO L225 Difference]: With dead ends: 362 [2018-12-02 14:09:20,009 INFO L226 Difference]: Without dead ends: 196 [2018-12-02 14:09:20,009 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-12-02 14:09:20,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-12-02 14:09:20,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 194. [2018-12-02 14:09:20,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-12-02 14:09:20,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 229 transitions. [2018-12-02 14:09:20,014 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 229 transitions. Word has length 65 [2018-12-02 14:09:20,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:20,015 INFO L480 AbstractCegarLoop]: Abstraction has 194 states and 229 transitions. [2018-12-02 14:09:20,015 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-02 14:09:20,015 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 229 transitions. [2018-12-02 14:09:20,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-12-02 14:09:20,015 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:20,015 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:20,016 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:20,016 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:20,016 INFO L82 PathProgramCache]: Analyzing trace with hash -420268702, now seen corresponding path program 5 times [2018-12-02 14:09:20,016 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:20,016 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:20,020 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:20,020 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:09:20,020 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:20,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:20,124 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 70 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-02 14:09:20,124 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:20,124 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:20,146 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-02 14:09:21,355 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-12-02 14:09:21,356 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:09:21,358 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:21,446 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 51 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-12-02 14:09:21,462 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:21,462 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-12-02 14:09:21,462 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-12-02 14:09:21,463 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-12-02 14:09:21,463 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-12-02 14:09:21,463 INFO L87 Difference]: Start difference. First operand 194 states and 229 transitions. Second operand 17 states. [2018-12-02 14:09:21,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:21,571 INFO L93 Difference]: Finished difference Result 375 states and 447 transitions. [2018-12-02 14:09:21,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-02 14:09:21,571 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 68 [2018-12-02 14:09:21,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:21,572 INFO L225 Difference]: With dead ends: 375 [2018-12-02 14:09:21,572 INFO L226 Difference]: Without dead ends: 209 [2018-12-02 14:09:21,573 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-12-02 14:09:21,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-12-02 14:09:21,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 203. [2018-12-02 14:09:21,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-12-02 14:09:21,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 238 transitions. [2018-12-02 14:09:21,581 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 238 transitions. Word has length 68 [2018-12-02 14:09:21,581 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:21,581 INFO L480 AbstractCegarLoop]: Abstraction has 203 states and 238 transitions. [2018-12-02 14:09:21,581 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-12-02 14:09:21,581 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 238 transitions. [2018-12-02 14:09:21,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-12-02 14:09:21,582 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:21,582 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:21,582 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:21,582 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:21,582 INFO L82 PathProgramCache]: Analyzing trace with hash -1212679597, now seen corresponding path program 6 times [2018-12-02 14:09:21,583 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:21,583 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:21,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:21,587 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:09:21,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:21,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:21,689 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 1 proven. 70 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-12-02 14:09:21,689 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:21,689 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:21,708 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-02 14:09:36,651 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-12-02 14:09:36,651 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:09:36,656 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:36,778 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 0 proven. 92 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-12-02 14:09:36,797 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:36,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2018-12-02 14:09:36,797 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-12-02 14:09:36,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-12-02 14:09:36,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-12-02 14:09:36,798 INFO L87 Difference]: Start difference. First operand 203 states and 238 transitions. Second operand 19 states. [2018-12-02 14:09:36,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:36,919 INFO L93 Difference]: Finished difference Result 390 states and 462 transitions. [2018-12-02 14:09:36,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-02 14:09:36,920 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 74 [2018-12-02 14:09:36,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:36,920 INFO L225 Difference]: With dead ends: 390 [2018-12-02 14:09:36,920 INFO L226 Difference]: Without dead ends: 218 [2018-12-02 14:09:36,921 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-12-02 14:09:36,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-12-02 14:09:36,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 212. [2018-12-02 14:09:36,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2018-12-02 14:09:36,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 247 transitions. [2018-12-02 14:09:36,925 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 247 transitions. Word has length 74 [2018-12-02 14:09:36,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:36,925 INFO L480 AbstractCegarLoop]: Abstraction has 212 states and 247 transitions. [2018-12-02 14:09:36,925 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-12-02 14:09:36,925 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 247 transitions. [2018-12-02 14:09:36,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-12-02 14:09:36,926 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:36,926 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:36,926 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:36,926 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:36,926 INFO L82 PathProgramCache]: Analyzing trace with hash -38749886, now seen corresponding path program 7 times [2018-12-02 14:09:36,926 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:36,926 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:36,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:36,929 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:09:36,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:36,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:37,039 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 1 proven. 92 refuted. 0 times theorem prover too weak. 117 trivial. 0 not checked. [2018-12-02 14:09:37,039 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:37,039 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:37,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:37,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:37,111 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:37,263 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 93 trivial. 0 not checked. [2018-12-02 14:09:37,278 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:37,278 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 21 [2018-12-02 14:09:37,278 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-12-02 14:09:37,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-12-02 14:09:37,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-12-02 14:09:37,279 INFO L87 Difference]: Start difference. First operand 212 states and 247 transitions. Second operand 21 states. [2018-12-02 14:09:37,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:37,399 INFO L93 Difference]: Finished difference Result 403 states and 475 transitions. [2018-12-02 14:09:37,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-12-02 14:09:37,400 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 80 [2018-12-02 14:09:37,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:37,400 INFO L225 Difference]: With dead ends: 403 [2018-12-02 14:09:37,401 INFO L226 Difference]: Without dead ends: 225 [2018-12-02 14:09:37,401 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 90 GetRequests, 71 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-12-02 14:09:37,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-12-02 14:09:37,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 221. [2018-12-02 14:09:37,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-12-02 14:09:37,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 256 transitions. [2018-12-02 14:09:37,406 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 256 transitions. Word has length 80 [2018-12-02 14:09:37,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:37,406 INFO L480 AbstractCegarLoop]: Abstraction has 221 states and 256 transitions. [2018-12-02 14:09:37,406 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-12-02 14:09:37,406 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 256 transitions. [2018-12-02 14:09:37,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-02 14:09:37,407 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:37,407 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:37,407 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:37,408 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:37,408 INFO L82 PathProgramCache]: Analyzing trace with hash -622054029, now seen corresponding path program 8 times [2018-12-02 14:09:37,408 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:37,408 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:37,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:37,412 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:09:37,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:37,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:37,517 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-12-02 14:09:37,518 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:37,518 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:37,533 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-02 14:09:37,588 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-02 14:09:37,588 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:09:37,591 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:09:37,604 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-12-02 14:09:37,622 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:09:37,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2018-12-02 14:09:37,622 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-12-02 14:09:37,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-12-02 14:09:37,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-12-02 14:09:37,622 INFO L87 Difference]: Start difference. First operand 221 states and 256 transitions. Second operand 13 states. [2018-12-02 14:09:37,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:09:37,676 INFO L93 Difference]: Finished difference Result 373 states and 443 transitions. [2018-12-02 14:09:37,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-12-02 14:09:37,677 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 86 [2018-12-02 14:09:37,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:09:37,678 INFO L225 Difference]: With dead ends: 373 [2018-12-02 14:09:37,678 INFO L226 Difference]: Without dead ends: 227 [2018-12-02 14:09:37,678 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 86 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-12-02 14:09:37,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-12-02 14:09:37,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 227. [2018-12-02 14:09:37,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-12-02 14:09:37,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 262 transitions. [2018-12-02 14:09:37,686 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 262 transitions. Word has length 86 [2018-12-02 14:09:37,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:09:37,686 INFO L480 AbstractCegarLoop]: Abstraction has 227 states and 262 transitions. [2018-12-02 14:09:37,686 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-12-02 14:09:37,687 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 262 transitions. [2018-12-02 14:09:37,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-12-02 14:09:37,687 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:09:37,687 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:09:37,687 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:09:37,688 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:09:37,688 INFO L82 PathProgramCache]: Analyzing trace with hash -576225228, now seen corresponding path program 9 times [2018-12-02 14:09:37,688 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:09:37,688 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:09:37,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:37,692 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:09:37,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:09:37,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:09:38,598 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 31 [2018-12-02 14:09:38,780 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 40 [2018-12-02 14:09:39,358 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 37 [2018-12-02 14:09:39,730 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 37 [2018-12-02 14:09:40,632 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 291 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 14:09:40,632 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:09:40,632 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:09:40,648 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-02 14:10:07,259 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-12-02 14:10:07,260 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:10:07,268 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:10:07,492 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-12-02 14:10:07,493 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,502 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,502 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:16, output treesize:15 [2018-12-02 14:10:07,558 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:07,559 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:07,559 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-12-02 14:10:07,560 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,590 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-12-02 14:10:07,592 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-12-02 14:10:07,593 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,596 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,621 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-12-02 14:10:07,624 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-12-02 14:10:07,624 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,626 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,646 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,646 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:59, output treesize:49 [2018-12-02 14:10:07,729 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:07,732 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:07,734 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:07,735 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-12-02 14:10:07,735 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,825 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 634 treesize of output 452 [2018-12-02 14:10:07,913 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:07,917 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-12-02 14:10:07,917 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:07,955 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 154 treesize of output 146 [2018-12-02 14:10:07,958 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-12-02 14:10:07,959 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,002 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 141 treesize of output 150 [2018-12-02 14:10:08,007 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 1 [2018-12-02 14:10:08,007 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,024 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,035 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,049 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,099 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 191 treesize of output 105 [2018-12-02 14:10:08,143 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:08,146 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-12-02 14:10:08,146 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,165 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 58 [2018-12-02 14:10:08,168 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-12-02 14:10:08,168 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,194 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 70 [2018-12-02 14:10:08,196 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 23 [2018-12-02 14:10:08,197 INFO L267 ElimStorePlain]: Start of recursive call 14: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,209 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,216 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,224 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,254 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-1 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:08,254 INFO L202 ElimStorePlain]: Needed 14 recursive calls to eliminate 7 variables, input treesize:676, output treesize:101 [2018-12-02 14:10:08,359 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-12-02 14:10:08,362 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:08,362 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,378 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,420 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-12-02 14:10:08,423 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:08,423 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,433 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,457 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:08,458 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:08,478 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-12-02 14:10:08,481 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:08,481 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,498 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,545 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-12-02 14:10:08,548 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:08,548 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,558 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,582 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:08,582 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:08,603 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-12-02 14:10:08,606 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:08,607 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,621 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,666 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-12-02 14:10:08,669 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:08,669 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,679 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,704 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:08,704 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:08,724 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-12-02 14:10:08,727 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:08,727 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,742 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,786 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-12-02 14:10:08,789 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:08,789 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,798 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,824 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:08,824 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:08,844 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-12-02 14:10:08,847 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:08,847 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,863 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,907 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-12-02 14:10:08,910 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:08,910 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,920 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,944 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:08,944 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:08,966 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-12-02 14:10:08,969 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:08,969 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:08,984 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,030 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-12-02 14:10:09,033 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:09,034 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,044 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,069 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:09,069 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:09,088 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-12-02 14:10:09,091 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:09,091 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,107 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,153 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-12-02 14:10:09,156 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:09,156 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,166 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,192 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:09,193 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:09,213 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-12-02 14:10:09,216 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:09,217 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,232 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,280 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-12-02 14:10:09,284 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:09,284 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,294 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,319 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:09,319 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:09,345 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 149 treesize of output 166 [2018-12-02 14:10:09,348 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:09,348 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,363 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,408 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 114 treesize of output 110 [2018-12-02 14:10:09,411 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:09,411 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,423 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,450 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:09,450 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:09,469 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 149 treesize of output 166 [2018-12-02 14:10:09,471 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-12-02 14:10:09,472 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,486 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,531 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 114 treesize of output 110 [2018-12-02 14:10:09,534 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-12-02 14:10:09,535 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,546 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,570 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-12-02 14:10:09,570 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-12-02 14:10:09,832 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 36 [2018-12-02 14:10:09,835 INFO L683 Elim1Store]: detected equality via solver [2018-12-02 14:10:09,839 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 21 [2018-12-02 14:10:09,839 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,850 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2018-12-02 14:10:09,850 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,853 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,872 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2018-12-02 14:10:09,874 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-12-02 14:10:09,874 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,882 INFO L683 Elim1Store]: detected equality via solver [2018-12-02 14:10:09,882 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2018-12-02 14:10:09,882 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,886 INFO L267 ElimStorePlain]: Start of recursive call 5: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,896 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:09,896 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 6 variables, input treesize:84, output treesize:7 [2018-12-02 14:10:09,970 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 22 proven. 54 refuted. 0 times theorem prover too weak. 215 trivial. 0 not checked. [2018-12-02 14:10:10,000 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 14:10:10,000 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 14] total 46 [2018-12-02 14:10:10,001 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-12-02 14:10:10,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-12-02 14:10:10,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=1770, Unknown=0, NotChecked=0, Total=2070 [2018-12-02 14:10:10,001 INFO L87 Difference]: Start difference. First operand 227 states and 262 transitions. Second operand 46 states. [2018-12-02 14:10:10,840 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 66 [2018-12-02 14:10:11,498 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 63 [2018-12-02 14:10:13,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:10:13,336 INFO L93 Difference]: Finished difference Result 352 states and 422 transitions. [2018-12-02 14:10:13,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-02 14:10:13,337 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 89 [2018-12-02 14:10:13,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:10:13,338 INFO L225 Difference]: With dead ends: 352 [2018-12-02 14:10:13,338 INFO L226 Difference]: Without dead ends: 243 [2018-12-02 14:10:13,339 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 82 SyntacticMatches, 6 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 971 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=742, Invalid=3418, Unknown=0, NotChecked=0, Total=4160 [2018-12-02 14:10:13,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states. [2018-12-02 14:10:13,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 234. [2018-12-02 14:10:13,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-12-02 14:10:13,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 272 transitions. [2018-12-02 14:10:13,347 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 272 transitions. Word has length 89 [2018-12-02 14:10:13,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:10:13,347 INFO L480 AbstractCegarLoop]: Abstraction has 234 states and 272 transitions. [2018-12-02 14:10:13,347 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-12-02 14:10:13,347 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 272 transitions. [2018-12-02 14:10:13,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-02 14:10:13,348 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:10:13,348 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:10:13,348 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:10:13,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:10:13,349 INFO L82 PathProgramCache]: Analyzing trace with hash 1101225913, now seen corresponding path program 1 times [2018-12-02 14:10:13,349 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:10:13,349 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:10:13,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,354 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-02 14:10:13,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:10:13,439 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-12-02 14:10:13,440 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:10:13,440 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:10:13,440 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:10:13,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:10:13,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:10:13,441 INFO L87 Difference]: Start difference. First operand 234 states and 272 transitions. Second operand 4 states. [2018-12-02 14:10:13,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:10:13,488 INFO L93 Difference]: Finished difference Result 235 states and 273 transitions. [2018-12-02 14:10:13,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 14:10:13,488 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 90 [2018-12-02 14:10:13,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:10:13,490 INFO L225 Difference]: With dead ends: 235 [2018-12-02 14:10:13,490 INFO L226 Difference]: Without dead ends: 234 [2018-12-02 14:10:13,490 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 14:10:13,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2018-12-02 14:10:13,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 233. [2018-12-02 14:10:13,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233 states. [2018-12-02 14:10:13,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 271 transitions. [2018-12-02 14:10:13,501 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 271 transitions. Word has length 90 [2018-12-02 14:10:13,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:10:13,501 INFO L480 AbstractCegarLoop]: Abstraction has 233 states and 271 transitions. [2018-12-02 14:10:13,501 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:10:13,501 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 271 transitions. [2018-12-02 14:10:13,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-12-02 14:10:13,502 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:10:13,502 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:10:13,502 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:10:13,502 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:10:13,502 INFO L82 PathProgramCache]: Analyzing trace with hash -221734862, now seen corresponding path program 1 times [2018-12-02 14:10:13,502 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:10:13,502 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:10:13,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,508 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:10:13,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:10:13,549 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-12-02 14:10:13,549 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:10:13,549 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:10:13,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:10:13,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:10:13,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:10:13,550 INFO L87 Difference]: Start difference. First operand 233 states and 271 transitions. Second operand 3 states. [2018-12-02 14:10:13,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:10:13,567 INFO L93 Difference]: Finished difference Result 237 states and 275 transitions. [2018-12-02 14:10:13,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:10:13,568 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 91 [2018-12-02 14:10:13,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:10:13,569 INFO L225 Difference]: With dead ends: 237 [2018-12-02 14:10:13,569 INFO L226 Difference]: Without dead ends: 236 [2018-12-02 14:10:13,569 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:10:13,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-12-02 14:10:13,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 236. [2018-12-02 14:10:13,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-12-02 14:10:13,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 274 transitions. [2018-12-02 14:10:13,580 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 274 transitions. Word has length 91 [2018-12-02 14:10:13,581 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:10:13,581 INFO L480 AbstractCegarLoop]: Abstraction has 236 states and 274 transitions. [2018-12-02 14:10:13,581 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:10:13,581 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 274 transitions. [2018-12-02 14:10:13,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-12-02 14:10:13,582 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:10:13,582 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:10:13,582 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:10:13,582 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:10:13,582 INFO L82 PathProgramCache]: Analyzing trace with hash -43375882, now seen corresponding path program 1 times [2018-12-02 14:10:13,582 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:10:13,582 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:10:13,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,587 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:10:13,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:10:13,628 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-12-02 14:10:13,628 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:10:13,629 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:10:13,629 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:10:13,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:10:13,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:10:13,629 INFO L87 Difference]: Start difference. First operand 236 states and 274 transitions. Second operand 3 states. [2018-12-02 14:10:13,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:10:13,642 INFO L93 Difference]: Finished difference Result 236 states and 274 transitions. [2018-12-02 14:10:13,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:10:13,643 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 94 [2018-12-02 14:10:13,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:10:13,644 INFO L225 Difference]: With dead ends: 236 [2018-12-02 14:10:13,644 INFO L226 Difference]: Without dead ends: 219 [2018-12-02 14:10:13,644 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:10:13,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-12-02 14:10:13,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 218. [2018-12-02 14:10:13,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-12-02 14:10:13,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 250 transitions. [2018-12-02 14:10:13,654 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 250 transitions. Word has length 94 [2018-12-02 14:10:13,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:10:13,655 INFO L480 AbstractCegarLoop]: Abstraction has 218 states and 250 transitions. [2018-12-02 14:10:13,655 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:10:13,655 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 250 transitions. [2018-12-02 14:10:13,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-12-02 14:10:13,656 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:10:13,656 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 20, 10, 10, 10, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:10:13,656 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:10:13,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:10:13,656 INFO L82 PathProgramCache]: Analyzing trace with hash 1510247437, now seen corresponding path program 1 times [2018-12-02 14:10:13,657 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:10:13,657 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:10:13,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,662 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:10:13,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:10:13,726 INFO L134 CoverageAnalysis]: Checked inductivity of 759 backedges. 324 proven. 0 refuted. 0 times theorem prover too weak. 435 trivial. 0 not checked. [2018-12-02 14:10:13,726 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:10:13,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-02 14:10:13,727 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 14:10:13,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 14:10:13,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:10:13,727 INFO L87 Difference]: Start difference. First operand 218 states and 250 transitions. Second operand 3 states. [2018-12-02 14:10:13,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:10:13,751 INFO L93 Difference]: Finished difference Result 218 states and 250 transitions. [2018-12-02 14:10:13,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 14:10:13,751 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2018-12-02 14:10:13,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:10:13,752 INFO L225 Difference]: With dead ends: 218 [2018-12-02 14:10:13,752 INFO L226 Difference]: Without dead ends: 217 [2018-12-02 14:10:13,752 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 14:10:13,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-12-02 14:10:13,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2018-12-02 14:10:13,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-12-02 14:10:13,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 249 transitions. [2018-12-02 14:10:13,763 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 249 transitions. Word has length 114 [2018-12-02 14:10:13,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:10:13,763 INFO L480 AbstractCegarLoop]: Abstraction has 217 states and 249 transitions. [2018-12-02 14:10:13,763 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 14:10:13,764 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 249 transitions. [2018-12-02 14:10:13,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-12-02 14:10:13,765 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:10:13,765 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:10:13,765 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:10:13,765 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:10:13,765 INFO L82 PathProgramCache]: Analyzing trace with hash 1035682170, now seen corresponding path program 1 times [2018-12-02 14:10:13,765 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:10:13,765 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:10:13,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,771 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:10:13,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:10:13,833 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-12-02 14:10:13,834 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:10:13,834 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:10:13,834 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:10:13,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:10:13,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:10:13,834 INFO L87 Difference]: Start difference. First operand 217 states and 249 transitions. Second operand 4 states. [2018-12-02 14:10:13,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:10:13,858 INFO L93 Difference]: Finished difference Result 225 states and 258 transitions. [2018-12-02 14:10:13,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 14:10:13,858 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 126 [2018-12-02 14:10:13,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:10:13,859 INFO L225 Difference]: With dead ends: 225 [2018-12-02 14:10:13,859 INFO L226 Difference]: Without dead ends: 224 [2018-12-02 14:10:13,859 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:10:13,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-12-02 14:10:13,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 222. [2018-12-02 14:10:13,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-12-02 14:10:13,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 255 transitions. [2018-12-02 14:10:13,865 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 255 transitions. Word has length 126 [2018-12-02 14:10:13,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:10:13,866 INFO L480 AbstractCegarLoop]: Abstraction has 222 states and 255 transitions. [2018-12-02 14:10:13,866 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:10:13,866 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 255 transitions. [2018-12-02 14:10:13,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-12-02 14:10:13,866 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:10:13,866 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:10:13,867 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:10:13,867 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:10:13,867 INFO L82 PathProgramCache]: Analyzing trace with hash 2041376282, now seen corresponding path program 1 times [2018-12-02 14:10:13,867 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:10:13,867 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:10:13,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,870 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:10:13,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:10:13,925 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-12-02 14:10:13,925 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 14:10:13,925 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 14:10:13,925 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 14:10:13,925 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 14:10:13,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:10:13,926 INFO L87 Difference]: Start difference. First operand 222 states and 255 transitions. Second operand 4 states. [2018-12-02 14:10:13,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 14:10:13,943 INFO L93 Difference]: Finished difference Result 224 states and 257 transitions. [2018-12-02 14:10:13,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 14:10:13,943 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 127 [2018-12-02 14:10:13,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 14:10:13,944 INFO L225 Difference]: With dead ends: 224 [2018-12-02 14:10:13,944 INFO L226 Difference]: Without dead ends: 223 [2018-12-02 14:10:13,945 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-12-02 14:10:13,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-12-02 14:10:13,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 223. [2018-12-02 14:10:13,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-12-02 14:10:13,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 256 transitions. [2018-12-02 14:10:13,952 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 256 transitions. Word has length 127 [2018-12-02 14:10:13,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 14:10:13,952 INFO L480 AbstractCegarLoop]: Abstraction has 223 states and 256 transitions. [2018-12-02 14:10:13,952 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 14:10:13,952 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 256 transitions. [2018-12-02 14:10:13,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-12-02 14:10:13,953 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 14:10:13,953 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 20, 10, 10, 10, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 14:10:13,953 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-12-02 14:10:13,953 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 14:10:13,953 INFO L82 PathProgramCache]: Analyzing trace with hash -1749488180, now seen corresponding path program 10 times [2018-12-02 14:10:13,953 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 14:10:13,953 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 14:10:13,957 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:13,957 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 14:10:13,957 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 14:10:14,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 14:10:15,404 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 34 [2018-12-02 14:10:15,573 WARN L180 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 45 [2018-12-02 14:10:15,871 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 46 [2018-12-02 14:10:16,095 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 47 [2018-12-02 14:10:16,285 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 49 [2018-12-02 14:10:16,472 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 49 [2018-12-02 14:10:16,758 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 50 [2018-12-02 14:10:17,027 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 50 [2018-12-02 14:10:17,219 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 50 [2018-12-02 14:10:17,415 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 49 [2018-12-02 14:10:17,655 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 50 [2018-12-02 14:10:17,897 WARN L180 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 49 [2018-12-02 14:10:18,789 INFO L134 CoverageAnalysis]: Checked inductivity of 761 backedges. 0 proven. 527 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [2018-12-02 14:10:18,789 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 14:10:18,789 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b32d03b3-1ddc-47c3-a676-c372e798da3f/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:10:18,805 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-02 14:10:18,904 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-02 14:10:18,904 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-02 14:10:18,911 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 14:10:18,917 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 164 treesize of output 151 [2018-12-02 14:10:18,923 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:18,960 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 151 treesize of output 142 [2018-12-02 14:10:18,969 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 136 treesize of output 123 [2018-12-02 14:10:18,995 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 120 treesize of output 107 [2018-12-02 14:10:19,085 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,090 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,095 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,143 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,144 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 116 [2018-12-02 14:10:19,324 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 40 [2018-12-02 14:10:19,359 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,365 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,370 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,375 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,391 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,399 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,405 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,410 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,411 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 10 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 124 [2018-12-02 14:10:19,612 WARN L180 SmtUtils]: Spent 200.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 [2018-12-02 14:10:19,638 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,641 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,645 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,661 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,665 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,676 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,678 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,680 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,683 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,685 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,686 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 138 [2018-12-02 14:10:19,881 WARN L180 SmtUtils]: Spent 193.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 57 [2018-12-02 14:10:19,903 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,905 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,908 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,911 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,924 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,927 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,935 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,937 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,939 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,941 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,943 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,945 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:19,946 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 155 [2018-12-02 14:10:20,126 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 68 [2018-12-02 14:10:20,140 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,141 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,143 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,145 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,151 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,152 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,156 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,157 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,159 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,160 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,162 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,164 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,165 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,167 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:20,167 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 181 [2018-12-02 14:10:20,183 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 175 [2018-12-02 14:10:20,184 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:20,265 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:20,352 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:20,443 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:20,546 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:20,637 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:20,732 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:20,832 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:20,983 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,000 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,042 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 138 treesize of output 133 [2018-12-02 14:10:21,060 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 127 treesize of output 118 [2018-12-02 14:10:21,126 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,128 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,129 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,140 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,140 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 120 [2018-12-02 14:10:21,310 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-12-02 14:10:21,339 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,344 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,349 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,353 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,374 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,378 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,381 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,384 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,385 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 11 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 128 [2018-12-02 14:10:21,600 WARN L180 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-12-02 14:10:21,630 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,634 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,638 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,654 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,658 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,662 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,665 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,669 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,674 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,678 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,678 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 142 [2018-12-02 14:10:21,878 WARN L180 SmtUtils]: Spent 198.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 59 [2018-12-02 14:10:21,899 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,902 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,905 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,907 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,922 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,925 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,929 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,932 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,935 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,938 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,941 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,944 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:21,945 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 24 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 159 [2018-12-02 14:10:22,088 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 70 [2018-12-02 14:10:22,097 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,099 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,100 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,101 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,106 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,107 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,108 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,109 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,111 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,112 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,113 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,115 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,117 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,119 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,120 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 32 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 185 [2018-12-02 14:10:22,134 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 32 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 179 [2018-12-02 14:10:22,134 INFO L267 ElimStorePlain]: Start of recursive call 19: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:22,229 INFO L267 ElimStorePlain]: Start of recursive call 18: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:22,316 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:22,407 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:22,506 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:22,608 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:22,716 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:22,888 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,900 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,920 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:22,967 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 125 treesize of output 124 [2018-12-02 14:10:23,484 WARN L180 SmtUtils]: Spent 515.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 72 [2018-12-02 14:10:23,492 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,497 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,500 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,533 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,533 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 135 [2018-12-02 14:10:23,731 WARN L180 SmtUtils]: Spent 197.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 45 [2018-12-02 14:10:23,739 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,761 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,766 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,770 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,775 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,780 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,793 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,798 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,803 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:23,804 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 12 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 132 [2018-12-02 14:10:24,017 WARN L180 SmtUtils]: Spent 212.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 52 [2018-12-02 14:10:24,038 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,040 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,045 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,049 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,053 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,063 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,067 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,071 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,074 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,078 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,079 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 146 [2018-12-02 14:10:24,290 WARN L180 SmtUtils]: Spent 210.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 61 [2018-12-02 14:10:24,307 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,309 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,312 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,315 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,318 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,320 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,329 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,332 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,335 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,338 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,341 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,345 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,345 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 25 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 163 [2018-12-02 14:10:24,542 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 72 [2018-12-02 14:10:24,555 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,556 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,558 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,560 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,561 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,563 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,567 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,568 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,569 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,571 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,573 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,574 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,576 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,577 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:24,578 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 33 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 189 [2018-12-02 14:10:24,591 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 33 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 183 [2018-12-02 14:10:24,591 INFO L267 ElimStorePlain]: Start of recursive call 26: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:24,679 INFO L267 ElimStorePlain]: Start of recursive call 25: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:24,768 INFO L267 ElimStorePlain]: Start of recursive call 24: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:24,864 INFO L267 ElimStorePlain]: Start of recursive call 23: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:24,962 INFO L267 ElimStorePlain]: Start of recursive call 22: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:25,067 INFO L267 ElimStorePlain]: Start of recursive call 21: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:25,241 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:25,245 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:25,250 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:25,277 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:25,297 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:25,309 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:25,332 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:25,373 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 8 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 113 treesize of output 137 [2018-12-02 14:10:26,015 WARN L180 SmtUtils]: Spent 640.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 76 [2018-12-02 14:10:26,026 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,054 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,060 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,065 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,069 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,075 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,100 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,106 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,118 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,122 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,127 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,132 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,157 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,158 INFO L303 Elim1Store]: Index analysis took 141 ms [2018-12-02 14:10:26,197 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 14 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 100 treesize of output 146 [2018-12-02 14:10:26,844 WARN L180 SmtUtils]: Spent 645.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 82 [2018-12-02 14:10:26,869 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,873 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,876 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,880 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,898 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,902 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,911 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,915 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,919 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,923 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,926 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:26,926 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 99 treesize of output 150 [2018-12-02 14:10:27,130 WARN L180 SmtUtils]: Spent 203.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 57 [2018-12-02 14:10:27,151 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,153 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,156 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,159 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,170 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,172 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,180 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,183 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,186 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,189 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,191 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,193 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,195 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,196 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 157 [2018-12-02 14:10:27,376 WARN L180 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 68 [2018-12-02 14:10:27,388 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,390 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,391 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,392 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,398 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,400 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,404 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,406 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,407 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,409 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,410 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,412 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,413 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,415 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,416 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 181 [2018-12-02 14:10:27,431 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 175 [2018-12-02 14:10:27,432 INFO L267 ElimStorePlain]: Start of recursive call 32: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:27,515 INFO L267 ElimStorePlain]: Start of recursive call 31: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:27,598 INFO L267 ElimStorePlain]: Start of recursive call 30: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:27,698 INFO L267 ElimStorePlain]: Start of recursive call 29: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:27,887 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,891 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,895 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,899 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,904 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,908 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,924 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,927 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,932 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,941 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,944 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,946 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,949 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,953 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,956 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,979 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:27,980 INFO L303 Elim1Store]: Index analysis took 117 ms [2018-12-02 14:10:28,004 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 21 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 101 treesize of output 164 [2018-12-02 14:10:28,648 WARN L180 SmtUtils]: Spent 642.00 ms on a formula simplification. DAG size of input: 110 DAG size of output: 92 [2018-12-02 14:10:28,669 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,672 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,675 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,678 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,690 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,693 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,701 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,704 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,706 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,709 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,711 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,713 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,715 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,715 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 107 treesize of output 173 [2018-12-02 14:10:28,906 WARN L180 SmtUtils]: Spent 189.00 ms on a formula simplification. DAG size of input: 92 DAG size of output: 68 [2018-12-02 14:10:28,918 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,920 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,921 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,923 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,930 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,931 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,936 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,937 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,939 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,940 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,942 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,944 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,945 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,947 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,949 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:28,949 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 181 [2018-12-02 14:10:28,964 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 175 [2018-12-02 14:10:28,964 INFO L267 ElimStorePlain]: Start of recursive call 36: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:29,048 INFO L267 ElimStorePlain]: Start of recursive call 35: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:29,146 INFO L267 ElimStorePlain]: Start of recursive call 34: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:29,351 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,354 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,357 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,360 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,363 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,365 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,378 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,381 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,383 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,391 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,393 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,395 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,397 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,400 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,402 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,405 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,413 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,421 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,429 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:29,430 INFO L303 Elim1Store]: Index analysis took 102 ms [2018-12-02 14:10:29,448 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 29 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 109 treesize of output 187 [2018-12-02 14:10:30,067 WARN L180 SmtUtils]: Spent 617.00 ms on a formula simplification. DAG size of input: 124 DAG size of output: 102 [2018-12-02 14:10:30,080 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,082 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,083 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,085 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,086 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,088 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,094 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,095 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,097 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,101 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,102 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,104 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,105 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,107 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,108 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,110 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,111 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,115 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,117 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,118 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,120 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,126 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,137 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 38 disjoint index pairs (out of 45 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 124 treesize of output 215 [2018-12-02 14:10:30,171 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 39 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 211 treesize of output 213 [2018-12-02 14:10:30,172 INFO L267 ElimStorePlain]: Start of recursive call 39: End of recursive call: and 2 xjuncts. [2018-12-02 14:10:30,657 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,658 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,663 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,666 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,667 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,668 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,670 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,671 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,672 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:30,673 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 143 treesize of output 191 [2018-12-02 14:10:30,673 INFO L267 ElimStorePlain]: Start of recursive call 40: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:31,084 INFO L267 ElimStorePlain]: Start of recursive call 38: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-12-02 14:10:31,579 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,581 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,583 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,585 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,591 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,593 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,597 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,598 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,600 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,601 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,603 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,604 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,606 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,607 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,609 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:31,610 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 122 treesize of output 197 [2018-12-02 14:10:31,626 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 175 [2018-12-02 14:10:31,627 INFO L267 ElimStorePlain]: Start of recursive call 42: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:31,735 INFO L267 ElimStorePlain]: Start of recursive call 41: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:32,249 INFO L267 ElimStorePlain]: Start of recursive call 37: 2 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-12-02 14:10:32,867 INFO L267 ElimStorePlain]: Start of recursive call 33: 2 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-12-02 14:10:33,591 INFO L267 ElimStorePlain]: Start of recursive call 28: 2 dim-1 vars, End of recursive call: and 6 xjuncts. [2018-12-02 14:10:34,390 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,395 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,401 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,406 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,410 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,430 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,442 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,447 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,452 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,453 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 13 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 148 [2018-12-02 14:10:34,693 WARN L180 SmtUtils]: Spent 239.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 54 [2018-12-02 14:10:34,701 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,704 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,708 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,712 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,728 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,733 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,743 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,747 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,751 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,755 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,760 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,760 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 150 [2018-12-02 14:10:34,989 WARN L180 SmtUtils]: Spent 227.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 63 [2018-12-02 14:10:34,995 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:34,998 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,001 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,004 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,016 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,020 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,025 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,027 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,030 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,031 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,033 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,036 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,036 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 26 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 169 [2018-12-02 14:10:35,235 WARN L180 SmtUtils]: Spent 197.00 ms on a formula simplification. DAG size of input: 90 DAG size of output: 74 [2018-12-02 14:10:35,240 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,242 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,243 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,245 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,252 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,253 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,257 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,259 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,260 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,262 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,263 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,265 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,266 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,267 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:35,268 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 34 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 193 [2018-12-02 14:10:35,278 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 34 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 187 [2018-12-02 14:10:35,278 INFO L267 ElimStorePlain]: Start of recursive call 47: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:35,367 INFO L267 ElimStorePlain]: Start of recursive call 46: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:35,457 INFO L267 ElimStorePlain]: Start of recursive call 45: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:35,555 INFO L267 ElimStorePlain]: Start of recursive call 44: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:35,661 INFO L267 ElimStorePlain]: Start of recursive call 43: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-02 14:10:36,486 INFO L267 ElimStorePlain]: Start of recursive call 27: 2 dim-1 vars, End of recursive call: and 7 xjuncts. [2018-12-02 14:10:37,431 INFO L267 ElimStorePlain]: Start of recursive call 20: 2 dim-1 vars, End of recursive call: and 8 xjuncts. [2018-12-02 14:10:38,460 INFO L267 ElimStorePlain]: Start of recursive call 12: 2 dim-1 vars, End of recursive call: and 9 xjuncts. [2018-12-02 14:10:39,636 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: and 10 xjuncts. [2018-12-02 14:10:40,796 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 10 xjuncts. [2018-12-02 14:10:41,953 INFO L701 Elim1Store]: detected not equals via solver [2018-12-02 14:10:41,956 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 18 [2018-12-02 14:10:41,956 INFO L267 ElimStorePlain]: Start of recursive call 48: End of recursive call: and 1 xjuncts. [2018-12-02 14:10:43,085 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-1 vars, 1 dim-2 vars, End of recursive call: 63 dim-0 vars, and 10 xjuncts. [2018-12-02 14:10:43,086 INFO L202 ElimStorePlain]: Needed 48 recursive calls to eliminate 9 variables, input treesize:181, output treesize:1832 [2018-12-02 14:11:41,998 WARN L194 Executor]: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000) stderr output: (error "out of memory") [2018-12-02 14:11:42,199 WARN L521 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 14:11:42,201 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:225) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.logic.Util.checkSat(Util.java:61) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.getRedundancy(SimplifyDDA.java:626) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getRedundancy(SimplifyDDAWithTimeout.java:122) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA$Simplifier.walk(SimplifyDDA.java:371) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.simplifyOnce(SimplifyDDA.java:650) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getSimplifiedTerm(SimplifyDDAWithTimeout.java:191) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SmtUtils.simplify(SmtUtils.java:151) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:354) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:299) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp$UnifyPostprocessor.postprocess(TraceCheckSpWp.java:575) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:439) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeStrongestPostconditionSequence(IterativePredicateTransformer.java:200) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:286) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:175) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:162) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructForwardBackward(TraceCheckConstructor.java:224) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructTraceCheck(TraceCheckConstructor.java:188) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:165) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.MultiTrackRefinementStrategy.getTraceCheck(MultiTrackRefinementStrategy.java:232) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:223) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:197) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:70) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:456) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:434) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:334) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:174) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1427) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:630) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:419) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:205) ... 45 more [2018-12-02 14:11:42,208 INFO L168 Benchmark]: Toolchain (without parser) took 147899.46 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 235.4 MB). Free memory was 951.7 MB in the beginning and 1.2 GB in the end (delta: -242.7 MB). Peak memory consumption was 403.2 MB. Max. memory is 11.5 GB. [2018-12-02 14:11:42,209 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 14:11:42,209 INFO L168 Benchmark]: CACSL2BoogieTranslator took 590.99 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 108.5 MB). Free memory was 951.7 MB in the beginning and 1.0 GB in the end (delta: -71.9 MB). Peak memory consumption was 50.5 MB. Max. memory is 11.5 GB. [2018-12-02 14:11:42,210 INFO L168 Benchmark]: Boogie Procedure Inliner took 28.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-02 14:11:42,210 INFO L168 Benchmark]: Boogie Preprocessor took 40.14 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-12-02 14:11:42,211 INFO L168 Benchmark]: RCFGBuilder took 587.23 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 949.6 MB in the end (delta: 66.0 MB). Peak memory consumption was 66.0 MB. Max. memory is 11.5 GB. [2018-12-02 14:11:42,211 INFO L168 Benchmark]: TraceAbstraction took 146649.34 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 126.9 MB). Free memory was 946.9 MB in the beginning and 1.2 GB in the end (delta: -247.5 MB). Peak memory consumption was 289.8 MB. Max. memory is 11.5 GB. [2018-12-02 14:11:42,215 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 590.99 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 108.5 MB). Free memory was 951.7 MB in the beginning and 1.0 GB in the end (delta: -71.9 MB). Peak memory consumption was 50.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 28.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 40.14 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 587.23 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 949.6 MB in the end (delta: 66.0 MB). Peak memory consumption was 66.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 146649.34 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 126.9 MB). Free memory was 946.9 MB in the beginning and 1.2 GB in the end (delta: -247.5 MB). Peak memory consumption was 289.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...