./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 532163d21d7e473fbfa4a073427e9fd2a45c7337 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-03 01:10:00,892 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-03 01:10:00,893 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-03 01:10:00,899 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-03 01:10:00,899 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-03 01:10:00,899 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-03 01:10:00,900 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-03 01:10:00,901 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-03 01:10:00,902 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-03 01:10:00,902 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-03 01:10:00,902 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-03 01:10:00,903 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-03 01:10:00,903 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-03 01:10:00,903 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-03 01:10:00,904 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-03 01:10:00,904 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-03 01:10:00,905 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-03 01:10:00,906 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-03 01:10:00,907 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-03 01:10:00,907 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-03 01:10:00,908 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-03 01:10:00,908 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-03 01:10:00,910 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-03 01:10:00,910 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-03 01:10:00,910 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-03 01:10:00,910 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-03 01:10:00,911 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-03 01:10:00,911 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-03 01:10:00,912 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-03 01:10:00,912 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-03 01:10:00,912 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-03 01:10:00,913 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-03 01:10:00,913 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-03 01:10:00,913 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-03 01:10:00,913 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-03 01:10:00,914 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-03 01:10:00,914 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-12-03 01:10:00,921 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-03 01:10:00,921 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-03 01:10:00,922 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-03 01:10:00,922 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-03 01:10:00,922 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-03 01:10:00,922 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-03 01:10:00,922 INFO L133 SettingsManager]: * Use SBE=true [2018-12-03 01:10:00,922 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-03 01:10:00,922 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-03 01:10:00,922 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-03 01:10:00,923 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-03 01:10:00,923 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-03 01:10:00,924 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-03 01:10:00,924 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 532163d21d7e473fbfa4a073427e9fd2a45c7337 [2018-12-03 01:10:00,942 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-03 01:10:00,950 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-03 01:10:00,953 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-03 01:10:00,954 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-03 01:10:00,954 INFO L276 PluginConnector]: CDTParser initialized [2018-12-03 01:10:00,955 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c [2018-12-03 01:10:00,995 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/data/ef079278d/7019a354d26743dcadba786189cae22f/FLAG5d16f3d45 [2018-12-03 01:10:01,380 INFO L307 CDTParser]: Found 1 translation units. [2018-12-03 01:10:01,380 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c [2018-12-03 01:10:01,385 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/data/ef079278d/7019a354d26743dcadba786189cae22f/FLAG5d16f3d45 [2018-12-03 01:10:01,395 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/data/ef079278d/7019a354d26743dcadba786189cae22f [2018-12-03 01:10:01,397 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-03 01:10:01,398 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-03 01:10:01,399 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-03 01:10:01,399 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-03 01:10:01,401 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-03 01:10:01,401 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,403 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4c1e788d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01, skipping insertion in model container [2018-12-03 01:10:01,404 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,409 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-03 01:10:01,428 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-03 01:10:01,534 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-03 01:10:01,537 INFO L191 MainTranslator]: Completed pre-run [2018-12-03 01:10:01,558 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-03 01:10:01,567 INFO L195 MainTranslator]: Completed translation [2018-12-03 01:10:01,568 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01 WrapperNode [2018-12-03 01:10:01,568 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-03 01:10:01,568 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-03 01:10:01,568 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-03 01:10:01,568 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-03 01:10:01,573 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,577 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,612 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-03 01:10:01,612 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-03 01:10:01,612 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-03 01:10:01,612 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-03 01:10:01,618 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,618 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,620 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,620 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,625 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,631 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,632 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... [2018-12-03 01:10:01,633 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-03 01:10:01,634 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-03 01:10:01,634 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-03 01:10:01,634 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-03 01:10:01,634 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-03 01:10:01,665 INFO L130 BoogieDeclarations]: Found specification of procedure P_1 [2018-12-03 01:10:01,666 INFO L138 BoogieDeclarations]: Found implementation of procedure P_1 [2018-12-03 01:10:01,666 INFO L130 BoogieDeclarations]: Found specification of procedure write_data [2018-12-03 01:10:01,666 INFO L138 BoogieDeclarations]: Found implementation of procedure write_data [2018-12-03 01:10:01,666 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-03 01:10:01,666 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-03 01:10:01,666 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-03 01:10:01,666 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-03 01:10:01,666 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-03 01:10:01,666 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-03 01:10:01,666 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-03 01:10:01,666 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-03 01:10:01,666 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-03 01:10:01,666 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-03 01:10:01,667 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-03 01:10:01,667 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-03 01:10:01,667 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-03 01:10:01,667 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-03 01:10:01,667 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-03 01:10:01,667 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-03 01:10:01,667 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-03 01:10:01,667 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-03 01:10:01,667 INFO L130 BoogieDeclarations]: Found specification of procedure is_P_1_triggered [2018-12-03 01:10:01,667 INFO L138 BoogieDeclarations]: Found implementation of procedure is_P_1_triggered [2018-12-03 01:10:01,667 INFO L130 BoogieDeclarations]: Found specification of procedure read_data [2018-12-03 01:10:01,667 INFO L138 BoogieDeclarations]: Found implementation of procedure read_data [2018-12-03 01:10:01,667 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-03 01:10:01,667 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-03 01:10:01,667 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-03 01:10:01,668 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-03 01:10:01,668 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-03 01:10:01,668 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-03 01:10:01,668 INFO L130 BoogieDeclarations]: Found specification of procedure C_1 [2018-12-03 01:10:01,668 INFO L138 BoogieDeclarations]: Found implementation of procedure C_1 [2018-12-03 01:10:01,668 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-03 01:10:01,668 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-03 01:10:01,668 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-03 01:10:01,668 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-03 01:10:01,668 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-03 01:10:01,668 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-03 01:10:01,668 INFO L130 BoogieDeclarations]: Found specification of procedure is_C_1_triggered [2018-12-03 01:10:01,668 INFO L138 BoogieDeclarations]: Found implementation of procedure is_C_1_triggered [2018-12-03 01:10:01,668 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-03 01:10:01,668 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-03 01:10:01,898 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-03 01:10:01,898 INFO L280 CfgBuilder]: Removed 4 assue(true) statements. [2018-12-03 01:10:01,898 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 01:10:01 BoogieIcfgContainer [2018-12-03 01:10:01,898 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-03 01:10:01,899 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-03 01:10:01,899 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-03 01:10:01,901 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-03 01:10:01,901 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.12 01:10:01" (1/3) ... [2018-12-03 01:10:01,901 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@178e39bb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.12 01:10:01, skipping insertion in model container [2018-12-03 01:10:01,902 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.12 01:10:01" (2/3) ... [2018-12-03 01:10:01,902 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@178e39bb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.12 01:10:01, skipping insertion in model container [2018-12-03 01:10:01,902 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 01:10:01" (3/3) ... [2018-12-03 01:10:01,903 INFO L112 eAbstractionObserver]: Analyzing ICFG kundu1_false-unreach-call_false-termination.cil.c [2018-12-03 01:10:01,909 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-03 01:10:01,914 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-03 01:10:01,923 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-03 01:10:01,943 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-03 01:10:01,943 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-03 01:10:01,943 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-03 01:10:01,943 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-03 01:10:01,943 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-03 01:10:01,943 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-03 01:10:01,943 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-03 01:10:01,944 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-03 01:10:01,944 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-03 01:10:01,956 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states. [2018-12-03 01:10:01,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-03 01:10:01,961 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:01,962 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:01,963 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:01,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:01,966 INFO L82 PathProgramCache]: Analyzing trace with hash -1385664965, now seen corresponding path program 1 times [2018-12-03 01:10:01,967 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:01,968 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:01,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:01,996 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:01,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:02,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:02,094 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:02,094 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-03 01:10:02,097 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-03 01:10:02,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-03 01:10:02,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:02,106 INFO L87 Difference]: Start difference. First operand 150 states. Second operand 4 states. [2018-12-03 01:10:02,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:02,217 INFO L93 Difference]: Finished difference Result 282 states and 384 transitions. [2018-12-03 01:10:02,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-03 01:10:02,218 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2018-12-03 01:10:02,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:02,229 INFO L225 Difference]: With dead ends: 282 [2018-12-03 01:10:02,229 INFO L226 Difference]: Without dead ends: 140 [2018-12-03 01:10:02,232 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:02,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-12-03 01:10:02,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-12-03 01:10:02,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-12-03 01:10:02,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 179 transitions. [2018-12-03 01:10:02,266 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 179 transitions. Word has length 72 [2018-12-03 01:10:02,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:02,267 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 179 transitions. [2018-12-03 01:10:02,267 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-03 01:10:02,267 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 179 transitions. [2018-12-03 01:10:02,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-03 01:10:02,269 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:02,269 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:02,269 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:02,269 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:02,269 INFO L82 PathProgramCache]: Analyzing trace with hash -1426339715, now seen corresponding path program 1 times [2018-12-03 01:10:02,269 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:02,269 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:02,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:02,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:02,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:02,346 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:02,347 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-03 01:10:02,348 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-03 01:10:02,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-03 01:10:02,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:02,349 INFO L87 Difference]: Start difference. First operand 140 states and 179 transitions. Second operand 4 states. [2018-12-03 01:10:02,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:02,481 INFO L93 Difference]: Finished difference Result 373 states and 490 transitions. [2018-12-03 01:10:02,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-03 01:10:02,482 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2018-12-03 01:10:02,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:02,484 INFO L225 Difference]: With dead ends: 373 [2018-12-03 01:10:02,485 INFO L226 Difference]: Without dead ends: 253 [2018-12-03 01:10:02,486 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:02,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states. [2018-12-03 01:10:02,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 238. [2018-12-03 01:10:02,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-12-03 01:10:02,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 301 transitions. [2018-12-03 01:10:02,514 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 301 transitions. Word has length 72 [2018-12-03 01:10:02,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:02,514 INFO L480 AbstractCegarLoop]: Abstraction has 238 states and 301 transitions. [2018-12-03 01:10:02,514 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-03 01:10:02,515 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 301 transitions. [2018-12-03 01:10:02,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-03 01:10:02,516 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:02,516 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:02,517 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:02,517 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:02,517 INFO L82 PathProgramCache]: Analyzing trace with hash 1691683492, now seen corresponding path program 1 times [2018-12-03 01:10:02,517 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:02,517 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:02,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,518 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:02,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:02,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:02,573 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:02,573 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-03 01:10:02,573 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-03 01:10:02,574 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-03 01:10:02,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:02,574 INFO L87 Difference]: Start difference. First operand 238 states and 301 transitions. Second operand 4 states. [2018-12-03 01:10:02,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:02,697 INFO L93 Difference]: Finished difference Result 573 states and 746 transitions. [2018-12-03 01:10:02,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-03 01:10:02,698 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2018-12-03 01:10:02,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:02,699 INFO L225 Difference]: With dead ends: 573 [2018-12-03 01:10:02,699 INFO L226 Difference]: Without dead ends: 355 [2018-12-03 01:10:02,701 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:02,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355 states. [2018-12-03 01:10:02,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355 to 339. [2018-12-03 01:10:02,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 339 states. [2018-12-03 01:10:02,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 339 states to 339 states and 428 transitions. [2018-12-03 01:10:02,722 INFO L78 Accepts]: Start accepts. Automaton has 339 states and 428 transitions. Word has length 73 [2018-12-03 01:10:02,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:02,722 INFO L480 AbstractCegarLoop]: Abstraction has 339 states and 428 transitions. [2018-12-03 01:10:02,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-03 01:10:02,722 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 428 transitions. [2018-12-03 01:10:02,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-03 01:10:02,723 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:02,723 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:02,723 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:02,723 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:02,723 INFO L82 PathProgramCache]: Analyzing trace with hash -73133117, now seen corresponding path program 1 times [2018-12-03 01:10:02,723 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:02,723 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:02,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,724 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:02,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:02,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:02,784 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:02,784 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-03 01:10:02,784 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-03 01:10:02,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-03 01:10:02,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-03 01:10:02,784 INFO L87 Difference]: Start difference. First operand 339 states and 428 transitions. Second operand 6 states. [2018-12-03 01:10:02,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:02,817 INFO L93 Difference]: Finished difference Result 688 states and 882 transitions. [2018-12-03 01:10:02,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 01:10:02,817 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-03 01:10:02,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:02,819 INFO L225 Difference]: With dead ends: 688 [2018-12-03 01:10:02,819 INFO L226 Difference]: Without dead ends: 369 [2018-12-03 01:10:02,820 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-03 01:10:02,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 369 states. [2018-12-03 01:10:02,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 354. [2018-12-03 01:10:02,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2018-12-03 01:10:02,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 443 transitions. [2018-12-03 01:10:02,839 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 443 transitions. Word has length 73 [2018-12-03 01:10:02,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:02,839 INFO L480 AbstractCegarLoop]: Abstraction has 354 states and 443 transitions. [2018-12-03 01:10:02,839 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-03 01:10:02,839 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 443 transitions. [2018-12-03 01:10:02,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-03 01:10:02,840 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:02,840 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:02,840 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:02,840 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:02,841 INFO L82 PathProgramCache]: Analyzing trace with hash -1444940415, now seen corresponding path program 1 times [2018-12-03 01:10:02,841 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:02,841 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:02,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,841 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:02,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:02,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:02,899 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:02,899 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-03 01:10:02,899 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-03 01:10:02,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-03 01:10:02,899 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-03 01:10:02,900 INFO L87 Difference]: Start difference. First operand 354 states and 443 transitions. Second operand 6 states. [2018-12-03 01:10:02,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:02,945 INFO L93 Difference]: Finished difference Result 702 states and 887 transitions. [2018-12-03 01:10:02,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-03 01:10:02,945 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-03 01:10:02,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:02,947 INFO L225 Difference]: With dead ends: 702 [2018-12-03 01:10:02,947 INFO L226 Difference]: Without dead ends: 368 [2018-12-03 01:10:02,948 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-03 01:10:02,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states. [2018-12-03 01:10:02,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 364. [2018-12-03 01:10:02,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2018-12-03 01:10:02,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 452 transitions. [2018-12-03 01:10:02,970 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 452 transitions. Word has length 73 [2018-12-03 01:10:02,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:02,971 INFO L480 AbstractCegarLoop]: Abstraction has 364 states and 452 transitions. [2018-12-03 01:10:02,971 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-03 01:10:02,971 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 452 transitions. [2018-12-03 01:10:02,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-03 01:10:02,972 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:02,972 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:02,972 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:02,972 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:02,973 INFO L82 PathProgramCache]: Analyzing trace with hash -1422308161, now seen corresponding path program 1 times [2018-12-03 01:10:02,973 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:02,973 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:02,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,974 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:02,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:02,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:03,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:03,030 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:03,030 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-03 01:10:03,030 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-03 01:10:03,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-03 01:10:03,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-03 01:10:03,031 INFO L87 Difference]: Start difference. First operand 364 states and 452 transitions. Second operand 6 states. [2018-12-03 01:10:03,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:03,105 INFO L93 Difference]: Finished difference Result 926 states and 1173 transitions. [2018-12-03 01:10:03,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-03 01:10:03,106 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-03 01:10:03,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:03,108 INFO L225 Difference]: With dead ends: 926 [2018-12-03 01:10:03,108 INFO L226 Difference]: Without dead ends: 583 [2018-12-03 01:10:03,110 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-03 01:10:03,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states. [2018-12-03 01:10:03,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 570. [2018-12-03 01:10:03,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 570 states. [2018-12-03 01:10:03,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 570 states to 570 states and 714 transitions. [2018-12-03 01:10:03,135 INFO L78 Accepts]: Start accepts. Automaton has 570 states and 714 transitions. Word has length 73 [2018-12-03 01:10:03,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:03,135 INFO L480 AbstractCegarLoop]: Abstraction has 570 states and 714 transitions. [2018-12-03 01:10:03,135 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-03 01:10:03,136 INFO L276 IsEmpty]: Start isEmpty. Operand 570 states and 714 transitions. [2018-12-03 01:10:03,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-03 01:10:03,137 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:03,137 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:03,137 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:03,137 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:03,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1577822909, now seen corresponding path program 1 times [2018-12-03 01:10:03,137 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:03,138 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:03,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:03,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:03,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:03,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:03,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:03,197 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:03,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-03 01:10:03,197 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-03 01:10:03,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-03 01:10:03,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-03 01:10:03,197 INFO L87 Difference]: Start difference. First operand 570 states and 714 transitions. Second operand 6 states. [2018-12-03 01:10:03,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:03,640 INFO L93 Difference]: Finished difference Result 1162 states and 1558 transitions. [2018-12-03 01:10:03,640 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-03 01:10:03,640 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 86 [2018-12-03 01:10:03,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:03,644 INFO L225 Difference]: With dead ends: 1162 [2018-12-03 01:10:03,644 INFO L226 Difference]: Without dead ends: 824 [2018-12-03 01:10:03,645 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2018-12-03 01:10:03,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 824 states. [2018-12-03 01:10:03,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 824 to 771. [2018-12-03 01:10:03,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 771 states. [2018-12-03 01:10:03,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 771 states and 1019 transitions. [2018-12-03 01:10:03,674 INFO L78 Accepts]: Start accepts. Automaton has 771 states and 1019 transitions. Word has length 86 [2018-12-03 01:10:03,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:03,674 INFO L480 AbstractCegarLoop]: Abstraction has 771 states and 1019 transitions. [2018-12-03 01:10:03,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-03 01:10:03,674 INFO L276 IsEmpty]: Start isEmpty. Operand 771 states and 1019 transitions. [2018-12-03 01:10:03,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-03 01:10:03,675 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:03,675 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:03,675 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:03,676 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:03,676 INFO L82 PathProgramCache]: Analyzing trace with hash -627422246, now seen corresponding path program 1 times [2018-12-03 01:10:03,676 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:03,676 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:03,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:03,677 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:03,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:03,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:03,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:03,749 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:03,749 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-12-03 01:10:03,750 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-03 01:10:03,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-03 01:10:03,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-12-03 01:10:03,750 INFO L87 Difference]: Start difference. First operand 771 states and 1019 transitions. Second operand 8 states. [2018-12-03 01:10:04,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:04,504 INFO L93 Difference]: Finished difference Result 1991 states and 2867 transitions. [2018-12-03 01:10:04,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-12-03 01:10:04,505 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 90 [2018-12-03 01:10:04,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:04,509 INFO L225 Difference]: With dead ends: 1991 [2018-12-03 01:10:04,510 INFO L226 Difference]: Without dead ends: 1466 [2018-12-03 01:10:04,511 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=44, Invalid=138, Unknown=0, NotChecked=0, Total=182 [2018-12-03 01:10:04,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2018-12-03 01:10:04,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1355. [2018-12-03 01:10:04,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1355 states. [2018-12-03 01:10:04,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1882 transitions. [2018-12-03 01:10:04,565 INFO L78 Accepts]: Start accepts. Automaton has 1355 states and 1882 transitions. Word has length 90 [2018-12-03 01:10:04,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:04,565 INFO L480 AbstractCegarLoop]: Abstraction has 1355 states and 1882 transitions. [2018-12-03 01:10:04,565 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-03 01:10:04,565 INFO L276 IsEmpty]: Start isEmpty. Operand 1355 states and 1882 transitions. [2018-12-03 01:10:04,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-12-03 01:10:04,566 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:04,566 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:04,566 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:04,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:04,566 INFO L82 PathProgramCache]: Analyzing trace with hash 1334723078, now seen corresponding path program 1 times [2018-12-03 01:10:04,566 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:04,567 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:04,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:04,567 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:04,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:04,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:04,588 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-03 01:10:04,588 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:04,588 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:04,595 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:04,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:04,641 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:04,662 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-03 01:10:04,687 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:04,687 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 3 [2018-12-03 01:10:04,688 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-03 01:10:04,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-03 01:10:04,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 01:10:04,688 INFO L87 Difference]: Start difference. First operand 1355 states and 1882 transitions. Second operand 3 states. [2018-12-03 01:10:04,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:04,825 INFO L93 Difference]: Finished difference Result 3840 states and 5897 transitions. [2018-12-03 01:10:04,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-03 01:10:04,826 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 92 [2018-12-03 01:10:04,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:04,833 INFO L225 Difference]: With dead ends: 3840 [2018-12-03 01:10:04,833 INFO L226 Difference]: Without dead ends: 2506 [2018-12-03 01:10:04,838 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 92 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-03 01:10:04,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2506 states. [2018-12-03 01:10:04,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2506 to 2502. [2018-12-03 01:10:04,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2502 states. [2018-12-03 01:10:04,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2502 states to 2502 states and 3704 transitions. [2018-12-03 01:10:04,940 INFO L78 Accepts]: Start accepts. Automaton has 2502 states and 3704 transitions. Word has length 92 [2018-12-03 01:10:04,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:04,941 INFO L480 AbstractCegarLoop]: Abstraction has 2502 states and 3704 transitions. [2018-12-03 01:10:04,941 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-03 01:10:04,941 INFO L276 IsEmpty]: Start isEmpty. Operand 2502 states and 3704 transitions. [2018-12-03 01:10:04,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-12-03 01:10:04,942 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:04,942 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:04,942 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:04,942 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:04,942 INFO L82 PathProgramCache]: Analyzing trace with hash -1839079452, now seen corresponding path program 1 times [2018-12-03 01:10:04,942 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:04,942 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:04,943 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:04,943 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:04,943 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:04,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:04,994 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-03 01:10:04,994 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:04,994 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:05,003 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:05,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:05,043 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:05,066 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:05,081 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:05,081 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-12-03 01:10:05,082 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-03 01:10:05,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-03 01:10:05,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-12-03 01:10:05,082 INFO L87 Difference]: Start difference. First operand 2502 states and 3704 transitions. Second operand 9 states. [2018-12-03 01:10:06,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:06,229 INFO L93 Difference]: Finished difference Result 6390 states and 10750 transitions. [2018-12-03 01:10:06,229 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-12-03 01:10:06,229 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 96 [2018-12-03 01:10:06,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:06,242 INFO L225 Difference]: With dead ends: 6390 [2018-12-03 01:10:06,243 INFO L226 Difference]: Without dead ends: 3909 [2018-12-03 01:10:06,257 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 105 SyntacticMatches, 3 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=90, Invalid=252, Unknown=0, NotChecked=0, Total=342 [2018-12-03 01:10:06,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3909 states. [2018-12-03 01:10:06,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3909 to 3843. [2018-12-03 01:10:06,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3843 states. [2018-12-03 01:10:06,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3843 states to 3843 states and 5464 transitions. [2018-12-03 01:10:06,404 INFO L78 Accepts]: Start accepts. Automaton has 3843 states and 5464 transitions. Word has length 96 [2018-12-03 01:10:06,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:06,404 INFO L480 AbstractCegarLoop]: Abstraction has 3843 states and 5464 transitions. [2018-12-03 01:10:06,404 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-03 01:10:06,404 INFO L276 IsEmpty]: Start isEmpty. Operand 3843 states and 5464 transitions. [2018-12-03 01:10:06,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-12-03 01:10:06,405 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:06,405 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:06,405 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:06,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:06,406 INFO L82 PathProgramCache]: Analyzing trace with hash -758498226, now seen corresponding path program 1 times [2018-12-03 01:10:06,406 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:06,406 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:06,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:06,406 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:06,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:06,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:06,456 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-03 01:10:06,456 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:06,456 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:06,463 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:06,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:06,514 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:06,540 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-03 01:10:06,562 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:06,562 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-12-03 01:10:06,562 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-03 01:10:06,562 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-03 01:10:06,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-03 01:10:06,562 INFO L87 Difference]: Start difference. First operand 3843 states and 5464 transitions. Second operand 8 states. [2018-12-03 01:10:08,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:08,294 INFO L93 Difference]: Finished difference Result 17414 states and 28965 transitions. [2018-12-03 01:10:08,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-12-03 01:10:08,294 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 94 [2018-12-03 01:10:08,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:08,356 INFO L225 Difference]: With dead ends: 17414 [2018-12-03 01:10:08,356 INFO L226 Difference]: Without dead ends: 12986 [2018-12-03 01:10:08,391 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=146, Invalid=360, Unknown=0, NotChecked=0, Total=506 [2018-12-03 01:10:08,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12986 states. [2018-12-03 01:10:08,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12986 to 10564. [2018-12-03 01:10:08,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10564 states. [2018-12-03 01:10:08,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10564 states to 10564 states and 14050 transitions. [2018-12-03 01:10:08,889 INFO L78 Accepts]: Start accepts. Automaton has 10564 states and 14050 transitions. Word has length 94 [2018-12-03 01:10:08,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:08,889 INFO L480 AbstractCegarLoop]: Abstraction has 10564 states and 14050 transitions. [2018-12-03 01:10:08,889 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-03 01:10:08,889 INFO L276 IsEmpty]: Start isEmpty. Operand 10564 states and 14050 transitions. [2018-12-03 01:10:08,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 166 [2018-12-03 01:10:08,897 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:08,897 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:08,897 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:08,897 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:08,897 INFO L82 PathProgramCache]: Analyzing trace with hash -100635213, now seen corresponding path program 1 times [2018-12-03 01:10:08,898 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:08,898 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:08,898 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:08,898 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:08,898 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:08,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:08,953 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 19 proven. 20 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-12-03 01:10:08,953 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:08,953 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:08,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:09,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:09,004 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:09,031 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 58 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-12-03 01:10:09,055 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:09,055 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-12-03 01:10:09,056 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-03 01:10:09,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-03 01:10:09,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-12-03 01:10:09,056 INFO L87 Difference]: Start difference. First operand 10564 states and 14050 transitions. Second operand 9 states. [2018-12-03 01:10:09,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:09,402 INFO L93 Difference]: Finished difference Result 17912 states and 23709 transitions. [2018-12-03 01:10:09,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-03 01:10:09,403 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 165 [2018-12-03 01:10:09,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:09,421 INFO L225 Difference]: With dead ends: 17912 [2018-12-03 01:10:09,421 INFO L226 Difference]: Without dead ends: 6739 [2018-12-03 01:10:09,434 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 168 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2018-12-03 01:10:09,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6739 states. [2018-12-03 01:10:09,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6739 to 6213. [2018-12-03 01:10:09,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6213 states. [2018-12-03 01:10:09,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6213 states to 6213 states and 7934 transitions. [2018-12-03 01:10:09,654 INFO L78 Accepts]: Start accepts. Automaton has 6213 states and 7934 transitions. Word has length 165 [2018-12-03 01:10:09,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:09,655 INFO L480 AbstractCegarLoop]: Abstraction has 6213 states and 7934 transitions. [2018-12-03 01:10:09,655 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-03 01:10:09,655 INFO L276 IsEmpty]: Start isEmpty. Operand 6213 states and 7934 transitions. [2018-12-03 01:10:09,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-12-03 01:10:09,662 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:09,662 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:09,662 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:09,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:09,663 INFO L82 PathProgramCache]: Analyzing trace with hash 1811941414, now seen corresponding path program 1 times [2018-12-03 01:10:09,663 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:09,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:09,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:09,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:09,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:09,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:09,716 INFO L134 CoverageAnalysis]: Checked inductivity of 101 backedges. 20 proven. 14 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2018-12-03 01:10:09,717 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:09,717 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:09,723 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:09,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:09,786 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:09,826 INFO L134 CoverageAnalysis]: Checked inductivity of 101 backedges. 69 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-12-03 01:10:09,841 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:09,841 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-03 01:10:09,842 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-03 01:10:09,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-03 01:10:09,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-03 01:10:09,842 INFO L87 Difference]: Start difference. First operand 6213 states and 7934 transitions. Second operand 6 states. [2018-12-03 01:10:10,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:10,792 INFO L93 Difference]: Finished difference Result 18019 states and 23767 transitions. [2018-12-03 01:10:10,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-03 01:10:10,792 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 170 [2018-12-03 01:10:10,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:10,816 INFO L225 Difference]: With dead ends: 18019 [2018-12-03 01:10:10,816 INFO L226 Difference]: Without dead ends: 8848 [2018-12-03 01:10:10,828 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 177 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-12-03 01:10:10,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8848 states. [2018-12-03 01:10:11,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8848 to 7075. [2018-12-03 01:10:11,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7075 states. [2018-12-03 01:10:11,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7075 states to 7075 states and 8944 transitions. [2018-12-03 01:10:11,155 INFO L78 Accepts]: Start accepts. Automaton has 7075 states and 8944 transitions. Word has length 170 [2018-12-03 01:10:11,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:11,155 INFO L480 AbstractCegarLoop]: Abstraction has 7075 states and 8944 transitions. [2018-12-03 01:10:11,156 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-03 01:10:11,156 INFO L276 IsEmpty]: Start isEmpty. Operand 7075 states and 8944 transitions. [2018-12-03 01:10:11,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-12-03 01:10:11,158 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:11,158 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:11,158 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:11,159 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:11,159 INFO L82 PathProgramCache]: Analyzing trace with hash -1118584665, now seen corresponding path program 1 times [2018-12-03 01:10:11,159 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:11,159 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:11,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:11,159 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:11,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:11,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:11,211 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-12-03 01:10:11,212 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:11,212 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-03 01:10:11,212 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 01:10:11,212 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 01:10:11,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-03 01:10:11,213 INFO L87 Difference]: Start difference. First operand 7075 states and 8944 transitions. Second operand 5 states. [2018-12-03 01:10:12,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:12,087 INFO L93 Difference]: Finished difference Result 19015 states and 26279 transitions. [2018-12-03 01:10:12,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-03 01:10:12,088 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 203 [2018-12-03 01:10:12,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:12,139 INFO L225 Difference]: With dead ends: 19015 [2018-12-03 01:10:12,139 INFO L226 Difference]: Without dead ends: 12533 [2018-12-03 01:10:12,152 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-03 01:10:12,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12533 states. [2018-12-03 01:10:12,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12533 to 10400. [2018-12-03 01:10:12,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10400 states. [2018-12-03 01:10:12,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10400 states to 10400 states and 13123 transitions. [2018-12-03 01:10:12,644 INFO L78 Accepts]: Start accepts. Automaton has 10400 states and 13123 transitions. Word has length 203 [2018-12-03 01:10:12,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:12,644 INFO L480 AbstractCegarLoop]: Abstraction has 10400 states and 13123 transitions. [2018-12-03 01:10:12,644 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 01:10:12,644 INFO L276 IsEmpty]: Start isEmpty. Operand 10400 states and 13123 transitions. [2018-12-03 01:10:12,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-12-03 01:10:12,647 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:12,647 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:12,647 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:12,647 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:12,647 INFO L82 PathProgramCache]: Analyzing trace with hash -1366731159, now seen corresponding path program 1 times [2018-12-03 01:10:12,647 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:12,648 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:12,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:12,648 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:12,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:12,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:12,730 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 4 proven. 41 refuted. 0 times theorem prover too weak. 101 trivial. 0 not checked. [2018-12-03 01:10:12,730 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:12,730 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:12,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:12,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:12,798 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:12,821 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 89 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2018-12-03 01:10:12,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:12,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-12-03 01:10:12,847 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-03 01:10:12,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-03 01:10:12,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-03 01:10:12,847 INFO L87 Difference]: Start difference. First operand 10400 states and 13123 transitions. Second operand 8 states. [2018-12-03 01:10:13,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:13,875 INFO L93 Difference]: Finished difference Result 19496 states and 25422 transitions. [2018-12-03 01:10:13,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-03 01:10:13,875 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 203 [2018-12-03 01:10:13,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:13,907 INFO L225 Difference]: With dead ends: 19496 [2018-12-03 01:10:13,907 INFO L226 Difference]: Without dead ends: 10331 [2018-12-03 01:10:13,922 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 214 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-12-03 01:10:13,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10331 states. [2018-12-03 01:10:14,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10331 to 9253. [2018-12-03 01:10:14,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9253 states. [2018-12-03 01:10:14,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9253 states to 9253 states and 11289 transitions. [2018-12-03 01:10:14,338 INFO L78 Accepts]: Start accepts. Automaton has 9253 states and 11289 transitions. Word has length 203 [2018-12-03 01:10:14,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:14,339 INFO L480 AbstractCegarLoop]: Abstraction has 9253 states and 11289 transitions. [2018-12-03 01:10:14,339 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-03 01:10:14,339 INFO L276 IsEmpty]: Start isEmpty. Operand 9253 states and 11289 transitions. [2018-12-03 01:10:14,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-12-03 01:10:14,341 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:14,341 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:14,341 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:14,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:14,341 INFO L82 PathProgramCache]: Analyzing trace with hash -555580108, now seen corresponding path program 1 times [2018-12-03 01:10:14,341 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:14,341 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:14,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:14,342 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:14,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:14,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:14,463 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 122 trivial. 0 not checked. [2018-12-03 01:10:14,463 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:14,463 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:14,471 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:14,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:14,522 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:14,605 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 109 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-12-03 01:10:14,620 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:14,620 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2018-12-03 01:10:14,621 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-03 01:10:14,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-03 01:10:14,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2018-12-03 01:10:14,621 INFO L87 Difference]: Start difference. First operand 9253 states and 11289 transitions. Second operand 12 states. [2018-12-03 01:10:16,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:16,501 INFO L93 Difference]: Finished difference Result 16386 states and 20206 transitions. [2018-12-03 01:10:16,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-12-03 01:10:16,502 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 204 [2018-12-03 01:10:16,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:16,518 INFO L225 Difference]: With dead ends: 16386 [2018-12-03 01:10:16,518 INFO L226 Difference]: Without dead ends: 7873 [2018-12-03 01:10:16,528 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 224 SyntacticMatches, 3 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=319, Invalid=1487, Unknown=0, NotChecked=0, Total=1806 [2018-12-03 01:10:16,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7873 states. [2018-12-03 01:10:16,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7873 to 7619. [2018-12-03 01:10:16,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7619 states. [2018-12-03 01:10:16,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7619 states to 7619 states and 9114 transitions. [2018-12-03 01:10:16,913 INFO L78 Accepts]: Start accepts. Automaton has 7619 states and 9114 transitions. Word has length 204 [2018-12-03 01:10:16,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:16,913 INFO L480 AbstractCegarLoop]: Abstraction has 7619 states and 9114 transitions. [2018-12-03 01:10:16,913 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-03 01:10:16,913 INFO L276 IsEmpty]: Start isEmpty. Operand 7619 states and 9114 transitions. [2018-12-03 01:10:16,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-12-03 01:10:16,915 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:16,915 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:16,915 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:16,916 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:16,916 INFO L82 PathProgramCache]: Analyzing trace with hash -371471122, now seen corresponding path program 1 times [2018-12-03 01:10:16,916 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:16,916 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:16,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:16,916 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:16,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:16,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:16,974 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 28 proven. 7 refuted. 0 times theorem prover too weak. 110 trivial. 0 not checked. [2018-12-03 01:10:16,974 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:16,974 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:16,982 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:17,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:17,043 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:17,067 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 96 proven. 0 refuted. 0 times theorem prover too weak. 49 trivial. 0 not checked. [2018-12-03 01:10:17,081 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:17,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-12-03 01:10:17,082 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-03 01:10:17,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-03 01:10:17,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-03 01:10:17,082 INFO L87 Difference]: Start difference. First operand 7619 states and 9114 transitions. Second operand 5 states. [2018-12-03 01:10:17,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:17,394 INFO L93 Difference]: Finished difference Result 11247 states and 13466 transitions. [2018-12-03 01:10:17,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-03 01:10:17,395 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 222 [2018-12-03 01:10:17,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:17,407 INFO L225 Difference]: With dead ends: 11247 [2018-12-03 01:10:17,408 INFO L226 Difference]: Without dead ends: 4999 [2018-12-03 01:10:17,416 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 223 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-03 01:10:17,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4999 states. [2018-12-03 01:10:17,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4999 to 4960. [2018-12-03 01:10:17,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4960 states. [2018-12-03 01:10:17,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4960 states to 4960 states and 5843 transitions. [2018-12-03 01:10:17,639 INFO L78 Accepts]: Start accepts. Automaton has 4960 states and 5843 transitions. Word has length 222 [2018-12-03 01:10:17,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:17,639 INFO L480 AbstractCegarLoop]: Abstraction has 4960 states and 5843 transitions. [2018-12-03 01:10:17,639 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-03 01:10:17,639 INFO L276 IsEmpty]: Start isEmpty. Operand 4960 states and 5843 transitions. [2018-12-03 01:10:17,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2018-12-03 01:10:17,641 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:17,641 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:17,641 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:17,641 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:17,641 INFO L82 PathProgramCache]: Analyzing trace with hash -591790388, now seen corresponding path program 1 times [2018-12-03 01:10:17,641 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:17,641 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:17,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:17,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:17,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:17,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:17,700 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 21 proven. 4 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2018-12-03 01:10:17,700 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:17,700 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:17,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:17,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:17,774 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:17,804 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 100 proven. 4 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-12-03 01:10:17,819 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-03 01:10:17,820 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 6 [2018-12-03 01:10:17,820 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-03 01:10:17,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-03 01:10:17,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-03 01:10:17,820 INFO L87 Difference]: Start difference. First operand 4960 states and 5843 transitions. Second operand 6 states. [2018-12-03 01:10:18,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:18,370 INFO L93 Difference]: Finished difference Result 9471 states and 10989 transitions. [2018-12-03 01:10:18,370 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-03 01:10:18,370 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 223 [2018-12-03 01:10:18,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:18,377 INFO L225 Difference]: With dead ends: 9471 [2018-12-03 01:10:18,377 INFO L226 Difference]: Without dead ends: 4944 [2018-12-03 01:10:18,380 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 239 GetRequests, 230 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-12-03 01:10:18,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4944 states. [2018-12-03 01:10:18,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4944 to 4939. [2018-12-03 01:10:18,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4939 states. [2018-12-03 01:10:18,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4939 states to 4939 states and 5743 transitions. [2018-12-03 01:10:18,591 INFO L78 Accepts]: Start accepts. Automaton has 4939 states and 5743 transitions. Word has length 223 [2018-12-03 01:10:18,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:18,591 INFO L480 AbstractCegarLoop]: Abstraction has 4939 states and 5743 transitions. [2018-12-03 01:10:18,592 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-03 01:10:18,592 INFO L276 IsEmpty]: Start isEmpty. Operand 4939 states and 5743 transitions. [2018-12-03 01:10:18,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-12-03 01:10:18,593 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:18,593 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:18,593 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:18,593 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:18,593 INFO L82 PathProgramCache]: Analyzing trace with hash 1743806793, now seen corresponding path program 1 times [2018-12-03 01:10:18,593 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:18,593 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:18,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:18,594 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:18,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:18,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:18,697 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 5 proven. 19 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2018-12-03 01:10:18,697 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:18,697 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:18,705 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:18,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:18,766 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:18,842 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 33 proven. 15 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2018-12-03 01:10:18,866 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-03 01:10:18,867 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8] total 14 [2018-12-03 01:10:18,867 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-03 01:10:18,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-03 01:10:18,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2018-12-03 01:10:18,867 INFO L87 Difference]: Start difference. First operand 4939 states and 5743 transitions. Second operand 14 states. [2018-12-03 01:10:20,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:20,703 INFO L93 Difference]: Finished difference Result 12136 states and 15047 transitions. [2018-12-03 01:10:20,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-12-03 01:10:20,703 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 222 [2018-12-03 01:10:20,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:20,728 INFO L225 Difference]: With dead ends: 12136 [2018-12-03 01:10:20,728 INFO L226 Difference]: Without dead ends: 8389 [2018-12-03 01:10:20,733 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 222 SyntacticMatches, 9 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=158, Invalid=598, Unknown=0, NotChecked=0, Total=756 [2018-12-03 01:10:20,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8389 states. [2018-12-03 01:10:21,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8389 to 7317. [2018-12-03 01:10:21,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7317 states. [2018-12-03 01:10:21,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7317 states to 7317 states and 8801 transitions. [2018-12-03 01:10:21,126 INFO L78 Accepts]: Start accepts. Automaton has 7317 states and 8801 transitions. Word has length 222 [2018-12-03 01:10:21,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:21,126 INFO L480 AbstractCegarLoop]: Abstraction has 7317 states and 8801 transitions. [2018-12-03 01:10:21,126 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-03 01:10:21,126 INFO L276 IsEmpty]: Start isEmpty. Operand 7317 states and 8801 transitions. [2018-12-03 01:10:21,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 303 [2018-12-03 01:10:21,129 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:21,130 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:21,130 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:21,130 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:21,130 INFO L82 PathProgramCache]: Analyzing trace with hash -1699067980, now seen corresponding path program 1 times [2018-12-03 01:10:21,130 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:21,130 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:21,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:21,131 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:21,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:21,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:21,167 INFO L134 CoverageAnalysis]: Checked inductivity of 436 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 400 trivial. 0 not checked. [2018-12-03 01:10:21,167 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:21,168 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-03 01:10:21,168 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-03 01:10:21,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-03 01:10:21,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:21,168 INFO L87 Difference]: Start difference. First operand 7317 states and 8801 transitions. Second operand 4 states. [2018-12-03 01:10:21,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:21,536 INFO L93 Difference]: Finished difference Result 7931 states and 9479 transitions. [2018-12-03 01:10:21,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-03 01:10:21,537 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 302 [2018-12-03 01:10:21,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:21,547 INFO L225 Difference]: With dead ends: 7931 [2018-12-03 01:10:21,547 INFO L226 Difference]: Without dead ends: 7266 [2018-12-03 01:10:21,550 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:21,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7266 states. [2018-12-03 01:10:21,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7266 to 7161. [2018-12-03 01:10:21,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7161 states. [2018-12-03 01:10:21,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7161 states to 7161 states and 8629 transitions. [2018-12-03 01:10:21,903 INFO L78 Accepts]: Start accepts. Automaton has 7161 states and 8629 transitions. Word has length 302 [2018-12-03 01:10:21,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:21,903 INFO L480 AbstractCegarLoop]: Abstraction has 7161 states and 8629 transitions. [2018-12-03 01:10:21,903 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-03 01:10:21,903 INFO L276 IsEmpty]: Start isEmpty. Operand 7161 states and 8629 transitions. [2018-12-03 01:10:21,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 311 [2018-12-03 01:10:21,906 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:21,906 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:21,907 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:21,907 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:21,907 INFO L82 PathProgramCache]: Analyzing trace with hash -180039545, now seen corresponding path program 1 times [2018-12-03 01:10:21,907 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:21,907 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:21,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:21,907 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:21,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:21,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:21,985 INFO L134 CoverageAnalysis]: Checked inductivity of 436 backedges. 87 proven. 0 refuted. 0 times theorem prover too weak. 349 trivial. 0 not checked. [2018-12-03 01:10:21,985 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-03 01:10:21,986 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-03 01:10:21,986 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-03 01:10:21,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-03 01:10:21,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:21,986 INFO L87 Difference]: Start difference. First operand 7161 states and 8629 transitions. Second operand 4 states. [2018-12-03 01:10:22,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:22,343 INFO L93 Difference]: Finished difference Result 12132 states and 14804 transitions. [2018-12-03 01:10:22,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-03 01:10:22,343 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 310 [2018-12-03 01:10:22,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:22,354 INFO L225 Difference]: With dead ends: 12132 [2018-12-03 01:10:22,355 INFO L226 Difference]: Without dead ends: 5370 [2018-12-03 01:10:22,363 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-03 01:10:22,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5370 states. [2018-12-03 01:10:22,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5370 to 5239. [2018-12-03 01:10:22,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5239 states. [2018-12-03 01:10:22,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5239 states to 5239 states and 6105 transitions. [2018-12-03 01:10:22,657 INFO L78 Accepts]: Start accepts. Automaton has 5239 states and 6105 transitions. Word has length 310 [2018-12-03 01:10:22,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:22,657 INFO L480 AbstractCegarLoop]: Abstraction has 5239 states and 6105 transitions. [2018-12-03 01:10:22,657 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-03 01:10:22,657 INFO L276 IsEmpty]: Start isEmpty. Operand 5239 states and 6105 transitions. [2018-12-03 01:10:22,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 345 [2018-12-03 01:10:22,659 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:22,659 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:22,660 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:22,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:22,660 INFO L82 PathProgramCache]: Analyzing trace with hash -948129435, now seen corresponding path program 1 times [2018-12-03 01:10:22,660 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:22,660 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:22,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:22,660 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:22,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:22,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:22,747 INFO L134 CoverageAnalysis]: Checked inductivity of 538 backedges. 46 proven. 23 refuted. 0 times theorem prover too weak. 469 trivial. 0 not checked. [2018-12-03 01:10:22,748 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-03 01:10:22,748 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-03 01:10:22,754 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:22,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-03 01:10:22,837 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-03 01:10:22,915 INFO L134 CoverageAnalysis]: Checked inductivity of 538 backedges. 236 proven. 0 refuted. 0 times theorem prover too weak. 302 trivial. 0 not checked. [2018-12-03 01:10:22,930 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-03 01:10:22,931 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [5] total 10 [2018-12-03 01:10:22,931 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-03 01:10:22,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-03 01:10:22,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-12-03 01:10:22,931 INFO L87 Difference]: Start difference. First operand 5239 states and 6105 transitions. Second operand 10 states. [2018-12-03 01:10:23,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-03 01:10:23,733 INFO L93 Difference]: Finished difference Result 12677 states and 15058 transitions. [2018-12-03 01:10:23,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-03 01:10:23,734 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 344 [2018-12-03 01:10:23,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-03 01:10:23,742 INFO L225 Difference]: With dead ends: 12677 [2018-12-03 01:10:23,742 INFO L226 Difference]: Without dead ends: 3838 [2018-12-03 01:10:23,750 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 345 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2018-12-03 01:10:23,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3838 states. [2018-12-03 01:10:23,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3838 to 3497. [2018-12-03 01:10:23,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3497 states. [2018-12-03 01:10:23,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3497 states to 3497 states and 3997 transitions. [2018-12-03 01:10:23,948 INFO L78 Accepts]: Start accepts. Automaton has 3497 states and 3997 transitions. Word has length 344 [2018-12-03 01:10:23,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-03 01:10:23,949 INFO L480 AbstractCegarLoop]: Abstraction has 3497 states and 3997 transitions. [2018-12-03 01:10:23,949 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-03 01:10:23,949 INFO L276 IsEmpty]: Start isEmpty. Operand 3497 states and 3997 transitions. [2018-12-03 01:10:23,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-12-03 01:10:23,952 INFO L394 BasicCegarLoop]: Found error trace [2018-12-03 01:10:23,952 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-03 01:10:23,952 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-03 01:10:23,952 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-03 01:10:23,952 INFO L82 PathProgramCache]: Analyzing trace with hash -1394352896, now seen corresponding path program 1 times [2018-12-03 01:10:23,953 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-03 01:10:23,953 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-03 01:10:23,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:23,953 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-03 01:10:23,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-03 01:10:23,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-03 01:10:23,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-03 01:10:24,069 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-03 01:10:24,163 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.12 01:10:24 BoogieIcfgContainer [2018-12-03 01:10:24,163 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-03 01:10:24,164 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-03 01:10:24,164 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-03 01:10:24,164 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-03 01:10:24,164 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.12 01:10:01" (3/4) ... [2018-12-03 01:10:24,166 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-03 01:10:24,263 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_fd8bd7f6-b883-4824-8249-8d2b417bab76/bin-2019/uautomizer/witness.graphml [2018-12-03 01:10:24,263 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-03 01:10:24,264 INFO L168 Benchmark]: Toolchain (without parser) took 22866.28 ms. Allocated memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: 1.5 GB). Free memory was 954.4 MB in the beginning and 828.5 MB in the end (delta: 125.9 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2018-12-03 01:10:24,264 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-03 01:10:24,264 INFO L168 Benchmark]: CACSL2BoogieTranslator took 169.20 ms. Allocated memory is still 1.0 GB. Free memory was 954.4 MB in the beginning and 941.0 MB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. [2018-12-03 01:10:24,265 INFO L168 Benchmark]: Boogie Procedure Inliner took 43.60 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 91.2 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -150.9 MB). Peak memory consumption was 15.8 MB. Max. memory is 11.5 GB. [2018-12-03 01:10:24,265 INFO L168 Benchmark]: Boogie Preprocessor took 21.50 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-03 01:10:24,265 INFO L168 Benchmark]: RCFGBuilder took 264.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 33.1 MB). Peak memory consumption was 33.1 MB. Max. memory is 11.5 GB. [2018-12-03 01:10:24,265 INFO L168 Benchmark]: TraceAbstraction took 22264.66 ms. Allocated memory was 1.1 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 1.1 GB in the beginning and 860.2 MB in the end (delta: 195.8 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2018-12-03 01:10:24,265 INFO L168 Benchmark]: Witness Printer took 99.54 ms. Allocated memory is still 2.5 GB. Free memory was 860.2 MB in the beginning and 828.5 MB in the end (delta: 31.7 MB). Peak memory consumption was 31.7 MB. Max. memory is 11.5 GB. [2018-12-03 01:10:24,266 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 169.20 ms. Allocated memory is still 1.0 GB. Free memory was 954.4 MB in the beginning and 941.0 MB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 43.60 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 91.2 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -150.9 MB). Peak memory consumption was 15.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 21.50 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 264.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 33.1 MB). Peak memory consumption was 33.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 22264.66 ms. Allocated memory was 1.1 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 1.1 GB in the beginning and 860.2 MB in the end (delta: 195.8 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. * Witness Printer took 99.54 ms. Allocated memory is still 2.5 GB. Free memory was 860.2 MB in the beginning and 828.5 MB in the end (delta: 31.7 MB). Peak memory consumption was 31.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int C_1_pc ; [L123] int C_1_st ; [L124] int C_1_i ; [L125] int C_1_ev ; [L126] int C_1_pr ; VAL [\old(C_1_ev)=76, \old(C_1_i)=68, \old(C_1_pc)=81, \old(C_1_pr)=78, \old(C_1_st)=80, \old(data_0)=74, \old(data_1)=67, \old(e)=66, \old(i)=70, \old(max_loop)=79, \old(num)=69, \old(P_1_ev)=71, \old(P_1_i)=77, \old(P_1_pc)=72, \old(P_1_st)=75, \old(timer)=73, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L490] int count ; [L491] int __retres2 ; [L495] num = 0 [L496] i = 0 [L497] max_loop = 2 [L499] timer = 0 [L500] P_1_pc = 0 [L501] C_1_pc = 0 [L503] count = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, count=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L504] CALL init_model() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L483] P_1_i = 1 [L484] C_1_i = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L504] RET init_model() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, count=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L505] CALL start_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L421] int kernel_st ; [L422] int tmp ; [L423] int tmp___0 ; [L427] kernel_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L428] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L429] CALL init_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L226] COND TRUE (int )P_1_i == 1 [L227] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L231] COND TRUE (int )C_1_i == 1 [L232] C_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L429] RET init_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L430] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L431] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, is_P_1_triggered()=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L189] COND FALSE !((int )C_1_pc == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, is_C_1_triggered()=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=0] [L431] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L432] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, exists_runnable_thread()=1, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___2=1] [L294] COND TRUE (int )C_1_st == 0 [L296] tmp___1 = __VERIFIER_nondet_int() [L298] COND TRUE \read(tmp___1) [L300] C_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=1, tmp___2=1] [L301] CALL C_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L128] char c ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L131] COND TRUE (int )C_1_pc == 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L146] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L148] COND TRUE num == 0 [L149] timer = 1 [L150] i += 1 [L151] C_1_pc = 1 [L152] C_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L301] RET C_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L72] COND TRUE (int )P_1_pc == 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(i___0)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(i___0)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, c=65, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, i___0=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L86] RET write_data(num, 'A') VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L286] RET P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=0] [L439] RET eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=2, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L443] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=2, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L447] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L448] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_P_1_triggered()=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___1=0] [L448] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L449] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L457] CALL fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L457] RET fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L458] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=1, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_P_1_triggered()=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1, tmp___1=0] [L458] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0] [L459] CALL reset_time_events() VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L459] RET reset_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0] [L465] CALL, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L417] return (__retres2); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L465] RET, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, stop_simulation()=0, timer=1, tmp=0] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1, tmp=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, i___0=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] RET write_data(num, 'A') VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L286] RET P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=0] [L439] RET eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L442] kernel_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L443] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L446] kernel_st = 3 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L447] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L448] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_P_1_triggered()=0, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___1=0] [L448] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L449] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L452] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L457] CALL fire_time_events() VAL [\old(C_1_ev)=2, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=2, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [\old(C_1_ev)=2, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=2, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L457] RET fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L458] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=1, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_P_1_triggered()=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1, tmp___1=0] [L458] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L459] CALL reset_time_events() VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L459] RET reset_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L465] CALL, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L417] return (__retres2); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L465] RET, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, stop_simulation()=0, timer=1, tmp=0, tmp___0=0] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1, tmp=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND FALSE !(i___0 == 1) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L56] CALL error() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L9] __VERIFIER_error() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 22 procedures, 150 locations, 1 error locations. UNSAFE Result, 22.2s OverallTime, 23 OverallIterations, 10 TraceHistogramMax, 14.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5923 SDtfs, 10234 SDslu, 8738 SDs, 0 SdLazy, 13489 SolverSat, 4794 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2395 GetRequests, 2152 SyntacticMatches, 26 SemanticMatches, 217 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 941 ImplicationChecksByTransitivity, 1.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=10564occurred in iteration=11, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 4.4s AutomataMinimizationTime, 22 MinimizatonAttempts, 10176 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 1.4s InterpolantComputationTime, 5857 NumberOfCodeBlocks, 5857 NumberOfCodeBlocksAsserted, 34 NumberOfCheckSat, 5464 ConstructedInterpolants, 0 QuantifiedInterpolants, 2006919 SizeOfPredicates, 20 NumberOfNonLiveVariables, 8251 ConjunctsInSsa, 97 ConjunctsInUnsatCore, 33 InterpolantComputations, 20 PerfectInterpolantSequences, 3869/4046 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...