./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i -s /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1b0573c26630ddc9e6f14ac761abccf9f58fcd1a .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i -s /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1b0573c26630ddc9e6f14ac761abccf9f58fcd1a .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN: Overapproximated counterexample --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-02 04:46:09,334 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-02 04:46:09,335 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-02 04:46:09,341 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-02 04:46:09,341 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-02 04:46:09,341 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-02 04:46:09,342 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-02 04:46:09,343 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-02 04:46:09,344 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-02 04:46:09,344 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-02 04:46:09,345 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-02 04:46:09,345 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-02 04:46:09,345 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-02 04:46:09,346 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-02 04:46:09,346 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-02 04:46:09,347 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-02 04:46:09,347 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-02 04:46:09,348 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-02 04:46:09,349 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-02 04:46:09,350 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-02 04:46:09,350 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-02 04:46:09,351 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-02 04:46:09,352 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-02 04:46:09,352 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 04:46:09,352 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 04:46:09,353 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 04:46:09,353 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 04:46:09,353 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 04:46:09,354 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 04:46:09,354 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 04:46:09,354 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 04:46:09,355 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 04:46:09,355 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 04:46:09,355 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 04:46:09,356 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 04:46:09,356 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 04:46:09,356 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/config/svcomp-Reach-64bit-Automizer_Default.epf [2018-12-02 04:46:09,363 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 04:46:09,363 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 04:46:09,364 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 04:46:09,364 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 04:46:09,364 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-02 04:46:09,365 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-02 04:46:09,365 INFO L133 SettingsManager]: * Use SBE=true [2018-12-02 04:46:09,365 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 04:46:09,365 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-02 04:46:09,365 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 04:46:09,365 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-02 04:46:09,365 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 04:46:09,365 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-02 04:46:09,366 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-02 04:46:09,366 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-02 04:46:09,366 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-02 04:46:09,366 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 04:46:09,366 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 04:46:09,366 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 04:46:09,366 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 04:46:09,366 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 04:46:09,367 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 04:46:09,367 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 04:46:09,367 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-02 04:46:09,367 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-02 04:46:09,367 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 04:46:09,367 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-02 04:46:09,367 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-02 04:46:09,367 INFO L133 SettingsManager]: * To the following directory=dump/ Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b0573c26630ddc9e6f14ac761abccf9f58fcd1a [2018-12-02 04:46:09,384 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 04:46:09,391 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 04:46:09,393 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 04:46:09,394 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 04:46:09,394 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 04:46:09,395 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-02 04:46:09,429 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data/38b2a460f/09dab454ff934622918a7f41c27e4fd3/FLAG91960ed06 [2018-12-02 04:46:09,893 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 04:46:09,894 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-02 04:46:09,904 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data/38b2a460f/09dab454ff934622918a7f41c27e4fd3/FLAG91960ed06 [2018-12-02 04:46:10,190 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data/38b2a460f/09dab454ff934622918a7f41c27e4fd3 [2018-12-02 04:46:10,196 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 04:46:10,199 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 04:46:10,201 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 04:46:10,201 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 04:46:10,208 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 04:46:10,209 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,215 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@51cb2369 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10, skipping insertion in model container [2018-12-02 04:46:10,215 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,230 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 04:46:10,294 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 04:46:10,743 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 04:46:10,760 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 04:46:10,854 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 04:46:10,891 INFO L195 MainTranslator]: Completed translation [2018-12-02 04:46:10,891 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10 WrapperNode [2018-12-02 04:46:10,891 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 04:46:10,892 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 04:46:10,892 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 04:46:10,892 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 04:46:10,897 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,919 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,927 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 04:46:10,927 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 04:46:10,927 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 04:46:10,927 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 04:46:10,933 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,933 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,939 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,940 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,964 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,970 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,976 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... [2018-12-02 04:46:10,982 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 04:46:10,983 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 04:46:10,983 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 04:46:10,983 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 04:46:10,984 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 04:46:11,018 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-12-02 04:46:11,018 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-12-02 04:46:11,018 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-12-02 04:46:11,018 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_get_drvdata [2018-12-02 04:46:11,018 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-12-02 04:46:11,019 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_unregister [2018-12-02 04:46:11,019 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-02 04:46:11,019 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-12-02 04:46:11,019 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-12-02 04:46:11,019 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-12-02 04:46:11,019 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-12-02 04:46:11,019 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-12-02 04:46:11,019 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize [2018-12-02 04:46:11,019 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-02 04:46:11,019 INFO L130 BoogieDeclarations]: Found specification of procedure external_alloc [2018-12-02 04:46:11,019 INFO L138 BoogieDeclarations]: Found implementation of procedure external_alloc [2018-12-02 04:46:11,019 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-12-02 04:46:11,019 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-12-02 04:46:11,019 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-12-02 04:46:11,020 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_time_to_tm [2018-12-02 04:46:11,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-12-02 04:46:11,020 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-12-02 04:46:11,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-12-02 04:46:11,020 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-12-02 04:46:11,020 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-12-02 04:46:11,020 INFO L138 BoogieDeclarations]: Found implementation of procedure irq_set_irq_wake [2018-12-02 04:46:11,020 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-12-02 04:46:11,020 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-12-02 04:46:11,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-12-02 04:46:11,020 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-12-02 04:46:11,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-12-02 04:46:11,020 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-12-02 04:46:11,020 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-12-02 04:46:11,020 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_tm_to_time [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_external_alloc [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-12-02 04:46:11,021 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-12-02 04:46:11,021 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-12-02 04:46:11,021 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-12-02 04:46:11,021 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-12-02 04:46:11,021 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-12-02 04:46:11,021 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_release_3 [2018-12-02 04:46:11,021 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-12-02 04:46:11,022 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-12-02 04:46:11,022 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-12-02 04:46:11,022 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-12-02 04:46:11,022 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-12-02 04:46:11,022 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-12-02 04:46:11,022 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-12-02 04:46:11,022 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-12-02 04:46:11,022 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-12-02 04:46:11,022 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-12-02 04:46:11,022 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-12-02 04:46:11,022 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_iounmap [2018-12-02 04:46:11,022 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-12-02 04:46:11,022 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_probe [2018-12-02 04:46:11,022 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-12-02 04:46:11,022 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_valid_tm [2018-12-02 04:46:11,023 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-12-02 04:46:11,023 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-12-02 04:46:11,023 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 04:46:11,023 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 04:46:11,023 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-12-02 04:46:11,023 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-12-02 04:46:11,023 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-12-02 04:46:11,023 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-12-02 04:46:11,023 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-12-02 04:46:11,023 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-12-02 04:46:11,023 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-12-02 04:46:11,023 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_update_irq [2018-12-02 04:46:11,023 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-12-02 04:46:11,023 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_unregister [2018-12-02 04:46:11,023 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 04:46:11,023 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-12-02 04:46:11,024 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-12-02 04:46:11,024 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-12-02 04:46:11,024 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-12-02 04:46:11,024 INFO L138 BoogieDeclarations]: Found implementation of procedure _raw_spin_unlock_irqrestore [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-12-02 04:46:11,024 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-12-02 04:46:11,024 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-12-02 04:46:11,024 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-12-02 04:46:11,024 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-12-02 04:46:11,024 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-12-02 04:46:11,025 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_resource [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-12-02 04:46:11,025 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_set_drvdata [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-12-02 04:46:11,025 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-12-02 04:46:11,025 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-12-02 04:46:11,025 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-12-02 04:46:11,025 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-12-02 04:46:11,025 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-12-02 04:46:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-12-02 04:46:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-12-02 04:46:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-12-02 04:46:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-12-02 04:46:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-12-02 04:46:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-12-02 04:46:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_3 [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-12-02 04:46:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_2 [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-12-02 04:46:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-12-02 04:46:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-12-02 04:46:11,027 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2018-12-02 04:46:11,027 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-12-02 04:46:11,027 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-12-02 04:46:11,027 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-12-02 04:46:11,027 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-12-02 04:46:11,027 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 04:46:11,027 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 04:46:11,771 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 04:46:11,772 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-12-02 04:46:11,772 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:11 BoogieIcfgContainer [2018-12-02 04:46:11,772 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 04:46:11,773 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 04:46:11,773 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 04:46:11,775 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 04:46:11,775 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 04:46:10" (1/3) ... [2018-12-02 04:46:11,775 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@72d24e1a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 04:46:11, skipping insertion in model container [2018-12-02 04:46:11,775 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:10" (2/3) ... [2018-12-02 04:46:11,776 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@72d24e1a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 04:46:11, skipping insertion in model container [2018-12-02 04:46:11,776 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:11" (3/3) ... [2018-12-02 04:46:11,777 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-02 04:46:11,783 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 04:46:11,789 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-02 04:46:11,799 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-02 04:46:11,819 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-02 04:46:11,819 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 04:46:11,819 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-02 04:46:11,819 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 04:46:11,819 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 04:46:11,819 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 04:46:11,819 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 04:46:11,820 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 04:46:11,820 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 04:46:11,836 INFO L276 IsEmpty]: Start isEmpty. Operand 486 states. [2018-12-02 04:46:11,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 04:46:11,844 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:11,844 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:11,846 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:11,849 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:11,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1646624460, now seen corresponding path program 1 times [2018-12-02 04:46:11,850 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:11,851 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:11,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:11,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:11,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:11,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:12,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:12,054 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:12,054 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:46:12,056 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:46:12,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:46:12,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:12,069 INFO L87 Difference]: Start difference. First operand 486 states. Second operand 3 states. [2018-12-02 04:46:12,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:12,141 INFO L93 Difference]: Finished difference Result 822 states and 1040 transitions. [2018-12-02 04:46:12,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:46:12,142 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-02 04:46:12,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:12,153 INFO L225 Difference]: With dead ends: 822 [2018-12-02 04:46:12,153 INFO L226 Difference]: Without dead ends: 331 [2018-12-02 04:46:12,157 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:12,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states. [2018-12-02 04:46:12,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 331. [2018-12-02 04:46:12,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 331 states. [2018-12-02 04:46:12,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 331 states to 331 states and 401 transitions. [2018-12-02 04:46:12,206 INFO L78 Accepts]: Start accepts. Automaton has 331 states and 401 transitions. Word has length 47 [2018-12-02 04:46:12,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:12,207 INFO L480 AbstractCegarLoop]: Abstraction has 331 states and 401 transitions. [2018-12-02 04:46:12,207 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:46:12,208 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 401 transitions. [2018-12-02 04:46:12,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-12-02 04:46:12,211 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:12,211 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:12,211 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:12,212 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:12,212 INFO L82 PathProgramCache]: Analyzing trace with hash -884307126, now seen corresponding path program 1 times [2018-12-02 04:46:12,212 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:12,212 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:12,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:12,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:12,326 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:12,326 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:12,326 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:12,327 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:12,328 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:12,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:12,328 INFO L87 Difference]: Start difference. First operand 331 states and 401 transitions. Second operand 5 states. [2018-12-02 04:46:12,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:12,442 INFO L93 Difference]: Finished difference Result 970 states and 1194 transitions. [2018-12-02 04:46:12,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 04:46:12,442 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-12-02 04:46:12,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:12,445 INFO L225 Difference]: With dead ends: 970 [2018-12-02 04:46:12,445 INFO L226 Difference]: Without dead ends: 656 [2018-12-02 04:46:12,447 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:12,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 656 states. [2018-12-02 04:46:12,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 656 to 643. [2018-12-02 04:46:12,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 643 states. [2018-12-02 04:46:12,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 786 transitions. [2018-12-02 04:46:12,476 INFO L78 Accepts]: Start accepts. Automaton has 643 states and 786 transitions. Word has length 70 [2018-12-02 04:46:12,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:12,476 INFO L480 AbstractCegarLoop]: Abstraction has 643 states and 786 transitions. [2018-12-02 04:46:12,476 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:12,476 INFO L276 IsEmpty]: Start isEmpty. Operand 643 states and 786 transitions. [2018-12-02 04:46:12,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-12-02 04:46:12,478 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:12,478 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:12,478 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:12,478 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:12,478 INFO L82 PathProgramCache]: Analyzing trace with hash -1544904286, now seen corresponding path program 1 times [2018-12-02 04:46:12,478 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:12,479 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:12,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,481 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:12,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:12,518 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:12,518 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:12,518 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:46:12,519 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:46:12,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:46:12,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:12,519 INFO L87 Difference]: Start difference. First operand 643 states and 786 transitions. Second operand 3 states. [2018-12-02 04:46:12,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:12,580 INFO L93 Difference]: Finished difference Result 1516 states and 1857 transitions. [2018-12-02 04:46:12,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:46:12,580 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2018-12-02 04:46:12,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:12,583 INFO L225 Difference]: With dead ends: 1516 [2018-12-02 04:46:12,583 INFO L226 Difference]: Without dead ends: 890 [2018-12-02 04:46:12,585 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:12,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 890 states. [2018-12-02 04:46:12,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 890 to 887. [2018-12-02 04:46:12,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 887 states. [2018-12-02 04:46:12,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 887 states to 887 states and 1086 transitions. [2018-12-02 04:46:12,611 INFO L78 Accepts]: Start accepts. Automaton has 887 states and 1086 transitions. Word has length 68 [2018-12-02 04:46:12,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:12,611 INFO L480 AbstractCegarLoop]: Abstraction has 887 states and 1086 transitions. [2018-12-02 04:46:12,611 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:46:12,612 INFO L276 IsEmpty]: Start isEmpty. Operand 887 states and 1086 transitions. [2018-12-02 04:46:12,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-12-02 04:46:12,612 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:12,613 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:12,613 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:12,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:12,613 INFO L82 PathProgramCache]: Analyzing trace with hash -1663745524, now seen corresponding path program 1 times [2018-12-02 04:46:12,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:12,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:12,615 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,615 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:12,615 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:12,665 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:12,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:12,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:12,666 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:12,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:12,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:12,666 INFO L87 Difference]: Start difference. First operand 887 states and 1086 transitions. Second operand 5 states. [2018-12-02 04:46:12,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:12,744 INFO L93 Difference]: Finished difference Result 1780 states and 2200 transitions. [2018-12-02 04:46:12,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:46:12,745 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2018-12-02 04:46:12,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:12,749 INFO L225 Difference]: With dead ends: 1780 [2018-12-02 04:46:12,749 INFO L226 Difference]: Without dead ends: 919 [2018-12-02 04:46:12,751 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:12,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states. [2018-12-02 04:46:12,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 895. [2018-12-02 04:46:12,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 895 states. [2018-12-02 04:46:12,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 895 states to 895 states and 1088 transitions. [2018-12-02 04:46:12,793 INFO L78 Accepts]: Start accepts. Automaton has 895 states and 1088 transitions. Word has length 71 [2018-12-02 04:46:12,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:12,794 INFO L480 AbstractCegarLoop]: Abstraction has 895 states and 1088 transitions. [2018-12-02 04:46:12,794 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:12,794 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 1088 transitions. [2018-12-02 04:46:12,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-02 04:46:12,795 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:12,796 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:12,796 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:12,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:12,796 INFO L82 PathProgramCache]: Analyzing trace with hash -1782427673, now seen corresponding path program 1 times [2018-12-02 04:46:12,796 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:12,796 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:12,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:12,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:12,869 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:12,870 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:12,870 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:12,870 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:12,870 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:12,870 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:12,870 INFO L87 Difference]: Start difference. First operand 895 states and 1088 transitions. Second operand 5 states. [2018-12-02 04:46:12,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:12,942 INFO L93 Difference]: Finished difference Result 1796 states and 2200 transitions. [2018-12-02 04:46:12,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:46:12,943 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2018-12-02 04:46:12,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:12,945 INFO L225 Difference]: With dead ends: 1796 [2018-12-02 04:46:12,945 INFO L226 Difference]: Without dead ends: 927 [2018-12-02 04:46:12,947 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:12,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states. [2018-12-02 04:46:12,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 903. [2018-12-02 04:46:12,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 903 states. [2018-12-02 04:46:12,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 903 states to 903 states and 1090 transitions. [2018-12-02 04:46:12,972 INFO L78 Accepts]: Start accepts. Automaton has 903 states and 1090 transitions. Word has length 72 [2018-12-02 04:46:12,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:12,972 INFO L480 AbstractCegarLoop]: Abstraction has 903 states and 1090 transitions. [2018-12-02 04:46:12,972 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:12,972 INFO L276 IsEmpty]: Start isEmpty. Operand 903 states and 1090 transitions. [2018-12-02 04:46:12,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-02 04:46:12,973 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:12,973 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:12,973 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:12,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:12,973 INFO L82 PathProgramCache]: Analyzing trace with hash 1402464713, now seen corresponding path program 1 times [2018-12-02 04:46:12,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:12,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:12,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:12,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:12,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:13,028 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:13,029 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:13,029 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:13,029 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:13,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:13,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:13,030 INFO L87 Difference]: Start difference. First operand 903 states and 1090 transitions. Second operand 5 states. [2018-12-02 04:46:13,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:13,109 INFO L93 Difference]: Finished difference Result 1707 states and 2078 transitions. [2018-12-02 04:46:13,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:46:13,110 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2018-12-02 04:46:13,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:13,113 INFO L225 Difference]: With dead ends: 1707 [2018-12-02 04:46:13,113 INFO L226 Difference]: Without dead ends: 830 [2018-12-02 04:46:13,115 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:13,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states. [2018-12-02 04:46:13,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 812. [2018-12-02 04:46:13,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-12-02 04:46:13,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 974 transitions. [2018-12-02 04:46:13,140 INFO L78 Accepts]: Start accepts. Automaton has 812 states and 974 transitions. Word has length 73 [2018-12-02 04:46:13,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:13,140 INFO L480 AbstractCegarLoop]: Abstraction has 812 states and 974 transitions. [2018-12-02 04:46:13,140 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:13,140 INFO L276 IsEmpty]: Start isEmpty. Operand 812 states and 974 transitions. [2018-12-02 04:46:13,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-12-02 04:46:13,141 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:13,142 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:13,142 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:13,142 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:13,142 INFO L82 PathProgramCache]: Analyzing trace with hash -1316738903, now seen corresponding path program 1 times [2018-12-02 04:46:13,142 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:13,142 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:13,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:13,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:13,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:13,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:13,237 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-02 04:46:13,238 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:46:13,238 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:46:13,248 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:13,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:13,341 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:13,374 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-02 04:46:13,400 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:46:13,400 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [9] total 11 [2018-12-02 04:46:13,400 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-12-02 04:46:13,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-12-02 04:46:13,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-12-02 04:46:13,400 INFO L87 Difference]: Start difference. First operand 812 states and 974 transitions. Second operand 11 states. [2018-12-02 04:46:15,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:15,047 INFO L93 Difference]: Finished difference Result 2158 states and 2676 transitions. [2018-12-02 04:46:15,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-02 04:46:15,047 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 85 [2018-12-02 04:46:15,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:15,052 INFO L225 Difference]: With dead ends: 2158 [2018-12-02 04:46:15,052 INFO L226 Difference]: Without dead ends: 1369 [2018-12-02 04:46:15,055 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=116, Invalid=436, Unknown=0, NotChecked=0, Total=552 [2018-12-02 04:46:15,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1369 states. [2018-12-02 04:46:15,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1369 to 1156. [2018-12-02 04:46:15,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1156 states. [2018-12-02 04:46:15,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1156 states to 1156 states and 1393 transitions. [2018-12-02 04:46:15,100 INFO L78 Accepts]: Start accepts. Automaton has 1156 states and 1393 transitions. Word has length 85 [2018-12-02 04:46:15,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:15,100 INFO L480 AbstractCegarLoop]: Abstraction has 1156 states and 1393 transitions. [2018-12-02 04:46:15,100 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-12-02 04:46:15,101 INFO L276 IsEmpty]: Start isEmpty. Operand 1156 states and 1393 transitions. [2018-12-02 04:46:15,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-12-02 04:46:15,102 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:15,102 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:15,102 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:15,102 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:15,102 INFO L82 PathProgramCache]: Analyzing trace with hash -179237916, now seen corresponding path program 1 times [2018-12-02 04:46:15,102 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:15,102 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:15,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:15,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:15,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:15,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:15,187 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-02 04:46:15,187 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:46:15,187 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:46:15,196 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:15,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:15,274 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:15,306 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:46:15,322 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:46:15,322 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5] total 13 [2018-12-02 04:46:15,322 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-12-02 04:46:15,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-12-02 04:46:15,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2018-12-02 04:46:15,323 INFO L87 Difference]: Start difference. First operand 1156 states and 1393 transitions. Second operand 13 states. [2018-12-02 04:46:15,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:15,990 INFO L93 Difference]: Finished difference Result 2675 states and 3235 transitions. [2018-12-02 04:46:15,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-12-02 04:46:15,991 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 87 [2018-12-02 04:46:15,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:15,994 INFO L225 Difference]: With dead ends: 2675 [2018-12-02 04:46:15,994 INFO L226 Difference]: Without dead ends: 1543 [2018-12-02 04:46:15,996 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=147, Invalid=609, Unknown=0, NotChecked=0, Total=756 [2018-12-02 04:46:15,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1543 states. [2018-12-02 04:46:16,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1543 to 1474. [2018-12-02 04:46:16,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1474 states. [2018-12-02 04:46:16,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1474 states to 1474 states and 1787 transitions. [2018-12-02 04:46:16,033 INFO L78 Accepts]: Start accepts. Automaton has 1474 states and 1787 transitions. Word has length 87 [2018-12-02 04:46:16,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:16,034 INFO L480 AbstractCegarLoop]: Abstraction has 1474 states and 1787 transitions. [2018-12-02 04:46:16,034 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-12-02 04:46:16,034 INFO L276 IsEmpty]: Start isEmpty. Operand 1474 states and 1787 transitions. [2018-12-02 04:46:16,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-12-02 04:46:16,035 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:16,036 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:16,036 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:16,036 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:16,036 INFO L82 PathProgramCache]: Analyzing trace with hash -505716382, now seen corresponding path program 1 times [2018-12-02 04:46:16,036 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:16,036 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:16,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:16,037 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:16,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:16,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:16,113 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-12-02 04:46:16,113 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:46:16,114 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:46:16,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:16,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:16,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:16,252 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:46:16,277 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:46:16,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 6] total 14 [2018-12-02 04:46:16,278 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-02 04:46:16,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-02 04:46:16,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2018-12-02 04:46:16,278 INFO L87 Difference]: Start difference. First operand 1474 states and 1787 transitions. Second operand 14 states. [2018-12-02 04:46:16,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:16,951 INFO L93 Difference]: Finished difference Result 3310 states and 4026 transitions. [2018-12-02 04:46:16,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-02 04:46:16,951 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 89 [2018-12-02 04:46:16,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:16,955 INFO L225 Difference]: With dead ends: 3310 [2018-12-02 04:46:16,955 INFO L226 Difference]: Without dead ends: 1861 [2018-12-02 04:46:16,957 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 109 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=162, Invalid=708, Unknown=0, NotChecked=0, Total=870 [2018-12-02 04:46:16,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1861 states. [2018-12-02 04:46:16,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1861 to 1475. [2018-12-02 04:46:16,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1475 states. [2018-12-02 04:46:16,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1475 states to 1475 states and 1788 transitions. [2018-12-02 04:46:16,995 INFO L78 Accepts]: Start accepts. Automaton has 1475 states and 1788 transitions. Word has length 89 [2018-12-02 04:46:16,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:16,995 INFO L480 AbstractCegarLoop]: Abstraction has 1475 states and 1788 transitions. [2018-12-02 04:46:16,995 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-02 04:46:16,995 INFO L276 IsEmpty]: Start isEmpty. Operand 1475 states and 1788 transitions. [2018-12-02 04:46:16,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-12-02 04:46:16,997 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:16,997 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:16,997 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:16,997 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:16,998 INFO L82 PathProgramCache]: Analyzing trace with hash -1680036611, now seen corresponding path program 1 times [2018-12-02 04:46:16,998 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:16,998 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:16,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:16,999 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:16,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:17,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:17,075 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-02 04:46:17,075 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 04:46:17,075 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 04:46:17,084 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:17,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:17,164 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:17,220 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 04:46:17,246 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:46:17,246 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7] total 15 [2018-12-02 04:46:17,247 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-02 04:46:17,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-02 04:46:17,247 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2018-12-02 04:46:17,247 INFO L87 Difference]: Start difference. First operand 1475 states and 1788 transitions. Second operand 15 states. [2018-12-02 04:46:17,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:17,811 INFO L93 Difference]: Finished difference Result 2867 states and 3473 transitions. [2018-12-02 04:46:17,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-02 04:46:17,811 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 91 [2018-12-02 04:46:17,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:17,814 INFO L225 Difference]: With dead ends: 2867 [2018-12-02 04:46:17,814 INFO L226 Difference]: Without dead ends: 1418 [2018-12-02 04:46:17,816 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=172, Invalid=758, Unknown=0, NotChecked=0, Total=930 [2018-12-02 04:46:17,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1418 states. [2018-12-02 04:46:17,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1418 to 402. [2018-12-02 04:46:17,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 402 states. [2018-12-02 04:46:17,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402 states to 402 states and 469 transitions. [2018-12-02 04:46:17,834 INFO L78 Accepts]: Start accepts. Automaton has 402 states and 469 transitions. Word has length 91 [2018-12-02 04:46:17,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:17,834 INFO L480 AbstractCegarLoop]: Abstraction has 402 states and 469 transitions. [2018-12-02 04:46:17,834 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-02 04:46:17,834 INFO L276 IsEmpty]: Start isEmpty. Operand 402 states and 469 transitions. [2018-12-02 04:46:17,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-12-02 04:46:17,835 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:17,835 INFO L402 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:17,835 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:17,835 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:17,835 INFO L82 PathProgramCache]: Analyzing trace with hash -389345042, now seen corresponding path program 1 times [2018-12-02 04:46:17,835 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:17,835 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:17,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:17,836 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:17,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:17,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:17,888 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-12-02 04:46:17,888 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:17,888 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:46:17,888 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:46:17,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:46:17,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:17,889 INFO L87 Difference]: Start difference. First operand 402 states and 469 transitions. Second operand 3 states. [2018-12-02 04:46:17,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:17,951 INFO L93 Difference]: Finished difference Result 856 states and 1016 transitions. [2018-12-02 04:46:17,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:46:17,952 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 101 [2018-12-02 04:46:17,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:17,953 INFO L225 Difference]: With dead ends: 856 [2018-12-02 04:46:17,954 INFO L226 Difference]: Without dead ends: 484 [2018-12-02 04:46:17,954 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:17,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 484 states. [2018-12-02 04:46:17,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 484 to 484. [2018-12-02 04:46:17,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-12-02 04:46:17,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 570 transitions. [2018-12-02 04:46:17,978 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 570 transitions. Word has length 101 [2018-12-02 04:46:17,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:17,978 INFO L480 AbstractCegarLoop]: Abstraction has 484 states and 570 transitions. [2018-12-02 04:46:17,978 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:46:17,978 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 570 transitions. [2018-12-02 04:46:17,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-12-02 04:46:17,979 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:17,979 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:17,980 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:17,980 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:17,980 INFO L82 PathProgramCache]: Analyzing trace with hash -14542213, now seen corresponding path program 1 times [2018-12-02 04:46:17,980 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:17,980 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:17,981 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:17,981 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:17,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:17,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:18,026 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-02 04:46:18,027 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:18,027 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:46:18,027 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:46:18,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:46:18,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:18,027 INFO L87 Difference]: Start difference. First operand 484 states and 570 transitions. Second operand 3 states. [2018-12-02 04:46:18,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:18,093 INFO L93 Difference]: Finished difference Result 1173 states and 1377 transitions. [2018-12-02 04:46:18,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:46:18,093 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 118 [2018-12-02 04:46:18,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:18,096 INFO L225 Difference]: With dead ends: 1173 [2018-12-02 04:46:18,096 INFO L226 Difference]: Without dead ends: 719 [2018-12-02 04:46:18,097 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:18,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 719 states. [2018-12-02 04:46:18,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 719 to 716. [2018-12-02 04:46:18,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 716 states. [2018-12-02 04:46:18,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 828 transitions. [2018-12-02 04:46:18,130 INFO L78 Accepts]: Start accepts. Automaton has 716 states and 828 transitions. Word has length 118 [2018-12-02 04:46:18,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:18,130 INFO L480 AbstractCegarLoop]: Abstraction has 716 states and 828 transitions. [2018-12-02 04:46:18,131 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:46:18,131 INFO L276 IsEmpty]: Start isEmpty. Operand 716 states and 828 transitions. [2018-12-02 04:46:18,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-12-02 04:46:18,132 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:18,132 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:18,132 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:18,132 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:18,132 INFO L82 PathProgramCache]: Analyzing trace with hash 1051230966, now seen corresponding path program 1 times [2018-12-02 04:46:18,133 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 04:46:18,133 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 04:46:18,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:18,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:18,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 04:46:18,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 04:46:18,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 04:46:18,269 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-02 04:46:18,293 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-12-02 04:46:18,329 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 194 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-02 04:46:18,330 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 192 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-02 04:46:18,330 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 234 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-02 04:46:18,330 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 226 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-02 04:46:18,341 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,342 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,342 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,343 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,344 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,349 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,349 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,350 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,350 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,355 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,355 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,356 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,356 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,357 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,357 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,358 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,358 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,358 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,359 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,359 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,359 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,360 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,360 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,360 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,360 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,361 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,361 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,361 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,361 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,362 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,362 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,362 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,362 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,363 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,363 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,364 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,364 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,364 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,365 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:18,390 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 04:46:18 BoogieIcfgContainer [2018-12-02 04:46:18,390 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-02 04:46:18,390 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-02 04:46:18,390 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-02 04:46:18,390 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-02 04:46:18,390 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:11" (3/4) ... [2018-12-02 04:46:18,393 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-12-02 04:46:18,393 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-02 04:46:18,393 INFO L168 Benchmark]: Toolchain (without parser) took 8196.77 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 355.5 MB). Free memory was 946.9 MB in the beginning and 1.1 GB in the end (delta: -172.6 MB). Peak memory consumption was 182.9 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:18,394 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 04:46:18,395 INFO L168 Benchmark]: CACSL2BoogieTranslator took 691.07 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.9 MB). Free memory was 946.9 MB in the beginning and 1.1 GB in the end (delta: -142.3 MB). Peak memory consumption was 52.6 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:18,395 INFO L168 Benchmark]: Boogie Procedure Inliner took 34.89 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:18,395 INFO L168 Benchmark]: Boogie Preprocessor took 55.63 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:18,396 INFO L168 Benchmark]: RCFGBuilder took 789.19 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 950.9 MB in the end (delta: 130.2 MB). Peak memory consumption was 130.2 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:18,396 INFO L168 Benchmark]: TraceAbstraction took 6617.13 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 217.6 MB). Free memory was 950.9 MB in the beginning and 1.1 GB in the end (delta: -168.5 MB). Peak memory consumption was 49.0 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:18,396 INFO L168 Benchmark]: Witness Printer took 3.01 ms. Allocated memory is still 1.4 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 04:46:18,399 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 691.07 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.9 MB). Free memory was 946.9 MB in the beginning and 1.1 GB in the end (delta: -142.3 MB). Peak memory consumption was 52.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 34.89 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 55.63 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 789.19 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 950.9 MB in the end (delta: 130.2 MB). Peak memory consumption was 130.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 6617.13 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 217.6 MB). Free memory was 950.9 MB in the beginning and 1.1 GB in the end (delta: -168.5 MB). Peak memory consumption was 49.0 MB. Max. memory is 11.5 GB. * Witness Printer took 3.01 ms. Allocated memory is still 1.4 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 194 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 192 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 234 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 226 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1664]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2219, overapproximation of bitwiseAnd at line 1830. Possible FailurePath: [L1687] int ldv_irq_1_2 = 0; [L1688] int LDV_IN_INTERRUPT = 1; [L1689] int ldv_irq_1_3 = 0; [L1690] struct platform_device *tegra_rtc_driver_group0 ; [L1691] void *ldv_irq_data_1_1 ; [L1692] int ldv_irq_1_1 = 0; [L1693] int ldv_irq_1_0 = 0; [L1694] int ldv_irq_line_1_3 ; [L1695] void *ldv_irq_data_1_0 ; [L1696] int ldv_state_variable_0 ; [L1697] struct device *tegra_rtc_ops_group1 ; [L1698] int ldv_state_variable_3 ; [L1699] int ldv_irq_line_1_0 ; [L1700] int ldv_state_variable_2 ; [L1701] void *ldv_irq_data_1_3 ; [L1702] int ref_cnt ; [L1703] int ldv_irq_line_1_1 ; [L1704] struct rtc_time *tegra_rtc_ops_group0 ; [L1705] void *ldv_irq_data_1_2 ; [L1706] int ldv_state_variable_1 ; [L1707] int ldv_irq_line_1_2 ; [L1708] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2050-L2052] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2218-L2219] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2235] int ldv_retval_2 ; [L2236] int ldv_retval_0 ; [L2238] int ldv_retval_1 ; [L2761] int ldv_init = 0; VAL [\old(LDV_IN_INTERRUPT)=172, \old(ldv_init)=198, \old(ldv_irq_1_0)=205, \old(ldv_irq_1_1)=197, \old(ldv_irq_1_2)=208, \old(ldv_irq_1_3)=196, \old(ldv_irq_data_1_0)=199, \old(ldv_irq_data_1_0)=161, \old(ldv_irq_data_1_1)=215, \old(ldv_irq_data_1_1)=187, \old(ldv_irq_data_1_2)=177, \old(ldv_irq_data_1_2)=191, \old(ldv_irq_data_1_3)=203, \old(ldv_irq_data_1_3)=154, \old(ldv_irq_line_1_0)=206, \old(ldv_irq_line_1_1)=233, \old(ldv_irq_line_1_2)=229, \old(ldv_irq_line_1_3)=167, \old(ldv_retval_0)=171, \old(ldv_retval_1)=164, \old(ldv_retval_2)=190, \old(ldv_state_variable_0)=186, \old(ldv_state_variable_1)=217, \old(ldv_state_variable_2)=209, \old(ldv_state_variable_3)=236, \old(ref_cnt)=204, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=224, \old(tegra_rtc_driver_group0)=200, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=180, \old(tegra_rtc_ops_group0)=202, \old(tegra_rtc_ops_group1)=221, \old(tegra_rtc_ops_group1)=195, \old(tegra_rtc_ops_group2)=157, \old(tegra_rtc_ops_group2)=174, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2390] struct seq_file *ldvarg1 ; [L2391] void *tmp ; [L2392] unsigned int ldvarg0 ; [L2393] unsigned int tmp___0 ; [L2394] pm_message_t ldvarg2 ; [L2395] int tmp___1 ; [L2396] int tmp___2 ; [L2397] int tmp___3 ; [L2398] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result={0:0}, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2400] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] tmp = ldv_zalloc(136U) [L2401] ldvarg1 = (struct seq_file *)tmp [L2402] tmp___0 = __VERIFIER_nondet_uint() [L2403] ldvarg0 = tmp___0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179] [L2404] FCALL ldv_initialize() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179] [L2405] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, memset((void *)(& ldvarg2), 0, 4U)={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179] [L2406] ldv_state_variable_1 = 1 [L2407] ref_cnt = 0 [L2408] ldv_state_variable_0 = 1 [L2409] ldv_state_variable_3 = 0 [L2410] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1] [L2421] COND TRUE ldv_state_variable_0 != 0 [L2422] tmp___2 = __VERIFIER_nondet_int() [L2424] case 0: [L2432] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2433] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2434] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2222] int tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] CALL, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={211:0}, arg1={-1:11}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2842] return __VERIFIER_nondet_int(); [L2224] RET, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe)=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2225] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2434] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2434] ldv_retval_0 = tegra_rtc_init() [L2435] COND TRUE ldv_retval_0 == 0 [L2436] ldv_state_variable_0 = 3 [L2437] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2438] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2355] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result={0:0}, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2357] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] tmp = ldv_zalloc(624U) [L2358] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2438] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2441] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=1, tmp___2=1] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: [L2566] case 1: [L2576] case 2: [L2596] case 3: [L2606] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2607] COND TRUE ldv_state_variable_2 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2608] CALL ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2830] return __VERIFIER_nondet_int(); [L2608] RET ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_probe_2()=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2609] ldv_state_variable_2 = 2 [L2610] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=4] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=0] [L2555] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=0] [L2560] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=179, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=179, tmp___1=3, tmp___2=1, tmp___4=0] [L2561] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2214] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1952] struct tegra_rtc_info *info ; [L1953] void *tmp ; [L1954] unsigned int status ; [L1955] unsigned long sl_irq_flags ; [L1956] u32 __v ; [L1957] u32 __v___0 ; VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_external_alloc(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={0:12}, arg0={0:12}, external_alloc()={182:228}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1959] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={182:228}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] tmp = dev_get_drvdata((struct device const *)dev) [L1960] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, enabled=0, info={182:228}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={182:228}] [L1961] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1835] struct tegra_rtc_info *info ; [L1836] void *tmp ; [L1837] int retries ; [L1838] int tmp___0 ; [L1839] u32 tmp___1 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_external_alloc(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, arg0={0:12}, arg0={0:12}, external_alloc()={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1841] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] tmp = dev_get_drvdata((struct device const *)dev) [L1842] info = (struct tegra_rtc_info *)tmp [L1843] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={165:0}] [L1854] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1825] u32 __v ; [L1826] u32 __v___0 ; [L1828] EXPR info->rtc_base [L1828] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1828] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1829] __v = __v___0 [L1830] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, __v=156, __v___0=156, info={165:0}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1854] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={165:0}] [L1854] tmp___1 = tegra_rtc_check_busy(info) [L1855] COND FALSE !(tmp___1 != 0U) [L1859] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result=0, __this_module={162:201}, dev={0:12}, dev={0:12}, info={165:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={165:0}, tmp___1=0] [L1961] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, dev={0:12}, dev={0:12}, enabled=0, info={182:228}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={182:228}] [L1962] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2775] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2777] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1664] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:201}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={211:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 65 procedures, 488 locations, 1 error locations. UNSAFE Result, 6.5s OverallTime, 13 OverallIterations, 4 TraceHistogramMax, 4.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5095 SDtfs, 6528 SDslu, 18164 SDs, 0 SdLazy, 4405 SolverSat, 1524 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 513 GetRequests, 380 SyntacticMatches, 0 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 383 ImplicationChecksByTransitivity, 1.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1475occurred in iteration=9, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 12 MinimizatonAttempts, 1769 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 1443 NumberOfCodeBlocks, 1443 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 1308 ConstructedInterpolants, 0 QuantifiedInterpolants, 150756 SizeOfPredicates, 4 NumberOfNonLiveVariables, 3756 ConjunctsInSsa, 18 ConjunctsInUnsatCore, 16 InterpolantComputations, 9 PerfectInterpolantSequences, 221/250 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-635dfa2 [2018-12-02 04:46:19,731 INFO L170 SettingsManager]: Resetting all preferences to default values... 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[2018-12-02 04:46:19,749 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 04:46:19,749 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 04:46:19,750 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 04:46:19,750 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 04:46:19,751 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 04:46:19,751 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 04:46:19,751 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 04:46:19,752 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 04:46:19,752 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 04:46:19,752 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 04:46:19,752 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 04:46:19,753 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 04:46:19,753 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 04:46:19,753 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2018-12-02 04:46:19,760 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 04:46:19,760 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 04:46:19,761 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 04:46:19,761 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 04:46:19,761 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-02 04:46:19,761 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-02 04:46:19,761 INFO L133 SettingsManager]: * Use SBE=true [2018-12-02 04:46:19,761 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 04:46:19,761 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-02 04:46:19,762 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 04:46:19,762 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 04:46:19,763 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * Command for external solver=cvc4 --incremental --rewrite-divk --print-success --lang smt [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-02 04:46:19,763 INFO L133 SettingsManager]: * To the following directory=dump/ Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b0573c26630ddc9e6f14ac761abccf9f58fcd1a [2018-12-02 04:46:19,781 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 04:46:19,788 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 04:46:19,790 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 04:46:19,791 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 04:46:19,791 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 04:46:19,791 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-02 04:46:19,827 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data/2f28a6b8f/fe34b00886b04c7085f225a91a2a0958/FLAGd2d45a54e [2018-12-02 04:46:20,368 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 04:46:20,368 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-02 04:46:20,379 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data/2f28a6b8f/fe34b00886b04c7085f225a91a2a0958/FLAGd2d45a54e [2018-12-02 04:46:20,861 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/data/2f28a6b8f/fe34b00886b04c7085f225a91a2a0958 [2018-12-02 04:46:20,863 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 04:46:20,864 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 04:46:20,865 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 04:46:20,865 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 04:46:20,867 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 04:46:20,868 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 04:46:20" (1/1) ... [2018-12-02 04:46:20,869 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@47abe2bb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:20, skipping insertion in model container [2018-12-02 04:46:20,870 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 04:46:20" (1/1) ... [2018-12-02 04:46:20,874 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 04:46:20,909 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 04:46:21,291 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 04:46:21,369 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 04:46:21,442 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 04:46:21,478 INFO L195 MainTranslator]: Completed translation [2018-12-02 04:46:21,479 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21 WrapperNode [2018-12-02 04:46:21,479 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 04:46:21,479 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 04:46:21,479 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 04:46:21,479 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 04:46:21,484 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,501 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,508 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 04:46:21,508 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 04:46:21,508 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 04:46:21,508 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 04:46:21,514 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,514 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,519 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,520 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,539 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,544 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,548 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... [2018-12-02 04:46:21,552 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 04:46:21,553 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 04:46:21,553 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 04:46:21,553 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 04:46:21,553 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 04:46:21,592 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-12-02 04:46:21,593 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-12-02 04:46:21,593 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-12-02 04:46:21,593 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_get_drvdata [2018-12-02 04:46:21,593 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1 [2018-12-02 04:46:21,593 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-12-02 04:46:21,593 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_unregister [2018-12-02 04:46:21,593 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE8 [2018-12-02 04:46:21,593 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-02 04:46:21,594 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-12-02 04:46:21,594 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-12-02 04:46:21,594 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-12-02 04:46:21,594 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-12-02 04:46:21,594 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-12-02 04:46:21,594 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-12-02 04:46:21,594 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize [2018-12-02 04:46:21,594 INFO L130 BoogieDeclarations]: Found specification of procedure external_alloc [2018-12-02 04:46:21,594 INFO L138 BoogieDeclarations]: Found implementation of procedure external_alloc [2018-12-02 04:46:21,595 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-12-02 04:46:21,595 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-12-02 04:46:21,595 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-12-02 04:46:21,595 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_time_to_tm [2018-12-02 04:46:21,595 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-12-02 04:46:21,595 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-12-02 04:46:21,595 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-12-02 04:46:21,595 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-12-02 04:46:21,595 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-12-02 04:46:21,595 INFO L138 BoogieDeclarations]: Found implementation of procedure irq_set_irq_wake [2018-12-02 04:46:21,595 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-12-02 04:46:21,596 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-12-02 04:46:21,596 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-12-02 04:46:21,596 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-12-02 04:46:21,596 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-12-02 04:46:21,596 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-12-02 04:46:21,596 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-12-02 04:46:21,596 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_tm_to_time [2018-12-02 04:46:21,596 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_external_alloc [2018-12-02 04:46:21,596 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-12-02 04:46:21,596 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2018-12-02 04:46:21,596 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-12-02 04:46:21,597 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2018-12-02 04:46:21,597 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-12-02 04:46:21,597 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2018-12-02 04:46:21,597 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-12-02 04:46:21,597 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-12-02 04:46:21,597 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-12-02 04:46:21,597 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-12-02 04:46:21,597 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-12-02 04:46:21,597 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_release_3 [2018-12-02 04:46:21,597 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-12-02 04:46:21,597 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-12-02 04:46:21,597 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-12-02 04:46:21,598 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-12-02 04:46:21,598 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-12-02 04:46:21,598 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-12-02 04:46:21,598 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-12-02 04:46:21,598 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-12-02 04:46:21,598 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-12-02 04:46:21,598 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-12-02 04:46:21,598 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-12-02 04:46:21,598 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_iounmap [2018-12-02 04:46:21,598 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-12-02 04:46:21,599 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_probe [2018-12-02 04:46:21,599 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-12-02 04:46:21,599 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_valid_tm [2018-12-02 04:46:21,599 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-12-02 04:46:21,599 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-12-02 04:46:21,599 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 04:46:21,599 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 04:46:21,599 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-12-02 04:46:21,599 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-12-02 04:46:21,599 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-12-02 04:46:21,599 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-12-02 04:46:21,600 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-12-02 04:46:21,600 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-12-02 04:46:21,600 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-12-02 04:46:21,600 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_update_irq [2018-12-02 04:46:21,600 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-12-02 04:46:21,600 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_unregister [2018-12-02 04:46:21,600 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 04:46:21,600 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 04:46:21,600 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-12-02 04:46:21,600 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2018-12-02 04:46:21,600 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-12-02 04:46:21,600 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-12-02 04:46:21,601 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-12-02 04:46:21,601 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-12-02 04:46:21,601 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-12-02 04:46:21,601 INFO L138 BoogieDeclarations]: Found implementation of procedure _raw_spin_unlock_irqrestore [2018-12-02 04:46:21,601 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-12-02 04:46:21,601 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-12-02 04:46:21,601 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-12-02 04:46:21,601 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-12-02 04:46:21,601 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-12-02 04:46:21,601 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-12-02 04:46:21,601 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-12-02 04:46:21,601 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-12-02 04:46:21,602 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-12-02 04:46:21,602 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-12-02 04:46:21,602 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_resource [2018-12-02 04:46:21,602 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE8 [2018-12-02 04:46:21,602 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1 [2018-12-02 04:46:21,602 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-12-02 04:46:21,602 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-02 04:46:21,602 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-12-02 04:46:21,602 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_set_drvdata [2018-12-02 04:46:21,602 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-12-02 04:46:21,602 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-12-02 04:46:21,602 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-12-02 04:46:21,603 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-12-02 04:46:21,603 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-12-02 04:46:21,603 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-12-02 04:46:21,603 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-12-02 04:46:21,603 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1 [2018-12-02 04:46:21,603 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-12-02 04:46:21,603 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-12-02 04:46:21,603 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-12-02 04:46:21,603 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-12-02 04:46:21,603 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-12-02 04:46:21,603 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-12-02 04:46:21,603 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-12-02 04:46:21,604 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-12-02 04:46:21,604 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-12-02 04:46:21,604 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-12-02 04:46:21,604 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-12-02 04:46:21,604 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-12-02 04:46:21,604 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-12-02 04:46:21,604 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-12-02 04:46:21,604 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-12-02 04:46:21,604 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_3 [2018-12-02 04:46:21,604 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-12-02 04:46:21,604 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_2 [2018-12-02 04:46:21,604 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-12-02 04:46:21,605 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-12-02 04:46:21,605 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-12-02 04:46:21,605 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2018-12-02 04:46:21,605 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-12-02 04:46:21,605 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-12-02 04:46:21,605 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-12-02 04:46:21,605 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-12-02 04:46:21,605 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 04:46:21,605 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 04:46:24,539 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 04:46:24,539 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-12-02 04:46:24,540 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:24 BoogieIcfgContainer [2018-12-02 04:46:24,540 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 04:46:24,541 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 04:46:24,541 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 04:46:24,543 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 04:46:24,544 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 04:46:20" (1/3) ... [2018-12-02 04:46:24,544 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@22cb6dd0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 04:46:24, skipping insertion in model container [2018-12-02 04:46:24,545 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 04:46:21" (2/3) ... [2018-12-02 04:46:24,545 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@22cb6dd0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 04:46:24, skipping insertion in model container [2018-12-02 04:46:24,545 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:24" (3/3) ... [2018-12-02 04:46:24,546 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-02 04:46:24,555 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 04:46:24,562 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-02 04:46:24,576 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-02 04:46:24,602 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-02 04:46:24,603 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 04:46:24,603 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-02 04:46:24,603 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 04:46:24,603 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 04:46:24,603 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 04:46:24,603 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 04:46:24,603 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 04:46:24,603 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 04:46:24,625 INFO L276 IsEmpty]: Start isEmpty. Operand 486 states. [2018-12-02 04:46:24,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 04:46:24,632 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:24,633 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:24,635 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:24,640 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:24,640 INFO L82 PathProgramCache]: Analyzing trace with hash 1646624460, now seen corresponding path program 1 times [2018-12-02 04:46:24,644 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:24,645 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:24,664 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:24,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:24,789 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:24,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 04:46:24,822 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:24,826 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:24,826 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:46:24,829 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:46:24,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:46:24,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:24,843 INFO L87 Difference]: Start difference. First operand 486 states. Second operand 3 states. [2018-12-02 04:46:24,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:24,923 INFO L93 Difference]: Finished difference Result 822 states and 1040 transitions. [2018-12-02 04:46:24,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:46:24,925 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-02 04:46:24,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:24,934 INFO L225 Difference]: With dead ends: 822 [2018-12-02 04:46:24,934 INFO L226 Difference]: Without dead ends: 331 [2018-12-02 04:46:24,938 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:24,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states. [2018-12-02 04:46:24,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 331. [2018-12-02 04:46:24,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 331 states. [2018-12-02 04:46:24,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 331 states to 331 states and 401 transitions. [2018-12-02 04:46:24,980 INFO L78 Accepts]: Start accepts. Automaton has 331 states and 401 transitions. Word has length 47 [2018-12-02 04:46:24,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:24,981 INFO L480 AbstractCegarLoop]: Abstraction has 331 states and 401 transitions. [2018-12-02 04:46:24,981 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:46:24,981 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 401 transitions. [2018-12-02 04:46:24,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-12-02 04:46:24,983 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:24,984 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:24,984 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:24,984 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:24,984 INFO L82 PathProgramCache]: Analyzing trace with hash -884307126, now seen corresponding path program 1 times [2018-12-02 04:46:24,985 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:24,985 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:25,002 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:25,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:25,111 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:25,145 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:25,145 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:25,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:25,148 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:25,149 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:25,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:25,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:25,149 INFO L87 Difference]: Start difference. First operand 331 states and 401 transitions. Second operand 5 states. [2018-12-02 04:46:25,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:25,269 INFO L93 Difference]: Finished difference Result 970 states and 1194 transitions. [2018-12-02 04:46:25,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 04:46:25,269 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-12-02 04:46:25,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:25,274 INFO L225 Difference]: With dead ends: 970 [2018-12-02 04:46:25,274 INFO L226 Difference]: Without dead ends: 656 [2018-12-02 04:46:25,276 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:25,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 656 states. [2018-12-02 04:46:25,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 656 to 643. [2018-12-02 04:46:25,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 643 states. [2018-12-02 04:46:25,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 786 transitions. [2018-12-02 04:46:25,322 INFO L78 Accepts]: Start accepts. Automaton has 643 states and 786 transitions. Word has length 70 [2018-12-02 04:46:25,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:25,322 INFO L480 AbstractCegarLoop]: Abstraction has 643 states and 786 transitions. [2018-12-02 04:46:25,322 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:25,323 INFO L276 IsEmpty]: Start isEmpty. Operand 643 states and 786 transitions. [2018-12-02 04:46:25,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-12-02 04:46:25,325 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:25,326 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:25,326 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:25,326 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:25,326 INFO L82 PathProgramCache]: Analyzing trace with hash -1663745524, now seen corresponding path program 1 times [2018-12-02 04:46:25,327 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:25,327 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:25,345 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:25,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:25,467 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:25,489 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:25,489 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:25,491 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:25,491 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:25,491 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:25,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:25,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:25,491 INFO L87 Difference]: Start difference. First operand 643 states and 786 transitions. Second operand 5 states. [2018-12-02 04:46:25,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:25,578 INFO L93 Difference]: Finished difference Result 1285 states and 1586 transitions. [2018-12-02 04:46:25,579 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:46:25,579 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2018-12-02 04:46:25,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:25,582 INFO L225 Difference]: With dead ends: 1285 [2018-12-02 04:46:25,582 INFO L226 Difference]: Without dead ends: 659 [2018-12-02 04:46:25,583 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:25,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2018-12-02 04:46:25,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 647. [2018-12-02 04:46:25,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 647 states. [2018-12-02 04:46:25,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 647 states to 647 states and 786 transitions. [2018-12-02 04:46:25,613 INFO L78 Accepts]: Start accepts. Automaton has 647 states and 786 transitions. Word has length 71 [2018-12-02 04:46:25,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:25,614 INFO L480 AbstractCegarLoop]: Abstraction has 647 states and 786 transitions. [2018-12-02 04:46:25,614 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:25,614 INFO L276 IsEmpty]: Start isEmpty. Operand 647 states and 786 transitions. [2018-12-02 04:46:25,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-12-02 04:46:25,616 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:25,616 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:25,616 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:25,616 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:25,616 INFO L82 PathProgramCache]: Analyzing trace with hash -1544904286, now seen corresponding path program 1 times [2018-12-02 04:46:25,617 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:25,617 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:25,643 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:25,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:25,741 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:25,750 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:25,750 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:25,752 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:25,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:46:25,752 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:46:25,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:46:25,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:25,752 INFO L87 Difference]: Start difference. First operand 647 states and 786 transitions. Second operand 3 states. [2018-12-02 04:46:25,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:25,826 INFO L93 Difference]: Finished difference Result 1528 states and 1859 transitions. [2018-12-02 04:46:25,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:46:25,826 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2018-12-02 04:46:25,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:25,829 INFO L225 Difference]: With dead ends: 1528 [2018-12-02 04:46:25,830 INFO L226 Difference]: Without dead ends: 898 [2018-12-02 04:46:25,831 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:25,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 898 states. [2018-12-02 04:46:25,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 898 to 895. [2018-12-02 04:46:25,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 895 states. [2018-12-02 04:46:25,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 895 states to 895 states and 1088 transitions. [2018-12-02 04:46:25,861 INFO L78 Accepts]: Start accepts. Automaton has 895 states and 1088 transitions. Word has length 68 [2018-12-02 04:46:25,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:25,861 INFO L480 AbstractCegarLoop]: Abstraction has 895 states and 1088 transitions. [2018-12-02 04:46:25,861 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:46:25,862 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 1088 transitions. [2018-12-02 04:46:25,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-02 04:46:25,863 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:25,863 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:25,863 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:25,863 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:25,864 INFO L82 PathProgramCache]: Analyzing trace with hash -1782427673, now seen corresponding path program 1 times [2018-12-02 04:46:25,864 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:25,864 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:25,881 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:25,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:25,968 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:25,985 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:25,985 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:25,987 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:25,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:25,987 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:25,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:25,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:25,988 INFO L87 Difference]: Start difference. First operand 895 states and 1088 transitions. Second operand 5 states. [2018-12-02 04:46:26,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:26,062 INFO L93 Difference]: Finished difference Result 1796 states and 2200 transitions. [2018-12-02 04:46:26,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:46:26,063 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2018-12-02 04:46:26,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:26,066 INFO L225 Difference]: With dead ends: 1796 [2018-12-02 04:46:26,066 INFO L226 Difference]: Without dead ends: 927 [2018-12-02 04:46:26,068 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:26,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states. [2018-12-02 04:46:26,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 903. [2018-12-02 04:46:26,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 903 states. [2018-12-02 04:46:26,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 903 states to 903 states and 1090 transitions. [2018-12-02 04:46:26,096 INFO L78 Accepts]: Start accepts. Automaton has 903 states and 1090 transitions. Word has length 72 [2018-12-02 04:46:26,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:26,097 INFO L480 AbstractCegarLoop]: Abstraction has 903 states and 1090 transitions. [2018-12-02 04:46:26,097 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:26,097 INFO L276 IsEmpty]: Start isEmpty. Operand 903 states and 1090 transitions. [2018-12-02 04:46:26,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-02 04:46:26,098 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:26,098 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:26,098 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:26,098 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:26,098 INFO L82 PathProgramCache]: Analyzing trace with hash 1402464713, now seen corresponding path program 1 times [2018-12-02 04:46:26,098 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:26,098 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:26,115 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:26,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:26,228 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:26,258 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:26,258 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:26,260 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:26,260 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 04:46:26,261 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 04:46:26,261 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 04:46:26,261 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:26,261 INFO L87 Difference]: Start difference. First operand 903 states and 1090 transitions. Second operand 5 states. [2018-12-02 04:46:26,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:26,364 INFO L93 Difference]: Finished difference Result 1707 states and 2078 transitions. [2018-12-02 04:46:26,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-02 04:46:26,365 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2018-12-02 04:46:26,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:26,368 INFO L225 Difference]: With dead ends: 1707 [2018-12-02 04:46:26,368 INFO L226 Difference]: Without dead ends: 830 [2018-12-02 04:46:26,371 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 69 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:26,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states. [2018-12-02 04:46:26,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 812. [2018-12-02 04:46:26,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-12-02 04:46:26,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 974 transitions. [2018-12-02 04:46:26,402 INFO L78 Accepts]: Start accepts. Automaton has 812 states and 974 transitions. Word has length 73 [2018-12-02 04:46:26,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:26,402 INFO L480 AbstractCegarLoop]: Abstraction has 812 states and 974 transitions. [2018-12-02 04:46:26,402 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 04:46:26,402 INFO L276 IsEmpty]: Start isEmpty. Operand 812 states and 974 transitions. [2018-12-02 04:46:26,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-12-02 04:46:26,403 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:26,404 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:26,404 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:26,404 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:26,404 INFO L82 PathProgramCache]: Analyzing trace with hash -1316738903, now seen corresponding path program 1 times [2018-12-02 04:46:26,404 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:26,404 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:26,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:26,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:26,548 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:26,610 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-02 04:46:26,611 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:46:26,795 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-02 04:46:26,797 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 04:46:26,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 13 [2018-12-02 04:46:26,797 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-12-02 04:46:26,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-12-02 04:46:26,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-12-02 04:46:26,798 INFO L87 Difference]: Start difference. First operand 812 states and 974 transitions. Second operand 13 states. [2018-12-02 04:46:29,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:29,193 INFO L93 Difference]: Finished difference Result 2154 states and 2671 transitions. [2018-12-02 04:46:29,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-02 04:46:29,194 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 85 [2018-12-02 04:46:29,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:29,197 INFO L225 Difference]: With dead ends: 2154 [2018-12-02 04:46:29,197 INFO L226 Difference]: Without dead ends: 1368 [2018-12-02 04:46:29,199 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 158 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=152, Invalid=498, Unknown=0, NotChecked=0, Total=650 [2018-12-02 04:46:29,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1368 states. [2018-12-02 04:46:29,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1368 to 1155. [2018-12-02 04:46:29,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1155 states. [2018-12-02 04:46:29,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1155 states to 1155 states and 1392 transitions. [2018-12-02 04:46:29,236 INFO L78 Accepts]: Start accepts. Automaton has 1155 states and 1392 transitions. Word has length 85 [2018-12-02 04:46:29,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:29,236 INFO L480 AbstractCegarLoop]: Abstraction has 1155 states and 1392 transitions. [2018-12-02 04:46:29,236 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-12-02 04:46:29,236 INFO L276 IsEmpty]: Start isEmpty. Operand 1155 states and 1392 transitions. [2018-12-02 04:46:29,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-02 04:46:29,237 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:29,237 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:29,237 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:29,237 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:29,237 INFO L82 PathProgramCache]: Analyzing trace with hash 1516400962, now seen corresponding path program 1 times [2018-12-02 04:46:29,238 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:29,238 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:29,262 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:29,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:29,362 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:29,436 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:29,436 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:46:29,616 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:29,619 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:46:29,619 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 14 [2018-12-02 04:46:29,619 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-02 04:46:29,619 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-02 04:46:29,620 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-02 04:46:29,620 INFO L87 Difference]: Start difference. First operand 1155 states and 1392 transitions. Second operand 14 states. [2018-12-02 04:46:31,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:31,002 INFO L93 Difference]: Finished difference Result 2670 states and 3229 transitions. [2018-12-02 04:46:31,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-12-02 04:46:31,003 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 86 [2018-12-02 04:46:31,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:31,008 INFO L225 Difference]: With dead ends: 2670 [2018-12-02 04:46:31,008 INFO L226 Difference]: Without dead ends: 1541 [2018-12-02 04:46:31,011 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 182 GetRequests, 159 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-12-02 04:46:31,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1541 states. [2018-12-02 04:46:31,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1541 to 1472. [2018-12-02 04:46:31,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1472 states. [2018-12-02 04:46:31,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1472 states to 1472 states and 1785 transitions. [2018-12-02 04:46:31,059 INFO L78 Accepts]: Start accepts. Automaton has 1472 states and 1785 transitions. Word has length 86 [2018-12-02 04:46:31,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:31,060 INFO L480 AbstractCegarLoop]: Abstraction has 1472 states and 1785 transitions. [2018-12-02 04:46:31,060 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-02 04:46:31,060 INFO L276 IsEmpty]: Start isEmpty. Operand 1472 states and 1785 transitions. [2018-12-02 04:46:31,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-12-02 04:46:31,061 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:31,061 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:31,061 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:31,061 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:31,062 INFO L82 PathProgramCache]: Analyzing trace with hash -2059129438, now seen corresponding path program 1 times [2018-12-02 04:46:31,062 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:31,062 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 10 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:31,087 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:31,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:31,183 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:31,243 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:31,243 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:46:31,368 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:31,370 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:46:31,370 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 14 [2018-12-02 04:46:31,370 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-02 04:46:31,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-02 04:46:31,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-02 04:46:31,371 INFO L87 Difference]: Start difference. First operand 1472 states and 1785 transitions. Second operand 14 states. [2018-12-02 04:46:33,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:33,016 INFO L93 Difference]: Finished difference Result 3304 states and 4019 transitions. [2018-12-02 04:46:33,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-12-02 04:46:33,017 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 87 [2018-12-02 04:46:33,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:33,020 INFO L225 Difference]: With dead ends: 3304 [2018-12-02 04:46:33,020 INFO L226 Difference]: Without dead ends: 1858 [2018-12-02 04:46:33,023 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 161 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-12-02 04:46:33,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1858 states. [2018-12-02 04:46:33,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1858 to 1472. [2018-12-02 04:46:33,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1472 states. [2018-12-02 04:46:33,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1472 states to 1472 states and 1785 transitions. [2018-12-02 04:46:33,096 INFO L78 Accepts]: Start accepts. Automaton has 1472 states and 1785 transitions. Word has length 87 [2018-12-02 04:46:33,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:33,096 INFO L480 AbstractCegarLoop]: Abstraction has 1472 states and 1785 transitions. [2018-12-02 04:46:33,096 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-02 04:46:33,096 INFO L276 IsEmpty]: Start isEmpty. Operand 1472 states and 1785 transitions. [2018-12-02 04:46:33,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-12-02 04:46:33,098 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:33,098 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:33,098 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:33,098 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:33,098 INFO L82 PathProgramCache]: Analyzing trace with hash 1854992155, now seen corresponding path program 1 times [2018-12-02 04:46:33,099 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:33,099 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:33,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:33,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:33,251 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:33,316 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:33,317 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:46:33,490 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:33,493 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:46:33,493 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 14 [2018-12-02 04:46:33,493 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-02 04:46:33,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-02 04:46:33,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-02 04:46:33,494 INFO L87 Difference]: Start difference. First operand 1472 states and 1785 transitions. Second operand 14 states. [2018-12-02 04:46:34,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:34,498 INFO L93 Difference]: Finished difference Result 2860 states and 3465 transitions. [2018-12-02 04:46:34,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-02 04:46:34,499 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 88 [2018-12-02 04:46:34,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:34,502 INFO L225 Difference]: With dead ends: 2860 [2018-12-02 04:46:34,502 INFO L226 Difference]: Without dead ends: 1414 [2018-12-02 04:46:34,504 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 163 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2018-12-02 04:46:34,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states. [2018-12-02 04:46:34,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 398. [2018-12-02 04:46:34,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 398 states. [2018-12-02 04:46:34,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 398 states to 398 states and 465 transitions. [2018-12-02 04:46:34,530 INFO L78 Accepts]: Start accepts. Automaton has 398 states and 465 transitions. Word has length 88 [2018-12-02 04:46:34,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:34,530 INFO L480 AbstractCegarLoop]: Abstraction has 398 states and 465 transitions. [2018-12-02 04:46:34,530 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-02 04:46:34,530 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states and 465 transitions. [2018-12-02 04:46:34,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-12-02 04:46:34,531 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:34,532 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:34,532 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:34,532 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:34,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1289094802, now seen corresponding path program 1 times [2018-12-02 04:46:34,532 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:34,532 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 12 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:34,556 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:34,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:34,664 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:34,672 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 04:46:34,672 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:34,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:34,674 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:46:34,674 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:46:34,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:46:34,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:34,674 INFO L87 Difference]: Start difference. First operand 398 states and 465 transitions. Second operand 3 states. [2018-12-02 04:46:34,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:34,775 INFO L93 Difference]: Finished difference Result 852 states and 1012 transitions. [2018-12-02 04:46:34,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:46:34,776 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 97 [2018-12-02 04:46:34,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:34,777 INFO L225 Difference]: With dead ends: 852 [2018-12-02 04:46:34,777 INFO L226 Difference]: Without dead ends: 480 [2018-12-02 04:46:34,778 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:34,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states. [2018-12-02 04:46:34,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2018-12-02 04:46:34,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2018-12-02 04:46:34,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 566 transitions. [2018-12-02 04:46:34,803 INFO L78 Accepts]: Start accepts. Automaton has 480 states and 566 transitions. Word has length 97 [2018-12-02 04:46:34,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:34,803 INFO L480 AbstractCegarLoop]: Abstraction has 480 states and 566 transitions. [2018-12-02 04:46:34,804 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:46:34,804 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 566 transitions. [2018-12-02 04:46:34,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-12-02 04:46:34,805 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:34,805 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:34,805 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:34,805 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:34,805 INFO L82 PathProgramCache]: Analyzing trace with hash -94289413, now seen corresponding path program 1 times [2018-12-02 04:46:34,806 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:34,806 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:34,831 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:34,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:34,961 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:34,974 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-02 04:46:34,974 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:34,976 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:34,976 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 04:46:34,976 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 04:46:34,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 04:46:34,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:34,977 INFO L87 Difference]: Start difference. First operand 480 states and 566 transitions. Second operand 3 states. [2018-12-02 04:46:35,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:35,134 INFO L93 Difference]: Finished difference Result 1169 states and 1373 transitions. [2018-12-02 04:46:35,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 04:46:35,134 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2018-12-02 04:46:35,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:35,136 INFO L225 Difference]: With dead ends: 1169 [2018-12-02 04:46:35,136 INFO L226 Difference]: Without dead ends: 715 [2018-12-02 04:46:35,137 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 04:46:35,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2018-12-02 04:46:35,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 712. [2018-12-02 04:46:35,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 712 states. [2018-12-02 04:46:35,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 712 states to 712 states and 824 transitions. [2018-12-02 04:46:35,183 INFO L78 Accepts]: Start accepts. Automaton has 712 states and 824 transitions. Word has length 114 [2018-12-02 04:46:35,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:35,183 INFO L480 AbstractCegarLoop]: Abstraction has 712 states and 824 transitions. [2018-12-02 04:46:35,183 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 04:46:35,183 INFO L276 IsEmpty]: Start isEmpty. Operand 712 states and 824 transitions. [2018-12-02 04:46:35,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-02 04:46:35,184 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:35,184 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:35,184 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:35,184 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:35,184 INFO L82 PathProgramCache]: Analyzing trace with hash -1420932234, now seen corresponding path program 1 times [2018-12-02 04:46:35,185 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:35,185 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 14 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:35,210 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:35,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:35,521 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:35,534 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-02 04:46:35,535 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-02 04:46:35,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 04:46:35,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 04:46:35,538 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 04:46:35,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 04:46:35,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 04:46:35,539 INFO L87 Difference]: Start difference. First operand 712 states and 824 transitions. Second operand 4 states. [2018-12-02 04:46:35,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:35,593 INFO L93 Difference]: Finished difference Result 1402 states and 1625 transitions. [2018-12-02 04:46:35,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 04:46:35,593 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 115 [2018-12-02 04:46:35,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:35,595 INFO L225 Difference]: With dead ends: 1402 [2018-12-02 04:46:35,595 INFO L226 Difference]: Without dead ends: 713 [2018-12-02 04:46:35,596 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 04:46:35,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states. [2018-12-02 04:46:35,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 713. [2018-12-02 04:46:35,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 713 states. [2018-12-02 04:46:35,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 713 states to 713 states and 825 transitions. [2018-12-02 04:46:35,632 INFO L78 Accepts]: Start accepts. Automaton has 713 states and 825 transitions. Word has length 115 [2018-12-02 04:46:35,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:35,632 INFO L480 AbstractCegarLoop]: Abstraction has 713 states and 825 transitions. [2018-12-02 04:46:35,632 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 04:46:35,632 INFO L276 IsEmpty]: Start isEmpty. Operand 713 states and 825 transitions. [2018-12-02 04:46:35,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-12-02 04:46:35,633 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:35,634 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:35,634 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:35,634 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:35,634 INFO L82 PathProgramCache]: Analyzing trace with hash 732072980, now seen corresponding path program 1 times [2018-12-02 04:46:35,634 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:35,634 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:35,660 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 04:46:35,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 04:46:35,960 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 04:46:35,977 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-02 04:46:35,977 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-02 04:46:36,044 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-02 04:46:36,047 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 04:46:36,047 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-12-02 04:46:36,047 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-02 04:46:36,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-02 04:46:36,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-02 04:46:36,048 INFO L87 Difference]: Start difference. First operand 713 states and 825 transitions. Second operand 8 states. [2018-12-02 04:46:36,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 04:46:36,168 INFO L93 Difference]: Finished difference Result 1407 states and 1632 transitions. [2018-12-02 04:46:36,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-02 04:46:36,169 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 116 [2018-12-02 04:46:36,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 04:46:36,171 INFO L225 Difference]: With dead ends: 1407 [2018-12-02 04:46:36,171 INFO L226 Difference]: Without dead ends: 716 [2018-12-02 04:46:36,171 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 224 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-12-02 04:46:36,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states. [2018-12-02 04:46:36,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 716. [2018-12-02 04:46:36,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 716 states. [2018-12-02 04:46:36,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 828 transitions. [2018-12-02 04:46:36,214 INFO L78 Accepts]: Start accepts. Automaton has 716 states and 828 transitions. Word has length 116 [2018-12-02 04:46:36,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 04:46:36,214 INFO L480 AbstractCegarLoop]: Abstraction has 716 states and 828 transitions. [2018-12-02 04:46:36,214 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-02 04:46:36,214 INFO L276 IsEmpty]: Start isEmpty. Operand 716 states and 828 transitions. [2018-12-02 04:46:36,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-12-02 04:46:36,215 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 04:46:36,215 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 04:46:36,215 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 04:46:36,215 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 04:46:36,216 INFO L82 PathProgramCache]: Analyzing trace with hash 1051230966, now seen corresponding path program 2 times [2018-12-02 04:46:36,216 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-02 04:46:36,216 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/cvc4 Starting monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-02 04:46:36,234 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-12-02 04:46:36,944 ERROR L235 seRefinementStrategy]: Caught known exception: Array theory solver does not yet support write-chains connecting two different constant arrays [2018-12-02 04:46:36,944 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-12-02 04:46:36,944 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_488a9a9e-7fa7-414d-9033-470bd832c33c/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-12-02 04:46:36,953 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-02 04:46:39,193 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-02 04:46:39,193 INFO L250 tOrderPrioritization]: Conjunction of SSA is sat [2018-12-02 04:46:41,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 04:46:42,140 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-02 04:46:42,195 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-12-02 04:46:42,227 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-12-02 04:46:42,227 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-02 04:46:42,227 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-02 04:46:42,227 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-02 04:46:42,227 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-02 04:46:42,228 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-12-02 04:46:42,229 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-02 04:46:42,229 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-12-02 04:46:42,229 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-02 04:46:42,229 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-02 04:46:42,229 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-02 04:46:42,229 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,230 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,231 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,232 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,232 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,233 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,233 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,234 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,234 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,235 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,235 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,236 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,236 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,236 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,237 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,237 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,238 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,239 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,239 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,239 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,240 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,240 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,240 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,240 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,241 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,241 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,241 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,241 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,242 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,242 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,243 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,243 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,244 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,244 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,245 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,245 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,246 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,246 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,246 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,247 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,247 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,247 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,247 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,248 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,248 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,248 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,248 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,249 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,249 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,249 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,250 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,250 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,250 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,250 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,251 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,251 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,251 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,252 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,252 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,252 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,253 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,253 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,253 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,253 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,253 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,253 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,254 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,254 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,254 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,254 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,255 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,255 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,255 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,255 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,255 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,255 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,256 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,256 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,256 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,256 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,256 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,256 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,257 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,257 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,257 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,257 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,257 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,258 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,258 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,258 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,258 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,258 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,259 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,259 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,259 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,259 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,259 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,260 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,260 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,260 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,260 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,260 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,260 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,261 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,261 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,261 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,261 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,261 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,261 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,262 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,262 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,262 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-02 04:46:42,262 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,262 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,263 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,263 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,263 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,263 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,264 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,264 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,264 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,264 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,265 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,265 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,266 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,266 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,266 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,266 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,267 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,267 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,267 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,268 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,268 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,268 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,268 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,269 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,269 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,269 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,269 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,270 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,270 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,270 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,271 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,271 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,271 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,271 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,272 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,272 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,273 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,273 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,273 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,273 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,274 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,274 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,274 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,274 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,275 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,275 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,275 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,275 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-02 04:46:42,287 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 04:46:42 BoogieIcfgContainer [2018-12-02 04:46:42,287 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-02 04:46:42,288 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-02 04:46:42,288 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-02 04:46:42,288 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-02 04:46:42,288 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 04:46:24" (3/4) ... [2018-12-02 04:46:42,291 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-12-02 04:46:42,291 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-02 04:46:42,291 INFO L168 Benchmark]: Toolchain (without parser) took 21427.93 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 391.1 MB). Free memory was 938.0 MB in the beginning and 833.6 MB in the end (delta: 104.4 MB). Peak memory consumption was 495.5 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:42,292 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 972.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 04:46:42,292 INFO L168 Benchmark]: CACSL2BoogieTranslator took 614.16 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.1 MB). Free memory was 938.0 MB in the beginning and 1.1 GB in the end (delta: -146.0 MB). Peak memory consumption was 67.2 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:42,293 INFO L168 Benchmark]: Boogie Procedure Inliner took 28.89 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 04:46:42,293 INFO L168 Benchmark]: Boogie Preprocessor took 44.52 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:42,293 INFO L168 Benchmark]: RCFGBuilder took 2987.32 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 941.7 MB in the end (delta: 135.4 MB). Peak memory consumption was 135.4 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:42,293 INFO L168 Benchmark]: TraceAbstraction took 17746.72 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 249.0 MB). Free memory was 941.7 MB in the beginning and 833.6 MB in the end (delta: 108.2 MB). Peak memory consumption was 357.2 MB. Max. memory is 11.5 GB. [2018-12-02 04:46:42,293 INFO L168 Benchmark]: Witness Printer took 3.21 ms. Allocated memory is still 1.4 GB. Free memory is still 833.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 04:46:42,295 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 972.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 614.16 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.1 MB). Free memory was 938.0 MB in the beginning and 1.1 GB in the end (delta: -146.0 MB). Peak memory consumption was 67.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 28.89 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.52 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 2987.32 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 941.7 MB in the end (delta: 135.4 MB). Peak memory consumption was 135.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 17746.72 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 249.0 MB). Free memory was 941.7 MB in the beginning and 833.6 MB in the end (delta: 108.2 MB). Peak memory consumption was 357.2 MB. Max. memory is 11.5 GB. * Witness Printer took 3.21 ms. Allocated memory is still 1.4 GB. Free memory is still 833.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1664]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2219. Possible FailurePath: [L1687] int ldv_irq_1_2 = 0; [L1688] int LDV_IN_INTERRUPT = 1; [L1689] int ldv_irq_1_3 = 0; [L1690] struct platform_device *tegra_rtc_driver_group0 ; [L1691] void *ldv_irq_data_1_1 ; [L1692] int ldv_irq_1_1 = 0; [L1693] int ldv_irq_1_0 = 0; [L1694] int ldv_irq_line_1_3 ; [L1695] void *ldv_irq_data_1_0 ; [L1696] int ldv_state_variable_0 ; [L1697] struct device *tegra_rtc_ops_group1 ; [L1698] int ldv_state_variable_3 ; [L1699] int ldv_irq_line_1_0 ; [L1700] int ldv_state_variable_2 ; [L1701] void *ldv_irq_data_1_3 ; [L1702] int ref_cnt ; [L1703] int ldv_irq_line_1_1 ; [L1704] struct rtc_time *tegra_rtc_ops_group0 ; [L1705] void *ldv_irq_data_1_2 ; [L1706] int ldv_state_variable_1 ; [L1707] int ldv_irq_line_1_2 ; [L1708] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2050-L2052] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2218-L2219] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2235] int ldv_retval_2 ; [L2236] int ldv_retval_0 ; [L2238] int ldv_retval_1 ; [L2761] int ldv_init = 0; VAL [\old(LDV_IN_INTERRUPT)=0, \old(ldv_init)=0, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_line_1_0)=0, \old(ldv_irq_line_1_1)=0, \old(ldv_irq_line_1_2)=0, \old(ldv_irq_line_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group2)=null, \old(tegra_rtc_ops_group2)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2390] struct seq_file *ldvarg1 ; [L2391] void *tmp ; [L2392] unsigned int ldvarg0 ; [L2393] unsigned int tmp___0 ; [L2394] pm_message_t ldvarg2 ; [L2395] int tmp___1 ; [L2396] int tmp___2 ; [L2397] int tmp___3 ; [L2398] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=268435456] [L2400] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] tmp = ldv_zalloc(136U) [L2401] ldvarg1 = (struct seq_file *)tmp [L2402] tmp___0 = __VERIFIER_nondet_uint() [L2403] ldvarg0 = tmp___0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2404] FCALL ldv_initialize() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2405] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, memset((void *)(& ldvarg2), 0, 4U)={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2406] ldv_state_variable_1 = 1 [L2407] ref_cnt = 0 [L2408] ldv_state_variable_0 = 1 [L2409] ldv_state_variable_3 = 0 [L2410] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1] [L2421] COND TRUE ldv_state_variable_0 != 0 [L2422] tmp___2 = __VERIFIER_nondet_int() [L2424] case 0: [L2432] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2433] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2434] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2222] int tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] CALL, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={8192:0}, arg1={-1:11}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2842] return __VERIFIER_nondet_int(); [L2224] RET, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe)=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2225] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2434] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2434] ldv_retval_0 = tegra_rtc_init() [L2435] COND TRUE ldv_retval_0 == 0 [L2436] ldv_state_variable_0 = 3 [L2437] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2438] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2355] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=8388608] [L2357] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] tmp = ldv_zalloc(624U) [L2358] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2438] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2441] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: [L2566] case 1: [L2576] case 2: [L2596] case 3: [L2606] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2607] COND TRUE ldv_state_variable_2 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2608] CALL ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2830] return __VERIFIER_nondet_int(); [L2608] RET ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_probe_2()=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2609] ldv_state_variable_2 = 2 [L2610] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2555] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2560] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={1099956256:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2561] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2214] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1952] struct tegra_rtc_info *info ; [L1953] void *tmp ; [L1954] unsigned int status ; [L1955] unsigned long sl_irq_flags ; [L1956] u32 __v ; [L1957] u32 __v___0 ; VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_external_alloc(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, arg0={0:12}, external_alloc()={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1959] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={0:0}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] tmp = dev_get_drvdata((struct device const *)dev) [L1960] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1961] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1835] struct tegra_rtc_info *info ; [L1836] void *tmp ; [L1837] int retries ; [L1838] int tmp___0 ; [L1839] u32 tmp___1 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_external_alloc(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, arg0={0:12}, external_alloc()={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1841] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] tmp = dev_get_drvdata((struct device const *)dev) [L1842] info = (struct tegra_rtc_info *)tmp [L1843] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1854] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1825] u32 __v ; [L1826] u32 __v___0 ; [L1828] EXPR info->rtc_base [L1828] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1828] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1829] __v = __v___0 [L1830] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, __v=0, __v___0=0, info={0:0}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1854] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1854] tmp___1 = tegra_rtc_check_busy(info) [L1855] COND FALSE !(tmp___1 != 0U) [L1859] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___1=0] [L1961] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={0:0}] [L1962] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2775] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2777] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1664] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={8192:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={66:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 65 procedures, 488 locations, 1 error locations. UNSAFE Result, 17.6s OverallTime, 15 OverallIterations, 4 TraceHistogramMax, 7.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5824 SDtfs, 5886 SDslu, 13119 SDs, 0 SdLazy, 4992 SolverSat, 658 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1697 GetRequests, 1565 SyntacticMatches, 5 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1472occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 14 MinimizatonAttempts, 1757 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 3.5s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 1308 NumberOfCodeBlocks, 1308 NumberOfCodeBlocksAsserted, 16 NumberOfCheckSat, 1632 ConstructedInterpolants, 0 QuantifiedInterpolants, 256606 SizeOfPredicates, 41 NumberOfNonLiveVariables, 7187 ConjunctsInSsa, 95 ConjunctsInUnsatCore, 19 InterpolantComputations, 10 PerfectInterpolantSequences, 245/287 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...