./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe006_power.opt_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe006_power.opt_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b2136a9c10453b968eccf837dc70324a87bc3dbd ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-01 15:32:19,299 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-01 15:32:19,300 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-01 15:32:19,307 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-01 15:32:19,308 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-01 15:32:19,308 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-01 15:32:19,309 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-01 15:32:19,310 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-01 15:32:19,311 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-01 15:32:19,311 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-01 15:32:19,312 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-01 15:32:19,312 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-01 15:32:19,313 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-01 15:32:19,314 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-01 15:32:19,314 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-01 15:32:19,315 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-01 15:32:19,315 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-01 15:32:19,317 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-01 15:32:19,318 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-01 15:32:19,319 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-01 15:32:19,320 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-01 15:32:19,320 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-01 15:32:19,322 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-01 15:32:19,322 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-01 15:32:19,322 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-01 15:32:19,323 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-01 15:32:19,324 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-01 15:32:19,324 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-01 15:32:19,325 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-01 15:32:19,325 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-01 15:32:19,325 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-01 15:32:19,326 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-01 15:32:19,326 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-01 15:32:19,326 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-01 15:32:19,327 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-01 15:32:19,327 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-01 15:32:19,327 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-12-01 15:32:19,337 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-01 15:32:19,337 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-01 15:32:19,338 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-01 15:32:19,338 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-01 15:32:19,338 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-01 15:32:19,338 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-01 15:32:19,338 INFO L133 SettingsManager]: * Use SBE=true [2018-12-01 15:32:19,339 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-01 15:32:19,339 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-01 15:32:19,340 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-01 15:32:19,340 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-01 15:32:19,340 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-01 15:32:19,340 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-01 15:32:19,340 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-01 15:32:19,340 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-01 15:32:19,340 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-01 15:32:19,340 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-01 15:32:19,340 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-01 15:32:19,341 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-01 15:32:19,341 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-01 15:32:19,341 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-01 15:32:19,341 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-01 15:32:19,341 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b2136a9c10453b968eccf837dc70324a87bc3dbd [2018-12-01 15:32:19,362 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-01 15:32:19,370 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-01 15:32:19,372 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-01 15:32:19,373 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-01 15:32:19,373 INFO L276 PluginConnector]: CDTParser initialized [2018-12-01 15:32:19,373 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe006_power.opt_false-unreach-call.i [2018-12-01 15:32:19,413 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/data/f40b97ab7/2013d6da2da146ed85e7394f8f2a60db/FLAG4740b3552 [2018-12-01 15:32:19,833 INFO L307 CDTParser]: Found 1 translation units. [2018-12-01 15:32:19,833 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/sv-benchmarks/c/pthread-wmm/safe006_power.opt_false-unreach-call.i [2018-12-01 15:32:19,841 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/data/f40b97ab7/2013d6da2da146ed85e7394f8f2a60db/FLAG4740b3552 [2018-12-01 15:32:19,852 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/data/f40b97ab7/2013d6da2da146ed85e7394f8f2a60db [2018-12-01 15:32:19,854 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-01 15:32:19,855 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-01 15:32:19,855 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-01 15:32:19,855 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-01 15:32:19,857 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-01 15:32:19,858 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 01.12 03:32:19" (1/1) ... [2018-12-01 15:32:19,859 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4599fb93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:19, skipping insertion in model container [2018-12-01 15:32:19,860 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 01.12 03:32:19" (1/1) ... [2018-12-01 15:32:19,864 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-01 15:32:19,892 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-01 15:32:20,107 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-01 15:32:20,118 INFO L191 MainTranslator]: Completed pre-run [2018-12-01 15:32:20,206 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-01 15:32:20,237 INFO L195 MainTranslator]: Completed translation [2018-12-01 15:32:20,237 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20 WrapperNode [2018-12-01 15:32:20,237 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-01 15:32:20,237 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-01 15:32:20,237 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-01 15:32:20,238 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-01 15:32:20,243 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,254 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,269 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-01 15:32:20,269 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-01 15:32:20,269 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-01 15:32:20,269 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-01 15:32:20,275 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,275 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,277 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,278 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,284 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,286 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,288 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... [2018-12-01 15:32:20,290 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-01 15:32:20,290 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-01 15:32:20,290 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-01 15:32:20,290 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-01 15:32:20,291 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-01 15:32:20,323 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-01 15:32:20,323 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-01 15:32:20,323 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-01 15:32:20,323 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-12-01 15:32:20,323 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-01 15:32:20,323 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-12-01 15:32:20,323 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-12-01 15:32:20,323 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-12-01 15:32:20,323 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-12-01 15:32:20,323 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-12-01 15:32:20,324 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-12-01 15:32:20,324 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-01 15:32:20,324 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-01 15:32:20,325 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-12-01 15:32:20,710 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-01 15:32:20,710 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-12-01 15:32:20,711 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 01.12 03:32:20 BoogieIcfgContainer [2018-12-01 15:32:20,711 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-01 15:32:20,711 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-01 15:32:20,711 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-01 15:32:20,713 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-01 15:32:20,713 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 01.12 03:32:19" (1/3) ... [2018-12-01 15:32:20,714 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1c51d8a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 01.12 03:32:20, skipping insertion in model container [2018-12-01 15:32:20,714 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 03:32:20" (2/3) ... [2018-12-01 15:32:20,714 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1c51d8a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 01.12 03:32:20, skipping insertion in model container [2018-12-01 15:32:20,714 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 01.12 03:32:20" (3/3) ... [2018-12-01 15:32:20,715 INFO L112 eAbstractionObserver]: Analyzing ICFG safe006_power.opt_false-unreach-call.i [2018-12-01 15:32:20,741 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,742 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,742 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,742 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,742 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,742 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,742 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,743 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,743 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,743 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,743 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,743 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,743 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~mem3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,743 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,744 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,744 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~mem3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,744 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,744 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,744 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,744 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,744 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,744 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,745 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,745 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,745 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,745 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,745 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,745 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,745 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,746 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,746 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,746 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,746 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,746 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,746 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,746 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,746 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,747 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,747 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,747 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,747 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,748 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,748 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,748 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,748 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,748 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,748 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,748 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,748 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,749 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,749 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,749 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,749 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet12.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,749 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,749 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,749 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,750 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet14.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,750 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,750 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,750 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,750 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,750 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,750 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,752 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,752 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,752 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,752 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,752 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,753 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,753 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,753 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,753 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,753 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,753 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,753 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,754 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,754 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,754 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,754 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,754 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,754 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,755 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,755 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,755 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,755 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,755 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,755 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,756 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,756 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,756 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,756 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,756 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,756 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,756 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,757 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,757 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,757 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,757 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,757 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,757 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,758 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,758 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,758 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,758 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,758 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,758 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,759 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,759 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,759 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,759 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,759 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,759 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,759 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,760 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,760 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,760 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,760 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,760 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,760 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,761 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,761 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,761 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,761 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,761 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,761 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,761 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,761 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,762 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,762 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,762 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,762 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,762 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,762 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,763 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,763 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,763 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,763 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,763 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,763 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,764 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,764 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,764 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,764 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,764 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,764 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,764 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,764 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,765 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,766 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,766 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,766 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,766 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,766 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,766 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,766 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,766 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,767 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,767 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,767 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,767 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,767 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,767 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,767 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,767 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,768 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,769 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,769 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,769 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,769 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,769 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,769 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,769 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,769 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,770 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,770 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,770 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,770 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,770 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,770 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,770 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,770 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,771 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,771 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,771 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,771 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,771 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,771 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,771 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,771 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,772 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,772 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,772 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,772 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,772 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,772 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,772 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,773 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,773 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,773 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,773 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,773 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,773 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,773 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~mem60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,774 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,774 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,774 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,774 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,774 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,774 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,775 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,776 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,776 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,776 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,776 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,776 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,776 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,776 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,776 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,777 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,777 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,777 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,777 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,777 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,777 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,777 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,777 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet67.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-12-01 15:32:20,782 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-12-01 15:32:20,782 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-01 15:32:20,789 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-12-01 15:32:20,801 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-12-01 15:32:20,818 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-01 15:32:20,819 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-01 15:32:20,819 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-01 15:32:20,819 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-01 15:32:20,819 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-01 15:32:20,819 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-01 15:32:20,819 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-01 15:32:20,819 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-01 15:32:20,820 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-01 15:32:20,828 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 200places, 259 transitions [2018-12-01 15:32:23,961 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 65314 states. [2018-12-01 15:32:23,963 INFO L276 IsEmpty]: Start isEmpty. Operand 65314 states. [2018-12-01 15:32:23,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-12-01 15:32:23,967 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:23,968 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:23,969 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:23,972 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:23,973 INFO L82 PathProgramCache]: Analyzing trace with hash -1016272846, now seen corresponding path program 1 times [2018-12-01 15:32:23,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:23,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:24,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:24,009 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:24,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:24,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:24,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:24,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:24,112 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 15:32:24,114 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 15:32:24,122 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 15:32:24,122 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:24,124 INFO L87 Difference]: Start difference. First operand 65314 states. Second operand 4 states. [2018-12-01 15:32:24,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:24,960 INFO L93 Difference]: Finished difference Result 113402 states and 445073 transitions. [2018-12-01 15:32:24,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 15:32:24,961 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-12-01 15:32:24,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:25,262 INFO L225 Difference]: With dead ends: 113402 [2018-12-01 15:32:25,262 INFO L226 Difference]: Without dead ends: 86242 [2018-12-01 15:32:25,263 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:25,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86242 states. [2018-12-01 15:32:26,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86242 to 53058. [2018-12-01 15:32:26,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53058 states. [2018-12-01 15:32:26,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53058 states to 53058 states and 208767 transitions. [2018-12-01 15:32:26,812 INFO L78 Accepts]: Start accepts. Automaton has 53058 states and 208767 transitions. Word has length 49 [2018-12-01 15:32:26,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:26,812 INFO L480 AbstractCegarLoop]: Abstraction has 53058 states and 208767 transitions. [2018-12-01 15:32:26,812 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 15:32:26,813 INFO L276 IsEmpty]: Start isEmpty. Operand 53058 states and 208767 transitions. [2018-12-01 15:32:26,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-12-01 15:32:26,819 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:26,820 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:26,820 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:26,820 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:26,820 INFO L82 PathProgramCache]: Analyzing trace with hash -267205330, now seen corresponding path program 1 times [2018-12-01 15:32:26,820 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:26,820 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:26,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:26,823 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:26,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:26,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:26,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:26,865 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:26,865 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-01 15:32:26,866 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-01 15:32:26,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-01 15:32:26,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 15:32:26,866 INFO L87 Difference]: Start difference. First operand 53058 states and 208767 transitions. Second operand 3 states. [2018-12-01 15:32:27,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:27,109 INFO L93 Difference]: Finished difference Result 53058 states and 208358 transitions. [2018-12-01 15:32:27,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-01 15:32:27,109 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2018-12-01 15:32:27,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:27,238 INFO L225 Difference]: With dead ends: 53058 [2018-12-01 15:32:27,238 INFO L226 Difference]: Without dead ends: 53058 [2018-12-01 15:32:27,239 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 15:32:27,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53058 states. [2018-12-01 15:32:28,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53058 to 53058. [2018-12-01 15:32:28,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53058 states. [2018-12-01 15:32:28,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53058 states to 53058 states and 208358 transitions. [2018-12-01 15:32:28,247 INFO L78 Accepts]: Start accepts. Automaton has 53058 states and 208358 transitions. Word has length 61 [2018-12-01 15:32:28,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:28,247 INFO L480 AbstractCegarLoop]: Abstraction has 53058 states and 208358 transitions. [2018-12-01 15:32:28,247 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-01 15:32:28,247 INFO L276 IsEmpty]: Start isEmpty. Operand 53058 states and 208358 transitions. [2018-12-01 15:32:28,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-12-01 15:32:28,251 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:28,251 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:28,251 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:28,251 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:28,251 INFO L82 PathProgramCache]: Analyzing trace with hash 1475605005, now seen corresponding path program 1 times [2018-12-01 15:32:28,251 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:28,251 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:28,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:28,253 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:28,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:28,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:28,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:28,301 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:28,301 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 15:32:28,302 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 15:32:28,302 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 15:32:28,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:28,302 INFO L87 Difference]: Start difference. First operand 53058 states and 208358 transitions. Second operand 4 states. [2018-12-01 15:32:28,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:28,366 INFO L93 Difference]: Finished difference Result 14752 states and 50098 transitions. [2018-12-01 15:32:28,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 15:32:28,367 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 61 [2018-12-01 15:32:28,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:28,394 INFO L225 Difference]: With dead ends: 14752 [2018-12-01 15:32:28,394 INFO L226 Difference]: Without dead ends: 13006 [2018-12-01 15:32:28,394 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:28,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13006 states. [2018-12-01 15:32:28,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13006 to 13006. [2018-12-01 15:32:28,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13006 states. [2018-12-01 15:32:28,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13006 states to 13006 states and 43944 transitions. [2018-12-01 15:32:28,549 INFO L78 Accepts]: Start accepts. Automaton has 13006 states and 43944 transitions. Word has length 61 [2018-12-01 15:32:28,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:28,549 INFO L480 AbstractCegarLoop]: Abstraction has 13006 states and 43944 transitions. [2018-12-01 15:32:28,549 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 15:32:28,549 INFO L276 IsEmpty]: Start isEmpty. Operand 13006 states and 43944 transitions. [2018-12-01 15:32:28,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-12-01 15:32:28,550 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:28,550 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:28,550 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:28,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:28,551 INFO L82 PathProgramCache]: Analyzing trace with hash 1874201971, now seen corresponding path program 1 times [2018-12-01 15:32:28,551 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:28,551 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:28,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:28,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:28,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:28,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:28,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:28,627 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:28,628 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 15:32:28,628 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 15:32:28,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 15:32:28,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:28,628 INFO L87 Difference]: Start difference. First operand 13006 states and 43944 transitions. Second operand 6 states. [2018-12-01 15:32:29,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:29,004 INFO L93 Difference]: Finished difference Result 27890 states and 91756 transitions. [2018-12-01 15:32:29,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-12-01 15:32:29,004 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 62 [2018-12-01 15:32:29,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:29,044 INFO L225 Difference]: With dead ends: 27890 [2018-12-01 15:32:29,044 INFO L226 Difference]: Without dead ends: 27790 [2018-12-01 15:32:29,045 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=74, Unknown=0, NotChecked=0, Total=110 [2018-12-01 15:32:29,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27790 states. [2018-12-01 15:32:29,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27790 to 16773. [2018-12-01 15:32:29,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16773 states. [2018-12-01 15:32:29,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16773 states to 16773 states and 55428 transitions. [2018-12-01 15:32:29,340 INFO L78 Accepts]: Start accepts. Automaton has 16773 states and 55428 transitions. Word has length 62 [2018-12-01 15:32:29,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:29,341 INFO L480 AbstractCegarLoop]: Abstraction has 16773 states and 55428 transitions. [2018-12-01 15:32:29,341 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 15:32:29,341 INFO L276 IsEmpty]: Start isEmpty. Operand 16773 states and 55428 transitions. [2018-12-01 15:32:29,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-12-01 15:32:29,343 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:29,343 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:29,343 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:29,343 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:29,343 INFO L82 PathProgramCache]: Analyzing trace with hash -1781281892, now seen corresponding path program 1 times [2018-12-01 15:32:29,343 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:29,343 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:29,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:29,345 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:29,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:29,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:29,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:29,365 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:29,365 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-01 15:32:29,365 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-01 15:32:29,365 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-01 15:32:29,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 15:32:29,365 INFO L87 Difference]: Start difference. First operand 16773 states and 55428 transitions. Second operand 3 states. [2018-12-01 15:32:29,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:29,444 INFO L93 Difference]: Finished difference Result 23727 states and 77133 transitions. [2018-12-01 15:32:29,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-01 15:32:29,445 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2018-12-01 15:32:29,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:29,479 INFO L225 Difference]: With dead ends: 23727 [2018-12-01 15:32:29,479 INFO L226 Difference]: Without dead ends: 23727 [2018-12-01 15:32:29,479 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 15:32:29,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23727 states. [2018-12-01 15:32:29,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23727 to 18701. [2018-12-01 15:32:29,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18701 states. [2018-12-01 15:32:29,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18701 states to 18701 states and 60885 transitions. [2018-12-01 15:32:29,705 INFO L78 Accepts]: Start accepts. Automaton has 18701 states and 60885 transitions. Word has length 64 [2018-12-01 15:32:29,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:29,706 INFO L480 AbstractCegarLoop]: Abstraction has 18701 states and 60885 transitions. [2018-12-01 15:32:29,706 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-01 15:32:29,706 INFO L276 IsEmpty]: Start isEmpty. Operand 18701 states and 60885 transitions. [2018-12-01 15:32:29,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-12-01 15:32:29,709 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:29,709 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:29,709 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:29,709 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:29,709 INFO L82 PathProgramCache]: Analyzing trace with hash -571649263, now seen corresponding path program 1 times [2018-12-01 15:32:29,709 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:29,710 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:29,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:29,711 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:29,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:29,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:29,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:29,843 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:29,844 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-12-01 15:32:29,844 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-01 15:32:29,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-01 15:32:29,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-12-01 15:32:29,844 INFO L87 Difference]: Start difference. First operand 18701 states and 60885 transitions. Second operand 10 states. [2018-12-01 15:32:30,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:30,681 INFO L93 Difference]: Finished difference Result 26205 states and 83034 transitions. [2018-12-01 15:32:30,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-12-01 15:32:30,682 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 68 [2018-12-01 15:32:30,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:30,715 INFO L225 Difference]: With dead ends: 26205 [2018-12-01 15:32:30,715 INFO L226 Difference]: Without dead ends: 26086 [2018-12-01 15:32:30,716 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 140 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=200, Invalid=556, Unknown=0, NotChecked=0, Total=756 [2018-12-01 15:32:30,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26086 states. [2018-12-01 15:32:30,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26086 to 20328. [2018-12-01 15:32:30,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20328 states. [2018-12-01 15:32:31,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20328 states to 20328 states and 65644 transitions. [2018-12-01 15:32:31,021 INFO L78 Accepts]: Start accepts. Automaton has 20328 states and 65644 transitions. Word has length 68 [2018-12-01 15:32:31,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:31,021 INFO L480 AbstractCegarLoop]: Abstraction has 20328 states and 65644 transitions. [2018-12-01 15:32:31,021 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-01 15:32:31,021 INFO L276 IsEmpty]: Start isEmpty. Operand 20328 states and 65644 transitions. [2018-12-01 15:32:31,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-12-01 15:32:31,027 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:31,027 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:31,027 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:31,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:31,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1407972401, now seen corresponding path program 1 times [2018-12-01 15:32:31,027 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:31,027 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:31,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:31,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:31,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:31,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:31,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:31,077 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:31,077 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 15:32:31,077 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 15:32:31,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 15:32:31,077 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:31,077 INFO L87 Difference]: Start difference. First operand 20328 states and 65644 transitions. Second operand 4 states. [2018-12-01 15:32:31,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:31,209 INFO L93 Difference]: Finished difference Result 22000 states and 70954 transitions. [2018-12-01 15:32:31,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 15:32:31,209 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2018-12-01 15:32:31,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:31,236 INFO L225 Difference]: With dead ends: 22000 [2018-12-01 15:32:31,237 INFO L226 Difference]: Without dead ends: 22000 [2018-12-01 15:32:31,237 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:31,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22000 states. [2018-12-01 15:32:31,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22000 to 21472. [2018-12-01 15:32:31,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21472 states. [2018-12-01 15:32:31,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21472 states to 21472 states and 69230 transitions. [2018-12-01 15:32:31,476 INFO L78 Accepts]: Start accepts. Automaton has 21472 states and 69230 transitions. Word has length 76 [2018-12-01 15:32:31,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:31,476 INFO L480 AbstractCegarLoop]: Abstraction has 21472 states and 69230 transitions. [2018-12-01 15:32:31,476 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 15:32:31,476 INFO L276 IsEmpty]: Start isEmpty. Operand 21472 states and 69230 transitions. [2018-12-01 15:32:31,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-12-01 15:32:31,481 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:31,481 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:31,481 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:31,481 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:31,481 INFO L82 PathProgramCache]: Analyzing trace with hash -1144184560, now seen corresponding path program 1 times [2018-12-01 15:32:31,481 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:31,481 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:31,482 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:31,483 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:31,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:31,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:31,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:31,552 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:31,552 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-12-01 15:32:31,552 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-01 15:32:31,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-01 15:32:31,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:31,552 INFO L87 Difference]: Start difference. First operand 21472 states and 69230 transitions. Second operand 7 states. [2018-12-01 15:32:32,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:32,058 INFO L93 Difference]: Finished difference Result 37517 states and 120136 transitions. [2018-12-01 15:32:32,058 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-01 15:32:32,058 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 76 [2018-12-01 15:32:32,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:32,107 INFO L225 Difference]: With dead ends: 37517 [2018-12-01 15:32:32,107 INFO L226 Difference]: Without dead ends: 37446 [2018-12-01 15:32:32,108 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-12-01 15:32:32,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37446 states. [2018-12-01 15:32:32,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37446 to 24138. [2018-12-01 15:32:32,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24138 states. [2018-12-01 15:32:32,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24138 states to 24138 states and 77250 transitions. [2018-12-01 15:32:32,451 INFO L78 Accepts]: Start accepts. Automaton has 24138 states and 77250 transitions. Word has length 76 [2018-12-01 15:32:32,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:32,452 INFO L480 AbstractCegarLoop]: Abstraction has 24138 states and 77250 transitions. [2018-12-01 15:32:32,452 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-01 15:32:32,452 INFO L276 IsEmpty]: Start isEmpty. Operand 24138 states and 77250 transitions. [2018-12-01 15:32:32,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-12-01 15:32:32,460 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:32,460 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:32,460 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:32,461 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:32,461 INFO L82 PathProgramCache]: Analyzing trace with hash -457594562, now seen corresponding path program 1 times [2018-12-01 15:32:32,461 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:32,461 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:32,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:32,462 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:32,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:32,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:32,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:32,494 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:32,494 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-01 15:32:32,494 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-01 15:32:32,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-01 15:32:32,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 15:32:32,495 INFO L87 Difference]: Start difference. First operand 24138 states and 77250 transitions. Second operand 3 states. [2018-12-01 15:32:32,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:32,734 INFO L93 Difference]: Finished difference Result 25009 states and 79558 transitions. [2018-12-01 15:32:32,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-01 15:32:32,735 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 82 [2018-12-01 15:32:32,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:32,768 INFO L225 Difference]: With dead ends: 25009 [2018-12-01 15:32:32,768 INFO L226 Difference]: Without dead ends: 25009 [2018-12-01 15:32:32,768 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 15:32:32,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25009 states. [2018-12-01 15:32:33,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25009 to 24700. [2018-12-01 15:32:33,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24700 states. [2018-12-01 15:32:33,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24700 states to 24700 states and 78706 transitions. [2018-12-01 15:32:33,171 INFO L78 Accepts]: Start accepts. Automaton has 24700 states and 78706 transitions. Word has length 82 [2018-12-01 15:32:33,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:33,171 INFO L480 AbstractCegarLoop]: Abstraction has 24700 states and 78706 transitions. [2018-12-01 15:32:33,171 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-01 15:32:33,171 INFO L276 IsEmpty]: Start isEmpty. Operand 24700 states and 78706 transitions. [2018-12-01 15:32:33,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-12-01 15:32:33,179 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:33,179 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:33,180 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:33,180 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:33,180 INFO L82 PathProgramCache]: Analyzing trace with hash -1806342675, now seen corresponding path program 1 times [2018-12-01 15:32:33,180 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:33,180 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:33,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:33,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:33,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:33,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:33,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:33,224 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:33,224 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 15:32:33,224 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 15:32:33,225 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 15:32:33,225 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:33,225 INFO L87 Difference]: Start difference. First operand 24700 states and 78706 transitions. Second operand 4 states. [2018-12-01 15:32:33,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:33,516 INFO L93 Difference]: Finished difference Result 32283 states and 100846 transitions. [2018-12-01 15:32:33,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 15:32:33,517 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 82 [2018-12-01 15:32:33,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:33,557 INFO L225 Difference]: With dead ends: 32283 [2018-12-01 15:32:33,557 INFO L226 Difference]: Without dead ends: 32283 [2018-12-01 15:32:33,557 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:33,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32283 states. [2018-12-01 15:32:33,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32283 to 28601. [2018-12-01 15:32:33,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28601 states. [2018-12-01 15:32:33,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28601 states to 28601 states and 90017 transitions. [2018-12-01 15:32:33,898 INFO L78 Accepts]: Start accepts. Automaton has 28601 states and 90017 transitions. Word has length 82 [2018-12-01 15:32:33,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:33,899 INFO L480 AbstractCegarLoop]: Abstraction has 28601 states and 90017 transitions. [2018-12-01 15:32:33,899 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 15:32:33,899 INFO L276 IsEmpty]: Start isEmpty. Operand 28601 states and 90017 transitions. [2018-12-01 15:32:33,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-12-01 15:32:33,911 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:33,911 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:33,911 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:33,911 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:33,911 INFO L82 PathProgramCache]: Analyzing trace with hash 1307367553, now seen corresponding path program 1 times [2018-12-01 15:32:33,911 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:33,912 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:33,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:33,913 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:33,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:33,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:33,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:33,966 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:33,967 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 15:32:33,967 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 15:32:33,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 15:32:33,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:33,967 INFO L87 Difference]: Start difference. First operand 28601 states and 90017 transitions. Second operand 6 states. [2018-12-01 15:32:34,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:34,854 INFO L93 Difference]: Finished difference Result 37655 states and 116057 transitions. [2018-12-01 15:32:34,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-01 15:32:34,854 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 84 [2018-12-01 15:32:34,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:34,903 INFO L225 Difference]: With dead ends: 37655 [2018-12-01 15:32:34,904 INFO L226 Difference]: Without dead ends: 37600 [2018-12-01 15:32:34,904 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:34,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37600 states. [2018-12-01 15:32:35,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37600 to 31640. [2018-12-01 15:32:35,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31640 states. [2018-12-01 15:32:35,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31640 states to 31640 states and 98637 transitions. [2018-12-01 15:32:35,294 INFO L78 Accepts]: Start accepts. Automaton has 31640 states and 98637 transitions. Word has length 84 [2018-12-01 15:32:35,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:35,294 INFO L480 AbstractCegarLoop]: Abstraction has 31640 states and 98637 transitions. [2018-12-01 15:32:35,294 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 15:32:35,294 INFO L276 IsEmpty]: Start isEmpty. Operand 31640 states and 98637 transitions. [2018-12-01 15:32:35,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-12-01 15:32:35,308 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:35,308 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:35,308 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:35,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:35,308 INFO L82 PathProgramCache]: Analyzing trace with hash -2025985726, now seen corresponding path program 1 times [2018-12-01 15:32:35,308 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:35,308 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:35,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:35,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:35,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:35,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:35,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:35,392 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:35,392 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 15:32:35,392 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 15:32:35,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 15:32:35,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:35,392 INFO L87 Difference]: Start difference. First operand 31640 states and 98637 transitions. Second operand 6 states. [2018-12-01 15:32:35,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:35,809 INFO L93 Difference]: Finished difference Result 35112 states and 106384 transitions. [2018-12-01 15:32:35,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-01 15:32:35,810 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 84 [2018-12-01 15:32:35,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:35,847 INFO L225 Difference]: With dead ends: 35112 [2018-12-01 15:32:35,847 INFO L226 Difference]: Without dead ends: 35112 [2018-12-01 15:32:35,847 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-12-01 15:32:35,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35112 states. [2018-12-01 15:32:36,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35112 to 32373. [2018-12-01 15:32:36,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32373 states. [2018-12-01 15:32:36,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32373 states to 32373 states and 99374 transitions. [2018-12-01 15:32:36,200 INFO L78 Accepts]: Start accepts. Automaton has 32373 states and 99374 transitions. Word has length 84 [2018-12-01 15:32:36,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:36,200 INFO L480 AbstractCegarLoop]: Abstraction has 32373 states and 99374 transitions. [2018-12-01 15:32:36,200 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 15:32:36,200 INFO L276 IsEmpty]: Start isEmpty. Operand 32373 states and 99374 transitions. [2018-12-01 15:32:36,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-12-01 15:32:36,214 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:36,214 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:36,214 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:36,215 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:36,215 INFO L82 PathProgramCache]: Analyzing trace with hash -781221245, now seen corresponding path program 1 times [2018-12-01 15:32:36,215 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:36,215 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:36,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:36,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:36,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:36,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:36,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:36,277 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:36,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 15:32:36,277 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 15:32:36,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 15:32:36,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:36,277 INFO L87 Difference]: Start difference. First operand 32373 states and 99374 transitions. Second operand 5 states. [2018-12-01 15:32:36,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:36,578 INFO L93 Difference]: Finished difference Result 39225 states and 118481 transitions. [2018-12-01 15:32:36,579 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-01 15:32:36,579 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-12-01 15:32:36,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:36,626 INFO L225 Difference]: With dead ends: 39225 [2018-12-01 15:32:36,626 INFO L226 Difference]: Without dead ends: 39225 [2018-12-01 15:32:36,626 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:36,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39225 states. [2018-12-01 15:32:36,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39225 to 35801. [2018-12-01 15:32:36,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35801 states. [2018-12-01 15:32:37,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35801 states to 35801 states and 108276 transitions. [2018-12-01 15:32:37,034 INFO L78 Accepts]: Start accepts. Automaton has 35801 states and 108276 transitions. Word has length 84 [2018-12-01 15:32:37,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:37,034 INFO L480 AbstractCegarLoop]: Abstraction has 35801 states and 108276 transitions. [2018-12-01 15:32:37,034 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 15:32:37,034 INFO L276 IsEmpty]: Start isEmpty. Operand 35801 states and 108276 transitions. [2018-12-01 15:32:37,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-12-01 15:32:37,047 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:37,047 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:37,047 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:37,047 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:37,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1778293598, now seen corresponding path program 1 times [2018-12-01 15:32:37,047 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:37,047 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:37,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:37,048 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:37,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:37,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:37,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:37,085 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:37,085 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 15:32:37,086 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 15:32:37,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 15:32:37,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:37,086 INFO L87 Difference]: Start difference. First operand 35801 states and 108276 transitions. Second operand 5 states. [2018-12-01 15:32:37,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:37,596 INFO L93 Difference]: Finished difference Result 53698 states and 161639 transitions. [2018-12-01 15:32:37,596 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-01 15:32:37,597 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-12-01 15:32:37,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:37,663 INFO L225 Difference]: With dead ends: 53698 [2018-12-01 15:32:37,663 INFO L226 Difference]: Without dead ends: 53698 [2018-12-01 15:32:37,663 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-01 15:32:37,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53698 states. [2018-12-01 15:32:38,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53698 to 45753. [2018-12-01 15:32:38,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45753 states. [2018-12-01 15:32:38,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45753 states to 45753 states and 137727 transitions. [2018-12-01 15:32:38,207 INFO L78 Accepts]: Start accepts. Automaton has 45753 states and 137727 transitions. Word has length 84 [2018-12-01 15:32:38,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:38,207 INFO L480 AbstractCegarLoop]: Abstraction has 45753 states and 137727 transitions. [2018-12-01 15:32:38,207 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 15:32:38,207 INFO L276 IsEmpty]: Start isEmpty. Operand 45753 states and 137727 transitions. [2018-12-01 15:32:38,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-12-01 15:32:38,220 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:38,220 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:38,220 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:38,220 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:38,220 INFO L82 PathProgramCache]: Analyzing trace with hash 719722339, now seen corresponding path program 1 times [2018-12-01 15:32:38,220 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:38,220 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:38,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:38,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:38,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:38,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:38,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:38,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:38,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 15:32:38,250 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 15:32:38,250 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 15:32:38,250 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:38,251 INFO L87 Difference]: Start difference. First operand 45753 states and 137727 transitions. Second operand 4 states. [2018-12-01 15:32:38,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:38,871 INFO L93 Difference]: Finished difference Result 60113 states and 180825 transitions. [2018-12-01 15:32:38,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 15:32:38,871 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 84 [2018-12-01 15:32:38,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:38,951 INFO L225 Difference]: With dead ends: 60113 [2018-12-01 15:32:38,951 INFO L226 Difference]: Without dead ends: 59685 [2018-12-01 15:32:38,952 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:39,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59685 states. [2018-12-01 15:32:39,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59685 to 55877. [2018-12-01 15:32:39,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55877 states. [2018-12-01 15:32:39,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55877 states to 55877 states and 168476 transitions. [2018-12-01 15:32:39,618 INFO L78 Accepts]: Start accepts. Automaton has 55877 states and 168476 transitions. Word has length 84 [2018-12-01 15:32:39,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:39,618 INFO L480 AbstractCegarLoop]: Abstraction has 55877 states and 168476 transitions. [2018-12-01 15:32:39,618 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 15:32:39,618 INFO L276 IsEmpty]: Start isEmpty. Operand 55877 states and 168476 transitions. [2018-12-01 15:32:39,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-12-01 15:32:39,639 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:39,640 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:39,640 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:39,640 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:39,640 INFO L82 PathProgramCache]: Analyzing trace with hash 426319332, now seen corresponding path program 1 times [2018-12-01 15:32:39,640 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:39,640 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:39,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:39,641 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:39,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:39,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:39,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:39,686 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:39,686 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 15:32:39,686 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 15:32:39,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 15:32:39,687 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:39,687 INFO L87 Difference]: Start difference. First operand 55877 states and 168476 transitions. Second operand 5 states. [2018-12-01 15:32:39,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:39,730 INFO L93 Difference]: Finished difference Result 12621 states and 29962 transitions. [2018-12-01 15:32:39,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 15:32:39,730 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 84 [2018-12-01 15:32:39,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:39,737 INFO L225 Difference]: With dead ends: 12621 [2018-12-01 15:32:39,737 INFO L226 Difference]: Without dead ends: 10165 [2018-12-01 15:32:39,738 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:39,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10165 states. [2018-12-01 15:32:39,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10165 to 8860. [2018-12-01 15:32:39,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8860 states. [2018-12-01 15:32:39,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8860 states to 8860 states and 20404 transitions. [2018-12-01 15:32:39,811 INFO L78 Accepts]: Start accepts. Automaton has 8860 states and 20404 transitions. Word has length 84 [2018-12-01 15:32:39,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:39,812 INFO L480 AbstractCegarLoop]: Abstraction has 8860 states and 20404 transitions. [2018-12-01 15:32:39,812 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 15:32:39,812 INFO L276 IsEmpty]: Start isEmpty. Operand 8860 states and 20404 transitions. [2018-12-01 15:32:39,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-12-01 15:32:39,817 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:39,817 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:39,817 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:39,817 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:39,817 INFO L82 PathProgramCache]: Analyzing trace with hash -371203702, now seen corresponding path program 1 times [2018-12-01 15:32:39,818 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:39,818 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:39,818 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:39,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:39,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:39,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:39,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:39,850 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:39,850 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 15:32:39,850 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 15:32:39,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 15:32:39,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:39,850 INFO L87 Difference]: Start difference. First operand 8860 states and 20404 transitions. Second operand 5 states. [2018-12-01 15:32:39,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:39,951 INFO L93 Difference]: Finished difference Result 10299 states and 23671 transitions. [2018-12-01 15:32:39,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-01 15:32:39,951 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 88 [2018-12-01 15:32:39,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:39,958 INFO L225 Difference]: With dead ends: 10299 [2018-12-01 15:32:39,958 INFO L226 Difference]: Without dead ends: 10299 [2018-12-01 15:32:39,958 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-12-01 15:32:39,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10299 states. [2018-12-01 15:32:40,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10299 to 9297. [2018-12-01 15:32:40,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9297 states. [2018-12-01 15:32:40,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9297 states to 9297 states and 21406 transitions. [2018-12-01 15:32:40,026 INFO L78 Accepts]: Start accepts. Automaton has 9297 states and 21406 transitions. Word has length 88 [2018-12-01 15:32:40,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:40,026 INFO L480 AbstractCegarLoop]: Abstraction has 9297 states and 21406 transitions. [2018-12-01 15:32:40,026 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 15:32:40,026 INFO L276 IsEmpty]: Start isEmpty. Operand 9297 states and 21406 transitions. [2018-12-01 15:32:40,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-12-01 15:32:40,031 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:40,031 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:40,032 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:40,032 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:40,032 INFO L82 PathProgramCache]: Analyzing trace with hash 1371606633, now seen corresponding path program 1 times [2018-12-01 15:32:40,032 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:40,032 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:40,033 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:40,033 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:40,033 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:40,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:40,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:40,096 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:40,096 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 15:32:40,096 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 15:32:40,097 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 15:32:40,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:40,097 INFO L87 Difference]: Start difference. First operand 9297 states and 21406 transitions. Second operand 5 states. [2018-12-01 15:32:40,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:40,134 INFO L93 Difference]: Finished difference Result 12160 states and 27850 transitions. [2018-12-01 15:32:40,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 15:32:40,135 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 88 [2018-12-01 15:32:40,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:40,143 INFO L225 Difference]: With dead ends: 12160 [2018-12-01 15:32:40,143 INFO L226 Difference]: Without dead ends: 12079 [2018-12-01 15:32:40,143 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:40,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12079 states. [2018-12-01 15:32:40,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12079 to 8791. [2018-12-01 15:32:40,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8791 states. [2018-12-01 15:32:40,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8791 states to 8791 states and 19961 transitions. [2018-12-01 15:32:40,220 INFO L78 Accepts]: Start accepts. Automaton has 8791 states and 19961 transitions. Word has length 88 [2018-12-01 15:32:40,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:40,220 INFO L480 AbstractCegarLoop]: Abstraction has 8791 states and 19961 transitions. [2018-12-01 15:32:40,220 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 15:32:40,220 INFO L276 IsEmpty]: Start isEmpty. Operand 8791 states and 19961 transitions. [2018-12-01 15:32:40,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-12-01 15:32:40,225 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:40,225 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:40,225 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:40,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:40,226 INFO L82 PathProgramCache]: Analyzing trace with hash -425344726, now seen corresponding path program 1 times [2018-12-01 15:32:40,226 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:40,226 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:40,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:40,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:40,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:40,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:40,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:40,286 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:40,286 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-12-01 15:32:40,287 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-01 15:32:40,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-01 15:32:40,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:40,287 INFO L87 Difference]: Start difference. First operand 8791 states and 19961 transitions. Second operand 7 states. [2018-12-01 15:32:40,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:40,613 INFO L93 Difference]: Finished difference Result 13227 states and 30329 transitions. [2018-12-01 15:32:40,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-01 15:32:40,613 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 88 [2018-12-01 15:32:40,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:40,621 INFO L225 Difference]: With dead ends: 13227 [2018-12-01 15:32:40,621 INFO L226 Difference]: Without dead ends: 13108 [2018-12-01 15:32:40,622 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 9 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=106, Invalid=236, Unknown=0, NotChecked=0, Total=342 [2018-12-01 15:32:40,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13108 states. [2018-12-01 15:32:40,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13108 to 8754. [2018-12-01 15:32:40,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8754 states. [2018-12-01 15:32:40,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8754 states to 8754 states and 19814 transitions. [2018-12-01 15:32:40,702 INFO L78 Accepts]: Start accepts. Automaton has 8754 states and 19814 transitions. Word has length 88 [2018-12-01 15:32:40,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:40,702 INFO L480 AbstractCegarLoop]: Abstraction has 8754 states and 19814 transitions. [2018-12-01 15:32:40,702 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-01 15:32:40,702 INFO L276 IsEmpty]: Start isEmpty. Operand 8754 states and 19814 transitions. [2018-12-01 15:32:40,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-12-01 15:32:40,708 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:40,708 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:40,708 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:40,709 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:40,709 INFO L82 PathProgramCache]: Analyzing trace with hash -2047011829, now seen corresponding path program 1 times [2018-12-01 15:32:40,709 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:40,709 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:40,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:40,710 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:40,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:40,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:40,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:40,741 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:40,742 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 15:32:40,742 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 15:32:40,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 15:32:40,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:40,742 INFO L87 Difference]: Start difference. First operand 8754 states and 19814 transitions. Second operand 4 states. [2018-12-01 15:32:40,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:40,930 INFO L93 Difference]: Finished difference Result 12754 states and 28548 transitions. [2018-12-01 15:32:40,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 15:32:40,931 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-12-01 15:32:40,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:40,940 INFO L225 Difference]: With dead ends: 12754 [2018-12-01 15:32:40,940 INFO L226 Difference]: Without dead ends: 12754 [2018-12-01 15:32:40,940 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:40,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12754 states. [2018-12-01 15:32:41,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12754 to 10443. [2018-12-01 15:32:41,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10443 states. [2018-12-01 15:32:41,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10443 states to 10443 states and 23241 transitions. [2018-12-01 15:32:41,033 INFO L78 Accepts]: Start accepts. Automaton has 10443 states and 23241 transitions. Word has length 109 [2018-12-01 15:32:41,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:41,033 INFO L480 AbstractCegarLoop]: Abstraction has 10443 states and 23241 transitions. [2018-12-01 15:32:41,034 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 15:32:41,034 INFO L276 IsEmpty]: Start isEmpty. Operand 10443 states and 23241 transitions. [2018-12-01 15:32:41,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-12-01 15:32:41,041 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:41,041 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:41,041 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:41,041 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:41,041 INFO L82 PathProgramCache]: Analyzing trace with hash -414935268, now seen corresponding path program 1 times [2018-12-01 15:32:41,041 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:41,042 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:41,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:41,042 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:41,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:41,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:41,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:41,107 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:41,107 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 15:32:41,107 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 15:32:41,107 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 15:32:41,107 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:41,108 INFO L87 Difference]: Start difference. First operand 10443 states and 23241 transitions. Second operand 4 states. [2018-12-01 15:32:41,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:41,177 INFO L93 Difference]: Finished difference Result 10839 states and 24007 transitions. [2018-12-01 15:32:41,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 15:32:41,177 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-12-01 15:32:41,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:41,184 INFO L225 Difference]: With dead ends: 10839 [2018-12-01 15:32:41,184 INFO L226 Difference]: Without dead ends: 10839 [2018-12-01 15:32:41,184 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:41,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10839 states. [2018-12-01 15:32:41,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10839 to 10267. [2018-12-01 15:32:41,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10267 states. [2018-12-01 15:32:41,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10267 states to 10267 states and 22812 transitions. [2018-12-01 15:32:41,268 INFO L78 Accepts]: Start accepts. Automaton has 10267 states and 22812 transitions. Word has length 109 [2018-12-01 15:32:41,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:41,268 INFO L480 AbstractCegarLoop]: Abstraction has 10267 states and 22812 transitions. [2018-12-01 15:32:41,268 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 15:32:41,268 INFO L276 IsEmpty]: Start isEmpty. Operand 10267 states and 22812 transitions. [2018-12-01 15:32:41,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-01 15:32:41,275 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:41,275 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:41,275 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:41,276 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:41,276 INFO L82 PathProgramCache]: Analyzing trace with hash -1563716653, now seen corresponding path program 1 times [2018-12-01 15:32:41,276 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:41,276 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:41,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:41,277 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:41,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:41,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:41,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:41,303 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:41,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 15:32:41,303 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 15:32:41,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 15:32:41,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:41,303 INFO L87 Difference]: Start difference. First operand 10267 states and 22812 transitions. Second operand 5 states. [2018-12-01 15:32:41,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:41,455 INFO L93 Difference]: Finished difference Result 13596 states and 30029 transitions. [2018-12-01 15:32:41,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-01 15:32:41,455 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2018-12-01 15:32:41,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:41,464 INFO L225 Difference]: With dead ends: 13596 [2018-12-01 15:32:41,464 INFO L226 Difference]: Without dead ends: 13596 [2018-12-01 15:32:41,464 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-01 15:32:41,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13596 states. [2018-12-01 15:32:41,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13596 to 10703. [2018-12-01 15:32:41,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10703 states. [2018-12-01 15:32:41,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10703 states to 10703 states and 23735 transitions. [2018-12-01 15:32:41,551 INFO L78 Accepts]: Start accepts. Automaton has 10703 states and 23735 transitions. Word has length 111 [2018-12-01 15:32:41,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:41,551 INFO L480 AbstractCegarLoop]: Abstraction has 10703 states and 23735 transitions. [2018-12-01 15:32:41,551 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 15:32:41,551 INFO L276 IsEmpty]: Start isEmpty. Operand 10703 states and 23735 transitions. [2018-12-01 15:32:41,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-01 15:32:41,558 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:41,558 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:41,558 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:41,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:41,558 INFO L82 PathProgramCache]: Analyzing trace with hash -1552400526, now seen corresponding path program 1 times [2018-12-01 15:32:41,559 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:41,559 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:41,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:41,559 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:41,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:41,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:41,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:41,601 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:41,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 15:32:41,601 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 15:32:41,601 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 15:32:41,601 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:41,601 INFO L87 Difference]: Start difference. First operand 10703 states and 23735 transitions. Second operand 5 states. [2018-12-01 15:32:41,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:41,932 INFO L93 Difference]: Finished difference Result 18447 states and 41332 transitions. [2018-12-01 15:32:41,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-01 15:32:41,933 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2018-12-01 15:32:41,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:41,945 INFO L225 Difference]: With dead ends: 18447 [2018-12-01 15:32:41,945 INFO L226 Difference]: Without dead ends: 18447 [2018-12-01 15:32:41,945 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:41,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18447 states. [2018-12-01 15:32:42,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18447 to 11580. [2018-12-01 15:32:42,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11580 states. [2018-12-01 15:32:42,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11580 states to 11580 states and 25588 transitions. [2018-12-01 15:32:42,065 INFO L78 Accepts]: Start accepts. Automaton has 11580 states and 25588 transitions. Word has length 111 [2018-12-01 15:32:42,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:42,066 INFO L480 AbstractCegarLoop]: Abstraction has 11580 states and 25588 transitions. [2018-12-01 15:32:42,066 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 15:32:42,066 INFO L276 IsEmpty]: Start isEmpty. Operand 11580 states and 25588 transitions. [2018-12-01 15:32:42,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-01 15:32:42,075 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:42,075 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:42,075 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:42,075 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:42,076 INFO L82 PathProgramCache]: Analyzing trace with hash 665357427, now seen corresponding path program 1 times [2018-12-01 15:32:42,076 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:42,076 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:42,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:42,077 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:42,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:42,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:42,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:42,162 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:42,162 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-12-01 15:32:42,162 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-01 15:32:42,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-01 15:32:42,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-12-01 15:32:42,163 INFO L87 Difference]: Start difference. First operand 11580 states and 25588 transitions. Second operand 8 states. [2018-12-01 15:32:42,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:42,657 INFO L93 Difference]: Finished difference Result 15058 states and 33182 transitions. [2018-12-01 15:32:42,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-12-01 15:32:42,658 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 111 [2018-12-01 15:32:42,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:42,674 INFO L225 Difference]: With dead ends: 15058 [2018-12-01 15:32:42,674 INFO L226 Difference]: Without dead ends: 15026 [2018-12-01 15:32:42,675 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2018-12-01 15:32:42,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15026 states. [2018-12-01 15:32:42,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15026 to 13154. [2018-12-01 15:32:42,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13154 states. [2018-12-01 15:32:42,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13154 states to 13154 states and 29004 transitions. [2018-12-01 15:32:42,793 INFO L78 Accepts]: Start accepts. Automaton has 13154 states and 29004 transitions. Word has length 111 [2018-12-01 15:32:42,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:42,793 INFO L480 AbstractCegarLoop]: Abstraction has 13154 states and 29004 transitions. [2018-12-01 15:32:42,794 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-01 15:32:42,794 INFO L276 IsEmpty]: Start isEmpty. Operand 13154 states and 29004 transitions. [2018-12-01 15:32:42,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-01 15:32:42,804 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:42,804 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:42,804 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:42,805 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:42,805 INFO L82 PathProgramCache]: Analyzing trace with hash 371954420, now seen corresponding path program 1 times [2018-12-01 15:32:42,805 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:42,805 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:42,806 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:42,806 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:42,806 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:42,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:42,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:42,882 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:42,882 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-12-01 15:32:42,883 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-01 15:32:42,883 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-01 15:32:42,883 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-12-01 15:32:42,883 INFO L87 Difference]: Start difference. First operand 13154 states and 29004 transitions. Second operand 8 states. [2018-12-01 15:32:43,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:43,244 INFO L93 Difference]: Finished difference Result 20925 states and 47168 transitions. [2018-12-01 15:32:43,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-01 15:32:43,244 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 111 [2018-12-01 15:32:43,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:43,257 INFO L225 Difference]: With dead ends: 20925 [2018-12-01 15:32:43,258 INFO L226 Difference]: Without dead ends: 20925 [2018-12-01 15:32:43,258 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2018-12-01 15:32:43,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20925 states. [2018-12-01 15:32:43,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20925 to 14592. [2018-12-01 15:32:43,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14592 states. [2018-12-01 15:32:43,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14592 states to 14592 states and 32454 transitions. [2018-12-01 15:32:43,404 INFO L78 Accepts]: Start accepts. Automaton has 14592 states and 32454 transitions. Word has length 111 [2018-12-01 15:32:43,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:43,404 INFO L480 AbstractCegarLoop]: Abstraction has 14592 states and 32454 transitions. [2018-12-01 15:32:43,404 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-01 15:32:43,404 INFO L276 IsEmpty]: Start isEmpty. Operand 14592 states and 32454 transitions. [2018-12-01 15:32:43,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-01 15:32:43,415 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:43,415 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:43,415 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:43,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:43,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1435500043, now seen corresponding path program 1 times [2018-12-01 15:32:43,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:43,416 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:43,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:43,416 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:43,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:43,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:43,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:43,478 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:43,478 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 15:32:43,478 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 15:32:43,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 15:32:43,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:43,478 INFO L87 Difference]: Start difference. First operand 14592 states and 32454 transitions. Second operand 6 states. [2018-12-01 15:32:43,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:43,534 INFO L93 Difference]: Finished difference Result 17742 states and 39492 transitions. [2018-12-01 15:32:43,534 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 15:32:43,534 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 111 [2018-12-01 15:32:43,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:43,546 INFO L225 Difference]: With dead ends: 17742 [2018-12-01 15:32:43,546 INFO L226 Difference]: Without dead ends: 17742 [2018-12-01 15:32:43,546 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:43,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17742 states. [2018-12-01 15:32:43,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17742 to 14780. [2018-12-01 15:32:43,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14780 states. [2018-12-01 15:32:43,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14780 states to 14780 states and 32665 transitions. [2018-12-01 15:32:43,674 INFO L78 Accepts]: Start accepts. Automaton has 14780 states and 32665 transitions. Word has length 111 [2018-12-01 15:32:43,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:43,674 INFO L480 AbstractCegarLoop]: Abstraction has 14780 states and 32665 transitions. [2018-12-01 15:32:43,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 15:32:43,674 INFO L276 IsEmpty]: Start isEmpty. Operand 14780 states and 32665 transitions. [2018-12-01 15:32:43,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-01 15:32:43,685 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:43,685 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:43,685 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:43,686 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:43,686 INFO L82 PathProgramCache]: Analyzing trace with hash 26079956, now seen corresponding path program 1 times [2018-12-01 15:32:43,686 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:43,686 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:43,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:43,687 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:43,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:43,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:43,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:43,771 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:43,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-12-01 15:32:43,772 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-01 15:32:43,772 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-01 15:32:43,772 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-12-01 15:32:43,772 INFO L87 Difference]: Start difference. First operand 14780 states and 32665 transitions. Second operand 9 states. [2018-12-01 15:32:44,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:44,266 INFO L93 Difference]: Finished difference Result 19158 states and 42700 transitions. [2018-12-01 15:32:44,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-01 15:32:44,266 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 111 [2018-12-01 15:32:44,266 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:44,281 INFO L225 Difference]: With dead ends: 19158 [2018-12-01 15:32:44,281 INFO L226 Difference]: Without dead ends: 19158 [2018-12-01 15:32:44,281 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=79, Invalid=263, Unknown=0, NotChecked=0, Total=342 [2018-12-01 15:32:44,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19158 states. [2018-12-01 15:32:44,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19158 to 15775. [2018-12-01 15:32:44,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15775 states. [2018-12-01 15:32:44,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15775 states to 15775 states and 34847 transitions. [2018-12-01 15:32:44,424 INFO L78 Accepts]: Start accepts. Automaton has 15775 states and 34847 transitions. Word has length 111 [2018-12-01 15:32:44,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:44,425 INFO L480 AbstractCegarLoop]: Abstraction has 15775 states and 34847 transitions. [2018-12-01 15:32:44,425 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-01 15:32:44,425 INFO L276 IsEmpty]: Start isEmpty. Operand 15775 states and 34847 transitions. [2018-12-01 15:32:44,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-01 15:32:44,436 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:44,436 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:44,436 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:44,437 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:44,437 INFO L82 PathProgramCache]: Analyzing trace with hash 2044885332, now seen corresponding path program 1 times [2018-12-01 15:32:44,437 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:44,437 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:44,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:44,438 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:44,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:44,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:44,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:44,496 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:44,496 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 15:32:44,496 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 15:32:44,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 15:32:44,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:44,496 INFO L87 Difference]: Start difference. First operand 15775 states and 34847 transitions. Second operand 6 states. [2018-12-01 15:32:44,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:44,614 INFO L93 Difference]: Finished difference Result 15749 states and 34232 transitions. [2018-12-01 15:32:44,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-01 15:32:44,614 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 111 [2018-12-01 15:32:44,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:44,624 INFO L225 Difference]: With dead ends: 15749 [2018-12-01 15:32:44,624 INFO L226 Difference]: Without dead ends: 15749 [2018-12-01 15:32:44,624 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-12-01 15:32:44,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15749 states. [2018-12-01 15:32:44,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15749 to 11082. [2018-12-01 15:32:44,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11082 states. [2018-12-01 15:32:44,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11082 states to 11082 states and 24041 transitions. [2018-12-01 15:32:44,736 INFO L78 Accepts]: Start accepts. Automaton has 11082 states and 24041 transitions. Word has length 111 [2018-12-01 15:32:44,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:44,736 INFO L480 AbstractCegarLoop]: Abstraction has 11082 states and 24041 transitions. [2018-12-01 15:32:44,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 15:32:44,736 INFO L276 IsEmpty]: Start isEmpty. Operand 11082 states and 24041 transitions. [2018-12-01 15:32:44,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-12-01 15:32:44,743 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:44,743 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:44,743 INFO L423 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:44,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:44,744 INFO L82 PathProgramCache]: Analyzing trace with hash -1401074152, now seen corresponding path program 1 times [2018-12-01 15:32:44,744 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:44,744 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:44,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:44,745 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:44,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:44,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:44,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:44,784 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:44,784 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 15:32:44,784 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 15:32:44,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 15:32:44,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:44,784 INFO L87 Difference]: Start difference. First operand 11082 states and 24041 transitions. Second operand 6 states. [2018-12-01 15:32:45,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:45,043 INFO L93 Difference]: Finished difference Result 12712 states and 27446 transitions. [2018-12-01 15:32:45,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-01 15:32:45,043 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 113 [2018-12-01 15:32:45,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:45,052 INFO L225 Difference]: With dead ends: 12712 [2018-12-01 15:32:45,052 INFO L226 Difference]: Without dead ends: 12712 [2018-12-01 15:32:45,053 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2018-12-01 15:32:45,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12712 states. [2018-12-01 15:32:45,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12712 to 11153. [2018-12-01 15:32:45,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11153 states. [2018-12-01 15:32:45,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11153 states to 11153 states and 24176 transitions. [2018-12-01 15:32:45,173 INFO L78 Accepts]: Start accepts. Automaton has 11153 states and 24176 transitions. Word has length 113 [2018-12-01 15:32:45,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:45,173 INFO L480 AbstractCegarLoop]: Abstraction has 11153 states and 24176 transitions. [2018-12-01 15:32:45,173 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 15:32:45,173 INFO L276 IsEmpty]: Start isEmpty. Operand 11153 states and 24176 transitions. [2018-12-01 15:32:45,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-12-01 15:32:45,184 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:45,184 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:45,184 INFO L423 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:45,184 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:45,184 INFO L82 PathProgramCache]: Analyzing trace with hash 883789303, now seen corresponding path program 1 times [2018-12-01 15:32:45,184 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:45,184 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:45,185 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:45,185 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:45,185 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:45,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:45,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:45,227 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:45,227 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 15:32:45,227 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 15:32:45,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 15:32:45,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 15:32:45,227 INFO L87 Difference]: Start difference. First operand 11153 states and 24176 transitions. Second operand 4 states. [2018-12-01 15:32:45,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:45,400 INFO L93 Difference]: Finished difference Result 13401 states and 29068 transitions. [2018-12-01 15:32:45,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 15:32:45,401 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 113 [2018-12-01 15:32:45,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:45,409 INFO L225 Difference]: With dead ends: 13401 [2018-12-01 15:32:45,410 INFO L226 Difference]: Without dead ends: 13306 [2018-12-01 15:32:45,410 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:45,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13306 states. [2018-12-01 15:32:45,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13306 to 11739. [2018-12-01 15:32:45,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11739 states. [2018-12-01 15:32:45,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11739 states to 11739 states and 25493 transitions. [2018-12-01 15:32:45,519 INFO L78 Accepts]: Start accepts. Automaton has 11739 states and 25493 transitions. Word has length 113 [2018-12-01 15:32:45,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:45,520 INFO L480 AbstractCegarLoop]: Abstraction has 11739 states and 25493 transitions. [2018-12-01 15:32:45,520 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 15:32:45,520 INFO L276 IsEmpty]: Start isEmpty. Operand 11739 states and 25493 transitions. [2018-12-01 15:32:45,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-12-01 15:32:45,530 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:45,530 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:45,531 INFO L423 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:45,531 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:45,531 INFO L82 PathProgramCache]: Analyzing trace with hash 1845403320, now seen corresponding path program 1 times [2018-12-01 15:32:45,531 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:45,531 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:45,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:45,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:45,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:45,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:45,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:45,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:45,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-12-01 15:32:45,606 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-01 15:32:45,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-01 15:32:45,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:45,607 INFO L87 Difference]: Start difference. First operand 11739 states and 25493 transitions. Second operand 7 states. [2018-12-01 15:32:45,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:45,723 INFO L93 Difference]: Finished difference Result 13402 states and 29199 transitions. [2018-12-01 15:32:45,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-01 15:32:45,724 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 113 [2018-12-01 15:32:45,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:45,732 INFO L225 Difference]: With dead ends: 13402 [2018-12-01 15:32:45,732 INFO L226 Difference]: Without dead ends: 13402 [2018-12-01 15:32:45,732 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-12-01 15:32:45,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13402 states. [2018-12-01 15:32:45,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13402 to 10290. [2018-12-01 15:32:45,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10290 states. [2018-12-01 15:32:45,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10290 states to 10290 states and 22261 transitions. [2018-12-01 15:32:45,818 INFO L78 Accepts]: Start accepts. Automaton has 10290 states and 22261 transitions. Word has length 113 [2018-12-01 15:32:45,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:45,818 INFO L480 AbstractCegarLoop]: Abstraction has 10290 states and 22261 transitions. [2018-12-01 15:32:45,818 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-01 15:32:45,819 INFO L276 IsEmpty]: Start isEmpty. Operand 10290 states and 22261 transitions. [2018-12-01 15:32:45,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-12-01 15:32:45,826 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:45,826 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:45,826 INFO L423 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:45,826 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:45,826 INFO L82 PathProgramCache]: Analyzing trace with hash -1204799495, now seen corresponding path program 1 times [2018-12-01 15:32:45,826 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:45,827 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:45,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:45,827 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:45,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:45,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:45,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:45,885 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:45,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 15:32:45,885 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 15:32:45,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 15:32:45,885 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-01 15:32:45,885 INFO L87 Difference]: Start difference. First operand 10290 states and 22261 transitions. Second operand 5 states. [2018-12-01 15:32:45,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:45,916 INFO L93 Difference]: Finished difference Result 10290 states and 22245 transitions. [2018-12-01 15:32:45,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 15:32:45,916 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-12-01 15:32:45,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:45,923 INFO L225 Difference]: With dead ends: 10290 [2018-12-01 15:32:45,923 INFO L226 Difference]: Without dead ends: 10290 [2018-12-01 15:32:45,923 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:45,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10290 states. [2018-12-01 15:32:45,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10290 to 10290. [2018-12-01 15:32:45,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10290 states. [2018-12-01 15:32:45,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10290 states to 10290 states and 22245 transitions. [2018-12-01 15:32:45,993 INFO L78 Accepts]: Start accepts. Automaton has 10290 states and 22245 transitions. Word has length 113 [2018-12-01 15:32:45,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:45,993 INFO L480 AbstractCegarLoop]: Abstraction has 10290 states and 22245 transitions. [2018-12-01 15:32:45,993 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 15:32:45,993 INFO L276 IsEmpty]: Start isEmpty. Operand 10290 states and 22245 transitions. [2018-12-01 15:32:46,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-12-01 15:32:46,000 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:46,000 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:46,000 INFO L423 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:46,000 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:46,000 INFO L82 PathProgramCache]: Analyzing trace with hash 1282713338, now seen corresponding path program 1 times [2018-12-01 15:32:46,000 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:46,000 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:46,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,001 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:46,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:46,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:46,021 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:46,021 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-01 15:32:46,022 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-01 15:32:46,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-01 15:32:46,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 15:32:46,022 INFO L87 Difference]: Start difference. First operand 10290 states and 22245 transitions. Second operand 3 states. [2018-12-01 15:32:46,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:46,037 INFO L93 Difference]: Finished difference Result 10290 states and 22229 transitions. [2018-12-01 15:32:46,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-01 15:32:46,037 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2018-12-01 15:32:46,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:46,044 INFO L225 Difference]: With dead ends: 10290 [2018-12-01 15:32:46,044 INFO L226 Difference]: Without dead ends: 10290 [2018-12-01 15:32:46,045 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 15:32:46,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10290 states. [2018-12-01 15:32:46,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10290 to 10290. [2018-12-01 15:32:46,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10290 states. [2018-12-01 15:32:46,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10290 states to 10290 states and 22229 transitions. [2018-12-01 15:32:46,120 INFO L78 Accepts]: Start accepts. Automaton has 10290 states and 22229 transitions. Word has length 113 [2018-12-01 15:32:46,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:46,120 INFO L480 AbstractCegarLoop]: Abstraction has 10290 states and 22229 transitions. [2018-12-01 15:32:46,120 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-01 15:32:46,120 INFO L276 IsEmpty]: Start isEmpty. Operand 10290 states and 22229 transitions. [2018-12-01 15:32:46,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-01 15:32:46,128 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:46,128 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:46,128 INFO L423 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:46,128 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:46,128 INFO L82 PathProgramCache]: Analyzing trace with hash 1031376510, now seen corresponding path program 1 times [2018-12-01 15:32:46,128 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:46,128 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:46,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:46,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:46,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:46,210 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:46,211 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-12-01 15:32:46,211 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-01 15:32:46,211 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-01 15:32:46,211 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-12-01 15:32:46,211 INFO L87 Difference]: Start difference. First operand 10290 states and 22229 transitions. Second operand 9 states. [2018-12-01 15:32:46,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:46,470 INFO L93 Difference]: Finished difference Result 12562 states and 27279 transitions. [2018-12-01 15:32:46,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-01 15:32:46,470 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 115 [2018-12-01 15:32:46,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:46,472 INFO L225 Difference]: With dead ends: 12562 [2018-12-01 15:32:46,472 INFO L226 Difference]: Without dead ends: 2404 [2018-12-01 15:32:46,472 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2018-12-01 15:32:46,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2404 states. [2018-12-01 15:32:46,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2404 to 2404. [2018-12-01 15:32:46,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2404 states. [2018-12-01 15:32:46,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2404 states to 2404 states and 5331 transitions. [2018-12-01 15:32:46,485 INFO L78 Accepts]: Start accepts. Automaton has 2404 states and 5331 transitions. Word has length 115 [2018-12-01 15:32:46,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:46,486 INFO L480 AbstractCegarLoop]: Abstraction has 2404 states and 5331 transitions. [2018-12-01 15:32:46,486 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-01 15:32:46,486 INFO L276 IsEmpty]: Start isEmpty. Operand 2404 states and 5331 transitions. [2018-12-01 15:32:46,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-01 15:32:46,487 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:46,487 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:46,487 INFO L423 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:46,487 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:46,488 INFO L82 PathProgramCache]: Analyzing trace with hash 1562191195, now seen corresponding path program 1 times [2018-12-01 15:32:46,488 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:46,488 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:46,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,489 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:46,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:46,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:46,545 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:46,545 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 15:32:46,545 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 15:32:46,546 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 15:32:46,546 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:46,546 INFO L87 Difference]: Start difference. First operand 2404 states and 5331 transitions. Second operand 6 states. [2018-12-01 15:32:46,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:46,644 INFO L93 Difference]: Finished difference Result 2352 states and 5122 transitions. [2018-12-01 15:32:46,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 15:32:46,645 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 115 [2018-12-01 15:32:46,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:46,646 INFO L225 Difference]: With dead ends: 2352 [2018-12-01 15:32:46,646 INFO L226 Difference]: Without dead ends: 2352 [2018-12-01 15:32:46,646 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:46,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2352 states. [2018-12-01 15:32:46,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2352 to 1937. [2018-12-01 15:32:46,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1937 states. [2018-12-01 15:32:46,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1937 states to 1937 states and 4208 transitions. [2018-12-01 15:32:46,658 INFO L78 Accepts]: Start accepts. Automaton has 1937 states and 4208 transitions. Word has length 115 [2018-12-01 15:32:46,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:46,658 INFO L480 AbstractCegarLoop]: Abstraction has 1937 states and 4208 transitions. [2018-12-01 15:32:46,659 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 15:32:46,659 INFO L276 IsEmpty]: Start isEmpty. Operand 1937 states and 4208 transitions. [2018-12-01 15:32:46,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-01 15:32:46,660 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:46,660 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:46,660 INFO L423 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:46,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:46,660 INFO L82 PathProgramCache]: Analyzing trace with hash 432349851, now seen corresponding path program 1 times [2018-12-01 15:32:46,660 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:46,660 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:46,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,661 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:46,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:46,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:46,732 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:46,732 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 15:32:46,733 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 15:32:46,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 15:32:46,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-12-01 15:32:46,733 INFO L87 Difference]: Start difference. First operand 1937 states and 4208 transitions. Second operand 6 states. [2018-12-01 15:32:46,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:46,823 INFO L93 Difference]: Finished difference Result 2169 states and 4671 transitions. [2018-12-01 15:32:46,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-01 15:32:46,823 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 115 [2018-12-01 15:32:46,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:46,825 INFO L225 Difference]: With dead ends: 2169 [2018-12-01 15:32:46,825 INFO L226 Difference]: Without dead ends: 2138 [2018-12-01 15:32:46,825 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-12-01 15:32:46,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2138 states. [2018-12-01 15:32:46,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2138 to 1835. [2018-12-01 15:32:46,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1835 states. [2018-12-01 15:32:46,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1835 states to 1835 states and 3985 transitions. [2018-12-01 15:32:46,836 INFO L78 Accepts]: Start accepts. Automaton has 1835 states and 3985 transitions. Word has length 115 [2018-12-01 15:32:46,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:46,836 INFO L480 AbstractCegarLoop]: Abstraction has 1835 states and 3985 transitions. [2018-12-01 15:32:46,836 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 15:32:46,836 INFO L276 IsEmpty]: Start isEmpty. Operand 1835 states and 3985 transitions. [2018-12-01 15:32:46,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-01 15:32:46,837 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:46,838 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:46,838 INFO L423 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:46,838 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:46,838 INFO L82 PathProgramCache]: Analyzing trace with hash 1125451548, now seen corresponding path program 2 times [2018-12-01 15:32:46,838 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:46,838 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:46,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,839 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:46,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:46,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:47,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:47,013 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:47,013 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2018-12-01 15:32:47,013 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-12-01 15:32:47,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-12-01 15:32:47,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=232, Unknown=0, NotChecked=0, Total=272 [2018-12-01 15:32:47,013 INFO L87 Difference]: Start difference. First operand 1835 states and 3985 transitions. Second operand 17 states. [2018-12-01 15:32:47,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:47,419 INFO L93 Difference]: Finished difference Result 1991 states and 4323 transitions. [2018-12-01 15:32:47,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-12-01 15:32:47,419 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 115 [2018-12-01 15:32:47,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:47,420 INFO L225 Difference]: With dead ends: 1991 [2018-12-01 15:32:47,420 INFO L226 Difference]: Without dead ends: 1895 [2018-12-01 15:32:47,421 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=144, Invalid=612, Unknown=0, NotChecked=0, Total=756 [2018-12-01 15:32:47,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1895 states. [2018-12-01 15:32:47,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1895 to 1835. [2018-12-01 15:32:47,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1835 states. [2018-12-01 15:32:47,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1835 states to 1835 states and 3969 transitions. [2018-12-01 15:32:47,431 INFO L78 Accepts]: Start accepts. Automaton has 1835 states and 3969 transitions. Word has length 115 [2018-12-01 15:32:47,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:47,432 INFO L480 AbstractCegarLoop]: Abstraction has 1835 states and 3969 transitions. [2018-12-01 15:32:47,432 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-12-01 15:32:47,432 INFO L276 IsEmpty]: Start isEmpty. Operand 1835 states and 3969 transitions. [2018-12-01 15:32:47,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-01 15:32:47,433 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:47,433 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:47,433 INFO L423 AbstractCegarLoop]: === Iteration 38 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:47,433 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:47,433 INFO L82 PathProgramCache]: Analyzing trace with hash -617358787, now seen corresponding path program 1 times [2018-12-01 15:32:47,433 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:47,433 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:47,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:47,434 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-01 15:32:47,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:47,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 15:32:47,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 15:32:47,848 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 15:32:47,848 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [] total 27 [2018-12-01 15:32:47,848 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-01 15:32:47,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-01 15:32:47,848 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=634, Unknown=0, NotChecked=0, Total=702 [2018-12-01 15:32:47,848 INFO L87 Difference]: Start difference. First operand 1835 states and 3969 transitions. Second operand 27 states. [2018-12-01 15:32:49,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 15:32:49,537 INFO L93 Difference]: Finished difference Result 2965 states and 6511 transitions. [2018-12-01 15:32:49,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-01 15:32:49,537 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 115 [2018-12-01 15:32:49,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 15:32:49,538 INFO L225 Difference]: With dead ends: 2965 [2018-12-01 15:32:49,538 INFO L226 Difference]: Without dead ends: 1998 [2018-12-01 15:32:49,539 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 418 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=393, Invalid=1959, Unknown=0, NotChecked=0, Total=2352 [2018-12-01 15:32:49,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1998 states. [2018-12-01 15:32:49,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1998 to 1847. [2018-12-01 15:32:49,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1847 states. [2018-12-01 15:32:49,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1847 states to 1847 states and 3985 transitions. [2018-12-01 15:32:49,550 INFO L78 Accepts]: Start accepts. Automaton has 1847 states and 3985 transitions. Word has length 115 [2018-12-01 15:32:49,550 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 15:32:49,550 INFO L480 AbstractCegarLoop]: Abstraction has 1847 states and 3985 transitions. [2018-12-01 15:32:49,550 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-01 15:32:49,550 INFO L276 IsEmpty]: Start isEmpty. Operand 1847 states and 3985 transitions. [2018-12-01 15:32:49,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-01 15:32:49,551 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 15:32:49,551 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 15:32:49,551 INFO L423 AbstractCegarLoop]: === Iteration 39 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 15:32:49,551 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 15:32:49,551 INFO L82 PathProgramCache]: Analyzing trace with hash -313970737, now seen corresponding path program 2 times [2018-12-01 15:32:49,551 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 15:32:49,551 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 15:32:49,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:49,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 15:32:49,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 15:32:49,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-01 15:32:49,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-01 15:32:49,606 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-01 15:32:49,726 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-12-01 15:32:49,727 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 01.12 03:32:49 BasicIcfg [2018-12-01 15:32:49,727 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-01 15:32:49,727 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-01 15:32:49,727 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-01 15:32:49,727 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-01 15:32:49,728 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 01.12 03:32:20" (3/4) ... [2018-12-01 15:32:49,729 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-01 15:32:49,841 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_c01eaa4e-046c-4ddc-8f2b-3401a7abb659/bin-2019/uautomizer/witness.graphml [2018-12-01 15:32:49,841 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-01 15:32:49,842 INFO L168 Benchmark]: Toolchain (without parser) took 29987.82 ms. Allocated memory was 1.0 GB in the beginning and 3.4 GB in the end (delta: 2.4 GB). Free memory was 951.7 MB in the beginning and 1.4 GB in the end (delta: -444.8 MB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. [2018-12-01 15:32:49,843 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-01 15:32:49,843 INFO L168 Benchmark]: CACSL2BoogieTranslator took 381.89 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 120.1 MB). Free memory was 951.7 MB in the beginning and 1.1 GB in the end (delta: -146.2 MB). Peak memory consumption was 32.9 MB. Max. memory is 11.5 GB. [2018-12-01 15:32:49,844 INFO L168 Benchmark]: Boogie Procedure Inliner took 31.32 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-12-01 15:32:49,844 INFO L168 Benchmark]: Boogie Preprocessor took 21.19 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-01 15:32:49,844 INFO L168 Benchmark]: RCFGBuilder took 420.49 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 66.6 MB). Peak memory consumption was 66.6 MB. Max. memory is 11.5 GB. [2018-12-01 15:32:49,844 INFO L168 Benchmark]: TraceAbstraction took 29015.75 ms. Allocated memory was 1.1 GB in the beginning and 3.4 GB in the end (delta: 2.3 GB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -462.6 MB). Peak memory consumption was 1.8 GB. Max. memory is 11.5 GB. [2018-12-01 15:32:49,845 INFO L168 Benchmark]: Witness Printer took 114.41 ms. Allocated memory is still 3.4 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 92.0 MB). Peak memory consumption was 92.0 MB. Max. memory is 11.5 GB. [2018-12-01 15:32:49,846 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 381.89 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 120.1 MB). Free memory was 951.7 MB in the beginning and 1.1 GB in the end (delta: -146.2 MB). Peak memory consumption was 32.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 31.32 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 21.19 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 420.49 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 66.6 MB). Peak memory consumption was 66.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 29015.75 ms. Allocated memory was 1.1 GB in the beginning and 3.4 GB in the end (delta: 2.3 GB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -462.6 MB). Peak memory consumption was 1.8 GB. Max. memory is 11.5 GB. * Witness Printer took 114.41 ms. Allocated memory is still 3.4 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 92.0 MB). Peak memory consumption was 92.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L676] -1 _Bool __unbuffered_p1_EAX$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0] [L677] -1 int __unbuffered_p1_EAX$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0] [L678] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0] [L679] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0] [L680] -1 _Bool __unbuffered_p1_EAX$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0] [L681] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0] [L682] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0] [L683] -1 _Bool __unbuffered_p1_EAX$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0] [L684] -1 _Bool __unbuffered_p1_EAX$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0] [L685] -1 int *__unbuffered_p1_EAX$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}] [L686] -1 int __unbuffered_p1_EAX$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0] [L687] -1 _Bool __unbuffered_p1_EAX$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0] [L688] -1 int __unbuffered_p1_EAX$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0] [L689] -1 _Bool __unbuffered_p1_EAX$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0] [L690] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0] [L691] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L693] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}] [L694] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0] [L695] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0] [L696] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L697] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L698] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L699] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L700] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L701] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L702] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L703] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L704] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L705] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L706] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L707] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L709] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L710] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L711] -1 _Bool weak$$choice1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L712] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L788] -1 pthread_t t1925; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L789] FCALL, FORK -1 pthread_create(&t1925, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L790] -1 pthread_t t1926; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L791] FCALL, FORK -1 pthread_create(&t1926, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L744] 0 weak$$choice0 = __VERIFIER_nondet_pointer() [L745] 0 weak$$choice2 = __VERIFIER_nondet_pointer() [L746] 0 x$flush_delayed = weak$$choice2 [L747] EXPR 0 \read(x) [L747] 0 x$mem_tmp = x [L748] 0 weak$$choice1 = __VERIFIER_nondet_pointer() [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L749] EXPR 0 \read(x) [L749] EXPR 0 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) VAL [!x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x))))=0, \read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L749] 0 x = !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L750] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L750] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) [L751] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L751] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) [L752] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L752] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) [L753] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L753] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L754] EXPR 0 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] 0 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L755] EXPR 0 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] 0 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L756] 0 __unbuffered_p1_EAX$read_delayed = (_Bool)1 [L757] 0 __unbuffered_p1_EAX$read_delayed_var = &x [L758] EXPR 0 \read(x) [L758] 0 __unbuffered_p1_EAX = x [L759] EXPR 0 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L759] 0 x = x$flush_delayed ? x$mem_tmp : x [L760] 0 x$flush_delayed = (_Bool)0 [L763] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L716] 1 __unbuffered_p0_EAX = y [L719] 1 x$w_buff1 = x$w_buff0 [L720] 1 x$w_buff0 = 1 [L721] 1 x$w_buff1_used = x$w_buff0_used [L722] 1 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 1 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L724] 1 x$r_buff1_thd0 = x$r_buff0_thd0 [L725] 1 x$r_buff1_thd1 = x$r_buff0_thd1 [L726] 1 x$r_buff1_thd2 = x$r_buff0_thd2 [L727] 1 x$r_buff0_thd1 = (_Bool)1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x [L766] EXPR 0 \read(x) [L766] EXPR 0 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L730] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=1] [L766] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L730] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L767] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L767] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L768] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L768] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L769] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L769] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L770] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L770] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L773] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L731] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L732] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L732] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L733] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L734] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L734] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L737] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L793] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x [L797] EXPR -1 \read(x) [L797] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L797] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L798] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L798] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L799] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L799] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L800] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L800] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L801] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L801] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L804] -1 weak$$choice1 = __VERIFIER_nondet_pointer() [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX [L805] EXPR -1 \read(*__unbuffered_p1_EAX$read_delayed_var) [L805] EXPR -1 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] EXPR -1 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L805] -1 __unbuffered_p1_EAX = __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX [L806] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p1_EAX == 1) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={6:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 318 locations, 3 error locations. UNSAFE Result, 28.9s OverallTime, 39 OverallIterations, 1 TraceHistogramMax, 13.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 12914 SDtfs, 16599 SDslu, 32730 SDs, 0 SdLazy, 12224 SolverSat, 840 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 443 GetRequests, 100 SyntacticMatches, 34 SemanticMatches, 309 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 884 ImplicationChecksByTransitivity, 3.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=65314occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 9.0s AutomataMinimizationTime, 38 MinimizatonAttempts, 145664 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.1s InterpolantComputationTime, 3699 NumberOfCodeBlocks, 3699 NumberOfCodeBlocksAsserted, 39 NumberOfCheckSat, 3546 ConstructedInterpolants, 0 QuantifiedInterpolants, 1005529 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 38 InterpolantComputations, 38 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...