./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-02 21:34:42,273 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-02 21:34:42,274 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-02 21:34:42,280 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-02 21:34:42,280 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-02 21:34:42,281 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-02 21:34:42,281 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-02 21:34:42,282 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-02 21:34:42,283 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-02 21:34:42,283 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-02 21:34:42,284 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-02 21:34:42,284 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-02 21:34:42,284 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-02 21:34:42,285 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-02 21:34:42,285 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-02 21:34:42,286 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-02 21:34:42,286 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-02 21:34:42,287 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-02 21:34:42,288 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-02 21:34:42,289 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-02 21:34:42,289 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-02 21:34:42,290 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-02 21:34:42,291 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-02 21:34:42,291 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-02 21:34:42,291 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-02 21:34:42,292 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-02 21:34:42,292 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-02 21:34:42,293 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-02 21:34:42,293 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-02 21:34:42,294 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-02 21:34:42,294 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-02 21:34:42,294 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-02 21:34:42,294 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-02 21:34:42,294 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-02 21:34:42,295 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-02 21:34:42,295 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-02 21:34:42,295 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-12-02 21:34:42,302 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-02 21:34:42,302 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-02 21:34:42,303 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-02 21:34:42,303 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-02 21:34:42,303 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-02 21:34:42,303 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-02 21:34:42,303 INFO L133 SettingsManager]: * Use SBE=true [2018-12-02 21:34:42,303 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-02 21:34:42,303 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-02 21:34:42,304 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-02 21:34:42,304 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 21:34:42,305 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-02 21:34:42,305 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 [2018-12-02 21:34:42,323 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-02 21:34:42,332 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-02 21:34:42,334 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-02 21:34:42,335 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-02 21:34:42,336 INFO L276 PluginConnector]: CDTParser initialized [2018-12-02 21:34:42,336 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c [2018-12-02 21:34:42,373 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/data/d24f4cda4/9c40f9af45664dc584525eafb85a1e5c/FLAG0bb98feba [2018-12-02 21:34:42,719 INFO L307 CDTParser]: Found 1 translation units. [2018-12-02 21:34:42,720 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c [2018-12-02 21:34:42,725 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/data/d24f4cda4/9c40f9af45664dc584525eafb85a1e5c/FLAG0bb98feba [2018-12-02 21:34:42,733 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/data/d24f4cda4/9c40f9af45664dc584525eafb85a1e5c [2018-12-02 21:34:42,735 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-02 21:34:42,735 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-02 21:34:42,736 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-02 21:34:42,736 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-02 21:34:42,738 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-02 21:34:42,738 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,740 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@484c0a6e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42, skipping insertion in model container [2018-12-02 21:34:42,740 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,744 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-02 21:34:42,761 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-02 21:34:42,869 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 21:34:42,872 INFO L191 MainTranslator]: Completed pre-run [2018-12-02 21:34:42,899 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-02 21:34:42,908 INFO L195 MainTranslator]: Completed translation [2018-12-02 21:34:42,908 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42 WrapperNode [2018-12-02 21:34:42,908 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-02 21:34:42,909 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-02 21:34:42,909 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-02 21:34:42,909 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-02 21:34:42,913 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,918 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,952 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-02 21:34:42,952 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-02 21:34:42,952 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-02 21:34:42,952 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-02 21:34:42,959 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,959 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,960 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,960 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,965 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,973 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,974 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... [2018-12-02 21:34:42,976 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-02 21:34:42,976 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-02 21:34:42,976 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-02 21:34:42,977 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-02 21:34:42,977 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-02 21:34:43,009 INFO L130 BoogieDeclarations]: Found specification of procedure read [2018-12-02 21:34:43,009 INFO L138 BoogieDeclarations]: Found implementation of procedure read [2018-12-02 21:34:43,009 INFO L130 BoogieDeclarations]: Found specification of procedure write_back [2018-12-02 21:34:43,009 INFO L138 BoogieDeclarations]: Found implementation of procedure write_back [2018-12-02 21:34:43,009 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-02 21:34:43,009 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-02 21:34:43,010 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-02 21:34:43,010 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-02 21:34:43,010 INFO L130 BoogieDeclarations]: Found specification of procedure compute2 [2018-12-02 21:34:43,010 INFO L138 BoogieDeclarations]: Found implementation of procedure compute2 [2018-12-02 21:34:43,010 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-02 21:34:43,010 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-02 21:34:43,010 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-02 21:34:43,010 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-02 21:34:43,010 INFO L130 BoogieDeclarations]: Found specification of procedure compute1 [2018-12-02 21:34:43,010 INFO L138 BoogieDeclarations]: Found implementation of procedure compute1 [2018-12-02 21:34:43,010 INFO L130 BoogieDeclarations]: Found specification of procedure write_loop [2018-12-02 21:34:43,011 INFO L138 BoogieDeclarations]: Found implementation of procedure write_loop [2018-12-02 21:34:43,011 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-02 21:34:43,011 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-02 21:34:43,011 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-02 21:34:43,011 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-02 21:34:43,299 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-02 21:34:43,300 INFO L280 CfgBuilder]: Removed 6 assue(true) statements. [2018-12-02 21:34:43,300 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 09:34:43 BoogieIcfgContainer [2018-12-02 21:34:43,300 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-02 21:34:43,300 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-02 21:34:43,300 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-02 21:34:43,303 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-02 21:34:43,303 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 09:34:42" (1/3) ... [2018-12-02 21:34:43,303 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@39bade28 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 09:34:43, skipping insertion in model container [2018-12-02 21:34:43,303 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 09:34:42" (2/3) ... [2018-12-02 21:34:43,304 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@39bade28 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 09:34:43, skipping insertion in model container [2018-12-02 21:34:43,304 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 09:34:43" (3/3) ... [2018-12-02 21:34:43,305 INFO L112 eAbstractionObserver]: Analyzing ICFG toy1_false-unreach-call_false-termination.cil.c [2018-12-02 21:34:43,311 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-02 21:34:43,316 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-02 21:34:43,326 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-02 21:34:43,345 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-02 21:34:43,346 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-02 21:34:43,346 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-02 21:34:43,346 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-02 21:34:43,346 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-02 21:34:43,346 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-02 21:34:43,346 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-02 21:34:43,347 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-02 21:34:43,347 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-02 21:34:43,359 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states. [2018-12-02 21:34:43,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:43,364 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:43,365 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:43,366 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:43,370 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:43,370 INFO L82 PathProgramCache]: Analyzing trace with hash -1366020299, now seen corresponding path program 1 times [2018-12-02 21:34:43,371 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:43,371 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:43,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:43,400 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:43,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:43,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:43,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:43,505 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:43,505 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 21:34:43,507 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 21:34:43,515 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 21:34:43,515 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:34:43,516 INFO L87 Difference]: Start difference. First operand 161 states. Second operand 3 states. [2018-12-02 21:34:43,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:43,549 INFO L93 Difference]: Finished difference Result 304 states and 521 transitions. [2018-12-02 21:34:43,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 21:34:43,550 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-02 21:34:43,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:43,557 INFO L225 Difference]: With dead ends: 304 [2018-12-02 21:34:43,558 INFO L226 Difference]: Without dead ends: 152 [2018-12-02 21:34:43,560 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:34:43,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-12-02 21:34:43,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 152. [2018-12-02 21:34:43,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-12-02 21:34:43,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 246 transitions. [2018-12-02 21:34:43,590 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 246 transitions. Word has length 47 [2018-12-02 21:34:43,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:43,590 INFO L480 AbstractCegarLoop]: Abstraction has 152 states and 246 transitions. [2018-12-02 21:34:43,590 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 21:34:43,590 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 246 transitions. [2018-12-02 21:34:43,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:43,591 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:43,592 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:43,592 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:43,592 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:43,592 INFO L82 PathProgramCache]: Analyzing trace with hash 684963699, now seen corresponding path program 1 times [2018-12-02 21:34:43,592 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:43,592 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:43,593 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:43,593 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:43,593 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:43,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:43,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:43,638 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:43,638 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:43,639 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:43,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:43,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:43,640 INFO L87 Difference]: Start difference. First operand 152 states and 246 transitions. Second operand 4 states. [2018-12-02 21:34:43,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:43,777 INFO L93 Difference]: Finished difference Result 394 states and 641 transitions. [2018-12-02 21:34:43,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 21:34:43,778 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-02 21:34:43,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:43,780 INFO L225 Difference]: With dead ends: 394 [2018-12-02 21:34:43,780 INFO L226 Difference]: Without dead ends: 259 [2018-12-02 21:34:43,781 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:43,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 259 states. [2018-12-02 21:34:43,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 259 to 249. [2018-12-02 21:34:43,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 249 states. [2018-12-02 21:34:43,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 402 transitions. [2018-12-02 21:34:43,805 INFO L78 Accepts]: Start accepts. Automaton has 249 states and 402 transitions. Word has length 47 [2018-12-02 21:34:43,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:43,806 INFO L480 AbstractCegarLoop]: Abstraction has 249 states and 402 transitions. [2018-12-02 21:34:43,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:43,806 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 402 transitions. [2018-12-02 21:34:43,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:43,808 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:43,808 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:43,808 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:43,808 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:43,809 INFO L82 PathProgramCache]: Analyzing trace with hash 959723313, now seen corresponding path program 1 times [2018-12-02 21:34:43,809 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:43,809 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:43,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:43,810 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:43,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:43,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:43,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:43,869 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:43,869 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:43,869 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:43,870 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:43,870 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:43,870 INFO L87 Difference]: Start difference. First operand 249 states and 402 transitions. Second operand 4 states. [2018-12-02 21:34:44,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:44,007 INFO L93 Difference]: Finished difference Result 675 states and 1099 transitions. [2018-12-02 21:34:44,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 21:34:44,007 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-02 21:34:44,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:44,009 INFO L225 Difference]: With dead ends: 675 [2018-12-02 21:34:44,009 INFO L226 Difference]: Without dead ends: 445 [2018-12-02 21:34:44,010 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:44,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445 states. [2018-12-02 21:34:44,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445 to 431. [2018-12-02 21:34:44,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 431 states. [2018-12-02 21:34:44,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431 states to 431 states and 699 transitions. [2018-12-02 21:34:44,036 INFO L78 Accepts]: Start accepts. Automaton has 431 states and 699 transitions. Word has length 47 [2018-12-02 21:34:44,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:44,037 INFO L480 AbstractCegarLoop]: Abstraction has 431 states and 699 transitions. [2018-12-02 21:34:44,037 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:44,037 INFO L276 IsEmpty]: Start isEmpty. Operand 431 states and 699 transitions. [2018-12-02 21:34:44,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:44,038 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:44,039 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:44,039 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:44,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:44,039 INFO L82 PathProgramCache]: Analyzing trace with hash 1661323187, now seen corresponding path program 1 times [2018-12-02 21:34:44,039 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:44,039 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:44,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:44,040 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:44,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:44,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:44,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:44,081 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:44,081 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:44,082 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:44,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:44,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:44,082 INFO L87 Difference]: Start difference. First operand 431 states and 699 transitions. Second operand 4 states. [2018-12-02 21:34:44,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:44,212 INFO L93 Difference]: Finished difference Result 1281 states and 2081 transitions. [2018-12-02 21:34:44,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 21:34:44,212 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-02 21:34:44,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:44,215 INFO L225 Difference]: With dead ends: 1281 [2018-12-02 21:34:44,215 INFO L226 Difference]: Without dead ends: 870 [2018-12-02 21:34:44,217 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:44,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 870 states. [2018-12-02 21:34:44,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 870 to 860. [2018-12-02 21:34:44,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 860 states. [2018-12-02 21:34:44,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 860 states to 860 states and 1387 transitions. [2018-12-02 21:34:44,250 INFO L78 Accepts]: Start accepts. Automaton has 860 states and 1387 transitions. Word has length 47 [2018-12-02 21:34:44,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:44,251 INFO L480 AbstractCegarLoop]: Abstraction has 860 states and 1387 transitions. [2018-12-02 21:34:44,251 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:44,251 INFO L276 IsEmpty]: Start isEmpty. Operand 860 states and 1387 transitions. [2018-12-02 21:34:44,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:44,253 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:44,253 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:44,253 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:44,253 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:44,253 INFO L82 PathProgramCache]: Analyzing trace with hash 1683955441, now seen corresponding path program 1 times [2018-12-02 21:34:44,254 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:44,254 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:44,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:44,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:44,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:44,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:44,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:44,281 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:44,281 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:44,282 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:44,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:44,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:44,282 INFO L87 Difference]: Start difference. First operand 860 states and 1387 transitions. Second operand 4 states. [2018-12-02 21:34:44,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:44,452 INFO L93 Difference]: Finished difference Result 3013 states and 4877 transitions. [2018-12-02 21:34:44,452 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 21:34:44,453 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-02 21:34:44,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:44,460 INFO L225 Difference]: With dead ends: 3013 [2018-12-02 21:34:44,460 INFO L226 Difference]: Without dead ends: 2185 [2018-12-02 21:34:44,462 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:44,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2185 states. [2018-12-02 21:34:44,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2185 to 2115. [2018-12-02 21:34:44,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2115 states. [2018-12-02 21:34:44,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2115 states to 2115 states and 3404 transitions. [2018-12-02 21:34:44,558 INFO L78 Accepts]: Start accepts. Automaton has 2115 states and 3404 transitions. Word has length 47 [2018-12-02 21:34:44,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:44,558 INFO L480 AbstractCegarLoop]: Abstraction has 2115 states and 3404 transitions. [2018-12-02 21:34:44,558 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:44,558 INFO L276 IsEmpty]: Start isEmpty. Operand 2115 states and 3404 transitions. [2018-12-02 21:34:44,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:44,560 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:44,560 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:44,561 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:44,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:44,561 INFO L82 PathProgramCache]: Analyzing trace with hash -1224808461, now seen corresponding path program 1 times [2018-12-02 21:34:44,561 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:44,561 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:44,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:44,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:44,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:44,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:44,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:44,624 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:44,625 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 21:34:44,625 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 21:34:44,625 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 21:34:44,625 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:44,625 INFO L87 Difference]: Start difference. First operand 2115 states and 3404 transitions. Second operand 5 states. [2018-12-02 21:34:44,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:44,893 INFO L93 Difference]: Finished difference Result 6477 states and 10462 transitions. [2018-12-02 21:34:44,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 21:34:44,893 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-12-02 21:34:44,893 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:44,909 INFO L225 Difference]: With dead ends: 6477 [2018-12-02 21:34:44,910 INFO L226 Difference]: Without dead ends: 4382 [2018-12-02 21:34:44,916 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-02 21:34:44,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4382 states. [2018-12-02 21:34:45,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4382 to 3296. [2018-12-02 21:34:45,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3296 states. [2018-12-02 21:34:45,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3296 states to 3296 states and 5300 transitions. [2018-12-02 21:34:45,027 INFO L78 Accepts]: Start accepts. Automaton has 3296 states and 5300 transitions. Word has length 47 [2018-12-02 21:34:45,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:45,027 INFO L480 AbstractCegarLoop]: Abstraction has 3296 states and 5300 transitions. [2018-12-02 21:34:45,027 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 21:34:45,027 INFO L276 IsEmpty]: Start isEmpty. Operand 3296 states and 5300 transitions. [2018-12-02 21:34:45,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:45,030 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:45,030 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:45,030 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:45,030 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:45,030 INFO L82 PathProgramCache]: Analyzing trace with hash -424223241, now seen corresponding path program 1 times [2018-12-02 21:34:45,030 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:45,030 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:45,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:45,031 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:45,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:45,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:45,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:45,065 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:45,065 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:45,066 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:45,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:45,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:45,066 INFO L87 Difference]: Start difference. First operand 3296 states and 5300 transitions. Second operand 4 states. [2018-12-02 21:34:45,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:45,282 INFO L93 Difference]: Finished difference Result 6609 states and 10702 transitions. [2018-12-02 21:34:45,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 21:34:45,282 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-02 21:34:45,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:45,291 INFO L225 Difference]: With dead ends: 6609 [2018-12-02 21:34:45,291 INFO L226 Difference]: Without dead ends: 3379 [2018-12-02 21:34:45,297 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:45,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3379 states. [2018-12-02 21:34:45,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3379 to 3359. [2018-12-02 21:34:45,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3359 states. [2018-12-02 21:34:45,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3359 states to 3359 states and 5291 transitions. [2018-12-02 21:34:45,406 INFO L78 Accepts]: Start accepts. Automaton has 3359 states and 5291 transitions. Word has length 47 [2018-12-02 21:34:45,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:45,406 INFO L480 AbstractCegarLoop]: Abstraction has 3359 states and 5291 transitions. [2018-12-02 21:34:45,406 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:45,406 INFO L276 IsEmpty]: Start isEmpty. Operand 3359 states and 5291 transitions. [2018-12-02 21:34:45,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:45,409 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:45,409 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:45,409 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:45,409 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:45,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1521415, now seen corresponding path program 1 times [2018-12-02 21:34:45,410 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:45,410 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:45,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:45,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:45,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:45,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:45,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:45,447 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:45,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:45,447 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:45,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:45,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:45,448 INFO L87 Difference]: Start difference. First operand 3359 states and 5291 transitions. Second operand 4 states. [2018-12-02 21:34:45,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:45,714 INFO L93 Difference]: Finished difference Result 6871 states and 10809 transitions. [2018-12-02 21:34:45,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 21:34:45,714 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-02 21:34:45,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:45,727 INFO L225 Difference]: With dead ends: 6871 [2018-12-02 21:34:45,727 INFO L226 Difference]: Without dead ends: 3594 [2018-12-02 21:34:45,735 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:45,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3594 states. [2018-12-02 21:34:45,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3594 to 3554. [2018-12-02 21:34:45,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3554 states. [2018-12-02 21:34:45,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3554 states to 3554 states and 5523 transitions. [2018-12-02 21:34:45,838 INFO L78 Accepts]: Start accepts. Automaton has 3554 states and 5523 transitions. Word has length 47 [2018-12-02 21:34:45,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:45,838 INFO L480 AbstractCegarLoop]: Abstraction has 3554 states and 5523 transitions. [2018-12-02 21:34:45,838 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:45,838 INFO L276 IsEmpty]: Start isEmpty. Operand 3554 states and 5523 transitions. [2018-12-02 21:34:45,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:45,839 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:45,839 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:45,839 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:45,839 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:45,840 INFO L82 PathProgramCache]: Analyzing trace with hash -819169865, now seen corresponding path program 1 times [2018-12-02 21:34:45,840 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:45,840 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:45,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:45,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:45,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:45,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:45,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:45,871 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:45,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:45,871 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:45,871 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:45,871 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:45,871 INFO L87 Difference]: Start difference. First operand 3554 states and 5523 transitions. Second operand 4 states. [2018-12-02 21:34:46,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:46,083 INFO L93 Difference]: Finished difference Result 7652 states and 12054 transitions. [2018-12-02 21:34:46,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 21:34:46,084 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-02 21:34:46,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:46,098 INFO L225 Difference]: With dead ends: 7652 [2018-12-02 21:34:46,099 INFO L226 Difference]: Without dead ends: 4156 [2018-12-02 21:34:46,110 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:46,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4156 states. [2018-12-02 21:34:46,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4156 to 4146. [2018-12-02 21:34:46,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4146 states. [2018-12-02 21:34:46,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4146 states to 4146 states and 6362 transitions. [2018-12-02 21:34:46,227 INFO L78 Accepts]: Start accepts. Automaton has 4146 states and 6362 transitions. Word has length 47 [2018-12-02 21:34:46,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:46,227 INFO L480 AbstractCegarLoop]: Abstraction has 4146 states and 6362 transitions. [2018-12-02 21:34:46,227 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:46,227 INFO L276 IsEmpty]: Start isEmpty. Operand 4146 states and 6362 transitions. [2018-12-02 21:34:46,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-02 21:34:46,228 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:46,228 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:46,228 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:46,228 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:46,229 INFO L82 PathProgramCache]: Analyzing trace with hash 1481652725, now seen corresponding path program 1 times [2018-12-02 21:34:46,229 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:46,229 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:46,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:46,229 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:46,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:46,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:46,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:46,254 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:46,254 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 21:34:46,254 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 21:34:46,254 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 21:34:46,255 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:34:46,255 INFO L87 Difference]: Start difference. First operand 4146 states and 6362 transitions. Second operand 3 states. [2018-12-02 21:34:46,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:46,441 INFO L93 Difference]: Finished difference Result 9137 states and 14288 transitions. [2018-12-02 21:34:46,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 21:34:46,441 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-02 21:34:46,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:46,452 INFO L225 Difference]: With dead ends: 9137 [2018-12-02 21:34:46,453 INFO L226 Difference]: Without dead ends: 5045 [2018-12-02 21:34:46,460 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:34:46,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5045 states. [2018-12-02 21:34:46,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5045 to 4973. [2018-12-02 21:34:46,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4973 states. [2018-12-02 21:34:46,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4973 states to 4973 states and 7578 transitions. [2018-12-02 21:34:46,584 INFO L78 Accepts]: Start accepts. Automaton has 4973 states and 7578 transitions. Word has length 47 [2018-12-02 21:34:46,584 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:46,584 INFO L480 AbstractCegarLoop]: Abstraction has 4973 states and 7578 transitions. [2018-12-02 21:34:46,584 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 21:34:46,585 INFO L276 IsEmpty]: Start isEmpty. Operand 4973 states and 7578 transitions. [2018-12-02 21:34:46,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-12-02 21:34:46,588 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:46,588 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:46,588 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:46,588 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:46,588 INFO L82 PathProgramCache]: Analyzing trace with hash 584484674, now seen corresponding path program 1 times [2018-12-02 21:34:46,588 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:46,588 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:46,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:46,589 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:46,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:46,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:46,622 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:46,622 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:46,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 21:34:46,623 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 21:34:46,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 21:34:46,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:46,623 INFO L87 Difference]: Start difference. First operand 4973 states and 7578 transitions. Second operand 5 states. [2018-12-02 21:34:47,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:47,182 INFO L93 Difference]: Finished difference Result 12503 states and 19791 transitions. [2018-12-02 21:34:47,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-02 21:34:47,182 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2018-12-02 21:34:47,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:47,200 INFO L225 Difference]: With dead ends: 12503 [2018-12-02 21:34:47,201 INFO L226 Difference]: Without dead ends: 7576 [2018-12-02 21:34:47,211 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-02 21:34:47,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7576 states. [2018-12-02 21:34:47,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7576 to 7478. [2018-12-02 21:34:47,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7478 states. [2018-12-02 21:34:47,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7478 states to 7478 states and 11595 transitions. [2018-12-02 21:34:47,424 INFO L78 Accepts]: Start accepts. Automaton has 7478 states and 11595 transitions. Word has length 67 [2018-12-02 21:34:47,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:47,424 INFO L480 AbstractCegarLoop]: Abstraction has 7478 states and 11595 transitions. [2018-12-02 21:34:47,424 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 21:34:47,425 INFO L276 IsEmpty]: Start isEmpty. Operand 7478 states and 11595 transitions. [2018-12-02 21:34:47,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-12-02 21:34:47,429 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:47,429 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:47,429 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:47,429 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:47,430 INFO L82 PathProgramCache]: Analyzing trace with hash -923082464, now seen corresponding path program 1 times [2018-12-02 21:34:47,430 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:47,430 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:47,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:47,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:47,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:47,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:47,470 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 19 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-12-02 21:34:47,471 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:34:47,471 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:34:47,478 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:47,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:47,550 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:34:47,590 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-12-02 21:34:47,614 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 21:34:47,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-12-02 21:34:47,615 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-02 21:34:47,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-02 21:34:47,615 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-02 21:34:47,615 INFO L87 Difference]: Start difference. First operand 7478 states and 11595 transitions. Second operand 8 states. [2018-12-02 21:34:49,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:49,023 INFO L93 Difference]: Finished difference Result 25947 states and 42735 transitions. [2018-12-02 21:34:49,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-12-02 21:34:49,024 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 81 [2018-12-02 21:34:49,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:49,047 INFO L225 Difference]: With dead ends: 25947 [2018-12-02 21:34:49,048 INFO L226 Difference]: Without dead ends: 6445 [2018-12-02 21:34:49,137 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=124, Invalid=338, Unknown=0, NotChecked=0, Total=462 [2018-12-02 21:34:49,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6445 states. [2018-12-02 21:34:49,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6445 to 4635. [2018-12-02 21:34:49,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4635 states. [2018-12-02 21:34:49,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4635 states to 4635 states and 6932 transitions. [2018-12-02 21:34:49,341 INFO L78 Accepts]: Start accepts. Automaton has 4635 states and 6932 transitions. Word has length 81 [2018-12-02 21:34:49,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:49,342 INFO L480 AbstractCegarLoop]: Abstraction has 4635 states and 6932 transitions. [2018-12-02 21:34:49,342 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-02 21:34:49,342 INFO L276 IsEmpty]: Start isEmpty. Operand 4635 states and 6932 transitions. [2018-12-02 21:34:49,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-12-02 21:34:49,348 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:49,348 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:49,348 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:49,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:49,348 INFO L82 PathProgramCache]: Analyzing trace with hash -608944855, now seen corresponding path program 1 times [2018-12-02 21:34:49,348 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:49,348 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:49,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:49,349 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:49,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:49,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:49,381 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-12-02 21:34:49,381 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:49,381 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 21:34:49,381 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 21:34:49,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 21:34:49,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:34:49,381 INFO L87 Difference]: Start difference. First operand 4635 states and 6932 transitions. Second operand 3 states. [2018-12-02 21:34:49,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:49,528 INFO L93 Difference]: Finished difference Result 8612 states and 12913 transitions. [2018-12-02 21:34:49,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 21:34:49,528 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 122 [2018-12-02 21:34:49,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:49,538 INFO L225 Difference]: With dead ends: 8612 [2018-12-02 21:34:49,538 INFO L226 Difference]: Without dead ends: 4635 [2018-12-02 21:34:49,546 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:34:49,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4635 states. [2018-12-02 21:34:49,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4635 to 4635. [2018-12-02 21:34:49,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4635 states. [2018-12-02 21:34:49,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4635 states to 4635 states and 6919 transitions. [2018-12-02 21:34:49,694 INFO L78 Accepts]: Start accepts. Automaton has 4635 states and 6919 transitions. Word has length 122 [2018-12-02 21:34:49,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:49,695 INFO L480 AbstractCegarLoop]: Abstraction has 4635 states and 6919 transitions. [2018-12-02 21:34:49,695 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 21:34:49,695 INFO L276 IsEmpty]: Start isEmpty. Operand 4635 states and 6919 transitions. [2018-12-02 21:34:49,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-12-02 21:34:49,701 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:49,701 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:49,701 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:49,701 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:49,701 INFO L82 PathProgramCache]: Analyzing trace with hash 1746860395, now seen corresponding path program 1 times [2018-12-02 21:34:49,701 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:49,701 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:49,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:49,702 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:49,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:49,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:49,807 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 17 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-02 21:34:49,808 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:34:49,808 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:34:49,816 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:49,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:49,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:34:49,908 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-12-02 21:34:49,924 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 21:34:49,924 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [9] total 10 [2018-12-02 21:34:49,924 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-02 21:34:49,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-02 21:34:49,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-12-02 21:34:49,925 INFO L87 Difference]: Start difference. First operand 4635 states and 6919 transitions. Second operand 10 states. [2018-12-02 21:34:50,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:50,995 INFO L93 Difference]: Finished difference Result 12415 states and 19035 transitions. [2018-12-02 21:34:50,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-02 21:34:50,995 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 122 [2018-12-02 21:34:50,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:51,018 INFO L225 Difference]: With dead ends: 12415 [2018-12-02 21:34:51,019 INFO L226 Difference]: Without dead ends: 7882 [2018-12-02 21:34:51,033 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 137 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=178, Invalid=578, Unknown=0, NotChecked=0, Total=756 [2018-12-02 21:34:51,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7882 states. [2018-12-02 21:34:51,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7882 to 5799. [2018-12-02 21:34:51,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5799 states. [2018-12-02 21:34:51,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5799 states to 5799 states and 8512 transitions. [2018-12-02 21:34:51,234 INFO L78 Accepts]: Start accepts. Automaton has 5799 states and 8512 transitions. Word has length 122 [2018-12-02 21:34:51,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:51,235 INFO L480 AbstractCegarLoop]: Abstraction has 5799 states and 8512 transitions. [2018-12-02 21:34:51,235 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-02 21:34:51,235 INFO L276 IsEmpty]: Start isEmpty. Operand 5799 states and 8512 transitions. [2018-12-02 21:34:51,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-12-02 21:34:51,244 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:51,244 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:51,244 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:51,244 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:51,244 INFO L82 PathProgramCache]: Analyzing trace with hash -837113155, now seen corresponding path program 1 times [2018-12-02 21:34:51,245 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:51,245 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:51,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:51,245 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:51,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:51,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:51,291 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-12-02 21:34:51,292 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:51,292 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:51,292 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:51,292 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:51,292 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:51,292 INFO L87 Difference]: Start difference. First operand 5799 states and 8512 transitions. Second operand 4 states. [2018-12-02 21:34:51,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:51,754 INFO L93 Difference]: Finished difference Result 14441 states and 21405 transitions. [2018-12-02 21:34:51,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 21:34:51,754 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 124 [2018-12-02 21:34:51,755 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:51,772 INFO L225 Difference]: With dead ends: 14441 [2018-12-02 21:34:51,772 INFO L226 Difference]: Without dead ends: 8651 [2018-12-02 21:34:51,778 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:51,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8651 states. [2018-12-02 21:34:52,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8651 to 8167. [2018-12-02 21:34:52,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8167 states. [2018-12-02 21:34:52,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8167 states to 8167 states and 12193 transitions. [2018-12-02 21:34:52,064 INFO L78 Accepts]: Start accepts. Automaton has 8167 states and 12193 transitions. Word has length 124 [2018-12-02 21:34:52,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:52,064 INFO L480 AbstractCegarLoop]: Abstraction has 8167 states and 12193 transitions. [2018-12-02 21:34:52,064 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:52,064 INFO L276 IsEmpty]: Start isEmpty. Operand 8167 states and 12193 transitions. [2018-12-02 21:34:52,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-12-02 21:34:52,071 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:52,072 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:52,072 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:52,072 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:52,072 INFO L82 PathProgramCache]: Analyzing trace with hash 369903519, now seen corresponding path program 1 times [2018-12-02 21:34:52,072 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:52,072 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:52,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:52,073 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:52,073 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:52,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:52,116 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-02 21:34:52,116 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:34:52,117 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:34:52,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:52,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:52,195 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:34:52,208 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-02 21:34:52,233 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 21:34:52,233 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-02 21:34:52,233 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 21:34:52,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 21:34:52,234 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 21:34:52,234 INFO L87 Difference]: Start difference. First operand 8167 states and 12193 transitions. Second operand 6 states. [2018-12-02 21:34:52,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:52,796 INFO L93 Difference]: Finished difference Result 18065 states and 28368 transitions. [2018-12-02 21:34:52,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 21:34:52,797 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 133 [2018-12-02 21:34:52,797 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:52,822 INFO L225 Difference]: With dead ends: 18065 [2018-12-02 21:34:52,822 INFO L226 Difference]: Without dead ends: 9924 [2018-12-02 21:34:52,838 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 137 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-12-02 21:34:52,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9924 states. [2018-12-02 21:34:53,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9924 to 9696. [2018-12-02 21:34:53,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9696 states. [2018-12-02 21:34:53,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9696 states to 9696 states and 14340 transitions. [2018-12-02 21:34:53,168 INFO L78 Accepts]: Start accepts. Automaton has 9696 states and 14340 transitions. Word has length 133 [2018-12-02 21:34:53,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:53,168 INFO L480 AbstractCegarLoop]: Abstraction has 9696 states and 14340 transitions. [2018-12-02 21:34:53,169 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 21:34:53,169 INFO L276 IsEmpty]: Start isEmpty. Operand 9696 states and 14340 transitions. [2018-12-02 21:34:53,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-12-02 21:34:53,175 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:53,176 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:53,176 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:53,176 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:53,176 INFO L82 PathProgramCache]: Analyzing trace with hash -355727781, now seen corresponding path program 1 times [2018-12-02 21:34:53,176 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:53,176 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:53,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:53,177 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:53,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:53,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:53,234 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 41 proven. 22 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 21:34:53,234 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:34:53,234 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:34:53,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:53,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:53,309 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:34:53,326 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 64 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-02 21:34:53,341 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 21:34:53,342 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [6] total 7 [2018-12-02 21:34:53,342 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-02 21:34:53,342 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-02 21:34:53,342 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-02 21:34:53,342 INFO L87 Difference]: Start difference. First operand 9696 states and 14340 transitions. Second operand 7 states. [2018-12-02 21:34:53,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:53,793 INFO L93 Difference]: Finished difference Result 13709 states and 20210 transitions. [2018-12-02 21:34:53,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-02 21:34:53,793 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 146 [2018-12-02 21:34:53,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:53,808 INFO L225 Difference]: With dead ends: 13709 [2018-12-02 21:34:53,808 INFO L226 Difference]: Without dead ends: 6207 [2018-12-02 21:34:53,820 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 152 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-12-02 21:34:53,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6207 states. [2018-12-02 21:34:54,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6207 to 5164. [2018-12-02 21:34:54,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5164 states. [2018-12-02 21:34:54,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5164 states to 5164 states and 7424 transitions. [2018-12-02 21:34:54,115 INFO L78 Accepts]: Start accepts. Automaton has 5164 states and 7424 transitions. Word has length 146 [2018-12-02 21:34:54,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:54,115 INFO L480 AbstractCegarLoop]: Abstraction has 5164 states and 7424 transitions. [2018-12-02 21:34:54,115 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-02 21:34:54,115 INFO L276 IsEmpty]: Start isEmpty. Operand 5164 states and 7424 transitions. [2018-12-02 21:34:54,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-12-02 21:34:54,119 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:54,119 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:54,119 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:54,119 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:54,119 INFO L82 PathProgramCache]: Analyzing trace with hash -1750678265, now seen corresponding path program 1 times [2018-12-02 21:34:54,119 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:54,119 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:54,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:54,120 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:54,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:54,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:54,145 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-12-02 21:34:54,146 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:54,146 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 21:34:54,146 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 21:34:54,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 21:34:54,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:34:54,146 INFO L87 Difference]: Start difference. First operand 5164 states and 7424 transitions. Second operand 3 states. [2018-12-02 21:34:54,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:54,394 INFO L93 Difference]: Finished difference Result 10725 states and 15493 transitions. [2018-12-02 21:34:54,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 21:34:54,394 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 149 [2018-12-02 21:34:54,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:54,403 INFO L225 Difference]: With dead ends: 10725 [2018-12-02 21:34:54,403 INFO L226 Difference]: Without dead ends: 5597 [2018-12-02 21:34:54,409 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:34:54,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5597 states. [2018-12-02 21:34:54,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5597 to 5593. [2018-12-02 21:34:54,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5593 states. [2018-12-02 21:34:54,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5593 states to 5593 states and 7751 transitions. [2018-12-02 21:34:54,618 INFO L78 Accepts]: Start accepts. Automaton has 5593 states and 7751 transitions. Word has length 149 [2018-12-02 21:34:54,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:54,619 INFO L480 AbstractCegarLoop]: Abstraction has 5593 states and 7751 transitions. [2018-12-02 21:34:54,619 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 21:34:54,619 INFO L276 IsEmpty]: Start isEmpty. Operand 5593 states and 7751 transitions. [2018-12-02 21:34:54,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-12-02 21:34:54,623 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:54,623 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:54,623 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:54,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:54,623 INFO L82 PathProgramCache]: Analyzing trace with hash -499469301, now seen corresponding path program 1 times [2018-12-02 21:34:54,623 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:54,623 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:54,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:54,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:54,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:54,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:54,646 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-12-02 21:34:54,647 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:54,647 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:54,647 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:54,647 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:54,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:54,647 INFO L87 Difference]: Start difference. First operand 5593 states and 7751 transitions. Second operand 4 states. [2018-12-02 21:34:54,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:54,913 INFO L93 Difference]: Finished difference Result 10661 states and 14772 transitions. [2018-12-02 21:34:54,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 21:34:54,914 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 149 [2018-12-02 21:34:54,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:54,922 INFO L225 Difference]: With dead ends: 10661 [2018-12-02 21:34:54,922 INFO L226 Difference]: Without dead ends: 5568 [2018-12-02 21:34:54,927 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:54,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5568 states. [2018-12-02 21:34:55,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5568 to 5568. [2018-12-02 21:34:55,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5568 states. [2018-12-02 21:34:55,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5568 states to 5568 states and 7716 transitions. [2018-12-02 21:34:55,144 INFO L78 Accepts]: Start accepts. Automaton has 5568 states and 7716 transitions. Word has length 149 [2018-12-02 21:34:55,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:55,144 INFO L480 AbstractCegarLoop]: Abstraction has 5568 states and 7716 transitions. [2018-12-02 21:34:55,144 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:55,144 INFO L276 IsEmpty]: Start isEmpty. Operand 5568 states and 7716 transitions. [2018-12-02 21:34:55,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-12-02 21:34:55,148 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:55,148 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:55,148 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:55,148 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:55,148 INFO L82 PathProgramCache]: Analyzing trace with hash 1288400521, now seen corresponding path program 1 times [2018-12-02 21:34:55,148 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:55,148 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:55,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:55,149 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:55,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:55,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:55,206 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 48 proven. 2 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-02 21:34:55,206 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:34:55,206 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:34:55,217 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:55,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:55,283 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:34:55,294 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-02 21:34:55,309 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 21:34:55,309 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-12-02 21:34:55,310 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 21:34:55,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 21:34:55,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:55,310 INFO L87 Difference]: Start difference. First operand 5568 states and 7716 transitions. Second operand 5 states. [2018-12-02 21:34:55,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:55,638 INFO L93 Difference]: Finished difference Result 12295 states and 17386 transitions. [2018-12-02 21:34:55,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-02 21:34:55,639 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 149 [2018-12-02 21:34:55,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:55,650 INFO L225 Difference]: With dead ends: 12295 [2018-12-02 21:34:55,650 INFO L226 Difference]: Without dead ends: 7421 [2018-12-02 21:34:55,656 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 152 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-02 21:34:55,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7421 states. [2018-12-02 21:34:55,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7421 to 6760. [2018-12-02 21:34:55,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6760 states. [2018-12-02 21:34:55,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6760 states to 6760 states and 9374 transitions. [2018-12-02 21:34:55,910 INFO L78 Accepts]: Start accepts. Automaton has 6760 states and 9374 transitions. Word has length 149 [2018-12-02 21:34:55,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:55,910 INFO L480 AbstractCegarLoop]: Abstraction has 6760 states and 9374 transitions. [2018-12-02 21:34:55,910 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 21:34:55,910 INFO L276 IsEmpty]: Start isEmpty. Operand 6760 states and 9374 transitions. [2018-12-02 21:34:55,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-12-02 21:34:55,913 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:55,913 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:55,913 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:55,913 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:55,913 INFO L82 PathProgramCache]: Analyzing trace with hash 219884168, now seen corresponding path program 1 times [2018-12-02 21:34:55,913 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:55,913 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:55,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:55,914 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:55,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:55,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:55,953 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 47 proven. 4 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 21:34:55,953 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:34:55,953 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:34:55,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:56,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:56,032 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:34:56,046 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 53 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-02 21:34:56,062 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 21:34:56,062 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-12-02 21:34:56,062 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 21:34:56,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 21:34:56,062 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:56,062 INFO L87 Difference]: Start difference. First operand 6760 states and 9374 transitions. Second operand 5 states. [2018-12-02 21:34:56,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:56,713 INFO L93 Difference]: Finished difference Result 17625 states and 24705 transitions. [2018-12-02 21:34:56,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-02 21:34:56,713 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 161 [2018-12-02 21:34:56,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:56,730 INFO L225 Difference]: With dead ends: 17625 [2018-12-02 21:34:56,731 INFO L226 Difference]: Without dead ends: 10006 [2018-12-02 21:34:56,745 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 166 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-12-02 21:34:56,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10006 states. [2018-12-02 21:34:57,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10006 to 9297. [2018-12-02 21:34:57,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9297 states. [2018-12-02 21:34:57,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9297 states to 9297 states and 11927 transitions. [2018-12-02 21:34:57,143 INFO L78 Accepts]: Start accepts. Automaton has 9297 states and 11927 transitions. Word has length 161 [2018-12-02 21:34:57,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:57,144 INFO L480 AbstractCegarLoop]: Abstraction has 9297 states and 11927 transitions. [2018-12-02 21:34:57,144 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 21:34:57,144 INFO L276 IsEmpty]: Start isEmpty. Operand 9297 states and 11927 transitions. [2018-12-02 21:34:57,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-12-02 21:34:57,148 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:57,148 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:57,148 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:57,148 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:57,148 INFO L82 PathProgramCache]: Analyzing trace with hash 1534020220, now seen corresponding path program 1 times [2018-12-02 21:34:57,148 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:57,148 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:57,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:57,149 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:57,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:57,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:57,186 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-12-02 21:34:57,186 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:57,186 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-02 21:34:57,186 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-02 21:34:57,187 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-02 21:34:57,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-02 21:34:57,187 INFO L87 Difference]: Start difference. First operand 9297 states and 11927 transitions. Second operand 4 states. [2018-12-02 21:34:57,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:57,599 INFO L93 Difference]: Finished difference Result 17385 states and 22273 transitions. [2018-12-02 21:34:57,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 21:34:57,599 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 162 [2018-12-02 21:34:57,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:57,613 INFO L225 Difference]: With dead ends: 17385 [2018-12-02 21:34:57,613 INFO L226 Difference]: Without dead ends: 9262 [2018-12-02 21:34:57,622 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:57,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9262 states. [2018-12-02 21:34:57,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9262 to 9262. [2018-12-02 21:34:57,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9262 states. [2018-12-02 21:34:58,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9262 states to 9262 states and 11881 transitions. [2018-12-02 21:34:58,008 INFO L78 Accepts]: Start accepts. Automaton has 9262 states and 11881 transitions. Word has length 162 [2018-12-02 21:34:58,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:58,008 INFO L480 AbstractCegarLoop]: Abstraction has 9262 states and 11881 transitions. [2018-12-02 21:34:58,008 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-02 21:34:58,008 INFO L276 IsEmpty]: Start isEmpty. Operand 9262 states and 11881 transitions. [2018-12-02 21:34:58,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-12-02 21:34:58,012 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:58,012 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:58,012 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:58,012 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:58,012 INFO L82 PathProgramCache]: Analyzing trace with hash 87439354, now seen corresponding path program 1 times [2018-12-02 21:34:58,012 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:58,012 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:58,013 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:58,013 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:58,013 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:58,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:58,068 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 37 proven. 10 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-12-02 21:34:58,068 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:34:58,068 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:34:58,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:58,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:58,139 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:34:58,173 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 53 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-02 21:34:58,189 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 21:34:58,189 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-02 21:34:58,190 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-02 21:34:58,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-02 21:34:58,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-02 21:34:58,190 INFO L87 Difference]: Start difference. First operand 9262 states and 11881 transitions. Second operand 6 states. [2018-12-02 21:34:58,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:58,798 INFO L93 Difference]: Finished difference Result 19043 states and 24533 transitions. [2018-12-02 21:34:58,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-02 21:34:58,799 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 162 [2018-12-02 21:34:58,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:58,812 INFO L225 Difference]: With dead ends: 19043 [2018-12-02 21:34:58,812 INFO L226 Difference]: Without dead ends: 9803 [2018-12-02 21:34:58,823 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 166 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-12-02 21:34:58,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9803 states. [2018-12-02 21:34:59,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9803 to 9784. [2018-12-02 21:34:59,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9784 states. [2018-12-02 21:34:59,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9784 states to 9784 states and 12089 transitions. [2018-12-02 21:34:59,250 INFO L78 Accepts]: Start accepts. Automaton has 9784 states and 12089 transitions. Word has length 162 [2018-12-02 21:34:59,250 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:34:59,250 INFO L480 AbstractCegarLoop]: Abstraction has 9784 states and 12089 transitions. [2018-12-02 21:34:59,250 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-02 21:34:59,250 INFO L276 IsEmpty]: Start isEmpty. Operand 9784 states and 12089 transitions. [2018-12-02 21:34:59,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 166 [2018-12-02 21:34:59,253 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:34:59,254 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:34:59,254 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:34:59,254 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:34:59,254 INFO L82 PathProgramCache]: Analyzing trace with hash -1788501607, now seen corresponding path program 1 times [2018-12-02 21:34:59,254 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:34:59,254 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:34:59,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:59,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:34:59,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:34:59,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:34:59,308 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-12-02 21:34:59,308 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:34:59,308 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-02 21:34:59,309 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-02 21:34:59,309 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-02 21:34:59,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-02 21:34:59,309 INFO L87 Difference]: Start difference. First operand 9784 states and 12089 transitions. Second operand 5 states. [2018-12-02 21:34:59,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:34:59,659 INFO L93 Difference]: Finished difference Result 15880 states and 19668 transitions. [2018-12-02 21:34:59,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-02 21:34:59,660 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 165 [2018-12-02 21:34:59,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:34:59,669 INFO L225 Difference]: With dead ends: 15880 [2018-12-02 21:34:59,670 INFO L226 Difference]: Without dead ends: 7164 [2018-12-02 21:34:59,679 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-02 21:34:59,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7164 states. [2018-12-02 21:35:00,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7164 to 7160. [2018-12-02 21:35:00,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7160 states. [2018-12-02 21:35:00,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7160 states to 7160 states and 8812 transitions. [2018-12-02 21:35:00,073 INFO L78 Accepts]: Start accepts. Automaton has 7160 states and 8812 transitions. Word has length 165 [2018-12-02 21:35:00,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:35:00,073 INFO L480 AbstractCegarLoop]: Abstraction has 7160 states and 8812 transitions. [2018-12-02 21:35:00,073 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-02 21:35:00,073 INFO L276 IsEmpty]: Start isEmpty. Operand 7160 states and 8812 transitions. [2018-12-02 21:35:00,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-12-02 21:35:00,075 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:35:00,075 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:35:00,075 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:35:00,075 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:35:00,075 INFO L82 PathProgramCache]: Analyzing trace with hash 1404636156, now seen corresponding path program 1 times [2018-12-02 21:35:00,075 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:35:00,075 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:35:00,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:35:00,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:35:00,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:35:00,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:35:00,280 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 43 proven. 65 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 21:35:00,280 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:35:00,280 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:35:00,286 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:35:00,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:35:00,357 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:35:00,414 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 71 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-02 21:35:00,430 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-02 21:35:00,430 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [16] total 20 [2018-12-02 21:35:00,430 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-12-02 21:35:00,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-12-02 21:35:00,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=340, Unknown=0, NotChecked=0, Total=380 [2018-12-02 21:35:00,431 INFO L87 Difference]: Start difference. First operand 7160 states and 8812 transitions. Second operand 20 states. [2018-12-02 21:35:12,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:35:12,590 INFO L93 Difference]: Finished difference Result 23518 states and 29556 transitions. [2018-12-02 21:35:12,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2018-12-02 21:35:12,590 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 212 [2018-12-02 21:35:12,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:35:12,611 INFO L225 Difference]: With dead ends: 23518 [2018-12-02 21:35:12,612 INFO L226 Difference]: Without dead ends: 17334 [2018-12-02 21:35:12,624 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 529 GetRequests, 311 SyntacticMatches, 1 SemanticMatches, 217 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19873 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=3379, Invalid=44363, Unknown=0, NotChecked=0, Total=47742 [2018-12-02 21:35:12,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17334 states. [2018-12-02 21:35:13,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17334 to 14619. [2018-12-02 21:35:13,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14619 states. [2018-12-02 21:35:13,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14619 states to 14619 states and 17907 transitions. [2018-12-02 21:35:13,334 INFO L78 Accepts]: Start accepts. Automaton has 14619 states and 17907 transitions. Word has length 212 [2018-12-02 21:35:13,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:35:13,335 INFO L480 AbstractCegarLoop]: Abstraction has 14619 states and 17907 transitions. [2018-12-02 21:35:13,335 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-12-02 21:35:13,335 INFO L276 IsEmpty]: Start isEmpty. Operand 14619 states and 17907 transitions. [2018-12-02 21:35:13,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-12-02 21:35:13,336 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:35:13,337 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:35:13,337 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:35:13,337 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:35:13,337 INFO L82 PathProgramCache]: Analyzing trace with hash -1746786478, now seen corresponding path program 1 times [2018-12-02 21:35:13,337 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:35:13,337 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:35:13,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:35:13,338 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:35:13,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:35:13,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:35:13,380 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 85 proven. 0 refuted. 0 times theorem prover too weak. 47 trivial. 0 not checked. [2018-12-02 21:35:13,380 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-02 21:35:13,381 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-02 21:35:13,381 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-02 21:35:13,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-02 21:35:13,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:35:13,381 INFO L87 Difference]: Start difference. First operand 14619 states and 17907 transitions. Second operand 3 states. [2018-12-02 21:35:14,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:35:14,014 INFO L93 Difference]: Finished difference Result 25362 states and 31594 transitions. [2018-12-02 21:35:14,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-02 21:35:14,015 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 234 [2018-12-02 21:35:14,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:35:14,036 INFO L225 Difference]: With dead ends: 25362 [2018-12-02 21:35:14,036 INFO L226 Difference]: Without dead ends: 13077 [2018-12-02 21:35:14,054 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-02 21:35:14,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13077 states. [2018-12-02 21:35:14,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13077 to 12961. [2018-12-02 21:35:14,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12961 states. [2018-12-02 21:35:14,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12961 states to 12961 states and 15694 transitions. [2018-12-02 21:35:14,708 INFO L78 Accepts]: Start accepts. Automaton has 12961 states and 15694 transitions. Word has length 234 [2018-12-02 21:35:14,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:35:14,708 INFO L480 AbstractCegarLoop]: Abstraction has 12961 states and 15694 transitions. [2018-12-02 21:35:14,708 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-02 21:35:14,708 INFO L276 IsEmpty]: Start isEmpty. Operand 12961 states and 15694 transitions. [2018-12-02 21:35:14,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-12-02 21:35:14,710 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:35:14,710 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:35:14,710 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:35:14,710 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:35:14,710 INFO L82 PathProgramCache]: Analyzing trace with hash -1718286188, now seen corresponding path program 1 times [2018-12-02 21:35:14,710 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:35:14,711 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:35:14,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:35:14,711 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:35:14,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:35:14,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:35:14,891 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 49 proven. 67 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-02 21:35:14,891 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-02 21:35:14,891 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-02 21:35:14,897 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:35:14,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-02 21:35:14,979 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-02 21:35:15,101 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 102 proven. 15 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-02 21:35:15,116 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-02 21:35:15,117 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 15] total 22 [2018-12-02 21:35:15,117 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-12-02 21:35:15,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-12-02 21:35:15,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=410, Unknown=0, NotChecked=0, Total=462 [2018-12-02 21:35:15,117 INFO L87 Difference]: Start difference. First operand 12961 states and 15694 transitions. Second operand 22 states. [2018-12-02 21:35:26,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-02 21:35:26,628 INFO L93 Difference]: Finished difference Result 28654 states and 35037 transitions. [2018-12-02 21:35:26,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2018-12-02 21:35:26,629 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 234 [2018-12-02 21:35:26,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-02 21:35:26,670 INFO L225 Difference]: With dead ends: 28654 [2018-12-02 21:35:26,670 INFO L226 Difference]: Without dead ends: 17656 [2018-12-02 21:35:26,688 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 446 GetRequests, 319 SyntacticMatches, 5 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5334 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1292, Invalid=13960, Unknown=0, NotChecked=0, Total=15252 [2018-12-02 21:35:26,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17656 states. [2018-12-02 21:35:27,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17656 to 15425. [2018-12-02 21:35:27,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15425 states. [2018-12-02 21:35:27,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15425 states to 15425 states and 18625 transitions. [2018-12-02 21:35:27,487 INFO L78 Accepts]: Start accepts. Automaton has 15425 states and 18625 transitions. Word has length 234 [2018-12-02 21:35:27,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-02 21:35:27,488 INFO L480 AbstractCegarLoop]: Abstraction has 15425 states and 18625 transitions. [2018-12-02 21:35:27,488 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-12-02 21:35:27,488 INFO L276 IsEmpty]: Start isEmpty. Operand 15425 states and 18625 transitions. [2018-12-02 21:35:27,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 236 [2018-12-02 21:35:27,490 INFO L394 BasicCegarLoop]: Found error trace [2018-12-02 21:35:27,490 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-02 21:35:27,490 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-02 21:35:27,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-02 21:35:27,490 INFO L82 PathProgramCache]: Analyzing trace with hash -1727712869, now seen corresponding path program 1 times [2018-12-02 21:35:27,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-02 21:35:27,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-02 21:35:27,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:35:27,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-02 21:35:27,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-02 21:35:27,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 21:35:27,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-02 21:35:27,570 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-02 21:35:27,686 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 09:35:27 BoogieIcfgContainer [2018-12-02 21:35:27,687 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-02 21:35:27,687 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-02 21:35:27,687 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-02 21:35:27,687 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-02 21:35:27,687 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 09:34:43" (3/4) ... [2018-12-02 21:35:27,689 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-02 21:35:27,789 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_8aa90c94-59cb-42d9-b55b-857daa057c97/bin-2019/uautomizer/witness.graphml [2018-12-02 21:35:27,789 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-02 21:35:27,790 INFO L168 Benchmark]: Toolchain (without parser) took 45054.79 ms. Allocated memory was 1.0 GB in the beginning and 3.2 GB in the end (delta: 2.2 GB). Free memory was 957.1 MB in the beginning and 764.7 MB in the end (delta: 192.4 MB). Peak memory consumption was 2.4 GB. Max. memory is 11.5 GB. [2018-12-02 21:35:27,790 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 21:35:27,791 INFO L168 Benchmark]: CACSL2BoogieTranslator took 172.30 ms. Allocated memory is still 1.0 GB. Free memory was 957.1 MB in the beginning and 941.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-12-02 21:35:27,791 INFO L168 Benchmark]: Boogie Procedure Inliner took 43.37 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 139.5 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -189.9 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. [2018-12-02 21:35:27,791 INFO L168 Benchmark]: Boogie Preprocessor took 24.14 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-02 21:35:27,791 INFO L168 Benchmark]: RCFGBuilder took 323.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 45.5 MB). Peak memory consumption was 45.5 MB. Max. memory is 11.5 GB. [2018-12-02 21:35:27,791 INFO L168 Benchmark]: TraceAbstraction took 44386.13 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.0 GB). Free memory was 1.1 GB in the beginning and 805.9 MB in the end (delta: 279.4 MB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2018-12-02 21:35:27,791 INFO L168 Benchmark]: Witness Printer took 102.47 ms. Allocated memory is still 3.2 GB. Free memory was 805.9 MB in the beginning and 764.7 MB in the end (delta: 41.3 MB). Peak memory consumption was 41.3 MB. Max. memory is 11.5 GB. [2018-12-02 21:35:27,792 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 172.30 ms. Allocated memory is still 1.0 GB. Free memory was 957.1 MB in the beginning and 941.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 43.37 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 139.5 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -189.9 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 24.14 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 323.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 45.5 MB). Peak memory consumption was 45.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 44386.13 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.0 GB). Free memory was 1.1 GB in the beginning and 805.9 MB in the end (delta: 279.4 MB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. * Witness Printer took 102.47 ms. Allocated memory is still 3.2 GB. Free memory was 805.9 MB in the beginning and 764.7 MB in the end (delta: 41.3 MB). Peak memory consumption was 41.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [\old(c)=17, \old(c1_i)=4, \old(c1_pc)=29, \old(c1_st)=24, \old(c2_i)=14, \old(c2_pc)=28, \old(c2_st)=25, \old(c_req_up)=30, \old(c_t)=20, \old(d)=23, \old(data)=18, \old(e_c)=11, \old(e_e)=31, \old(e_f)=21, \old(e_g)=10, \old(e_p_in)=8, \old(e_wl)=13, \old(p_in)=15, \old(p_out)=9, \old(processed)=16, \old(r_i)=26, \old(r_st)=7, \old(t_b)=12, \old(wb_i)=5, \old(wb_pc)=19, \old(wb_st)=3, \old(wl_i)=27, \old(wl_pc)=22, \old(wl_st)=6, c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L691] int __retres1 ; [L695] e_wl = 2 [L696] e_c = e_wl [L697] e_g = e_c [L698] e_f = e_g [L699] e_e = e_f [L700] wl_pc = 0 [L701] c1_pc = 0 [L702] c2_pc = 0 [L703] wb_pc = 0 [L704] wb_i = 1 [L705] c2_i = wb_i [L706] c1_i = c2_i [L707] wl_i = c1_i [L708] r_i = 0 [L709] c_req_up = 0 [L710] d = 0 [L711] c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=0, \old(e_e)=0, \old(e_f)=0, \old(e_g)=0, \old(e_wl)=0, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L712] CALL start_simulation() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L402] int kernel_st ; [L405] kernel_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L406] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L417] COND TRUE (int )wl_i == 1 [L418] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L422] COND TRUE (int )c1_i == 1 [L423] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L427] COND TRUE (int )c2_i == 1 [L428] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L432] COND TRUE (int )wb_i == 1 [L433] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L437] COND FALSE !((int )r_i == 1) [L440] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L442] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L447] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L452] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L457] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L462] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L467] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L475] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L485] COND FALSE !((int )c1_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L494] COND FALSE !((int )c2_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L503] COND FALSE !((int )wb_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L512] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L517] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L522] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L527] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L532] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L537] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L326] RET write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L341] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L139] COND TRUE (int )c1_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L150] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L341] RET compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L356] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L184] COND TRUE (int )c2_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L195] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L356] RET compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L371] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L229] COND TRUE (int )wb_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L240] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L371] RET write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L547] RET eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L561] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L577] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L582] COND TRUE (int )e_wl == 0 [L583] e_wl = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L587] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L588] COND TRUE (int )e_wl == 1 [L589] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L605] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L606] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L614] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L615] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L623] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L624] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L632] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L637] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L642] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L647] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L652] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L657] COND TRUE (int )e_wl == 1 [L658] e_wl = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L662] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L326] RET write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L341] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L139] COND FALSE !((int )c1_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L142] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L157] COND TRUE ! processed [L158] data += 1 [L159] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L160] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L161] COND TRUE (int )e_g == 1 [L162] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L169] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L150] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L341] RET compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L356] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L184] COND FALSE !((int )c2_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L187] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] COND TRUE ! processed [L203] data += 1 [L204] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L205] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L206] COND TRUE (int )e_g == 1 [L207] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L214] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L195] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L356] RET compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L371] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L229] COND FALSE !((int )wb_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L232] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L247] c_t = data [L248] c_req_up = 1 [L249] processed = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L240] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L371] RET write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L547] RET eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND TRUE (int )c_req_up == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L551] COND TRUE c != c_t [L552] c = c_t [L553] e_c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L557] c_req_up = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L561] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L577] COND TRUE (int )e_c == 0 [L578] e_c = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L582] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L587] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L595] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L596] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L605] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L606] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L614] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L615] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L623] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L624] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L632] COND TRUE (int )e_c == 1 [L633] r_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L637] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L642] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L647] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L652] COND TRUE (int )e_c == 1 [L653] e_c = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L657] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L665] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L668] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L671] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L674] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L319] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L349] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L364] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND TRUE (int )r_st == 0 [L381] tmp___3 = __VERIFIER_nondet_int() [L383] COND TRUE \read(tmp___3) [L385] r_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L386] CALL read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L261] d = c [L262] e_e = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L263] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L271] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L272] COND TRUE (int )e_e == 1 [L273] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L281] e_e = 2 [L282] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L386] RET read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L112] COND TRUE d == t + 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L120] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L124] CALL error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 11 procedures, 161 locations, 1 error locations. UNSAFE Result, 44.3s OverallTime, 28 OverallIterations, 6 TraceHistogramMax, 34.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9426 SDtfs, 28586 SDslu, 29317 SDs, 0 SdLazy, 28516 SolverSat, 5493 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 15.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2168 GetRequests, 1685 SyntacticMatches, 15 SemanticMatches, 468 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25498 ImplicationChecksByTransitivity, 6.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=15425occurred in iteration=27, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 6.8s AutomataMinimizationTime, 27 MinimizatonAttempts, 13537 StatesRemovedByMinimization, 23 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 1.3s InterpolantComputationTime, 4677 NumberOfCodeBlocks, 4677 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 4406 ConstructedInterpolants, 0 QuantifiedInterpolants, 1644921 SizeOfPredicates, 12 NumberOfNonLiveVariables, 9226 ConjunctsInSsa, 64 ConjunctsInUnsatCore, 36 InterpolantComputations, 26 PerfectInterpolantSequences, 1546/1760 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...