./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-01 07:46:45,630 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-01 07:46:45,631 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-01 07:46:45,637 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-01 07:46:45,638 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-01 07:46:45,638 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-01 07:46:45,639 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-01 07:46:45,639 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-01 07:46:45,640 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-01 07:46:45,641 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-01 07:46:45,641 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-01 07:46:45,641 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-01 07:46:45,642 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-01 07:46:45,642 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-01 07:46:45,642 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-01 07:46:45,643 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-01 07:46:45,643 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-01 07:46:45,644 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-01 07:46:45,645 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-01 07:46:45,646 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-01 07:46:45,646 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-01 07:46:45,647 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-01 07:46:45,648 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-01 07:46:45,648 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-01 07:46:45,648 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-01 07:46:45,648 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-01 07:46:45,649 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-01 07:46:45,649 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-01 07:46:45,650 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-01 07:46:45,650 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-01 07:46:45,650 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-01 07:46:45,651 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-01 07:46:45,651 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-01 07:46:45,651 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-01 07:46:45,651 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-01 07:46:45,652 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-01 07:46:45,652 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-12-01 07:46:45,659 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-01 07:46:45,659 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-01 07:46:45,659 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-01 07:46:45,659 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-01 07:46:45,660 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-01 07:46:45,660 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-01 07:46:45,660 INFO L133 SettingsManager]: * Use SBE=true [2018-12-01 07:46:45,660 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-01 07:46:45,660 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-01 07:46:45,660 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-01 07:46:45,660 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-01 07:46:45,660 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-01 07:46:45,661 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-01 07:46:45,661 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-01 07:46:45,662 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-01 07:46:45,662 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-01 07:46:45,662 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-01 07:46:45,662 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-01 07:46:45,662 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-01 07:46:45,662 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-01 07:46:45,662 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-01 07:46:45,662 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2018-12-01 07:46:45,680 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-01 07:46:45,690 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-01 07:46:45,692 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-01 07:46:45,694 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-01 07:46:45,694 INFO L276 PluginConnector]: CDTParser initialized [2018-12-01 07:46:45,694 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-01 07:46:45,741 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/data/8fecd7175/bc1e48416d264d589a265c9c3119e3af/FLAG9720489b8 [2018-12-01 07:46:46,070 INFO L307 CDTParser]: Found 1 translation units. [2018-12-01 07:46:46,070 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-01 07:46:46,075 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/data/8fecd7175/bc1e48416d264d589a265c9c3119e3af/FLAG9720489b8 [2018-12-01 07:46:46,476 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/data/8fecd7175/bc1e48416d264d589a265c9c3119e3af [2018-12-01 07:46:46,478 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-01 07:46:46,480 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-01 07:46:46,480 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-01 07:46:46,480 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-01 07:46:46,483 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-01 07:46:46,484 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,486 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@97cb65a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46, skipping insertion in model container [2018-12-01 07:46:46,486 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,492 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-01 07:46:46,515 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-01 07:46:46,629 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-01 07:46:46,633 INFO L191 MainTranslator]: Completed pre-run [2018-12-01 07:46:46,660 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-01 07:46:46,701 INFO L195 MainTranslator]: Completed translation [2018-12-01 07:46:46,702 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46 WrapperNode [2018-12-01 07:46:46,702 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-01 07:46:46,702 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-01 07:46:46,702 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-01 07:46:46,702 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-01 07:46:46,707 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,712 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,717 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-01 07:46:46,717 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-01 07:46:46,717 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-01 07:46:46,717 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-01 07:46:46,722 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,723 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,724 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,725 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,730 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,737 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,738 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... [2018-12-01 07:46:46,740 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-01 07:46:46,740 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-01 07:46:46,740 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-01 07:46:46,740 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-01 07:46:46,741 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-01 07:46:46,771 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-12-01 07:46:46,771 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-12-01 07:46:46,771 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-12-01 07:46:46,771 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-12-01 07:46:46,771 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-12-01 07:46:46,771 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-12-01 07:46:46,771 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2018-12-01 07:46:46,771 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2018-12-01 07:46:46,771 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-01 07:46:46,771 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-01 07:46:46,772 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-01 07:46:46,772 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-01 07:46:46,772 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-01 07:46:46,772 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-01 07:46:46,772 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-12-01 07:46:46,772 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-12-01 07:46:46,772 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-01 07:46:46,772 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-01 07:46:46,772 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-12-01 07:46:46,772 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-12-01 07:46:46,772 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-01 07:46:46,772 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-01 07:46:46,772 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2018-12-01 07:46:46,772 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2018-12-01 07:46:46,773 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-01 07:46:46,773 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-01 07:46:46,773 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-12-01 07:46:46,773 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-12-01 07:46:46,773 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-01 07:46:46,773 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-01 07:46:46,773 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-01 07:46:46,773 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-01 07:46:46,773 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-12-01 07:46:46,773 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-12-01 07:46:46,773 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-01 07:46:46,773 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-01 07:46:46,773 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-12-01 07:46:46,773 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-12-01 07:46:46,773 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-01 07:46:46,774 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-01 07:46:46,774 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-01 07:46:46,774 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-01 07:46:46,774 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-01 07:46:46,774 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-01 07:46:46,774 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-12-01 07:46:46,774 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-12-01 07:46:46,774 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-01 07:46:46,774 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-01 07:46:46,774 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-01 07:46:46,774 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-01 07:46:46,774 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-01 07:46:46,774 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-01 07:46:46,774 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-01 07:46:46,774 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-01 07:46:47,065 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-01 07:46:47,065 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-12-01 07:46:47,065 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 01.12 07:46:47 BoogieIcfgContainer [2018-12-01 07:46:47,065 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-01 07:46:47,066 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-01 07:46:47,066 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-01 07:46:47,068 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-01 07:46:47,068 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 01.12 07:46:46" (1/3) ... [2018-12-01 07:46:47,068 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@27759e19 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 01.12 07:46:47, skipping insertion in model container [2018-12-01 07:46:47,068 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 01.12 07:46:46" (2/3) ... [2018-12-01 07:46:47,069 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@27759e19 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 01.12 07:46:47, skipping insertion in model container [2018-12-01 07:46:47,069 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 01.12 07:46:47" (3/3) ... [2018-12-01 07:46:47,070 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-01 07:46:47,075 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-01 07:46:47,080 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-01 07:46:47,088 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-01 07:46:47,107 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-01 07:46:47,107 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-01 07:46:47,107 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-01 07:46:47,107 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-01 07:46:47,107 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-01 07:46:47,107 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-01 07:46:47,107 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-01 07:46:47,107 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-01 07:46:47,107 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-01 07:46:47,120 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states. [2018-12-01 07:46:47,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:47,126 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:47,127 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:47,128 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:47,131 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:47,131 INFO L82 PathProgramCache]: Analyzing trace with hash -2019614736, now seen corresponding path program 1 times [2018-12-01 07:46:47,132 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:47,133 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:47,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:47,161 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:47,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:47,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:47,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:47,324 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:47,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:47,328 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:47,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:47,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:47,340 INFO L87 Difference]: Start difference. First operand 229 states. Second operand 5 states. [2018-12-01 07:46:47,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:47,699 INFO L93 Difference]: Finished difference Result 475 states and 713 transitions. [2018-12-01 07:46:47,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:47,701 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-01 07:46:47,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:47,711 INFO L225 Difference]: With dead ends: 475 [2018-12-01 07:46:47,711 INFO L226 Difference]: Without dead ends: 256 [2018-12-01 07:46:47,714 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:47,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-12-01 07:46:47,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 220. [2018-12-01 07:46:47,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-01 07:46:47,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 304 transitions. [2018-12-01 07:46:47,757 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 304 transitions. Word has length 120 [2018-12-01 07:46:47,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:47,758 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 304 transitions. [2018-12-01 07:46:47,758 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:47,758 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 304 transitions. [2018-12-01 07:46:47,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:47,760 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:47,760 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:47,761 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:47,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:47,761 INFO L82 PathProgramCache]: Analyzing trace with hash 1218621358, now seen corresponding path program 1 times [2018-12-01 07:46:47,761 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:47,761 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:47,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:47,762 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:47,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:47,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:47,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:47,837 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:47,837 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:47,838 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:47,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:47,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:47,838 INFO L87 Difference]: Start difference. First operand 220 states and 304 transitions. Second operand 5 states. [2018-12-01 07:46:48,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:48,130 INFO L93 Difference]: Finished difference Result 454 states and 646 transitions. [2018-12-01 07:46:48,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:48,130 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-01 07:46:48,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:48,132 INFO L225 Difference]: With dead ends: 454 [2018-12-01 07:46:48,132 INFO L226 Difference]: Without dead ends: 256 [2018-12-01 07:46:48,134 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:48,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-12-01 07:46:48,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 220. [2018-12-01 07:46:48,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-01 07:46:48,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 303 transitions. [2018-12-01 07:46:48,153 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 303 transitions. Word has length 120 [2018-12-01 07:46:48,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:48,153 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 303 transitions. [2018-12-01 07:46:48,153 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:48,153 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 303 transitions. [2018-12-01 07:46:48,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:48,155 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:48,155 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:48,156 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:48,156 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:48,156 INFO L82 PathProgramCache]: Analyzing trace with hash -1724960720, now seen corresponding path program 1 times [2018-12-01 07:46:48,156 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:48,156 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:48,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:48,157 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:48,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:48,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:48,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:48,231 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:48,231 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:48,232 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:48,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:48,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:48,232 INFO L87 Difference]: Start difference. First operand 220 states and 303 transitions. Second operand 5 states. [2018-12-01 07:46:48,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:48,483 INFO L93 Difference]: Finished difference Result 452 states and 640 transitions. [2018-12-01 07:46:48,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:48,483 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-01 07:46:48,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:48,485 INFO L225 Difference]: With dead ends: 452 [2018-12-01 07:46:48,485 INFO L226 Difference]: Without dead ends: 254 [2018-12-01 07:46:48,486 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:48,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254 states. [2018-12-01 07:46:48,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254 to 220. [2018-12-01 07:46:48,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-01 07:46:48,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 302 transitions. [2018-12-01 07:46:48,504 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 302 transitions. Word has length 120 [2018-12-01 07:46:48,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:48,504 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 302 transitions. [2018-12-01 07:46:48,504 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:48,504 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 302 transitions. [2018-12-01 07:46:48,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:48,506 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:48,506 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:48,506 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:48,506 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:48,506 INFO L82 PathProgramCache]: Analyzing trace with hash 951031662, now seen corresponding path program 1 times [2018-12-01 07:46:48,506 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:48,507 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:48,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:48,507 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:48,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:48,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:48,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:48,558 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:48,559 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:48,559 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:48,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:48,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:48,559 INFO L87 Difference]: Start difference. First operand 220 states and 302 transitions. Second operand 5 states. [2018-12-01 07:46:48,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:48,851 INFO L93 Difference]: Finished difference Result 450 states and 634 transitions. [2018-12-01 07:46:48,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:48,851 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-01 07:46:48,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:48,852 INFO L225 Difference]: With dead ends: 450 [2018-12-01 07:46:48,852 INFO L226 Difference]: Without dead ends: 252 [2018-12-01 07:46:48,852 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:48,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-12-01 07:46:48,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 220. [2018-12-01 07:46:48,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-01 07:46:48,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 301 transitions. [2018-12-01 07:46:48,863 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 301 transitions. Word has length 120 [2018-12-01 07:46:48,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:48,863 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 301 transitions. [2018-12-01 07:46:48,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:48,863 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 301 transitions. [2018-12-01 07:46:48,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:48,864 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:48,864 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:48,864 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:48,864 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:48,865 INFO L82 PathProgramCache]: Analyzing trace with hash 67522672, now seen corresponding path program 1 times [2018-12-01 07:46:48,865 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:48,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:48,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:48,865 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:48,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:48,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:48,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:48,908 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:48,909 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:48,909 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:48,909 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:48,909 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:48,909 INFO L87 Difference]: Start difference. First operand 220 states and 301 transitions. Second operand 5 states. [2018-12-01 07:46:49,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:49,195 INFO L93 Difference]: Finished difference Result 471 states and 668 transitions. [2018-12-01 07:46:49,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:49,195 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-01 07:46:49,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:49,197 INFO L225 Difference]: With dead ends: 471 [2018-12-01 07:46:49,197 INFO L226 Difference]: Without dead ends: 273 [2018-12-01 07:46:49,198 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:49,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states. [2018-12-01 07:46:49,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 220. [2018-12-01 07:46:49,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-01 07:46:49,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 300 transitions. [2018-12-01 07:46:49,214 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 300 transitions. Word has length 120 [2018-12-01 07:46:49,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:49,214 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 300 transitions. [2018-12-01 07:46:49,215 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:49,215 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 300 transitions. [2018-12-01 07:46:49,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:49,216 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:49,216 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:49,216 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:49,216 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:49,216 INFO L82 PathProgramCache]: Analyzing trace with hash -1873059342, now seen corresponding path program 1 times [2018-12-01 07:46:49,216 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:49,216 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:49,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:49,217 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:49,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:49,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:49,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:49,253 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:49,253 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:49,253 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:49,253 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:49,253 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:49,253 INFO L87 Difference]: Start difference. First operand 220 states and 300 transitions. Second operand 5 states. [2018-12-01 07:46:49,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:49,471 INFO L93 Difference]: Finished difference Result 469 states and 662 transitions. [2018-12-01 07:46:49,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:49,471 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-01 07:46:49,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:49,473 INFO L225 Difference]: With dead ends: 469 [2018-12-01 07:46:49,473 INFO L226 Difference]: Without dead ends: 271 [2018-12-01 07:46:49,474 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:49,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-12-01 07:46:49,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 220. [2018-12-01 07:46:49,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-01 07:46:49,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 299 transitions. [2018-12-01 07:46:49,491 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 299 transitions. Word has length 120 [2018-12-01 07:46:49,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:49,491 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 299 transitions. [2018-12-01 07:46:49,491 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:49,491 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 299 transitions. [2018-12-01 07:46:49,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:49,492 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:49,493 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:49,493 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:49,493 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:49,493 INFO L82 PathProgramCache]: Analyzing trace with hash 4003888, now seen corresponding path program 1 times [2018-12-01 07:46:49,493 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:49,493 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:49,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:49,494 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:49,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:49,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:49,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:49,549 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:49,549 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:49,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:49,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:49,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:49,550 INFO L87 Difference]: Start difference. First operand 220 states and 299 transitions. Second operand 5 states. [2018-12-01 07:46:49,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:49,787 INFO L93 Difference]: Finished difference Result 467 states and 656 transitions. [2018-12-01 07:46:49,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:49,787 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-01 07:46:49,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:49,789 INFO L225 Difference]: With dead ends: 467 [2018-12-01 07:46:49,789 INFO L226 Difference]: Without dead ends: 269 [2018-12-01 07:46:49,790 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:49,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-12-01 07:46:49,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 220. [2018-12-01 07:46:49,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-01 07:46:49,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 298 transitions. [2018-12-01 07:46:49,807 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 298 transitions. Word has length 120 [2018-12-01 07:46:49,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:49,808 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 298 transitions. [2018-12-01 07:46:49,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:49,808 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 298 transitions. [2018-12-01 07:46:49,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:49,809 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:49,809 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:49,809 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:49,809 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:49,810 INFO L82 PathProgramCache]: Analyzing trace with hash -766729678, now seen corresponding path program 1 times [2018-12-01 07:46:49,810 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:49,810 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:49,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:49,810 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:49,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:49,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:49,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:49,852 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:49,852 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:49,852 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:49,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:49,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:49,853 INFO L87 Difference]: Start difference. First operand 220 states and 298 transitions. Second operand 5 states. [2018-12-01 07:46:50,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:50,100 INFO L93 Difference]: Finished difference Result 465 states and 650 transitions. [2018-12-01 07:46:50,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:50,100 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-01 07:46:50,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:50,102 INFO L225 Difference]: With dead ends: 465 [2018-12-01 07:46:50,102 INFO L226 Difference]: Without dead ends: 267 [2018-12-01 07:46:50,102 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:50,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-12-01 07:46:50,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 220. [2018-12-01 07:46:50,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-01 07:46:50,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 297 transitions. [2018-12-01 07:46:50,121 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 297 transitions. Word has length 120 [2018-12-01 07:46:50,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:50,121 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 297 transitions. [2018-12-01 07:46:50,122 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:50,122 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 297 transitions. [2018-12-01 07:46:50,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:50,123 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:50,123 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:50,123 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:50,123 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:50,123 INFO L82 PathProgramCache]: Analyzing trace with hash -1761423376, now seen corresponding path program 1 times [2018-12-01 07:46:50,123 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:50,123 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:50,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,124 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:50,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:50,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:50,162 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:50,162 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 07:46:50,162 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 07:46:50,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 07:46:50,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:50,162 INFO L87 Difference]: Start difference. First operand 220 states and 297 transitions. Second operand 6 states. [2018-12-01 07:46:50,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:50,189 INFO L93 Difference]: Finished difference Result 436 states and 607 transitions. [2018-12-01 07:46:50,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:50,189 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-01 07:46:50,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:50,190 INFO L225 Difference]: With dead ends: 436 [2018-12-01 07:46:50,191 INFO L226 Difference]: Without dead ends: 239 [2018-12-01 07:46:50,191 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:50,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-12-01 07:46:50,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 225. [2018-12-01 07:46:50,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-12-01 07:46:50,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 302 transitions. [2018-12-01 07:46:50,212 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 302 transitions. Word has length 120 [2018-12-01 07:46:50,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:50,212 INFO L480 AbstractCegarLoop]: Abstraction has 225 states and 302 transitions. [2018-12-01 07:46:50,212 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 07:46:50,212 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 302 transitions. [2018-12-01 07:46:50,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:50,213 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:50,213 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:50,213 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:50,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:50,213 INFO L82 PathProgramCache]: Analyzing trace with hash -27318926, now seen corresponding path program 1 times [2018-12-01 07:46:50,214 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:50,214 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:50,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:50,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:50,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:50,275 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:50,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 07:46:50,275 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 07:46:50,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 07:46:50,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:50,275 INFO L87 Difference]: Start difference. First operand 225 states and 302 transitions. Second operand 4 states. [2018-12-01 07:46:50,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:50,436 INFO L93 Difference]: Finished difference Result 622 states and 862 transitions. [2018-12-01 07:46:50,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 07:46:50,436 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-01 07:46:50,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:50,438 INFO L225 Difference]: With dead ends: 622 [2018-12-01 07:46:50,438 INFO L226 Difference]: Without dead ends: 420 [2018-12-01 07:46:50,439 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:50,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-12-01 07:46:50,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 415. [2018-12-01 07:46:50,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 415 states. [2018-12-01 07:46:50,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 415 states to 415 states and 556 transitions. [2018-12-01 07:46:50,486 INFO L78 Accepts]: Start accepts. Automaton has 415 states and 556 transitions. Word has length 120 [2018-12-01 07:46:50,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:50,486 INFO L480 AbstractCegarLoop]: Abstraction has 415 states and 556 transitions. [2018-12-01 07:46:50,486 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 07:46:50,486 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 556 transitions. [2018-12-01 07:46:50,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:50,487 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:50,487 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:50,487 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:50,488 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:50,488 INFO L82 PathProgramCache]: Analyzing trace with hash -512734447, now seen corresponding path program 1 times [2018-12-01 07:46:50,488 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:50,488 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:50,488 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,488 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:50,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:50,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:50,527 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:50,527 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 07:46:50,527 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 07:46:50,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 07:46:50,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:50,528 INFO L87 Difference]: Start difference. First operand 415 states and 556 transitions. Second operand 6 states. [2018-12-01 07:46:50,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:50,573 INFO L93 Difference]: Finished difference Result 823 states and 1130 transitions. [2018-12-01 07:46:50,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:50,574 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-01 07:46:50,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:50,576 INFO L225 Difference]: With dead ends: 823 [2018-12-01 07:46:50,576 INFO L226 Difference]: Without dead ends: 431 [2018-12-01 07:46:50,577 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:50,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states. [2018-12-01 07:46:50,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 420. [2018-12-01 07:46:50,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 420 states. [2018-12-01 07:46:50,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 560 transitions. [2018-12-01 07:46:50,611 INFO L78 Accepts]: Start accepts. Automaton has 420 states and 560 transitions. Word has length 120 [2018-12-01 07:46:50,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:50,611 INFO L480 AbstractCegarLoop]: Abstraction has 420 states and 560 transitions. [2018-12-01 07:46:50,611 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 07:46:50,612 INFO L276 IsEmpty]: Start isEmpty. Operand 420 states and 560 transitions. [2018-12-01 07:46:50,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:50,612 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:50,612 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:50,613 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:50,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:50,613 INFO L82 PathProgramCache]: Analyzing trace with hash -1244701873, now seen corresponding path program 1 times [2018-12-01 07:46:50,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:50,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:50,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:50,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:50,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:50,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:50,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 07:46:50,666 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 07:46:50,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 07:46:50,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:50,667 INFO L87 Difference]: Start difference. First operand 420 states and 560 transitions. Second operand 4 states. [2018-12-01 07:46:50,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:50,847 INFO L93 Difference]: Finished difference Result 1201 states and 1654 transitions. [2018-12-01 07:46:50,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 07:46:50,847 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-01 07:46:50,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:50,850 INFO L225 Difference]: With dead ends: 1201 [2018-12-01 07:46:50,850 INFO L226 Difference]: Without dead ends: 804 [2018-12-01 07:46:50,851 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:50,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 804 states. [2018-12-01 07:46:50,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 804 to 797. [2018-12-01 07:46:50,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 797 states. [2018-12-01 07:46:50,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 797 states to 797 states and 1060 transitions. [2018-12-01 07:46:50,892 INFO L78 Accepts]: Start accepts. Automaton has 797 states and 1060 transitions. Word has length 120 [2018-12-01 07:46:50,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:50,892 INFO L480 AbstractCegarLoop]: Abstraction has 797 states and 1060 transitions. [2018-12-01 07:46:50,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 07:46:50,892 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 1060 transitions. [2018-12-01 07:46:50,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:50,893 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:50,893 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:50,893 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:50,893 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:50,893 INFO L82 PathProgramCache]: Analyzing trace with hash -667773232, now seen corresponding path program 1 times [2018-12-01 07:46:50,893 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:50,893 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:50,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,894 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:50,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:50,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:50,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:50,928 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:50,929 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 07:46:50,929 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 07:46:50,929 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 07:46:50,929 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:50,929 INFO L87 Difference]: Start difference. First operand 797 states and 1060 transitions. Second operand 6 states. [2018-12-01 07:46:50,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:50,992 INFO L93 Difference]: Finished difference Result 1597 states and 2175 transitions. [2018-12-01 07:46:50,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:50,992 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-01 07:46:50,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:50,995 INFO L225 Difference]: With dead ends: 1597 [2018-12-01 07:46:50,995 INFO L226 Difference]: Without dead ends: 823 [2018-12-01 07:46:50,997 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:50,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 823 states. [2018-12-01 07:46:51,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 823 to 807. [2018-12-01 07:46:51,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-01 07:46:51,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1068 transitions. [2018-12-01 07:46:51,035 INFO L78 Accepts]: Start accepts. Automaton has 807 states and 1068 transitions. Word has length 120 [2018-12-01 07:46:51,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:51,035 INFO L480 AbstractCegarLoop]: Abstraction has 807 states and 1068 transitions. [2018-12-01 07:46:51,035 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 07:46:51,035 INFO L276 IsEmpty]: Start isEmpty. Operand 807 states and 1068 transitions. [2018-12-01 07:46:51,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:51,036 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:51,036 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:51,036 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:51,036 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:51,037 INFO L82 PathProgramCache]: Analyzing trace with hash 593144018, now seen corresponding path program 1 times [2018-12-01 07:46:51,037 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:51,037 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:51,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:51,037 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:51,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:51,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:51,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:51,086 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:51,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 07:46:51,086 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 07:46:51,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 07:46:51,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:51,087 INFO L87 Difference]: Start difference. First operand 807 states and 1068 transitions. Second operand 6 states. [2018-12-01 07:46:51,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:51,148 INFO L93 Difference]: Finished difference Result 1631 states and 2212 transitions. [2018-12-01 07:46:51,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:51,148 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-01 07:46:51,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:51,151 INFO L225 Difference]: With dead ends: 1631 [2018-12-01 07:46:51,151 INFO L226 Difference]: Without dead ends: 847 [2018-12-01 07:46:51,153 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:51,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 847 states. [2018-12-01 07:46:51,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 847 to 827. [2018-12-01 07:46:51,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 827 states. [2018-12-01 07:46:51,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 827 states to 827 states and 1088 transitions. [2018-12-01 07:46:51,205 INFO L78 Accepts]: Start accepts. Automaton has 827 states and 1088 transitions. Word has length 120 [2018-12-01 07:46:51,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:51,206 INFO L480 AbstractCegarLoop]: Abstraction has 827 states and 1088 transitions. [2018-12-01 07:46:51,206 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 07:46:51,206 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1088 transitions. [2018-12-01 07:46:51,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-01 07:46:51,207 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:51,207 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:51,207 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:51,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:51,207 INFO L82 PathProgramCache]: Analyzing trace with hash -1762661232, now seen corresponding path program 1 times [2018-12-01 07:46:51,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:51,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:51,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:51,208 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:51,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:51,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:51,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-01 07:46:51,247 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:51,247 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 07:46:51,248 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 07:46:51,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 07:46:51,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:51,248 INFO L87 Difference]: Start difference. First operand 827 states and 1088 transitions. Second operand 4 states. [2018-12-01 07:46:51,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:51,462 INFO L93 Difference]: Finished difference Result 2411 states and 3286 transitions. [2018-12-01 07:46:51,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 07:46:51,463 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-01 07:46:51,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:51,469 INFO L225 Difference]: With dead ends: 2411 [2018-12-01 07:46:51,469 INFO L226 Difference]: Without dead ends: 1607 [2018-12-01 07:46:51,471 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:51,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1607 states. [2018-12-01 07:46:51,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1607 to 1598. [2018-12-01 07:46:51,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1598 states. [2018-12-01 07:46:51,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1598 states to 1598 states and 2097 transitions. [2018-12-01 07:46:51,564 INFO L78 Accepts]: Start accepts. Automaton has 1598 states and 2097 transitions. Word has length 120 [2018-12-01 07:46:51,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:51,564 INFO L480 AbstractCegarLoop]: Abstraction has 1598 states and 2097 transitions. [2018-12-01 07:46:51,564 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 07:46:51,565 INFO L276 IsEmpty]: Start isEmpty. Operand 1598 states and 2097 transitions. [2018-12-01 07:46:51,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:51,566 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:51,566 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:51,566 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:51,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:51,566 INFO L82 PathProgramCache]: Analyzing trace with hash 1599710920, now seen corresponding path program 1 times [2018-12-01 07:46:51,566 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:51,566 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:51,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:51,567 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:51,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:51,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:51,600 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-01 07:46:51,600 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:51,600 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-01 07:46:51,600 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 07:46:51,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 07:46:51,601 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:51,601 INFO L87 Difference]: Start difference. First operand 1598 states and 2097 transitions. Second operand 6 states. [2018-12-01 07:46:51,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:51,692 INFO L93 Difference]: Finished difference Result 3201 states and 4303 transitions. [2018-12-01 07:46:51,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:51,692 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 141 [2018-12-01 07:46:51,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:51,696 INFO L225 Difference]: With dead ends: 3201 [2018-12-01 07:46:51,696 INFO L226 Difference]: Without dead ends: 1626 [2018-12-01 07:46:51,699 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:51,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1626 states. [2018-12-01 07:46:51,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1626 to 1618. [2018-12-01 07:46:51,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-01 07:46:51,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2113 transitions. [2018-12-01 07:46:51,771 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2113 transitions. Word has length 141 [2018-12-01 07:46:51,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:51,771 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2113 transitions. [2018-12-01 07:46:51,771 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 07:46:51,771 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2113 transitions. [2018-12-01 07:46:51,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:51,783 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:51,783 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:51,783 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:51,783 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:51,783 INFO L82 PathProgramCache]: Analyzing trace with hash 1801534854, now seen corresponding path program 1 times [2018-12-01 07:46:51,783 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:51,783 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:51,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:51,784 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:51,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:51,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:51,847 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-01 07:46:51,847 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:51,847 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:51,848 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:51,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:51,848 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:51,848 INFO L87 Difference]: Start difference. First operand 1618 states and 2113 transitions. Second operand 5 states. [2018-12-01 07:46:52,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:52,179 INFO L93 Difference]: Finished difference Result 3212 states and 4210 transitions. [2018-12-01 07:46:52,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:52,180 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-01 07:46:52,180 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:52,186 INFO L225 Difference]: With dead ends: 3212 [2018-12-01 07:46:52,186 INFO L226 Difference]: Without dead ends: 1618 [2018-12-01 07:46:52,190 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:52,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-01 07:46:52,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-01 07:46:52,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-01 07:46:52,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2097 transitions. [2018-12-01 07:46:52,279 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2097 transitions. Word has length 141 [2018-12-01 07:46:52,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:52,279 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2097 transitions. [2018-12-01 07:46:52,279 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:52,279 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2097 transitions. [2018-12-01 07:46:52,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:52,280 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:52,280 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:52,280 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:52,280 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:52,280 INFO L82 PathProgramCache]: Analyzing trace with hash -1106647032, now seen corresponding path program 1 times [2018-12-01 07:46:52,280 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:52,280 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:52,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:52,281 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:52,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:52,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:52,335 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-01 07:46:52,335 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:52,335 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:52,336 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:52,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:52,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:52,336 INFO L87 Difference]: Start difference. First operand 1618 states and 2097 transitions. Second operand 5 states. [2018-12-01 07:46:52,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:52,641 INFO L93 Difference]: Finished difference Result 3212 states and 4178 transitions. [2018-12-01 07:46:52,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:52,642 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-01 07:46:52,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:52,646 INFO L225 Difference]: With dead ends: 3212 [2018-12-01 07:46:52,646 INFO L226 Difference]: Without dead ends: 1618 [2018-12-01 07:46:52,649 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:52,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-01 07:46:52,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-01 07:46:52,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-01 07:46:52,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2081 transitions. [2018-12-01 07:46:52,745 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2081 transitions. Word has length 141 [2018-12-01 07:46:52,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:52,745 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2081 transitions. [2018-12-01 07:46:52,745 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:52,746 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2081 transitions. [2018-12-01 07:46:52,747 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:52,747 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:52,747 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:52,747 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:52,747 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:52,747 INFO L82 PathProgramCache]: Analyzing trace with hash -230628026, now seen corresponding path program 1 times [2018-12-01 07:46:52,747 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:52,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:52,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:52,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:52,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:52,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:52,828 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-01 07:46:52,828 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:52,828 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:52,829 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:52,829 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:52,829 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:52,829 INFO L87 Difference]: Start difference. First operand 1618 states and 2081 transitions. Second operand 5 states. [2018-12-01 07:46:53,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:53,146 INFO L93 Difference]: Finished difference Result 3212 states and 4146 transitions. [2018-12-01 07:46:53,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-01 07:46:53,147 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-01 07:46:53,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:53,150 INFO L225 Difference]: With dead ends: 3212 [2018-12-01 07:46:53,150 INFO L226 Difference]: Without dead ends: 1618 [2018-12-01 07:46:53,153 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:46:53,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-01 07:46:53,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-01 07:46:53,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-01 07:46:53,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2065 transitions. [2018-12-01 07:46:53,225 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2065 transitions. Word has length 141 [2018-12-01 07:46:53,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:53,225 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2065 transitions. [2018-12-01 07:46:53,225 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:53,225 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2065 transitions. [2018-12-01 07:46:53,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:53,226 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:53,227 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:53,227 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:53,227 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:53,227 INFO L82 PathProgramCache]: Analyzing trace with hash 213272648, now seen corresponding path program 1 times [2018-12-01 07:46:53,227 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:53,227 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:53,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:53,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:53,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:53,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:53,277 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-01 07:46:53,277 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:53,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:53,278 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:53,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:53,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:53,278 INFO L87 Difference]: Start difference. First operand 1618 states and 2065 transitions. Second operand 5 states. [2018-12-01 07:46:53,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:53,725 INFO L93 Difference]: Finished difference Result 4062 states and 5227 transitions. [2018-12-01 07:46:53,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:53,725 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-01 07:46:53,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:53,730 INFO L225 Difference]: With dead ends: 4062 [2018-12-01 07:46:53,730 INFO L226 Difference]: Without dead ends: 2468 [2018-12-01 07:46:53,733 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:53,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2468 states. [2018-12-01 07:46:53,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2468 to 2324. [2018-12-01 07:46:53,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2324 states. [2018-12-01 07:46:53,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 2887 transitions. [2018-12-01 07:46:53,853 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 2887 transitions. Word has length 141 [2018-12-01 07:46:53,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:53,854 INFO L480 AbstractCegarLoop]: Abstraction has 2324 states and 2887 transitions. [2018-12-01 07:46:53,854 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:53,854 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 2887 transitions. [2018-12-01 07:46:53,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:53,855 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:53,855 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:53,855 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:53,856 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:53,856 INFO L82 PathProgramCache]: Analyzing trace with hash 1751612678, now seen corresponding path program 1 times [2018-12-01 07:46:53,856 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:53,856 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:53,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:53,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:53,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:53,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:53,902 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-01 07:46:53,902 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:53,902 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:53,903 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:53,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:53,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:53,903 INFO L87 Difference]: Start difference. First operand 2324 states and 2887 transitions. Second operand 5 states. [2018-12-01 07:46:54,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:54,508 INFO L93 Difference]: Finished difference Result 5495 states and 7170 transitions. [2018-12-01 07:46:54,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:54,508 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-01 07:46:54,508 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:54,516 INFO L225 Difference]: With dead ends: 5495 [2018-12-01 07:46:54,516 INFO L226 Difference]: Without dead ends: 3197 [2018-12-01 07:46:54,520 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:54,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3197 states. [2018-12-01 07:46:54,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3197 to 2836. [2018-12-01 07:46:54,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2836 states. [2018-12-01 07:46:54,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2836 states to 2836 states and 3435 transitions. [2018-12-01 07:46:54,646 INFO L78 Accepts]: Start accepts. Automaton has 2836 states and 3435 transitions. Word has length 141 [2018-12-01 07:46:54,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:54,646 INFO L480 AbstractCegarLoop]: Abstraction has 2836 states and 3435 transitions. [2018-12-01 07:46:54,646 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:54,646 INFO L276 IsEmpty]: Start isEmpty. Operand 2836 states and 3435 transitions. [2018-12-01 07:46:54,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:54,648 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:54,648 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:54,648 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:54,648 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:54,648 INFO L82 PathProgramCache]: Analyzing trace with hash -276973432, now seen corresponding path program 1 times [2018-12-01 07:46:54,648 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:54,648 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:54,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:54,649 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:54,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:54,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:54,700 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-01 07:46:54,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:54,701 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:54,701 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:54,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:54,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:54,702 INFO L87 Difference]: Start difference. First operand 2836 states and 3435 transitions. Second operand 5 states. [2018-12-01 07:46:55,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:55,195 INFO L93 Difference]: Finished difference Result 6035 states and 7539 transitions. [2018-12-01 07:46:55,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:55,195 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-01 07:46:55,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:55,201 INFO L225 Difference]: With dead ends: 6035 [2018-12-01 07:46:55,201 INFO L226 Difference]: Without dead ends: 3225 [2018-12-01 07:46:55,205 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:55,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3225 states. [2018-12-01 07:46:55,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3225 to 3060. [2018-12-01 07:46:55,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3060 states. [2018-12-01 07:46:55,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3060 states to 3060 states and 3641 transitions. [2018-12-01 07:46:55,334 INFO L78 Accepts]: Start accepts. Automaton has 3060 states and 3641 transitions. Word has length 141 [2018-12-01 07:46:55,334 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:55,334 INFO L480 AbstractCegarLoop]: Abstraction has 3060 states and 3641 transitions. [2018-12-01 07:46:55,334 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:55,335 INFO L276 IsEmpty]: Start isEmpty. Operand 3060 states and 3641 transitions. [2018-12-01 07:46:55,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:55,336 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:55,336 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:55,336 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:55,336 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:55,336 INFO L82 PathProgramCache]: Analyzing trace with hash -758053690, now seen corresponding path program 1 times [2018-12-01 07:46:55,336 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:55,336 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:55,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:55,337 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:55,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:55,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:55,381 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-01 07:46:55,381 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:55,382 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-01 07:46:55,382 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-01 07:46:55,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-01 07:46:55,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-01 07:46:55,382 INFO L87 Difference]: Start difference. First operand 3060 states and 3641 transitions. Second operand 5 states. [2018-12-01 07:46:55,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:55,895 INFO L93 Difference]: Finished difference Result 6473 states and 8022 transitions. [2018-12-01 07:46:55,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-01 07:46:55,895 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-01 07:46:55,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:55,904 INFO L225 Difference]: With dead ends: 6473 [2018-12-01 07:46:55,904 INFO L226 Difference]: Without dead ends: 3437 [2018-12-01 07:46:55,909 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:46:55,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3437 states. [2018-12-01 07:46:56,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3437 to 3206. [2018-12-01 07:46:56,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3206 states. [2018-12-01 07:46:56,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3206 states to 3206 states and 3739 transitions. [2018-12-01 07:46:56,060 INFO L78 Accepts]: Start accepts. Automaton has 3206 states and 3739 transitions. Word has length 141 [2018-12-01 07:46:56,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:56,060 INFO L480 AbstractCegarLoop]: Abstraction has 3206 states and 3739 transitions. [2018-12-01 07:46:56,060 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-01 07:46:56,060 INFO L276 IsEmpty]: Start isEmpty. Operand 3206 states and 3739 transitions. [2018-12-01 07:46:56,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-01 07:46:56,061 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:56,061 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:56,061 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:56,061 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:56,062 INFO L82 PathProgramCache]: Analyzing trace with hash -773572408, now seen corresponding path program 1 times [2018-12-01 07:46:56,062 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:56,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:56,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:56,062 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:56,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:56,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:56,081 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-01 07:46:56,081 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-01 07:46:56,081 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-01 07:46:56,090 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:56,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:56,154 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-01 07:46:56,174 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-01 07:46:56,194 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-01 07:46:56,194 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 3 [2018-12-01 07:46:56,194 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-01 07:46:56,194 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-01 07:46:56,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 07:46:56,195 INFO L87 Difference]: Start difference. First operand 3206 states and 3739 transitions. Second operand 3 states. [2018-12-01 07:46:56,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:56,603 INFO L93 Difference]: Finished difference Result 9337 states and 11099 transitions. [2018-12-01 07:46:56,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-01 07:46:56,603 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 141 [2018-12-01 07:46:56,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:56,616 INFO L225 Difference]: With dead ends: 9337 [2018-12-01 07:46:56,617 INFO L226 Difference]: Without dead ends: 6157 [2018-12-01 07:46:56,623 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 141 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 07:46:56,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6157 states. [2018-12-01 07:46:57,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6157 to 5799. [2018-12-01 07:46:57,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5799 states. [2018-12-01 07:46:57,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5799 states to 5799 states and 6920 transitions. [2018-12-01 07:46:57,039 INFO L78 Accepts]: Start accepts. Automaton has 5799 states and 6920 transitions. Word has length 141 [2018-12-01 07:46:57,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:57,039 INFO L480 AbstractCegarLoop]: Abstraction has 5799 states and 6920 transitions. [2018-12-01 07:46:57,039 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-01 07:46:57,039 INFO L276 IsEmpty]: Start isEmpty. Operand 5799 states and 6920 transitions. [2018-12-01 07:46:57,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2018-12-01 07:46:57,041 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:57,041 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:57,041 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:57,042 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:57,042 INFO L82 PathProgramCache]: Analyzing trace with hash 804161786, now seen corresponding path program 1 times [2018-12-01 07:46:57,042 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:57,042 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:57,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:57,042 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:57,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:57,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:57,071 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-01 07:46:57,071 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:57,071 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-01 07:46:57,072 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-01 07:46:57,072 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-01 07:46:57,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 07:46:57,072 INFO L87 Difference]: Start difference. First operand 5799 states and 6920 transitions. Second operand 3 states. [2018-12-01 07:46:57,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:57,627 INFO L93 Difference]: Finished difference Result 17259 states and 20921 transitions. [2018-12-01 07:46:57,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-01 07:46:57,627 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 143 [2018-12-01 07:46:57,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:57,645 INFO L225 Difference]: With dead ends: 17259 [2018-12-01 07:46:57,645 INFO L226 Difference]: Without dead ends: 8725 [2018-12-01 07:46:57,658 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 07:46:57,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8725 states. [2018-12-01 07:46:58,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8725 to 8725. [2018-12-01 07:46:58,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8725 states. [2018-12-01 07:46:58,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8725 states to 8725 states and 10596 transitions. [2018-12-01 07:46:58,114 INFO L78 Accepts]: Start accepts. Automaton has 8725 states and 10596 transitions. Word has length 143 [2018-12-01 07:46:58,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:58,115 INFO L480 AbstractCegarLoop]: Abstraction has 8725 states and 10596 transitions. [2018-12-01 07:46:58,115 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-01 07:46:58,115 INFO L276 IsEmpty]: Start isEmpty. Operand 8725 states and 10596 transitions. [2018-12-01 07:46:58,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-12-01 07:46:58,121 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:58,122 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:58,122 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:58,122 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:58,122 INFO L82 PathProgramCache]: Analyzing trace with hash -1090290347, now seen corresponding path program 1 times [2018-12-01 07:46:58,122 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:58,122 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:58,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:58,123 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:58,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:58,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:58,175 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-12-01 07:46:58,175 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:58,176 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 07:46:58,176 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 07:46:58,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 07:46:58,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:58,176 INFO L87 Difference]: Start difference. First operand 8725 states and 10596 transitions. Second operand 4 states. [2018-12-01 07:46:58,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:46:58,945 INFO L93 Difference]: Finished difference Result 18513 states and 22907 transitions. [2018-12-01 07:46:58,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 07:46:58,946 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 204 [2018-12-01 07:46:58,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:46:58,962 INFO L225 Difference]: With dead ends: 18513 [2018-12-01 07:46:58,962 INFO L226 Difference]: Without dead ends: 9825 [2018-12-01 07:46:58,977 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:58,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9825 states. [2018-12-01 07:46:59,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9825 to 9801. [2018-12-01 07:46:59,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9801 states. [2018-12-01 07:46:59,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9801 states to 9801 states and 11445 transitions. [2018-12-01 07:46:59,454 INFO L78 Accepts]: Start accepts. Automaton has 9801 states and 11445 transitions. Word has length 204 [2018-12-01 07:46:59,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:46:59,454 INFO L480 AbstractCegarLoop]: Abstraction has 9801 states and 11445 transitions. [2018-12-01 07:46:59,454 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 07:46:59,454 INFO L276 IsEmpty]: Start isEmpty. Operand 9801 states and 11445 transitions. [2018-12-01 07:46:59,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-12-01 07:46:59,460 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:46:59,460 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:46:59,460 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:46:59,460 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:46:59,461 INFO L82 PathProgramCache]: Analyzing trace with hash 415933920, now seen corresponding path program 1 times [2018-12-01 07:46:59,461 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:46:59,461 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:46:59,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:59,461 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:46:59,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:46:59,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:46:59,506 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-12-01 07:46:59,506 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:46:59,506 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-01 07:46:59,506 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-01 07:46:59,506 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-01 07:46:59,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:46:59,507 INFO L87 Difference]: Start difference. First operand 9801 states and 11445 transitions. Second operand 4 states. [2018-12-01 07:47:00,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:47:00,103 INFO L93 Difference]: Finished difference Result 19567 states and 22834 transitions. [2018-12-01 07:47:00,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-01 07:47:00,104 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 212 [2018-12-01 07:47:00,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:47:00,118 INFO L225 Difference]: With dead ends: 19567 [2018-12-01 07:47:00,118 INFO L226 Difference]: Without dead ends: 9790 [2018-12-01 07:47:00,126 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-01 07:47:00,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9790 states. [2018-12-01 07:47:00,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9790 to 9790. [2018-12-01 07:47:00,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9790 states. [2018-12-01 07:47:00,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9790 states to 9790 states and 11421 transitions. [2018-12-01 07:47:00,594 INFO L78 Accepts]: Start accepts. Automaton has 9790 states and 11421 transitions. Word has length 212 [2018-12-01 07:47:00,594 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:47:00,594 INFO L480 AbstractCegarLoop]: Abstraction has 9790 states and 11421 transitions. [2018-12-01 07:47:00,595 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-01 07:47:00,595 INFO L276 IsEmpty]: Start isEmpty. Operand 9790 states and 11421 transitions. [2018-12-01 07:47:00,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 206 [2018-12-01 07:47:00,600 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:47:00,600 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:47:00,600 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:47:00,600 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:47:00,601 INFO L82 PathProgramCache]: Analyzing trace with hash -106589261, now seen corresponding path program 1 times [2018-12-01 07:47:00,601 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:47:00,601 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:47:00,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:00,601 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:00,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:00,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:00,641 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-01 07:47:00,641 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-01 07:47:00,641 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-01 07:47:00,641 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-01 07:47:00,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-01 07:47:00,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 07:47:00,642 INFO L87 Difference]: Start difference. First operand 9790 states and 11421 transitions. Second operand 3 states. [2018-12-01 07:47:01,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:47:01,522 INFO L93 Difference]: Finished difference Result 26195 states and 31407 transitions. [2018-12-01 07:47:01,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-01 07:47:01,523 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 205 [2018-12-01 07:47:01,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:47:01,550 INFO L225 Difference]: With dead ends: 26195 [2018-12-01 07:47:01,551 INFO L226 Difference]: Without dead ends: 16431 [2018-12-01 07:47:01,565 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 07:47:01,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16431 states. [2018-12-01 07:47:02,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16431 to 16425. [2018-12-01 07:47:02,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16425 states. [2018-12-01 07:47:02,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16425 states to 16425 states and 19526 transitions. [2018-12-01 07:47:02,399 INFO L78 Accepts]: Start accepts. Automaton has 16425 states and 19526 transitions. Word has length 205 [2018-12-01 07:47:02,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:47:02,400 INFO L480 AbstractCegarLoop]: Abstraction has 16425 states and 19526 transitions. [2018-12-01 07:47:02,400 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-01 07:47:02,400 INFO L276 IsEmpty]: Start isEmpty. Operand 16425 states and 19526 transitions. [2018-12-01 07:47:02,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-12-01 07:47:02,409 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:47:02,409 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:47:02,409 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:47:02,410 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:47:02,410 INFO L82 PathProgramCache]: Analyzing trace with hash 1744893044, now seen corresponding path program 1 times [2018-12-01 07:47:02,410 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:47:02,410 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:47:02,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:02,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:02,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:02,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:02,465 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-12-01 07:47:02,465 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-01 07:47:02,465 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-01 07:47:02,472 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:02,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:02,548 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-01 07:47:02,575 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 51 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-01 07:47:02,590 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-01 07:47:02,591 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [6] total 7 [2018-12-01 07:47:02,591 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-01 07:47:02,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-01 07:47:02,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-01 07:47:02,591 INFO L87 Difference]: Start difference. First operand 16425 states and 19526 transitions. Second operand 7 states. [2018-12-01 07:47:04,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:47:04,486 INFO L93 Difference]: Finished difference Result 39760 states and 50058 transitions. [2018-12-01 07:47:04,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-01 07:47:04,487 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 206 [2018-12-01 07:47:04,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:47:04,518 INFO L225 Difference]: With dead ends: 39760 [2018-12-01 07:47:04,518 INFO L226 Difference]: Without dead ends: 18061 [2018-12-01 07:47:04,548 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 208 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-12-01 07:47:04,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18061 states. [2018-12-01 07:47:05,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18061 to 18060. [2018-12-01 07:47:05,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18060 states. [2018-12-01 07:47:05,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18060 states to 18060 states and 21645 transitions. [2018-12-01 07:47:05,547 INFO L78 Accepts]: Start accepts. Automaton has 18060 states and 21645 transitions. Word has length 206 [2018-12-01 07:47:05,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:47:05,547 INFO L480 AbstractCegarLoop]: Abstraction has 18060 states and 21645 transitions. [2018-12-01 07:47:05,547 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-01 07:47:05,547 INFO L276 IsEmpty]: Start isEmpty. Operand 18060 states and 21645 transitions. [2018-12-01 07:47:05,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2018-12-01 07:47:05,565 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:47:05,565 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:47:05,565 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:47:05,565 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:47:05,565 INFO L82 PathProgramCache]: Analyzing trace with hash -1437082662, now seen corresponding path program 1 times [2018-12-01 07:47:05,565 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:47:05,566 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:47:05,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:05,566 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:05,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:05,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:05,622 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 6 proven. 39 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2018-12-01 07:47:05,622 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-01 07:47:05,623 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-01 07:47:05,628 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:05,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:05,701 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-01 07:47:05,746 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 147 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-12-01 07:47:05,761 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-01 07:47:05,761 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-01 07:47:05,761 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 07:47:05,762 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 07:47:05,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:47:05,762 INFO L87 Difference]: Start difference. First operand 18060 states and 21645 transitions. Second operand 6 states. [2018-12-01 07:47:09,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:47:09,178 INFO L93 Difference]: Finished difference Result 61178 states and 86352 transitions. [2018-12-01 07:47:09,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-01 07:47:09,178 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 292 [2018-12-01 07:47:09,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:47:09,280 INFO L225 Difference]: With dead ends: 61178 [2018-12-01 07:47:09,280 INFO L226 Difference]: Without dead ends: 43142 [2018-12-01 07:47:09,326 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 309 GetRequests, 299 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-12-01 07:47:09,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43142 states. [2018-12-01 07:47:11,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43142 to 41940. [2018-12-01 07:47:11,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41940 states. [2018-12-01 07:47:12,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41940 states to 41940 states and 53929 transitions. [2018-12-01 07:47:12,050 INFO L78 Accepts]: Start accepts. Automaton has 41940 states and 53929 transitions. Word has length 292 [2018-12-01 07:47:12,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:47:12,050 INFO L480 AbstractCegarLoop]: Abstraction has 41940 states and 53929 transitions. [2018-12-01 07:47:12,050 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 07:47:12,050 INFO L276 IsEmpty]: Start isEmpty. Operand 41940 states and 53929 transitions. [2018-12-01 07:47:12,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 286 [2018-12-01 07:47:12,073 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:47:12,073 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:47:12,073 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:47:12,073 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:47:12,073 INFO L82 PathProgramCache]: Analyzing trace with hash -2083964120, now seen corresponding path program 1 times [2018-12-01 07:47:12,073 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:47:12,073 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:47:12,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:12,074 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:12,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:12,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:12,133 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 17 proven. 7 refuted. 0 times theorem prover too weak. 154 trivial. 0 not checked. [2018-12-01 07:47:12,133 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-01 07:47:12,133 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-01 07:47:12,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:12,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:12,225 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-01 07:47:12,262 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 126 proven. 0 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-01 07:47:12,287 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-01 07:47:12,287 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-12-01 07:47:12,288 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 07:47:12,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 07:47:12,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:47:12,288 INFO L87 Difference]: Start difference. First operand 41940 states and 53929 transitions. Second operand 6 states. [2018-12-01 07:47:18,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:47:18,424 INFO L93 Difference]: Finished difference Result 129979 states and 186622 transitions. [2018-12-01 07:47:18,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-01 07:47:18,425 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 285 [2018-12-01 07:47:18,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:47:18,591 INFO L225 Difference]: With dead ends: 129979 [2018-12-01 07:47:18,591 INFO L226 Difference]: Without dead ends: 65200 [2018-12-01 07:47:18,732 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 293 GetRequests, 287 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-12-01 07:47:18,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65200 states. [2018-12-01 07:47:22,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65200 to 65095. [2018-12-01 07:47:22,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65095 states. [2018-12-01 07:47:23,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65095 states to 65095 states and 93537 transitions. [2018-12-01 07:47:23,165 INFO L78 Accepts]: Start accepts. Automaton has 65095 states and 93537 transitions. Word has length 285 [2018-12-01 07:47:23,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:47:23,166 INFO L480 AbstractCegarLoop]: Abstraction has 65095 states and 93537 transitions. [2018-12-01 07:47:23,166 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 07:47:23,166 INFO L276 IsEmpty]: Start isEmpty. Operand 65095 states and 93537 transitions. [2018-12-01 07:47:23,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 555 [2018-12-01 07:47:23,261 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:47:23,261 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:47:23,262 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:47:23,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:47:23,262 INFO L82 PathProgramCache]: Analyzing trace with hash -1098776527, now seen corresponding path program 1 times [2018-12-01 07:47:23,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:47:23,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:47:23,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:23,262 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:23,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:23,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:23,365 INFO L134 CoverageAnalysis]: Checked inductivity of 910 backedges. 40 proven. 22 refuted. 0 times theorem prover too weak. 848 trivial. 0 not checked. [2018-12-01 07:47:23,365 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-01 07:47:23,365 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-01 07:47:23,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:23,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:23,488 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-01 07:47:23,564 INFO L134 CoverageAnalysis]: Checked inductivity of 910 backedges. 514 proven. 0 refuted. 0 times theorem prover too weak. 396 trivial. 0 not checked. [2018-12-01 07:47:23,580 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-01 07:47:23,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-01 07:47:23,580 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-01 07:47:23,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-01 07:47:23,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-01 07:47:23,581 INFO L87 Difference]: Start difference. First operand 65095 states and 93537 transitions. Second operand 6 states. [2018-12-01 07:47:32,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:47:32,770 INFO L93 Difference]: Finished difference Result 180573 states and 271857 transitions. [2018-12-01 07:47:32,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-01 07:47:32,770 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 554 [2018-12-01 07:47:32,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:47:33,068 INFO L225 Difference]: With dead ends: 180573 [2018-12-01 07:47:33,068 INFO L226 Difference]: Without dead ends: 98598 [2018-12-01 07:47:33,383 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 573 GetRequests, 563 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2018-12-01 07:47:33,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98598 states. [2018-12-01 07:47:39,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98598 to 97738. [2018-12-01 07:47:39,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97738 states. [2018-12-01 07:47:39,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97738 states to 97738 states and 120954 transitions. [2018-12-01 07:47:39,791 INFO L78 Accepts]: Start accepts. Automaton has 97738 states and 120954 transitions. Word has length 554 [2018-12-01 07:47:39,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:47:39,792 INFO L480 AbstractCegarLoop]: Abstraction has 97738 states and 120954 transitions. [2018-12-01 07:47:39,792 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-01 07:47:39,792 INFO L276 IsEmpty]: Start isEmpty. Operand 97738 states and 120954 transitions. [2018-12-01 07:47:39,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 558 [2018-12-01 07:47:39,839 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:47:39,839 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:47:39,839 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:47:39,840 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:47:39,840 INFO L82 PathProgramCache]: Analyzing trace with hash 304938434, now seen corresponding path program 1 times [2018-12-01 07:47:39,840 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:47:39,840 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:47:39,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:39,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:39,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:39,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:39,969 INFO L134 CoverageAnalysis]: Checked inductivity of 923 backedges. 39 proven. 26 refuted. 0 times theorem prover too weak. 858 trivial. 0 not checked. [2018-12-01 07:47:39,970 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-01 07:47:39,970 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-01 07:47:39,977 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:40,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:40,106 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-01 07:47:40,181 INFO L134 CoverageAnalysis]: Checked inductivity of 923 backedges. 492 proven. 0 refuted. 0 times theorem prover too weak. 431 trivial. 0 not checked. [2018-12-01 07:47:40,196 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-01 07:47:40,196 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-12-01 07:47:40,197 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-01 07:47:40,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-01 07:47:40,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-12-01 07:47:40,197 INFO L87 Difference]: Start difference. First operand 97738 states and 120954 transitions. Second operand 9 states. [2018-12-01 07:47:41,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:47:41,894 INFO L93 Difference]: Finished difference Result 107066 states and 131975 transitions. [2018-12-01 07:47:41,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-12-01 07:47:41,895 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 557 [2018-12-01 07:47:41,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:47:41,916 INFO L225 Difference]: With dead ends: 107066 [2018-12-01 07:47:41,916 INFO L226 Difference]: Without dead ends: 4094 [2018-12-01 07:47:42,031 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 579 GetRequests, 561 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=73, Invalid=233, Unknown=0, NotChecked=0, Total=306 [2018-12-01 07:47:42,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4094 states. [2018-12-01 07:47:42,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4094 to 3801. [2018-12-01 07:47:42,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3801 states. [2018-12-01 07:47:42,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3801 states to 3801 states and 4135 transitions. [2018-12-01 07:47:42,263 INFO L78 Accepts]: Start accepts. Automaton has 3801 states and 4135 transitions. Word has length 557 [2018-12-01 07:47:42,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:47:42,263 INFO L480 AbstractCegarLoop]: Abstraction has 3801 states and 4135 transitions. [2018-12-01 07:47:42,263 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-01 07:47:42,263 INFO L276 IsEmpty]: Start isEmpty. Operand 3801 states and 4135 transitions. [2018-12-01 07:47:42,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 585 [2018-12-01 07:47:42,266 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:47:42,266 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:47:42,267 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:47:42,267 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:47:42,267 INFO L82 PathProgramCache]: Analyzing trace with hash -1713229204, now seen corresponding path program 1 times [2018-12-01 07:47:42,267 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:47:42,267 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:47:42,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:42,267 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:42,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:42,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:42,376 INFO L134 CoverageAnalysis]: Checked inductivity of 996 backedges. 64 proven. 50 refuted. 0 times theorem prover too weak. 882 trivial. 0 not checked. [2018-12-01 07:47:42,376 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-01 07:47:42,376 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-01 07:47:42,382 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:42,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-01 07:47:42,504 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-01 07:47:42,589 INFO L134 CoverageAnalysis]: Checked inductivity of 996 backedges. 556 proven. 0 refuted. 0 times theorem prover too weak. 440 trivial. 0 not checked. [2018-12-01 07:47:42,604 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-01 07:47:42,605 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 3 [2018-12-01 07:47:42,605 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-01 07:47:42,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-01 07:47:42,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 07:47:42,605 INFO L87 Difference]: Start difference. First operand 3801 states and 4135 transitions. Second operand 3 states. [2018-12-01 07:47:42,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-01 07:47:42,770 INFO L93 Difference]: Finished difference Result 6037 states and 6573 transitions. [2018-12-01 07:47:42,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-01 07:47:42,771 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 584 [2018-12-01 07:47:42,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-01 07:47:42,774 INFO L225 Difference]: With dead ends: 6037 [2018-12-01 07:47:42,774 INFO L226 Difference]: Without dead ends: 2395 [2018-12-01 07:47:42,777 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 586 GetRequests, 584 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-01 07:47:42,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2395 states. [2018-12-01 07:47:42,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2395 to 2395. [2018-12-01 07:47:42,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2395 states. [2018-12-01 07:47:42,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2395 states to 2395 states and 2567 transitions. [2018-12-01 07:47:42,917 INFO L78 Accepts]: Start accepts. Automaton has 2395 states and 2567 transitions. Word has length 584 [2018-12-01 07:47:42,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-01 07:47:42,917 INFO L480 AbstractCegarLoop]: Abstraction has 2395 states and 2567 transitions. [2018-12-01 07:47:42,917 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-01 07:47:42,917 INFO L276 IsEmpty]: Start isEmpty. Operand 2395 states and 2567 transitions. [2018-12-01 07:47:42,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 427 [2018-12-01 07:47:42,919 INFO L394 BasicCegarLoop]: Found error trace [2018-12-01 07:47:42,919 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-01 07:47:42,920 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-01 07:47:42,920 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-01 07:47:42,920 INFO L82 PathProgramCache]: Analyzing trace with hash -2114224743, now seen corresponding path program 1 times [2018-12-01 07:47:42,920 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-01 07:47:42,920 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-01 07:47:42,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:42,920 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-01 07:47:42,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-01 07:47:42,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-01 07:47:42,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-01 07:47:43,044 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-01 07:47:43,194 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 01.12 07:47:43 BoogieIcfgContainer [2018-12-01 07:47:43,194 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-01 07:47:43,194 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-01 07:47:43,194 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-01 07:47:43,194 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-01 07:47:43,195 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 01.12 07:46:47" (3/4) ... [2018-12-01 07:47:43,196 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-01 07:47:43,327 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_fb4f37ce-dc8a-47e2-ace2-a4e81bcd046d/bin-2019/uautomizer/witness.graphml [2018-12-01 07:47:43,327 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-01 07:47:43,328 INFO L168 Benchmark]: Toolchain (without parser) took 56849.09 ms. Allocated memory was 1.0 GB in the beginning and 5.4 GB in the end (delta: 4.4 GB). Free memory was 953.3 MB in the beginning and 1.3 GB in the end (delta: -382.5 MB). Peak memory consumption was 4.0 GB. Max. memory is 11.5 GB. [2018-12-01 07:47:43,329 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-01 07:47:43,329 INFO L168 Benchmark]: CACSL2BoogieTranslator took 221.57 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 103.8 MB). Free memory was 953.3 MB in the beginning and 1.1 GB in the end (delta: -150.7 MB). Peak memory consumption was 30.1 MB. Max. memory is 11.5 GB. [2018-12-01 07:47:43,329 INFO L168 Benchmark]: Boogie Procedure Inliner took 14.52 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-01 07:47:43,329 INFO L168 Benchmark]: Boogie Preprocessor took 23.31 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-01 07:47:43,329 INFO L168 Benchmark]: RCFGBuilder took 325.22 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.7 MB). Peak memory consumption was 47.7 MB. Max. memory is 11.5 GB. [2018-12-01 07:47:43,329 INFO L168 Benchmark]: TraceAbstraction took 56128.08 ms. Allocated memory was 1.1 GB in the beginning and 5.4 GB in the end (delta: 4.3 GB). Free memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: -361.0 MB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. [2018-12-01 07:47:43,329 INFO L168 Benchmark]: Witness Printer took 133.06 ms. Allocated memory is still 5.4 GB. Free memory was 1.4 GB in the beginning and 1.3 GB in the end (delta: 73.4 MB). Peak memory consumption was 73.4 MB. Max. memory is 11.5 GB. [2018-12-01 07:47:43,330 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 221.57 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 103.8 MB). Free memory was 953.3 MB in the beginning and 1.1 GB in the end (delta: -150.7 MB). Peak memory consumption was 30.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 14.52 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 23.31 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 325.22 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.7 MB). Peak memory consumption was 47.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 56128.08 ms. Allocated memory was 1.1 GB in the beginning and 5.4 GB in the end (delta: 4.3 GB). Free memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: -361.0 MB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. * Witness Printer took 133.06 ms. Allocated memory is still 5.4 GB. Free memory was 1.4 GB in the beginning and 1.3 GB in the end (delta: 73.4 MB). Peak memory consumption was 73.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [\old(E_1)=21, \old(E_2)=5, \old(E_3)=25, \old(E_4)=11, \old(M_E)=17, \old(m_i)=7, \old(m_pc)=15, \old(m_st)=16, \old(T1_E)=3, \old(t1_i)=19, \old(t1_pc)=9, \old(t1_st)=4, \old(T2_E)=18, \old(t2_i)=6, \old(t2_pc)=10, \old(t2_st)=13, \old(T3_E)=23, \old(t3_i)=24, \old(t3_pc)=8, \old(t3_st)=14, \old(T4_E)=26, \old(t4_i)=20, \old(t4_pc)=22, \old(t4_st)=12, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L815] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L815] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L816] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L759] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L762] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L762] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L397] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L160] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L473] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L417] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L417] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L180] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L180] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L214] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 27 procedures, 229 locations, 1 error locations. UNSAFE Result, 56.0s OverallTime, 35 OverallIterations, 7 TraceHistogramMax, 33.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 12204 SDtfs, 14506 SDslu, 14637 SDs, 0 SdLazy, 9537 SolverSat, 3591 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2921 GetRequests, 2723 SyntacticMatches, 47 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=97738occurred in iteration=32, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 18.8s AutomataMinimizationTime, 34 MinimizatonAttempts, 4178 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 9356 NumberOfCodeBlocks, 9356 NumberOfCodeBlocksAsserted, 42 NumberOfCheckSat, 8889 ConstructedInterpolants, 0 QuantifiedInterpolants, 3469596 SizeOfPredicates, 4 NumberOfNonLiveVariables, 10696 ConjunctsInSsa, 21 ConjunctsInUnsatCore, 41 InterpolantComputations, 34 PerfectInterpolantSequences, 6720/6878 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...