./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c -s /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9af739900018493f70ca6be86d814e194413d937 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-09 04:30:52,599 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 04:30:52,600 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 04:30:52,606 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 04:30:52,606 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 04:30:52,606 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 04:30:52,607 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 04:30:52,608 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 04:30:52,609 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 04:30:52,609 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 04:30:52,609 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 04:30:52,610 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 04:30:52,610 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 04:30:52,610 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 04:30:52,611 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 04:30:52,611 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 04:30:52,612 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 04:30:52,613 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 04:30:52,614 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 04:30:52,614 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 04:30:52,615 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 04:30:52,615 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 04:30:52,617 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 04:30:52,617 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 04:30:52,617 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 04:30:52,617 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 04:30:52,618 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 04:30:52,618 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 04:30:52,619 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 04:30:52,619 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 04:30:52,619 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 04:30:52,620 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 04:30:52,620 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 04:30:52,620 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 04:30:52,620 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 04:30:52,621 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 04:30:52,621 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-12-09 04:30:52,628 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 04:30:52,628 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 04:30:52,629 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 04:30:52,629 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 04:30:52,629 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-09 04:30:52,629 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-09 04:30:52,629 INFO L133 SettingsManager]: * Use SBE=true [2018-12-09 04:30:52,629 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-09 04:30:52,630 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-09 04:30:52,630 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 04:30:52,631 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 04:30:52,631 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 04:30:52,631 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 04:30:52,631 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 04:30:52,631 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 04:30:52,631 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 04:30:52,631 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-09 04:30:52,631 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 04:30:52,631 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9af739900018493f70ca6be86d814e194413d937 [2018-12-09 04:30:52,649 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 04:30:52,658 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 04:30:52,661 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 04:30:52,662 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 04:30:52,662 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 04:30:52,662 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-12-09 04:30:52,708 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/data/3e6e8eb5b/1fff4e871f7845edaaf0ca5387d0bff5/FLAG948a8df22 [2018-12-09 04:30:53,109 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 04:30:53,109 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-12-09 04:30:53,112 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/data/3e6e8eb5b/1fff4e871f7845edaaf0ca5387d0bff5/FLAG948a8df22 [2018-12-09 04:30:53,121 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/data/3e6e8eb5b/1fff4e871f7845edaaf0ca5387d0bff5 [2018-12-09 04:30:53,122 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 04:30:53,123 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-12-09 04:30:53,124 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 04:30:53,124 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 04:30:53,126 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 04:30:53,126 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,128 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@550eb617 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53, skipping insertion in model container [2018-12-09 04:30:53,128 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,132 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 04:30:53,140 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 04:30:53,223 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 04:30:53,228 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 04:30:53,238 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 04:30:53,246 INFO L195 MainTranslator]: Completed translation [2018-12-09 04:30:53,246 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53 WrapperNode [2018-12-09 04:30:53,247 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 04:30:53,247 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 04:30:53,247 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 04:30:53,247 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 04:30:53,254 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,255 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,259 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,259 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,263 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,266 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,267 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (1/1) ... [2018-12-09 04:30:53,267 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 04:30:53,268 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 04:30:53,268 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 04:30:53,268 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 04:30:53,268 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 04:30:53,330 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 04:30:53,330 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 04:30:53,330 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-12-09 04:30:53,330 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 04:30:53,330 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-12-09 04:30:53,330 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-09 04:30:53,330 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 04:30:53,331 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-09 04:30:53,331 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-09 04:30:53,331 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-09 04:30:53,331 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 04:30:53,331 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 04:30:53,462 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 04:30:53,462 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-12-09 04:30:53,463 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 04:30:53 BoogieIcfgContainer [2018-12-09 04:30:53,463 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 04:30:53,463 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 04:30:53,463 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 04:30:53,466 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 04:30:53,466 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 04:30:53" (1/3) ... [2018-12-09 04:30:53,467 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@530ea1ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 04:30:53, skipping insertion in model container [2018-12-09 04:30:53,467 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 04:30:53" (2/3) ... [2018-12-09 04:30:53,467 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@530ea1ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 04:30:53, skipping insertion in model container [2018-12-09 04:30:53,467 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 04:30:53" (3/3) ... [2018-12-09 04:30:53,469 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-12-09 04:30:53,477 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 04:30:53,483 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-12-09 04:30:53,496 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-12-09 04:30:53,511 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-09 04:30:53,511 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 04:30:53,512 INFO L383 AbstractCegarLoop]: Hoare is false [2018-12-09 04:30:53,512 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 04:30:53,512 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 04:30:53,512 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 04:30:53,512 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 04:30:53,512 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 04:30:53,512 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 04:30:53,523 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states. [2018-12-09 04:30:53,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-12-09 04:30:53,529 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:53,529 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:53,531 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:53,534 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:53,534 INFO L82 PathProgramCache]: Analyzing trace with hash 1909189377, now seen corresponding path program 1 times [2018-12-09 04:30:53,535 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:53,535 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:53,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:53,564 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:53,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:53,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:53,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 04:30:53,626 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 04:30:53,626 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 04:30:53,628 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 04:30:53,636 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 04:30:53,636 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 04:30:53,637 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 3 states. [2018-12-09 04:30:53,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:53,676 INFO L93 Difference]: Finished difference Result 58 states and 63 transitions. [2018-12-09 04:30:53,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 04:30:53,677 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 10 [2018-12-09 04:30:53,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:53,683 INFO L225 Difference]: With dead ends: 58 [2018-12-09 04:30:53,683 INFO L226 Difference]: Without dead ends: 54 [2018-12-09 04:30:53,684 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 04:30:53,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-12-09 04:30:53,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 39. [2018-12-09 04:30:53,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-12-09 04:30:53,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 42 transitions. [2018-12-09 04:30:53,707 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 42 transitions. Word has length 10 [2018-12-09 04:30:53,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:53,707 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 42 transitions. [2018-12-09 04:30:53,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 04:30:53,707 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 42 transitions. [2018-12-09 04:30:53,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-12-09 04:30:53,708 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:53,708 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:53,708 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:53,708 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:53,708 INFO L82 PathProgramCache]: Analyzing trace with hash -941983064, now seen corresponding path program 1 times [2018-12-09 04:30:53,708 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:53,708 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:53,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:53,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:53,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:53,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:53,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 04:30:53,760 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 04:30:53,760 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 04:30:53,761 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 04:30:53,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 04:30:53,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-09 04:30:53,762 INFO L87 Difference]: Start difference. First operand 39 states and 42 transitions. Second operand 6 states. [2018-12-09 04:30:53,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:53,851 INFO L93 Difference]: Finished difference Result 83 states and 88 transitions. [2018-12-09 04:30:53,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 04:30:53,852 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 11 [2018-12-09 04:30:53,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:53,853 INFO L225 Difference]: With dead ends: 83 [2018-12-09 04:30:53,853 INFO L226 Difference]: Without dead ends: 83 [2018-12-09 04:30:53,854 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 04:30:53,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-12-09 04:30:53,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 53. [2018-12-09 04:30:53,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-12-09 04:30:53,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 61 transitions. [2018-12-09 04:30:53,858 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 61 transitions. Word has length 11 [2018-12-09 04:30:53,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:53,858 INFO L480 AbstractCegarLoop]: Abstraction has 53 states and 61 transitions. [2018-12-09 04:30:53,858 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 04:30:53,858 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 61 transitions. [2018-12-09 04:30:53,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-09 04:30:53,858 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:53,859 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:53,859 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:53,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:53,859 INFO L82 PathProgramCache]: Analyzing trace with hash 863296133, now seen corresponding path program 1 times [2018-12-09 04:30:53,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:53,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:53,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:53,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:53,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:53,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:53,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 04:30:53,888 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 04:30:53,888 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 04:30:53,888 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 04:30:53,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 04:30:53,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 04:30:53,889 INFO L87 Difference]: Start difference. First operand 53 states and 61 transitions. Second operand 5 states. [2018-12-09 04:30:53,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:53,922 INFO L93 Difference]: Finished difference Result 52 states and 59 transitions. [2018-12-09 04:30:53,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 04:30:53,922 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 12 [2018-12-09 04:30:53,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:53,922 INFO L225 Difference]: With dead ends: 52 [2018-12-09 04:30:53,922 INFO L226 Difference]: Without dead ends: 52 [2018-12-09 04:30:53,923 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 04:30:53,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-12-09 04:30:53,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2018-12-09 04:30:53,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-12-09 04:30:53,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 59 transitions. [2018-12-09 04:30:53,928 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 59 transitions. Word has length 12 [2018-12-09 04:30:53,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:53,928 INFO L480 AbstractCegarLoop]: Abstraction has 52 states and 59 transitions. [2018-12-09 04:30:53,928 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 04:30:53,928 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 59 transitions. [2018-12-09 04:30:53,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-09 04:30:53,929 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:53,929 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:53,929 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:53,929 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:53,929 INFO L82 PathProgramCache]: Analyzing trace with hash 863296134, now seen corresponding path program 1 times [2018-12-09 04:30:53,929 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:53,929 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:53,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:53,930 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:53,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:53,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 04:30:54,006 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 04:30:54,006 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 04:30:54,007 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-09 04:30:54,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-09 04:30:54,007 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-12-09 04:30:54,007 INFO L87 Difference]: Start difference. First operand 52 states and 59 transitions. Second operand 7 states. [2018-12-09 04:30:54,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:54,098 INFO L93 Difference]: Finished difference Result 59 states and 64 transitions. [2018-12-09 04:30:54,098 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 04:30:54,099 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 12 [2018-12-09 04:30:54,099 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:54,099 INFO L225 Difference]: With dead ends: 59 [2018-12-09 04:30:54,099 INFO L226 Difference]: Without dead ends: 59 [2018-12-09 04:30:54,099 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-12-09 04:30:54,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-12-09 04:30:54,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 52. [2018-12-09 04:30:54,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-12-09 04:30:54,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 58 transitions. [2018-12-09 04:30:54,102 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 58 transitions. Word has length 12 [2018-12-09 04:30:54,102 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:54,102 INFO L480 AbstractCegarLoop]: Abstraction has 52 states and 58 transitions. [2018-12-09 04:30:54,102 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-09 04:30:54,102 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 58 transitions. [2018-12-09 04:30:54,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-12-09 04:30:54,102 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:54,102 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:54,103 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:54,103 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:54,103 INFO L82 PathProgramCache]: Analyzing trace with hash 1623425863, now seen corresponding path program 1 times [2018-12-09 04:30:54,103 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:54,103 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:54,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,179 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 04:30:54,180 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:54,180 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:54,186 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:54,234 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 04:30:54,248 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:54,248 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 3] total 9 [2018-12-09 04:30:54,248 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-09 04:30:54,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-09 04:30:54,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-12-09 04:30:54,249 INFO L87 Difference]: Start difference. First operand 52 states and 58 transitions. Second operand 10 states. [2018-12-09 04:30:54,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:54,374 INFO L93 Difference]: Finished difference Result 88 states and 97 transitions. [2018-12-09 04:30:54,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-09 04:30:54,374 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 16 [2018-12-09 04:30:54,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:54,375 INFO L225 Difference]: With dead ends: 88 [2018-12-09 04:30:54,375 INFO L226 Difference]: Without dead ends: 88 [2018-12-09 04:30:54,375 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-12-09 04:30:54,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-12-09 04:30:54,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 61. [2018-12-09 04:30:54,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-12-09 04:30:54,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 68 transitions. [2018-12-09 04:30:54,379 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 68 transitions. Word has length 16 [2018-12-09 04:30:54,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:54,379 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 68 transitions. [2018-12-09 04:30:54,379 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-09 04:30:54,379 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 68 transitions. [2018-12-09 04:30:54,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-12-09 04:30:54,379 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:54,379 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:54,379 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:54,380 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:54,380 INFO L82 PathProgramCache]: Analyzing trace with hash 2121234189, now seen corresponding path program 1 times [2018-12-09 04:30:54,380 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:54,380 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:54,380 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,380 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,380 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,434 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 04:30:54,434 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:54,434 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:54,440 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,449 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:54,484 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 04:30:54,498 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:54,498 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2018-12-09 04:30:54,499 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-09 04:30:54,499 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-09 04:30:54,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-12-09 04:30:54,499 INFO L87 Difference]: Start difference. First operand 61 states and 68 transitions. Second operand 10 states. [2018-12-09 04:30:54,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:54,656 INFO L93 Difference]: Finished difference Result 93 states and 98 transitions. [2018-12-09 04:30:54,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-09 04:30:54,656 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 20 [2018-12-09 04:30:54,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:54,657 INFO L225 Difference]: With dead ends: 93 [2018-12-09 04:30:54,657 INFO L226 Difference]: Without dead ends: 84 [2018-12-09 04:30:54,657 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=132, Unknown=0, NotChecked=0, Total=182 [2018-12-09 04:30:54,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-12-09 04:30:54,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 66. [2018-12-09 04:30:54,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-12-09 04:30:54,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 71 transitions. [2018-12-09 04:30:54,660 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 71 transitions. Word has length 20 [2018-12-09 04:30:54,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:54,660 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 71 transitions. [2018-12-09 04:30:54,660 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-09 04:30:54,660 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 71 transitions. [2018-12-09 04:30:54,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-09 04:30:54,661 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:54,661 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:54,661 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:54,661 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:54,661 INFO L82 PathProgramCache]: Analyzing trace with hash -523456178, now seen corresponding path program 2 times [2018-12-09 04:30:54,661 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:54,662 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:54,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,662 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,690 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 04:30:54,690 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 04:30:54,690 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-09 04:30:54,690 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 04:30:54,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 04:30:54,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 04:30:54,691 INFO L87 Difference]: Start difference. First operand 66 states and 71 transitions. Second operand 3 states. [2018-12-09 04:30:54,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:54,699 INFO L93 Difference]: Finished difference Result 64 states and 69 transitions. [2018-12-09 04:30:54,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 04:30:54,700 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-12-09 04:30:54,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:54,700 INFO L225 Difference]: With dead ends: 64 [2018-12-09 04:30:54,700 INFO L226 Difference]: Without dead ends: 64 [2018-12-09 04:30:54,700 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 04:30:54,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-12-09 04:30:54,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64. [2018-12-09 04:30:54,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-12-09 04:30:54,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 69 transitions. [2018-12-09 04:30:54,705 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 69 transitions. Word has length 25 [2018-12-09 04:30:54,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:54,705 INFO L480 AbstractCegarLoop]: Abstraction has 64 states and 69 transitions. [2018-12-09 04:30:54,705 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 04:30:54,705 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 69 transitions. [2018-12-09 04:30:54,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-09 04:30:54,706 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:54,706 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:54,706 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:54,706 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:54,706 INFO L82 PathProgramCache]: Analyzing trace with hash -523456177, now seen corresponding path program 1 times [2018-12-09 04:30:54,707 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:54,707 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:54,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,707 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:30:54,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,740 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 04:30:54,740 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 04:30:54,740 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-09 04:30:54,740 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 04:30:54,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 04:30:54,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 04:30:54,741 INFO L87 Difference]: Start difference. First operand 64 states and 69 transitions. Second operand 3 states. [2018-12-09 04:30:54,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:54,762 INFO L93 Difference]: Finished difference Result 68 states and 73 transitions. [2018-12-09 04:30:54,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 04:30:54,762 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-12-09 04:30:54,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:54,763 INFO L225 Difference]: With dead ends: 68 [2018-12-09 04:30:54,763 INFO L226 Difference]: Without dead ends: 68 [2018-12-09 04:30:54,763 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 04:30:54,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-12-09 04:30:54,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 66. [2018-12-09 04:30:54,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-12-09 04:30:54,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 71 transitions. [2018-12-09 04:30:54,765 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 71 transitions. Word has length 25 [2018-12-09 04:30:54,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:54,765 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 71 transitions. [2018-12-09 04:30:54,766 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 04:30:54,766 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 71 transitions. [2018-12-09 04:30:54,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-12-09 04:30:54,766 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:54,766 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:54,766 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:54,766 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:54,766 INFO L82 PathProgramCache]: Analyzing trace with hash 2020089664, now seen corresponding path program 1 times [2018-12-09 04:30:54,766 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:54,766 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:54,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,787 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 04:30:54,787 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:54,788 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:54,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,804 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:54,815 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 04:30:54,829 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:54,829 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-12-09 04:30:54,829 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 04:30:54,829 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 04:30:54,829 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-12-09 04:30:54,829 INFO L87 Difference]: Start difference. First operand 66 states and 71 transitions. Second operand 5 states. [2018-12-09 04:30:54,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:54,859 INFO L93 Difference]: Finished difference Result 90 states and 96 transitions. [2018-12-09 04:30:54,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 04:30:54,860 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2018-12-09 04:30:54,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:54,860 INFO L225 Difference]: With dead ends: 90 [2018-12-09 04:30:54,860 INFO L226 Difference]: Without dead ends: 90 [2018-12-09 04:30:54,860 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-12-09 04:30:54,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-12-09 04:30:54,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 73. [2018-12-09 04:30:54,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-12-09 04:30:54,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 80 transitions. [2018-12-09 04:30:54,863 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 80 transitions. Word has length 31 [2018-12-09 04:30:54,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:54,863 INFO L480 AbstractCegarLoop]: Abstraction has 73 states and 80 transitions. [2018-12-09 04:30:54,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 04:30:54,864 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 80 transitions. [2018-12-09 04:30:54,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 04:30:54,864 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:54,864 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:54,865 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:54,865 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:54,865 INFO L82 PathProgramCache]: Analyzing trace with hash -1860847279, now seen corresponding path program 1 times [2018-12-09 04:30:54,865 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:54,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:54,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,866 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:54,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,913 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 30 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 04:30:54,913 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:54,913 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:54,919 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:54,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:54,932 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:54,977 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 04:30:54,991 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:54,992 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 12 [2018-12-09 04:30:54,992 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-09 04:30:54,992 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-09 04:30:54,992 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-12-09 04:30:54,992 INFO L87 Difference]: Start difference. First operand 73 states and 80 transitions. Second operand 12 states. [2018-12-09 04:30:55,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:55,137 INFO L93 Difference]: Finished difference Result 94 states and 99 transitions. [2018-12-09 04:30:55,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-09 04:30:55,138 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 46 [2018-12-09 04:30:55,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:55,138 INFO L225 Difference]: With dead ends: 94 [2018-12-09 04:30:55,138 INFO L226 Difference]: Without dead ends: 91 [2018-12-09 04:30:55,138 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=87, Invalid=219, Unknown=0, NotChecked=0, Total=306 [2018-12-09 04:30:55,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-12-09 04:30:55,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 73. [2018-12-09 04:30:55,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-12-09 04:30:55,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 79 transitions. [2018-12-09 04:30:55,140 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 79 transitions. Word has length 46 [2018-12-09 04:30:55,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:55,141 INFO L480 AbstractCegarLoop]: Abstraction has 73 states and 79 transitions. [2018-12-09 04:30:55,141 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-09 04:30:55,141 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 79 transitions. [2018-12-09 04:30:55,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-12-09 04:30:55,141 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:55,141 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:55,142 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:55,142 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:55,142 INFO L82 PathProgramCache]: Analyzing trace with hash 1288534185, now seen corresponding path program 1 times [2018-12-09 04:30:55,142 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:55,142 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:55,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:55,142 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:55,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:55,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:55,200 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 60 proven. 7 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 04:30:55,201 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:55,201 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:55,207 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:55,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:55,221 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:55,267 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 65 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 04:30:55,281 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:55,281 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 15 [2018-12-09 04:30:55,281 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-09 04:30:55,281 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-09 04:30:55,281 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-12-09 04:30:55,282 INFO L87 Difference]: Start difference. First operand 73 states and 79 transitions. Second operand 15 states. [2018-12-09 04:30:55,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:55,395 INFO L93 Difference]: Finished difference Result 118 states and 122 transitions. [2018-12-09 04:30:55,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-09 04:30:55,395 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 48 [2018-12-09 04:30:55,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:55,396 INFO L225 Difference]: With dead ends: 118 [2018-12-09 04:30:55,396 INFO L226 Difference]: Without dead ends: 118 [2018-12-09 04:30:55,396 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=113, Invalid=267, Unknown=0, NotChecked=0, Total=380 [2018-12-09 04:30:55,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-12-09 04:30:55,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 99. [2018-12-09 04:30:55,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-12-09 04:30:55,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 105 transitions. [2018-12-09 04:30:55,399 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 105 transitions. Word has length 48 [2018-12-09 04:30:55,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:55,399 INFO L480 AbstractCegarLoop]: Abstraction has 99 states and 105 transitions. [2018-12-09 04:30:55,399 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-09 04:30:55,399 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 105 transitions. [2018-12-09 04:30:55,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-12-09 04:30:55,400 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:55,400 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:55,400 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:55,400 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:55,400 INFO L82 PathProgramCache]: Analyzing trace with hash -1743494932, now seen corresponding path program 2 times [2018-12-09 04:30:55,400 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:55,400 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:55,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:55,401 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:30:55,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:55,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:55,448 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-09 04:30:55,448 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:55,448 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:55,456 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:30:55,471 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:30:55,471 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:30:55,473 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:55,496 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-12-09 04:30:55,496 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-12-09 04:30:55,508 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:30:55,510 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:30:55,510 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-12-09 04:30:55,511 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-09 04:30:55,514 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-09 04:30:55,520 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-12-09 04:30:55,520 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-12-09 04:30:55,602 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-09 04:30:55,616 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:55,617 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 7 [2018-12-09 04:30:55,617 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-09 04:30:55,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-09 04:30:55,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-09 04:30:55,617 INFO L87 Difference]: Start difference. First operand 99 states and 105 transitions. Second operand 8 states. [2018-12-09 04:30:55,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:55,711 INFO L93 Difference]: Finished difference Result 103 states and 109 transitions. [2018-12-09 04:30:55,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 04:30:55,711 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-12-09 04:30:55,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:55,712 INFO L225 Difference]: With dead ends: 103 [2018-12-09 04:30:55,712 INFO L226 Difference]: Without dead ends: 103 [2018-12-09 04:30:55,712 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 45 SyntacticMatches, 4 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-12-09 04:30:55,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-12-09 04:30:55,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 101. [2018-12-09 04:30:55,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-12-09 04:30:55,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 107 transitions. [2018-12-09 04:30:55,714 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 107 transitions. Word has length 51 [2018-12-09 04:30:55,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:55,715 INFO L480 AbstractCegarLoop]: Abstraction has 101 states and 107 transitions. [2018-12-09 04:30:55,715 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-09 04:30:55,715 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 107 transitions. [2018-12-09 04:30:55,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-12-09 04:30:55,715 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:55,716 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:55,716 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:55,716 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:55,716 INFO L82 PathProgramCache]: Analyzing trace with hash 841147677, now seen corresponding path program 2 times [2018-12-09 04:30:55,716 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:55,716 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:55,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:55,717 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:30:55,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:55,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:55,820 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 39 proven. 19 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 04:30:55,820 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:55,820 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:55,826 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:30:55,832 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-12-09 04:30:55,833 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:30:55,834 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:55,846 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-12-09 04:30:55,846 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-12-09 04:30:55,850 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:30:55,852 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:30:55,853 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-12-09 04:30:55,853 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-09 04:30:55,857 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-09 04:30:55,861 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-12-09 04:30:55,861 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2018-12-09 04:30:55,988 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-12-09 04:30:56,003 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 04:30:56,003 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [10] total 14 [2018-12-09 04:30:56,004 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-09 04:30:56,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-09 04:30:56,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2018-12-09 04:30:56,004 INFO L87 Difference]: Start difference. First operand 101 states and 107 transitions. Second operand 14 states. [2018-12-09 04:30:56,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:56,198 INFO L93 Difference]: Finished difference Result 85 states and 87 transitions. [2018-12-09 04:30:56,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-12-09 04:30:56,198 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2018-12-09 04:30:56,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:56,199 INFO L225 Difference]: With dead ends: 85 [2018-12-09 04:30:56,199 INFO L226 Difference]: Without dead ends: 85 [2018-12-09 04:30:56,199 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 52 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=92, Invalid=328, Unknown=0, NotChecked=0, Total=420 [2018-12-09 04:30:56,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-12-09 04:30:56,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 83. [2018-12-09 04:30:56,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-12-09 04:30:56,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 85 transitions. [2018-12-09 04:30:56,200 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 85 transitions. Word has length 57 [2018-12-09 04:30:56,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:56,201 INFO L480 AbstractCegarLoop]: Abstraction has 83 states and 85 transitions. [2018-12-09 04:30:56,201 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-09 04:30:56,201 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 85 transitions. [2018-12-09 04:30:56,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-12-09 04:30:56,201 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:56,202 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:56,202 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:56,202 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:56,202 INFO L82 PathProgramCache]: Analyzing trace with hash -213546900, now seen corresponding path program 2 times [2018-12-09 04:30:56,202 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:56,202 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:56,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:56,202 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:30:56,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:56,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:56,287 INFO L134 CoverageAnalysis]: Checked inductivity of 199 backedges. 100 proven. 24 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-12-09 04:30:56,287 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:56,287 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:56,293 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:30:56,308 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:30:56,308 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:30:56,310 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:56,313 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:30:56,321 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:30:56,336 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:30:56,337 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:30:56,342 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:30:56,349 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:30:56,349 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:30:56,443 INFO L134 CoverageAnalysis]: Checked inductivity of 199 backedges. 100 proven. 16 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2018-12-09 04:30:56,457 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:56,457 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9] total 14 [2018-12-09 04:30:56,458 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-09 04:30:56,458 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-09 04:30:56,458 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=156, Unknown=0, NotChecked=0, Total=210 [2018-12-09 04:30:56,458 INFO L87 Difference]: Start difference. First operand 83 states and 85 transitions. Second operand 15 states. [2018-12-09 04:30:56,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:56,715 INFO L93 Difference]: Finished difference Result 135 states and 140 transitions. [2018-12-09 04:30:56,715 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-09 04:30:56,715 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 74 [2018-12-09 04:30:56,716 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:56,716 INFO L225 Difference]: With dead ends: 135 [2018-12-09 04:30:56,716 INFO L226 Difference]: Without dead ends: 135 [2018-12-09 04:30:56,717 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 64 SyntacticMatches, 4 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=178, Invalid=472, Unknown=0, NotChecked=0, Total=650 [2018-12-09 04:30:56,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-12-09 04:30:56,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 114. [2018-12-09 04:30:56,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-12-09 04:30:56,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 118 transitions. [2018-12-09 04:30:56,721 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 118 transitions. Word has length 74 [2018-12-09 04:30:56,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:56,721 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 118 transitions. [2018-12-09 04:30:56,721 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-09 04:30:56,721 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 118 transitions. [2018-12-09 04:30:56,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-09 04:30:56,722 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:56,722 INFO L402 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:56,722 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:56,723 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:56,723 INFO L82 PathProgramCache]: Analyzing trace with hash 868331390, now seen corresponding path program 3 times [2018-12-09 04:30:56,723 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:56,723 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:56,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:56,723 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:30:56,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:56,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:56,828 INFO L134 CoverageAnalysis]: Checked inductivity of 447 backedges. 306 proven. 87 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-12-09 04:30:56,829 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:56,829 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:56,835 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:30:56,858 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-12-09 04:30:56,859 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:30:56,862 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:56,865 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:30:56,867 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:30:56,872 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:30:56,873 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:30:56,878 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:30:56,885 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:30:56,885 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:30:57,082 INFO L134 CoverageAnalysis]: Checked inductivity of 447 backedges. 202 proven. 32 refuted. 0 times theorem prover too weak. 213 trivial. 0 not checked. [2018-12-09 04:30:57,097 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:57,097 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 10] total 23 [2018-12-09 04:30:57,097 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-12-09 04:30:57,097 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-12-09 04:30:57,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=438, Unknown=0, NotChecked=0, Total=506 [2018-12-09 04:30:57,097 INFO L87 Difference]: Start difference. First operand 114 states and 118 transitions. Second operand 23 states. [2018-12-09 04:30:57,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:57,890 INFO L93 Difference]: Finished difference Result 186 states and 191 transitions. [2018-12-09 04:30:57,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-09 04:30:57,890 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 105 [2018-12-09 04:30:57,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:57,891 INFO L225 Difference]: With dead ends: 186 [2018-12-09 04:30:57,891 INFO L226 Difference]: Without dead ends: 169 [2018-12-09 04:30:57,892 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 93 SyntacticMatches, 5 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 468 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=399, Invalid=1857, Unknown=0, NotChecked=0, Total=2256 [2018-12-09 04:30:57,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-12-09 04:30:57,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 145. [2018-12-09 04:30:57,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-12-09 04:30:57,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 148 transitions. [2018-12-09 04:30:57,896 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 148 transitions. Word has length 105 [2018-12-09 04:30:57,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:57,896 INFO L480 AbstractCegarLoop]: Abstraction has 145 states and 148 transitions. [2018-12-09 04:30:57,897 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-12-09 04:30:57,897 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 148 transitions. [2018-12-09 04:30:57,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 04:30:57,898 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:57,898 INFO L402 BasicCegarLoop]: trace histogram [18, 18, 17, 17, 17, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:57,898 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:57,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:57,899 INFO L82 PathProgramCache]: Analyzing trace with hash 1319679649, now seen corresponding path program 4 times [2018-12-09 04:30:57,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:57,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:57,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:57,900 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:30:57,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:57,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:58,042 INFO L134 CoverageAnalysis]: Checked inductivity of 881 backedges. 612 proven. 147 refuted. 0 times theorem prover too weak. 122 trivial. 0 not checked. [2018-12-09 04:30:58,043 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:58,043 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:58,048 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:30:58,072 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:30:58,072 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:30:58,074 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:58,178 INFO L134 CoverageAnalysis]: Checked inductivity of 881 backedges. 531 proven. 179 refuted. 0 times theorem prover too weak. 171 trivial. 0 not checked. [2018-12-09 04:30:58,193 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:58,193 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15] total 26 [2018-12-09 04:30:58,193 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-12-09 04:30:58,194 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-12-09 04:30:58,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=543, Unknown=0, NotChecked=0, Total=650 [2018-12-09 04:30:58,194 INFO L87 Difference]: Start difference. First operand 145 states and 148 transitions. Second operand 26 states. [2018-12-09 04:30:58,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:58,559 INFO L93 Difference]: Finished difference Result 180 states and 184 transitions. [2018-12-09 04:30:58,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-12-09 04:30:58,559 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 141 [2018-12-09 04:30:58,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:58,560 INFO L225 Difference]: With dead ends: 180 [2018-12-09 04:30:58,560 INFO L226 Difference]: Without dead ends: 174 [2018-12-09 04:30:58,561 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 134 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 301 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=313, Invalid=1169, Unknown=0, NotChecked=0, Total=1482 [2018-12-09 04:30:58,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-12-09 04:30:58,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 153. [2018-12-09 04:30:58,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-12-09 04:30:58,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 156 transitions. [2018-12-09 04:30:58,563 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 156 transitions. Word has length 141 [2018-12-09 04:30:58,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:58,563 INFO L480 AbstractCegarLoop]: Abstraction has 153 states and 156 transitions. [2018-12-09 04:30:58,563 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-12-09 04:30:58,563 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 156 transitions. [2018-12-09 04:30:58,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-12-09 04:30:58,564 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:58,564 INFO L402 BasicCegarLoop]: trace histogram [19, 19, 18, 18, 18, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:58,564 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:58,564 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:58,564 INFO L82 PathProgramCache]: Analyzing trace with hash -2005233562, now seen corresponding path program 5 times [2018-12-09 04:30:58,564 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:58,564 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:58,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:58,565 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:30:58,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:58,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:58,705 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 346 proven. 42 refuted. 0 times theorem prover too weak. 585 trivial. 0 not checked. [2018-12-09 04:30:58,705 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:58,705 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:58,712 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:30:58,759 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-12-09 04:30:58,760 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:30:58,764 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:58,767 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:30:58,769 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:30:58,778 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:30:58,778 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:30:58,787 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:30:58,795 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:30:58,795 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:30:58,926 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 346 proven. 42 refuted. 0 times theorem prover too weak. 585 trivial. 0 not checked. [2018-12-09 04:30:58,941 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:58,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10] total 15 [2018-12-09 04:30:58,941 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-12-09 04:30:58,941 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-12-09 04:30:58,941 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=167, Unknown=0, NotChecked=0, Total=240 [2018-12-09 04:30:58,941 INFO L87 Difference]: Start difference. First operand 153 states and 156 transitions. Second operand 16 states. [2018-12-09 04:30:59,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:30:59,105 INFO L93 Difference]: Finished difference Result 173 states and 177 transitions. [2018-12-09 04:30:59,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-09 04:30:59,106 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 146 [2018-12-09 04:30:59,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:30:59,106 INFO L225 Difference]: With dead ends: 173 [2018-12-09 04:30:59,106 INFO L226 Difference]: Without dead ends: 173 [2018-12-09 04:30:59,107 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 159 GetRequests, 130 SyntacticMatches, 10 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 99 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=302, Unknown=0, NotChecked=0, Total=420 [2018-12-09 04:30:59,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-12-09 04:30:59,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 155. [2018-12-09 04:30:59,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-12-09 04:30:59,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 158 transitions. [2018-12-09 04:30:59,109 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 158 transitions. Word has length 146 [2018-12-09 04:30:59,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:30:59,109 INFO L480 AbstractCegarLoop]: Abstraction has 155 states and 158 transitions. [2018-12-09 04:30:59,109 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-12-09 04:30:59,109 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 158 transitions. [2018-12-09 04:30:59,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-12-09 04:30:59,110 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:30:59,110 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 19, 19, 19, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:30:59,110 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:30:59,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:30:59,110 INFO L82 PathProgramCache]: Analyzing trace with hash 422435815, now seen corresponding path program 6 times [2018-12-09 04:30:59,111 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:30:59,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:30:59,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:59,111 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:30:59,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:30:59,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:30:59,236 INFO L134 CoverageAnalysis]: Checked inductivity of 1070 backedges. 420 proven. 65 refuted. 0 times theorem prover too weak. 585 trivial. 0 not checked. [2018-12-09 04:30:59,236 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:30:59,236 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:30:59,242 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:30:59,274 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-12-09 04:30:59,274 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:30:59,277 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:30:59,279 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:30:59,281 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:30:59,289 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:30:59,289 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:30:59,294 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:30:59,300 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:30:59,300 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:30:59,472 INFO L134 CoverageAnalysis]: Checked inductivity of 1070 backedges. 420 proven. 54 refuted. 0 times theorem prover too weak. 596 trivial. 0 not checked. [2018-12-09 04:30:59,486 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:30:59,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 18 [2018-12-09 04:30:59,486 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-12-09 04:30:59,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-12-09 04:30:59,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=258, Unknown=0, NotChecked=0, Total=342 [2018-12-09 04:30:59,487 INFO L87 Difference]: Start difference. First operand 155 states and 158 transitions. Second operand 19 states. [2018-12-09 04:31:00,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:00,092 INFO L93 Difference]: Finished difference Result 240 states and 249 transitions. [2018-12-09 04:31:00,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-12-09 04:31:00,093 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 151 [2018-12-09 04:31:00,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:00,095 INFO L225 Difference]: With dead ends: 240 [2018-12-09 04:31:00,095 INFO L226 Difference]: Without dead ends: 240 [2018-12-09 04:31:00,096 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 135 SyntacticMatches, 8 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 335 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=289, Invalid=833, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 04:31:00,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-12-09 04:31:00,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 196. [2018-12-09 04:31:00,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 196 states. [2018-12-09 04:31:00,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 201 transitions. [2018-12-09 04:31:00,102 INFO L78 Accepts]: Start accepts. Automaton has 196 states and 201 transitions. Word has length 151 [2018-12-09 04:31:00,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:00,103 INFO L480 AbstractCegarLoop]: Abstraction has 196 states and 201 transitions. [2018-12-09 04:31:00,103 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-12-09 04:31:00,103 INFO L276 IsEmpty]: Start isEmpty. Operand 196 states and 201 transitions. [2018-12-09 04:31:00,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 193 [2018-12-09 04:31:00,105 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:00,105 INFO L402 BasicCegarLoop]: trace histogram [26, 26, 25, 25, 25, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:00,106 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:00,106 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:00,106 INFO L82 PathProgramCache]: Analyzing trace with hash -92189437, now seen corresponding path program 7 times [2018-12-09 04:31:00,106 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:00,107 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:00,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:00,108 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:00,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:00,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:00,234 INFO L134 CoverageAnalysis]: Checked inductivity of 1830 backedges. 1091 proven. 314 refuted. 0 times theorem prover too weak. 425 trivial. 0 not checked. [2018-12-09 04:31:00,234 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:00,234 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:00,242 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:00,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:00,280 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:00,378 INFO L134 CoverageAnalysis]: Checked inductivity of 1830 backedges. 1137 proven. 55 refuted. 0 times theorem prover too weak. 638 trivial. 0 not checked. [2018-12-09 04:31:00,393 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:00,393 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 14] total 25 [2018-12-09 04:31:00,393 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-12-09 04:31:00,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-12-09 04:31:00,394 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=484, Unknown=0, NotChecked=0, Total=600 [2018-12-09 04:31:00,394 INFO L87 Difference]: Start difference. First operand 196 states and 201 transitions. Second operand 25 states. [2018-12-09 04:31:00,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:00,701 INFO L93 Difference]: Finished difference Result 245 states and 252 transitions. [2018-12-09 04:31:00,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-12-09 04:31:00,702 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 192 [2018-12-09 04:31:00,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:00,702 INFO L225 Difference]: With dead ends: 245 [2018-12-09 04:31:00,702 INFO L226 Difference]: Without dead ends: 239 [2018-12-09 04:31:00,703 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 187 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 321 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=326, Invalid=1156, Unknown=0, NotChecked=0, Total=1482 [2018-12-09 04:31:00,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-12-09 04:31:00,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 201. [2018-12-09 04:31:00,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2018-12-09 04:31:00,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 205 transitions. [2018-12-09 04:31:00,707 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 205 transitions. Word has length 192 [2018-12-09 04:31:00,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:00,707 INFO L480 AbstractCegarLoop]: Abstraction has 201 states and 205 transitions. [2018-12-09 04:31:00,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-12-09 04:31:00,707 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 205 transitions. [2018-12-09 04:31:00,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-12-09 04:31:00,708 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:00,708 INFO L402 BasicCegarLoop]: trace histogram [27, 27, 26, 26, 26, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:00,708 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:00,709 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:00,709 INFO L82 PathProgramCache]: Analyzing trace with hash 1169596100, now seen corresponding path program 8 times [2018-12-09 04:31:00,709 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:00,709 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:00,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:00,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:00,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:00,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:00,921 INFO L134 CoverageAnalysis]: Checked inductivity of 1963 backedges. 700 proven. 93 refuted. 0 times theorem prover too weak. 1170 trivial. 0 not checked. [2018-12-09 04:31:00,922 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:00,922 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:00,933 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:31:00,972 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:31:00,972 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:00,976 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:00,979 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:00,982 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:00,990 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:00,990 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:00,998 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:01,008 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:01,008 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:31:01,216 INFO L134 CoverageAnalysis]: Checked inductivity of 1963 backedges. 700 proven. 82 refuted. 0 times theorem prover too weak. 1181 trivial. 0 not checked. [2018-12-09 04:31:01,231 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:01,231 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 20 [2018-12-09 04:31:01,231 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-12-09 04:31:01,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-12-09 04:31:01,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=318, Unknown=0, NotChecked=0, Total=420 [2018-12-09 04:31:01,232 INFO L87 Difference]: Start difference. First operand 201 states and 205 transitions. Second operand 21 states. [2018-12-09 04:31:01,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:01,663 INFO L93 Difference]: Finished difference Result 316 states and 329 transitions. [2018-12-09 04:31:01,663 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-09 04:31:01,663 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 197 [2018-12-09 04:31:01,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:01,664 INFO L225 Difference]: With dead ends: 316 [2018-12-09 04:31:01,664 INFO L226 Difference]: Without dead ends: 316 [2018-12-09 04:31:01,664 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 178 SyntacticMatches, 10 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 442 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=355, Invalid=1051, Unknown=0, NotChecked=0, Total=1406 [2018-12-09 04:31:01,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 316 states. [2018-12-09 04:31:01,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 316 to 247. [2018-12-09 04:31:01,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 247 states. [2018-12-09 04:31:01,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 253 transitions. [2018-12-09 04:31:01,667 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 253 transitions. Word has length 197 [2018-12-09 04:31:01,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:01,668 INFO L480 AbstractCegarLoop]: Abstraction has 247 states and 253 transitions. [2018-12-09 04:31:01,668 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-12-09 04:31:01,668 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 253 transitions. [2018-12-09 04:31:01,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 244 [2018-12-09 04:31:01,668 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:01,668 INFO L402 BasicCegarLoop]: trace histogram [34, 34, 33, 33, 33, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:01,669 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:01,669 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:01,669 INFO L82 PathProgramCache]: Analyzing trace with hash 1339933063, now seen corresponding path program 9 times [2018-12-09 04:31:01,669 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:01,669 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:01,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:01,669 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:01,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:01,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:01,842 INFO L134 CoverageAnalysis]: Checked inductivity of 3126 backedges. 1042 proven. 126 refuted. 0 times theorem prover too weak. 1958 trivial. 0 not checked. [2018-12-09 04:31:01,842 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:01,842 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:01,848 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:31:01,891 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-12-09 04:31:01,891 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:01,894 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:02,117 INFO L134 CoverageAnalysis]: Checked inductivity of 3126 backedges. 1646 proven. 305 refuted. 0 times theorem prover too weak. 1175 trivial. 0 not checked. [2018-12-09 04:31:02,132 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:02,132 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 21] total 32 [2018-12-09 04:31:02,132 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 04:31:02,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 04:31:02,133 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=142, Invalid=850, Unknown=0, NotChecked=0, Total=992 [2018-12-09 04:31:02,133 INFO L87 Difference]: Start difference. First operand 247 states and 253 transitions. Second operand 32 states. [2018-12-09 04:31:03,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:03,070 INFO L93 Difference]: Finished difference Result 563 states and 584 transitions. [2018-12-09 04:31:03,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-12-09 04:31:03,071 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 243 [2018-12-09 04:31:03,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:03,072 INFO L225 Difference]: With dead ends: 563 [2018-12-09 04:31:03,072 INFO L226 Difference]: Without dead ends: 563 [2018-12-09 04:31:03,072 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 224 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 849 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=728, Invalid=3054, Unknown=0, NotChecked=0, Total=3782 [2018-12-09 04:31:03,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 563 states. [2018-12-09 04:31:03,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 563 to 449. [2018-12-09 04:31:03,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-12-09 04:31:03,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 466 transitions. [2018-12-09 04:31:03,079 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 466 transitions. Word has length 243 [2018-12-09 04:31:03,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:03,079 INFO L480 AbstractCegarLoop]: Abstraction has 449 states and 466 transitions. [2018-12-09 04:31:03,079 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 04:31:03,079 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 466 transitions. [2018-12-09 04:31:03,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 254 [2018-12-09 04:31:03,080 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:03,080 INFO L402 BasicCegarLoop]: trace histogram [36, 36, 35, 35, 35, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:03,080 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:03,080 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:03,080 INFO L82 PathProgramCache]: Analyzing trace with hash -65711679, now seen corresponding path program 10 times [2018-12-09 04:31:03,080 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:03,080 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:03,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:03,081 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:03,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:03,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:03,310 INFO L134 CoverageAnalysis]: Checked inductivity of 3479 backedges. 1221 proven. 164 refuted. 0 times theorem prover too weak. 2094 trivial. 0 not checked. [2018-12-09 04:31:03,310 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:03,310 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:03,315 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:31:03,350 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:31:03,350 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:03,353 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:03,585 INFO L134 CoverageAnalysis]: Checked inductivity of 3479 backedges. 1306 proven. 493 refuted. 0 times theorem prover too weak. 1680 trivial. 0 not checked. [2018-12-09 04:31:03,609 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:03,609 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 23] total 35 [2018-12-09 04:31:03,609 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-09 04:31:03,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-09 04:31:03,610 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=1024, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 04:31:03,610 INFO L87 Difference]: Start difference. First operand 449 states and 466 transitions. Second operand 35 states. [2018-12-09 04:31:04,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:04,746 INFO L93 Difference]: Finished difference Result 618 states and 641 transitions. [2018-12-09 04:31:04,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-12-09 04:31:04,747 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 253 [2018-12-09 04:31:04,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:04,749 INFO L225 Difference]: With dead ends: 618 [2018-12-09 04:31:04,749 INFO L226 Difference]: Without dead ends: 618 [2018-12-09 04:31:04,749 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1061 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=714, Invalid=3842, Unknown=0, NotChecked=0, Total=4556 [2018-12-09 04:31:04,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 618 states. [2018-12-09 04:31:04,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 618 to 578. [2018-12-09 04:31:04,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 578 states. [2018-12-09 04:31:04,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 578 states to 578 states and 601 transitions. [2018-12-09 04:31:04,759 INFO L78 Accepts]: Start accepts. Automaton has 578 states and 601 transitions. Word has length 253 [2018-12-09 04:31:04,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:04,759 INFO L480 AbstractCegarLoop]: Abstraction has 578 states and 601 transitions. [2018-12-09 04:31:04,759 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-09 04:31:04,759 INFO L276 IsEmpty]: Start isEmpty. Operand 578 states and 601 transitions. [2018-12-09 04:31:04,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 300 [2018-12-09 04:31:04,761 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:04,761 INFO L402 BasicCegarLoop]: trace histogram [43, 43, 42, 42, 42, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:04,762 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:04,762 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:04,762 INFO L82 PathProgramCache]: Analyzing trace with hash -1453092182, now seen corresponding path program 11 times [2018-12-09 04:31:04,762 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:04,762 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:04,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:04,762 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:04,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:04,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:04,954 INFO L134 CoverageAnalysis]: Checked inductivity of 4984 backedges. 2403 proven. 805 refuted. 0 times theorem prover too weak. 1776 trivial. 0 not checked. [2018-12-09 04:31:04,955 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:04,955 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:04,961 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:31:05,069 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-12-09 04:31:05,070 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:05,075 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:05,245 INFO L134 CoverageAnalysis]: Checked inductivity of 4984 backedges. 3067 proven. 456 refuted. 0 times theorem prover too weak. 1461 trivial. 0 not checked. [2018-12-09 04:31:05,261 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:05,261 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 30 [2018-12-09 04:31:05,261 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-09 04:31:05,261 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-09 04:31:05,261 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=158, Invalid=712, Unknown=0, NotChecked=0, Total=870 [2018-12-09 04:31:05,261 INFO L87 Difference]: Start difference. First operand 578 states and 601 transitions. Second operand 30 states. [2018-12-09 04:31:05,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:05,601 INFO L93 Difference]: Finished difference Result 535 states and 551 transitions. [2018-12-09 04:31:05,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-12-09 04:31:05,601 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 299 [2018-12-09 04:31:05,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:05,602 INFO L225 Difference]: With dead ends: 535 [2018-12-09 04:31:05,602 INFO L226 Difference]: Without dead ends: 523 [2018-12-09 04:31:05,603 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 335 GetRequests, 291 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 478 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=468, Invalid=1602, Unknown=0, NotChecked=0, Total=2070 [2018-12-09 04:31:05,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 523 states. [2018-12-09 04:31:05,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 523 to 511. [2018-12-09 04:31:05,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 511 states. [2018-12-09 04:31:05,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 511 states to 511 states and 527 transitions. [2018-12-09 04:31:05,611 INFO L78 Accepts]: Start accepts. Automaton has 511 states and 527 transitions. Word has length 299 [2018-12-09 04:31:05,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:05,612 INFO L480 AbstractCegarLoop]: Abstraction has 511 states and 527 transitions. [2018-12-09 04:31:05,612 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-09 04:31:05,612 INFO L276 IsEmpty]: Start isEmpty. Operand 511 states and 527 transitions. [2018-12-09 04:31:05,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 305 [2018-12-09 04:31:05,613 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:05,614 INFO L402 BasicCegarLoop]: trace histogram [44, 44, 43, 43, 43, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:05,614 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:05,614 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:05,614 INFO L82 PathProgramCache]: Analyzing trace with hash 1810634863, now seen corresponding path program 12 times [2018-12-09 04:31:05,614 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:05,614 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:05,615 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:05,615 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:05,615 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:05,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:05,821 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2809 proven. 625 refuted. 0 times theorem prover too weak. 1770 trivial. 0 not checked. [2018-12-09 04:31:05,821 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:05,821 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:05,827 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:31:05,945 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2018-12-09 04:31:05,945 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:05,951 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:05,954 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:05,956 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:05,969 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:05,970 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:05,978 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:05,987 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:05,987 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:31:06,564 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2414 proven. 504 refuted. 0 times theorem prover too weak. 2286 trivial. 0 not checked. [2018-12-09 04:31:06,579 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:06,579 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 17] total 38 [2018-12-09 04:31:06,579 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-12-09 04:31:06,579 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-12-09 04:31:06,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=1237, Unknown=0, NotChecked=0, Total=1406 [2018-12-09 04:31:06,580 INFO L87 Difference]: Start difference. First operand 511 states and 527 transitions. Second operand 38 states. [2018-12-09 04:31:10,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:10,056 INFO L93 Difference]: Finished difference Result 597 states and 613 transitions. [2018-12-09 04:31:10,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-12-09 04:31:10,056 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 304 [2018-12-09 04:31:10,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:10,058 INFO L225 Difference]: With dead ends: 597 [2018-12-09 04:31:10,058 INFO L226 Difference]: Without dead ends: 588 [2018-12-09 04:31:10,059 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 387 GetRequests, 277 SyntacticMatches, 13 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2852 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=1643, Invalid=8059, Unknown=0, NotChecked=0, Total=9702 [2018-12-09 04:31:10,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 588 states. [2018-12-09 04:31:10,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 588 to 562. [2018-12-09 04:31:10,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 562 states. [2018-12-09 04:31:10,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 562 states to 562 states and 577 transitions. [2018-12-09 04:31:10,068 INFO L78 Accepts]: Start accepts. Automaton has 562 states and 577 transitions. Word has length 304 [2018-12-09 04:31:10,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:10,068 INFO L480 AbstractCegarLoop]: Abstraction has 562 states and 577 transitions. [2018-12-09 04:31:10,068 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-12-09 04:31:10,068 INFO L276 IsEmpty]: Start isEmpty. Operand 562 states and 577 transitions. [2018-12-09 04:31:10,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-12-09 04:31:10,070 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:10,070 INFO L402 BasicCegarLoop]: trace histogram [53, 53, 52, 52, 52, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:10,071 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:10,071 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:10,071 INFO L82 PathProgramCache]: Analyzing trace with hash -48662420, now seen corresponding path program 13 times [2018-12-09 04:31:10,071 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:10,071 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:10,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:10,072 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:10,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:10,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:10,304 INFO L134 CoverageAnalysis]: Checked inductivity of 7542 backedges. 4691 proven. 537 refuted. 0 times theorem prover too weak. 2314 trivial. 0 not checked. [2018-12-09 04:31:10,305 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:10,305 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:10,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:10,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:10,372 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:10,585 INFO L134 CoverageAnalysis]: Checked inductivity of 7542 backedges. 3855 proven. 148 refuted. 0 times theorem prover too weak. 3539 trivial. 0 not checked. [2018-12-09 04:31:10,599 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:10,600 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 20] total 39 [2018-12-09 04:31:10,600 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-12-09 04:31:10,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-12-09 04:31:10,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=256, Invalid=1226, Unknown=0, NotChecked=0, Total=1482 [2018-12-09 04:31:10,600 INFO L87 Difference]: Start difference. First operand 562 states and 577 transitions. Second operand 39 states. [2018-12-09 04:31:11,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:11,380 INFO L93 Difference]: Finished difference Result 692 states and 706 transitions. [2018-12-09 04:31:11,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-12-09 04:31:11,381 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 360 [2018-12-09 04:31:11,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:11,382 INFO L225 Difference]: With dead ends: 692 [2018-12-09 04:31:11,382 INFO L226 Difference]: Without dead ends: 570 [2018-12-09 04:31:11,383 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 347 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1109 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=731, Invalid=3301, Unknown=0, NotChecked=0, Total=4032 [2018-12-09 04:31:11,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 570 states. [2018-12-09 04:31:11,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 570 to 399. [2018-12-09 04:31:11,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 399 states. [2018-12-09 04:31:11,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 399 states and 407 transitions. [2018-12-09 04:31:11,387 INFO L78 Accepts]: Start accepts. Automaton has 399 states and 407 transitions. Word has length 360 [2018-12-09 04:31:11,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:11,388 INFO L480 AbstractCegarLoop]: Abstraction has 399 states and 407 transitions. [2018-12-09 04:31:11,388 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-12-09 04:31:11,388 INFO L276 IsEmpty]: Start isEmpty. Operand 399 states and 407 transitions. [2018-12-09 04:31:11,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 366 [2018-12-09 04:31:11,389 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:11,389 INFO L402 BasicCegarLoop]: trace histogram [54, 54, 53, 53, 53, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:11,389 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:11,390 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:11,390 INFO L82 PathProgramCache]: Analyzing trace with hash -62569721, now seen corresponding path program 14 times [2018-12-09 04:31:11,390 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:11,390 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:11,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:11,390 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:11,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:11,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:11,675 INFO L134 CoverageAnalysis]: Checked inductivity of 7813 backedges. 2200 proven. 207 refuted. 0 times theorem prover too weak. 5406 trivial. 0 not checked. [2018-12-09 04:31:11,675 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:11,675 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:11,681 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:31:11,748 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:31:11,748 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:11,752 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:11,754 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:11,756 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:11,760 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:11,760 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:11,769 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:11,776 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:11,777 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:31:12,216 INFO L134 CoverageAnalysis]: Checked inductivity of 7813 backedges. 2200 proven. 202 refuted. 0 times theorem prover too weak. 5411 trivial. 0 not checked. [2018-12-09 04:31:12,231 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:12,231 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 26 [2018-12-09 04:31:12,231 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-09 04:31:12,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-09 04:31:12,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=534, Unknown=0, NotChecked=0, Total=702 [2018-12-09 04:31:12,232 INFO L87 Difference]: Start difference. First operand 399 states and 407 transitions. Second operand 27 states. [2018-12-09 04:31:12,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:12,863 INFO L93 Difference]: Finished difference Result 505 states and 517 transitions. [2018-12-09 04:31:12,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-12-09 04:31:12,863 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 365 [2018-12-09 04:31:12,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:12,865 INFO L225 Difference]: With dead ends: 505 [2018-12-09 04:31:12,865 INFO L226 Difference]: Without dead ends: 505 [2018-12-09 04:31:12,866 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 401 GetRequests, 337 SyntacticMatches, 16 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 847 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=595, Invalid=1855, Unknown=0, NotChecked=0, Total=2450 [2018-12-09 04:31:12,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 505 states. [2018-12-09 04:31:12,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 505 to 460. [2018-12-09 04:31:12,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-12-09 04:31:12,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 470 transitions. [2018-12-09 04:31:12,873 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 470 transitions. Word has length 365 [2018-12-09 04:31:12,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:12,873 INFO L480 AbstractCegarLoop]: Abstraction has 460 states and 470 transitions. [2018-12-09 04:31:12,873 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-09 04:31:12,873 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 470 transitions. [2018-12-09 04:31:12,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 427 [2018-12-09 04:31:12,876 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:12,876 INFO L402 BasicCegarLoop]: trace histogram [64, 64, 63, 63, 63, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:12,876 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:12,876 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:12,876 INFO L82 PathProgramCache]: Analyzing trace with hash 1376752291, now seen corresponding path program 15 times [2018-12-09 04:31:12,877 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:12,877 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:12,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:12,877 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:12,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:12,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:13,150 INFO L134 CoverageAnalysis]: Checked inductivity of 10953 backedges. 5169 proven. 1020 refuted. 0 times theorem prover too weak. 4764 trivial. 0 not checked. [2018-12-09 04:31:13,150 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:13,150 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:13,156 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:31:13,243 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-12-09 04:31:13,243 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:13,247 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:13,624 INFO L134 CoverageAnalysis]: Checked inductivity of 10953 backedges. 4880 proven. 659 refuted. 0 times theorem prover too weak. 5414 trivial. 0 not checked. [2018-12-09 04:31:13,649 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:13,649 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27] total 50 [2018-12-09 04:31:13,649 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-12-09 04:31:13,650 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-12-09 04:31:13,650 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=339, Invalid=2111, Unknown=0, NotChecked=0, Total=2450 [2018-12-09 04:31:13,650 INFO L87 Difference]: Start difference. First operand 460 states and 470 transitions. Second operand 50 states. [2018-12-09 04:31:14,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:14,876 INFO L93 Difference]: Finished difference Result 571 states and 580 transitions. [2018-12-09 04:31:14,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-12-09 04:31:14,876 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 426 [2018-12-09 04:31:14,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:14,877 INFO L225 Difference]: With dead ends: 571 [2018-12-09 04:31:14,877 INFO L226 Difference]: Without dead ends: 562 [2018-12-09 04:31:14,879 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 503 GetRequests, 404 SyntacticMatches, 0 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3183 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1464, Invalid=8636, Unknown=0, NotChecked=0, Total=10100 [2018-12-09 04:31:14,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 562 states. [2018-12-09 04:31:14,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 562 to 534. [2018-12-09 04:31:14,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 534 states. [2018-12-09 04:31:14,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 534 states to 534 states and 543 transitions. [2018-12-09 04:31:14,883 INFO L78 Accepts]: Start accepts. Automaton has 534 states and 543 transitions. Word has length 426 [2018-12-09 04:31:14,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:14,883 INFO L480 AbstractCegarLoop]: Abstraction has 534 states and 543 transitions. [2018-12-09 04:31:14,883 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-12-09 04:31:14,883 INFO L276 IsEmpty]: Start isEmpty. Operand 534 states and 543 transitions. [2018-12-09 04:31:14,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 432 [2018-12-09 04:31:14,884 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:14,885 INFO L402 BasicCegarLoop]: trace histogram [65, 65, 64, 64, 64, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:14,885 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:14,885 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:14,885 INFO L82 PathProgramCache]: Analyzing trace with hash -1122718684, now seen corresponding path program 16 times [2018-12-09 04:31:14,885 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:14,885 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:14,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:14,885 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:14,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:14,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:15,162 INFO L134 CoverageAnalysis]: Checked inductivity of 11280 backedges. 2970 proven. 255 refuted. 0 times theorem prover too weak. 8055 trivial. 0 not checked. [2018-12-09 04:31:15,162 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:15,162 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:15,170 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:31:15,269 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:31:15,269 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:15,274 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:15,276 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:15,278 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:15,285 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:15,286 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:15,291 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:15,296 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:15,297 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:31:15,696 INFO L134 CoverageAnalysis]: Checked inductivity of 11280 backedges. 2970 proven. 255 refuted. 0 times theorem prover too weak. 8055 trivial. 0 not checked. [2018-12-09 04:31:15,712 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:15,712 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 26 [2018-12-09 04:31:15,712 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-09 04:31:15,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-09 04:31:15,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=505, Unknown=0, NotChecked=0, Total=702 [2018-12-09 04:31:15,713 INFO L87 Difference]: Start difference. First operand 534 states and 543 transitions. Second operand 27 states. [2018-12-09 04:31:16,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:16,187 INFO L93 Difference]: Finished difference Result 574 states and 585 transitions. [2018-12-09 04:31:16,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-12-09 04:31:16,187 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 431 [2018-12-09 04:31:16,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:16,188 INFO L225 Difference]: With dead ends: 574 [2018-12-09 04:31:16,188 INFO L226 Difference]: Without dead ends: 574 [2018-12-09 04:31:16,189 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 456 GetRequests, 400 SyntacticMatches, 20 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 371 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=328, Invalid=1078, Unknown=0, NotChecked=0, Total=1406 [2018-12-09 04:31:16,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 574 states. [2018-12-09 04:31:16,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 574 to 539. [2018-12-09 04:31:16,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 539 states. [2018-12-09 04:31:16,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 539 states and 549 transitions. [2018-12-09 04:31:16,193 INFO L78 Accepts]: Start accepts. Automaton has 539 states and 549 transitions. Word has length 431 [2018-12-09 04:31:16,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:16,194 INFO L480 AbstractCegarLoop]: Abstraction has 539 states and 549 transitions. [2018-12-09 04:31:16,194 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-09 04:31:16,194 INFO L276 IsEmpty]: Start isEmpty. Operand 539 states and 549 transitions. [2018-12-09 04:31:16,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 437 [2018-12-09 04:31:16,195 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:16,195 INFO L402 BasicCegarLoop]: trace histogram [66, 66, 65, 65, 65, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:16,196 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:16,196 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:16,196 INFO L82 PathProgramCache]: Analyzing trace with hash 199583465, now seen corresponding path program 17 times [2018-12-09 04:31:16,196 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:16,196 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:16,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:16,196 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:16,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:16,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:16,458 INFO L134 CoverageAnalysis]: Checked inductivity of 11612 backedges. 3536 proven. 255 refuted. 0 times theorem prover too weak. 7821 trivial. 0 not checked. [2018-12-09 04:31:16,458 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:16,458 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:16,464 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:31:16,690 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 23 check-sat command(s) [2018-12-09 04:31:16,690 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:16,695 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:17,002 INFO L134 CoverageAnalysis]: Checked inductivity of 11612 backedges. 3451 proven. 967 refuted. 0 times theorem prover too weak. 7194 trivial. 0 not checked. [2018-12-09 04:31:17,017 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:17,018 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 30] total 43 [2018-12-09 04:31:17,018 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-12-09 04:31:17,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-12-09 04:31:17,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=364, Invalid=1442, Unknown=0, NotChecked=0, Total=1806 [2018-12-09 04:31:17,018 INFO L87 Difference]: Start difference. First operand 539 states and 549 transitions. Second operand 43 states. [2018-12-09 04:31:17,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:17,741 INFO L93 Difference]: Finished difference Result 638 states and 649 transitions. [2018-12-09 04:31:17,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-12-09 04:31:17,742 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 436 [2018-12-09 04:31:17,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:17,743 INFO L225 Difference]: With dead ends: 638 [2018-12-09 04:31:17,743 INFO L226 Difference]: Without dead ends: 638 [2018-12-09 04:31:17,743 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 484 GetRequests, 420 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 806 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=933, Invalid=3357, Unknown=0, NotChecked=0, Total=4290 [2018-12-09 04:31:17,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 638 states. [2018-12-09 04:31:17,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 638 to 610. [2018-12-09 04:31:17,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 610 states. [2018-12-09 04:31:17,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 610 states to 610 states and 621 transitions. [2018-12-09 04:31:17,748 INFO L78 Accepts]: Start accepts. Automaton has 610 states and 621 transitions. Word has length 436 [2018-12-09 04:31:17,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:17,748 INFO L480 AbstractCegarLoop]: Abstraction has 610 states and 621 transitions. [2018-12-09 04:31:17,749 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-12-09 04:31:17,749 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 621 transitions. [2018-12-09 04:31:17,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 498 [2018-12-09 04:31:17,750 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:17,750 INFO L402 BasicCegarLoop]: trace histogram [76, 76, 75, 75, 75, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:17,750 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:17,751 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:17,751 INFO L82 PathProgramCache]: Analyzing trace with hash -398596697, now seen corresponding path program 18 times [2018-12-09 04:31:17,751 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:17,751 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:17,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:17,751 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:17,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:17,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:18,102 INFO L134 CoverageAnalysis]: Checked inductivity of 15385 backedges. 3842 proven. 308 refuted. 0 times theorem prover too weak. 11235 trivial. 0 not checked. [2018-12-09 04:31:18,102 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:18,102 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:18,108 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:31:18,357 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-12-09 04:31:18,357 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:18,363 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:18,365 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:18,367 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:18,371 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:18,371 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:18,377 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:18,383 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:18,383 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:31:19,043 INFO L134 CoverageAnalysis]: Checked inductivity of 15385 backedges. 3842 proven. 312 refuted. 0 times theorem prover too weak. 11231 trivial. 0 not checked. [2018-12-09 04:31:19,059 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:19,059 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17] total 30 [2018-12-09 04:31:19,060 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-09 04:31:19,060 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-09 04:31:19,060 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=708, Unknown=0, NotChecked=0, Total=930 [2018-12-09 04:31:19,060 INFO L87 Difference]: Start difference. First operand 610 states and 621 transitions. Second operand 31 states. [2018-12-09 04:31:19,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:19,818 INFO L93 Difference]: Finished difference Result 729 states and 744 transitions. [2018-12-09 04:31:19,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-12-09 04:31:19,818 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 497 [2018-12-09 04:31:19,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:19,819 INFO L225 Difference]: With dead ends: 729 [2018-12-09 04:31:19,819 INFO L226 Difference]: Without dead ends: 729 [2018-12-09 04:31:19,820 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 540 GetRequests, 463 SyntacticMatches, 20 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1225 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=812, Invalid=2610, Unknown=0, NotChecked=0, Total=3422 [2018-12-09 04:31:19,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 729 states. [2018-12-09 04:31:19,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 729 to 676. [2018-12-09 04:31:19,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 676 states. [2018-12-09 04:31:19,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 676 states to 676 states and 689 transitions. [2018-12-09 04:31:19,824 INFO L78 Accepts]: Start accepts. Automaton has 676 states and 689 transitions. Word has length 497 [2018-12-09 04:31:19,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:19,824 INFO L480 AbstractCegarLoop]: Abstraction has 676 states and 689 transitions. [2018-12-09 04:31:19,824 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-09 04:31:19,824 INFO L276 IsEmpty]: Start isEmpty. Operand 676 states and 689 transitions. [2018-12-09 04:31:19,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 564 [2018-12-09 04:31:19,826 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:19,826 INFO L402 BasicCegarLoop]: trace histogram [87, 87, 86, 86, 86, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:19,826 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:19,827 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:19,827 INFO L82 PathProgramCache]: Analyzing trace with hash 1358790276, now seen corresponding path program 19 times [2018-12-09 04:31:19,827 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:19,827 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:19,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:19,827 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:19,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:19,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:20,134 INFO L134 CoverageAnalysis]: Checked inductivity of 20128 backedges. 7916 proven. 1940 refuted. 0 times theorem prover too weak. 10272 trivial. 0 not checked. [2018-12-09 04:31:20,135 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:20,135 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:20,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:20,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:20,227 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:20,496 INFO L134 CoverageAnalysis]: Checked inductivity of 20128 backedges. 10812 proven. 235 refuted. 0 times theorem prover too weak. 9081 trivial. 0 not checked. [2018-12-09 04:31:20,511 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:20,511 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 24] total 40 [2018-12-09 04:31:20,512 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-12-09 04:31:20,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-12-09 04:31:20,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=1249, Unknown=0, NotChecked=0, Total=1560 [2018-12-09 04:31:20,513 INFO L87 Difference]: Start difference. First operand 676 states and 689 transitions. Second operand 40 states. [2018-12-09 04:31:21,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:21,118 INFO L93 Difference]: Finished difference Result 715 states and 726 transitions. [2018-12-09 04:31:21,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-12-09 04:31:21,119 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 563 [2018-12-09 04:31:21,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:21,120 INFO L225 Difference]: With dead ends: 715 [2018-12-09 04:31:21,120 INFO L226 Difference]: Without dead ends: 706 [2018-12-09 04:31:21,121 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 615 GetRequests, 553 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1121 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=881, Invalid=3151, Unknown=0, NotChecked=0, Total=4032 [2018-12-09 04:31:21,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states. [2018-12-09 04:31:21,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 681. [2018-12-09 04:31:21,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 681 states. [2018-12-09 04:31:21,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 692 transitions. [2018-12-09 04:31:21,126 INFO L78 Accepts]: Start accepts. Automaton has 681 states and 692 transitions. Word has length 563 [2018-12-09 04:31:21,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:21,126 INFO L480 AbstractCegarLoop]: Abstraction has 681 states and 692 transitions. [2018-12-09 04:31:21,126 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-12-09 04:31:21,126 INFO L276 IsEmpty]: Start isEmpty. Operand 681 states and 692 transitions. [2018-12-09 04:31:21,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 574 [2018-12-09 04:31:21,129 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:21,129 INFO L402 BasicCegarLoop]: trace histogram [89, 89, 88, 88, 88, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:21,129 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:21,129 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:21,130 INFO L82 PathProgramCache]: Analyzing trace with hash 2121645886, now seen corresponding path program 20 times [2018-12-09 04:31:21,130 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:21,130 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:21,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:21,130 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:21,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:21,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:21,474 INFO L134 CoverageAnalysis]: Checked inductivity of 21021 backedges. 8942 proven. 1499 refuted. 0 times theorem prover too weak. 10580 trivial. 0 not checked. [2018-12-09 04:31:21,474 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:21,474 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:21,480 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:31:21,566 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:31:21,566 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:21,571 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:21,878 INFO L134 CoverageAnalysis]: Checked inductivity of 21021 backedges. 9084 proven. 286 refuted. 0 times theorem prover too weak. 11651 trivial. 0 not checked. [2018-12-09 04:31:21,893 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:21,894 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 26] total 43 [2018-12-09 04:31:21,894 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-12-09 04:31:21,894 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-12-09 04:31:21,894 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=1444, Unknown=0, NotChecked=0, Total=1806 [2018-12-09 04:31:21,894 INFO L87 Difference]: Start difference. First operand 681 states and 692 transitions. Second operand 43 states. [2018-12-09 04:31:22,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:22,633 INFO L93 Difference]: Finished difference Result 719 states and 729 transitions. [2018-12-09 04:31:22,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-12-09 04:31:22,634 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 573 [2018-12-09 04:31:22,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:22,635 INFO L225 Difference]: With dead ends: 719 [2018-12-09 04:31:22,635 INFO L226 Difference]: Without dead ends: 713 [2018-12-09 04:31:22,636 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 629 GetRequests, 562 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1338 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1025, Invalid=3667, Unknown=0, NotChecked=0, Total=4692 [2018-12-09 04:31:22,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states. [2018-12-09 04:31:22,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 686. [2018-12-09 04:31:22,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 686 states. [2018-12-09 04:31:22,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 696 transitions. [2018-12-09 04:31:22,643 INFO L78 Accepts]: Start accepts. Automaton has 686 states and 696 transitions. Word has length 573 [2018-12-09 04:31:22,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:22,643 INFO L480 AbstractCegarLoop]: Abstraction has 686 states and 696 transitions. [2018-12-09 04:31:22,643 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-12-09 04:31:22,643 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 696 transitions. [2018-12-09 04:31:22,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 579 [2018-12-09 04:31:22,647 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:22,647 INFO L402 BasicCegarLoop]: trace histogram [90, 90, 89, 89, 89, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:22,647 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:22,647 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:22,647 INFO L82 PathProgramCache]: Analyzing trace with hash 1114570729, now seen corresponding path program 21 times [2018-12-09 04:31:22,647 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:22,647 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:22,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:22,648 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:22,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:22,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:23,101 INFO L134 CoverageAnalysis]: Checked inductivity of 21475 backedges. 5005 proven. 366 refuted. 0 times theorem prover too weak. 16104 trivial. 0 not checked. [2018-12-09 04:31:23,101 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:23,101 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:23,107 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:31:23,206 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-12-09 04:31:23,206 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:23,210 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:23,213 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:23,216 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:23,220 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:23,221 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:23,230 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:23,243 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:23,244 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:31:23,742 INFO L134 CoverageAnalysis]: Checked inductivity of 21475 backedges. 5005 proven. 366 refuted. 0 times theorem prover too weak. 16104 trivial. 0 not checked. [2018-12-09 04:31:23,761 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:23,762 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18] total 19 [2018-12-09 04:31:23,762 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-12-09 04:31:23,762 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-12-09 04:31:23,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=147, Invalid=233, Unknown=0, NotChecked=0, Total=380 [2018-12-09 04:31:23,762 INFO L87 Difference]: Start difference. First operand 686 states and 696 transitions. Second operand 20 states. [2018-12-09 04:31:24,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:24,070 INFO L93 Difference]: Finished difference Result 729 states and 741 transitions. [2018-12-09 04:31:24,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-09 04:31:24,070 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 578 [2018-12-09 04:31:24,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:24,072 INFO L225 Difference]: With dead ends: 729 [2018-12-09 04:31:24,072 INFO L226 Difference]: Without dead ends: 729 [2018-12-09 04:31:24,072 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 607 GetRequests, 552 SyntacticMatches, 24 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 173 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=382, Invalid=674, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 04:31:24,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 729 states. [2018-12-09 04:31:24,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 729 to 691. [2018-12-09 04:31:24,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 691 states. [2018-12-09 04:31:24,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 691 states to 691 states and 702 transitions. [2018-12-09 04:31:24,077 INFO L78 Accepts]: Start accepts. Automaton has 691 states and 702 transitions. Word has length 578 [2018-12-09 04:31:24,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:24,077 INFO L480 AbstractCegarLoop]: Abstraction has 691 states and 702 transitions. [2018-12-09 04:31:24,077 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-12-09 04:31:24,077 INFO L276 IsEmpty]: Start isEmpty. Operand 691 states and 702 transitions. [2018-12-09 04:31:24,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 584 [2018-12-09 04:31:24,079 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:24,079 INFO L402 BasicCegarLoop]: trace histogram [91, 91, 90, 90, 90, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:24,079 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:24,080 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:24,080 INFO L82 PathProgramCache]: Analyzing trace with hash -1053710780, now seen corresponding path program 22 times [2018-12-09 04:31:24,080 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:24,080 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:24,080 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:24,080 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:24,080 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:24,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:24,424 INFO L134 CoverageAnalysis]: Checked inductivity of 21934 backedges. 5805 proven. 377 refuted. 0 times theorem prover too weak. 15752 trivial. 0 not checked. [2018-12-09 04:31:24,424 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:24,424 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:24,430 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:31:24,512 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:31:24,512 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:24,517 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:24,973 INFO L134 CoverageAnalysis]: Checked inductivity of 21934 backedges. 5706 proven. 1368 refuted. 0 times theorem prover too weak. 14860 trivial. 0 not checked. [2018-12-09 04:31:24,988 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:24,988 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 33] total 49 [2018-12-09 04:31:24,988 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-12-09 04:31:24,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-12-09 04:31:24,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=478, Invalid=1874, Unknown=0, NotChecked=0, Total=2352 [2018-12-09 04:31:24,989 INFO L87 Difference]: Start difference. First operand 691 states and 702 transitions. Second operand 49 states. [2018-12-09 04:31:26,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:26,023 INFO L93 Difference]: Finished difference Result 803 states and 815 transitions. [2018-12-09 04:31:26,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-12-09 04:31:26,024 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 583 [2018-12-09 04:31:26,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:26,025 INFO L225 Difference]: With dead ends: 803 [2018-12-09 04:31:26,025 INFO L226 Difference]: Without dead ends: 803 [2018-12-09 04:31:26,026 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 639 GetRequests, 565 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1073 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1249, Invalid=4451, Unknown=0, NotChecked=0, Total=5700 [2018-12-09 04:31:26,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 803 states. [2018-12-09 04:31:26,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 803 to 772. [2018-12-09 04:31:26,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 772 states. [2018-12-09 04:31:26,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 772 states to 772 states and 784 transitions. [2018-12-09 04:31:26,031 INFO L78 Accepts]: Start accepts. Automaton has 772 states and 784 transitions. Word has length 583 [2018-12-09 04:31:26,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:26,031 INFO L480 AbstractCegarLoop]: Abstraction has 772 states and 784 transitions. [2018-12-09 04:31:26,031 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-12-09 04:31:26,031 INFO L276 IsEmpty]: Start isEmpty. Operand 772 states and 784 transitions. [2018-12-09 04:31:26,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 655 [2018-12-09 04:31:26,034 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:26,034 INFO L402 BasicCegarLoop]: trace histogram [103, 103, 102, 102, 102, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:26,034 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:26,034 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:26,034 INFO L82 PathProgramCache]: Analyzing trace with hash 1839611212, now seen corresponding path program 23 times [2018-12-09 04:31:26,034 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:26,034 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:26,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:26,035 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:26,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:26,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:26,425 INFO L134 CoverageAnalysis]: Checked inductivity of 28059 backedges. 14877 proven. 1167 refuted. 0 times theorem prover too weak. 12015 trivial. 0 not checked. [2018-12-09 04:31:26,425 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:26,425 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:26,432 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:31:26,977 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-12-09 04:31:26,977 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:26,985 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:27,485 INFO L134 CoverageAnalysis]: Checked inductivity of 28059 backedges. 11370 proven. 1767 refuted. 0 times theorem prover too weak. 14922 trivial. 0 not checked. [2018-12-09 04:31:27,501 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:27,502 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 58 [2018-12-09 04:31:27,502 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-12-09 04:31:27,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-12-09 04:31:27,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=506, Invalid=2800, Unknown=0, NotChecked=0, Total=3306 [2018-12-09 04:31:27,502 INFO L87 Difference]: Start difference. First operand 772 states and 784 transitions. Second operand 58 states. [2018-12-09 04:31:28,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:28,985 INFO L93 Difference]: Finished difference Result 804 states and 814 transitions. [2018-12-09 04:31:28,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-12-09 04:31:28,985 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 654 [2018-12-09 04:31:28,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:28,986 INFO L225 Difference]: With dead ends: 804 [2018-12-09 04:31:28,986 INFO L226 Difference]: Without dead ends: 798 [2018-12-09 04:31:28,987 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 726 GetRequests, 630 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2821 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1671, Invalid=7835, Unknown=0, NotChecked=0, Total=9506 [2018-12-09 04:31:28,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 798 states. [2018-12-09 04:31:28,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 798 to 772. [2018-12-09 04:31:28,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 772 states. [2018-12-09 04:31:28,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 772 states to 772 states and 782 transitions. [2018-12-09 04:31:28,993 INFO L78 Accepts]: Start accepts. Automaton has 772 states and 782 transitions. Word has length 654 [2018-12-09 04:31:28,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:28,993 INFO L480 AbstractCegarLoop]: Abstraction has 772 states and 782 transitions. [2018-12-09 04:31:28,993 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-12-09 04:31:28,993 INFO L276 IsEmpty]: Start isEmpty. Operand 772 states and 782 transitions. [2018-12-09 04:31:28,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 660 [2018-12-09 04:31:28,995 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:28,995 INFO L402 BasicCegarLoop]: trace histogram [104, 104, 103, 103, 103, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:28,995 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:28,995 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:28,996 INFO L82 PathProgramCache]: Analyzing trace with hash -120136921, now seen corresponding path program 24 times [2018-12-09 04:31:28,996 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:28,996 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:28,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:28,996 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:28,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:29,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:29,458 INFO L134 CoverageAnalysis]: Checked inductivity of 28584 backedges. 6300 proven. 429 refuted. 0 times theorem prover too weak. 21855 trivial. 0 not checked. [2018-12-09 04:31:29,458 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:29,459 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:29,464 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:31:29,928 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 24 check-sat command(s) [2018-12-09 04:31:29,928 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:29,934 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:29,937 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:29,939 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:29,943 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:29,944 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:29,952 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:29,961 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:29,961 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:31:30,943 INFO L134 CoverageAnalysis]: Checked inductivity of 28584 backedges. 6300 proven. 446 refuted. 0 times theorem prover too weak. 21838 trivial. 0 not checked. [2018-12-09 04:31:30,958 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:30,959 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19] total 34 [2018-12-09 04:31:30,959 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-09 04:31:30,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-09 04:31:30,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=284, Invalid=906, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 04:31:30,959 INFO L87 Difference]: Start difference. First operand 772 states and 782 transitions. Second operand 35 states. [2018-12-09 04:31:31,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:31,849 INFO L93 Difference]: Finished difference Result 895 states and 908 transitions. [2018-12-09 04:31:31,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-12-09 04:31:31,849 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 659 [2018-12-09 04:31:31,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:31,851 INFO L225 Difference]: With dead ends: 895 [2018-12-09 04:31:31,851 INFO L226 Difference]: Without dead ends: 895 [2018-12-09 04:31:31,852 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 707 GetRequests, 619 SyntacticMatches, 24 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1583 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1013, Invalid=3277, Unknown=0, NotChecked=0, Total=4290 [2018-12-09 04:31:31,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 895 states. [2018-12-09 04:31:31,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 895 to 853. [2018-12-09 04:31:31,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 853 states. [2018-12-09 04:31:31,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 853 states to 853 states and 865 transitions. [2018-12-09 04:31:31,860 INFO L78 Accepts]: Start accepts. Automaton has 853 states and 865 transitions. Word has length 659 [2018-12-09 04:31:31,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:31,860 INFO L480 AbstractCegarLoop]: Abstraction has 853 states and 865 transitions. [2018-12-09 04:31:31,860 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-09 04:31:31,860 INFO L276 IsEmpty]: Start isEmpty. Operand 853 states and 865 transitions. [2018-12-09 04:31:31,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 741 [2018-12-09 04:31:31,865 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:31,865 INFO L402 BasicCegarLoop]: trace histogram [118, 118, 117, 117, 117, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:31,865 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:31,866 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:31,866 INFO L82 PathProgramCache]: Analyzing trace with hash -1843296445, now seen corresponding path program 25 times [2018-12-09 04:31:31,866 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:31,866 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:31,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:31,866 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:31,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:31,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:32,340 INFO L134 CoverageAnalysis]: Checked inductivity of 36712 backedges. 14191 proven. 2062 refuted. 0 times theorem prover too weak. 20459 trivial. 0 not checked. [2018-12-09 04:31:32,340 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:32,340 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:32,346 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:32,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:32,455 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:32,818 INFO L134 CoverageAnalysis]: Checked inductivity of 36712 backedges. 14365 proven. 403 refuted. 0 times theorem prover too weak. 21944 trivial. 0 not checked. [2018-12-09 04:31:32,833 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:32,833 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 30] total 49 [2018-12-09 04:31:32,834 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-12-09 04:31:32,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-12-09 04:31:32,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=476, Invalid=1876, Unknown=0, NotChecked=0, Total=2352 [2018-12-09 04:31:32,834 INFO L87 Difference]: Start difference. First operand 853 states and 865 transitions. Second operand 49 states. [2018-12-09 04:31:33,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:33,586 INFO L93 Difference]: Finished difference Result 894 states and 905 transitions. [2018-12-09 04:31:33,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-12-09 04:31:33,587 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 740 [2018-12-09 04:31:33,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:33,588 INFO L225 Difference]: With dead ends: 894 [2018-12-09 04:31:33,588 INFO L226 Difference]: Without dead ends: 888 [2018-12-09 04:31:33,588 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 804 GetRequests, 727 SyntacticMatches, 0 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1829 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1346, Invalid=4816, Unknown=0, NotChecked=0, Total=6162 [2018-12-09 04:31:33,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 888 states. [2018-12-09 04:31:33,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 888 to 858. [2018-12-09 04:31:33,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 858 states. [2018-12-09 04:31:33,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 858 states to 858 states and 869 transitions. [2018-12-09 04:31:33,593 INFO L78 Accepts]: Start accepts. Automaton has 858 states and 869 transitions. Word has length 740 [2018-12-09 04:31:33,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:33,593 INFO L480 AbstractCegarLoop]: Abstraction has 858 states and 869 transitions. [2018-12-09 04:31:33,593 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-12-09 04:31:33,593 INFO L276 IsEmpty]: Start isEmpty. Operand 858 states and 869 transitions. [2018-12-09 04:31:33,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 746 [2018-12-09 04:31:33,596 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:33,596 INFO L402 BasicCegarLoop]: trace histogram [119, 119, 118, 118, 118, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:33,596 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:33,596 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:33,596 INFO L82 PathProgramCache]: Analyzing trace with hash -1981355388, now seen corresponding path program 26 times [2018-12-09 04:31:33,596 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:33,597 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:33,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:33,597 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:33,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:33,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:34,105 INFO L134 CoverageAnalysis]: Checked inductivity of 37313 backedges. 7800 proven. 497 refuted. 0 times theorem prover too weak. 29016 trivial. 0 not checked. [2018-12-09 04:31:34,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:34,105 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:34,111 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:31:34,223 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:31:34,223 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:34,230 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:34,232 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:34,233 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:34,237 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:34,237 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:34,242 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:34,253 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:34,253 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:31:35,353 INFO L134 CoverageAnalysis]: Checked inductivity of 37313 backedges. 7800 proven. 522 refuted. 0 times theorem prover too weak. 28991 trivial. 0 not checked. [2018-12-09 04:31:35,368 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:35,368 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20] total 36 [2018-12-09 04:31:35,368 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-09 04:31:35,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-09 04:31:35,368 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=318, Invalid=1014, Unknown=0, NotChecked=0, Total=1332 [2018-12-09 04:31:35,369 INFO L87 Difference]: Start difference. First operand 858 states and 869 transitions. Second operand 37 states. [2018-12-09 04:31:36,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:36,372 INFO L93 Difference]: Finished difference Result 995 states and 1010 transitions. [2018-12-09 04:31:36,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-09 04:31:36,372 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 745 [2018-12-09 04:31:36,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:36,374 INFO L225 Difference]: With dead ends: 995 [2018-12-09 04:31:36,374 INFO L226 Difference]: Without dead ends: 995 [2018-12-09 04:31:36,375 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 796 GetRequests, 702 SyntacticMatches, 26 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1802 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1135, Invalid=3695, Unknown=0, NotChecked=0, Total=4830 [2018-12-09 04:31:36,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 995 states. [2018-12-09 04:31:36,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 995 to 944. [2018-12-09 04:31:36,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 944 states. [2018-12-09 04:31:36,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 944 states to 944 states and 957 transitions. [2018-12-09 04:31:36,381 INFO L78 Accepts]: Start accepts. Automaton has 944 states and 957 transitions. Word has length 745 [2018-12-09 04:31:36,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:36,382 INFO L480 AbstractCegarLoop]: Abstraction has 944 states and 957 transitions. [2018-12-09 04:31:36,382 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-09 04:31:36,382 INFO L276 IsEmpty]: Start isEmpty. Operand 944 states and 957 transitions. [2018-12-09 04:31:36,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 832 [2018-12-09 04:31:36,386 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:36,386 INFO L402 BasicCegarLoop]: trace histogram [134, 134, 133, 133, 133, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:36,386 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:36,386 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:36,387 INFO L82 PathProgramCache]: Analyzing trace with hash 1588837063, now seen corresponding path program 27 times [2018-12-09 04:31:36,387 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:36,387 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:36,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:36,387 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:36,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:36,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:36,949 INFO L134 CoverageAnalysis]: Checked inductivity of 47208 backedges. 23186 proven. 1572 refuted. 0 times theorem prover too weak. 22450 trivial. 0 not checked. [2018-12-09 04:31:36,949 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:36,949 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:36,955 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:31:37,128 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-12-09 04:31:37,128 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:37,133 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:37,875 INFO L134 CoverageAnalysis]: Checked inductivity of 47208 backedges. 16630 proven. 1549 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2018-12-09 04:31:37,890 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:37,891 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 37] total 70 [2018-12-09 04:31:37,891 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-12-09 04:31:37,891 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-12-09 04:31:37,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=695, Invalid=4135, Unknown=0, NotChecked=0, Total=4830 [2018-12-09 04:31:37,892 INFO L87 Difference]: Start difference. First operand 944 states and 957 transitions. Second operand 70 states. [2018-12-09 04:31:41,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:41,036 INFO L93 Difference]: Finished difference Result 1083 states and 1096 transitions. [2018-12-09 04:31:41,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2018-12-09 04:31:41,036 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 831 [2018-12-09 04:31:41,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:41,038 INFO L225 Difference]: With dead ends: 1083 [2018-12-09 04:31:41,038 INFO L226 Difference]: Without dead ends: 1077 [2018-12-09 04:31:41,039 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 932 GetRequests, 799 SyntacticMatches, 0 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5602 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2870, Invalid=15220, Unknown=0, NotChecked=0, Total=18090 [2018-12-09 04:31:41,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1077 states. [2018-12-09 04:31:41,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1077 to 1043. [2018-12-09 04:31:41,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1043 states. [2018-12-09 04:31:41,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1043 states to 1043 states and 1055 transitions. [2018-12-09 04:31:41,044 INFO L78 Accepts]: Start accepts. Automaton has 1043 states and 1055 transitions. Word has length 831 [2018-12-09 04:31:41,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:41,044 INFO L480 AbstractCegarLoop]: Abstraction has 1043 states and 1055 transitions. [2018-12-09 04:31:41,044 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-12-09 04:31:41,044 INFO L276 IsEmpty]: Start isEmpty. Operand 1043 states and 1055 transitions. [2018-12-09 04:31:41,047 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 837 [2018-12-09 04:31:41,048 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:41,048 INFO L402 BasicCegarLoop]: trace histogram [135, 135, 134, 134, 134, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:41,048 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:41,048 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:41,048 INFO L82 PathProgramCache]: Analyzing trace with hash -1695298804, now seen corresponding path program 28 times [2018-12-09 04:31:41,048 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:41,048 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:41,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:41,049 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:41,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:41,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:41,650 INFO L134 CoverageAnalysis]: Checked inductivity of 47890 backedges. 9520 proven. 570 refuted. 0 times theorem prover too weak. 37800 trivial. 0 not checked. [2018-12-09 04:31:41,651 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:41,651 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:41,657 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:31:41,848 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:31:41,848 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:41,857 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:41,860 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:41,862 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:41,867 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:41,867 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:41,874 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:41,886 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:41,886 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:31:42,947 INFO L134 CoverageAnalysis]: Checked inductivity of 47890 backedges. 9520 proven. 570 refuted. 0 times theorem prover too weak. 37800 trivial. 0 not checked. [2018-12-09 04:31:42,973 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:42,974 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 36 [2018-12-09 04:31:42,974 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-09 04:31:42,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-09 04:31:42,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=970, Unknown=0, NotChecked=0, Total=1332 [2018-12-09 04:31:42,975 INFO L87 Difference]: Start difference. First operand 1043 states and 1055 transitions. Second operand 37 states. [2018-12-09 04:31:43,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:43,822 INFO L93 Difference]: Finished difference Result 1089 states and 1103 transitions. [2018-12-09 04:31:43,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-12-09 04:31:43,823 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 836 [2018-12-09 04:31:43,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:43,824 INFO L225 Difference]: With dead ends: 1089 [2018-12-09 04:31:43,824 INFO L226 Difference]: Without dead ends: 1089 [2018-12-09 04:31:43,825 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 871 GetRequests, 790 SyntacticMatches, 30 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 781 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=593, Invalid=2163, Unknown=0, NotChecked=0, Total=2756 [2018-12-09 04:31:43,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1089 states. [2018-12-09 04:31:43,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1089 to 1048. [2018-12-09 04:31:43,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1048 states. [2018-12-09 04:31:43,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1048 states to 1048 states and 1061 transitions. [2018-12-09 04:31:43,830 INFO L78 Accepts]: Start accepts. Automaton has 1048 states and 1061 transitions. Word has length 836 [2018-12-09 04:31:43,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:43,830 INFO L480 AbstractCegarLoop]: Abstraction has 1048 states and 1061 transitions. [2018-12-09 04:31:43,830 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-09 04:31:43,830 INFO L276 IsEmpty]: Start isEmpty. Operand 1048 states and 1061 transitions. [2018-12-09 04:31:43,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 842 [2018-12-09 04:31:43,833 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:43,834 INFO L402 BasicCegarLoop]: trace histogram [136, 136, 135, 135, 135, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:43,834 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:43,834 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:43,834 INFO L82 PathProgramCache]: Analyzing trace with hash -1095935743, now seen corresponding path program 29 times [2018-12-09 04:31:43,834 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:43,834 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:43,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:43,834 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:43,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:43,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:44,337 INFO L134 CoverageAnalysis]: Checked inductivity of 48577 backedges. 10746 proven. 605 refuted. 0 times theorem prover too weak. 37226 trivial. 0 not checked. [2018-12-09 04:31:44,337 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:44,337 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:44,342 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:31:45,159 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-12-09 04:31:45,159 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:45,170 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:45,789 INFO L134 CoverageAnalysis]: Checked inductivity of 48577 backedges. 10626 proven. 2097 refuted. 0 times theorem prover too weak. 35854 trivial. 0 not checked. [2018-12-09 04:31:45,807 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:45,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 40] total 58 [2018-12-09 04:31:45,807 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-12-09 04:31:45,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-12-09 04:31:45,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=679, Invalid=2627, Unknown=0, NotChecked=0, Total=3306 [2018-12-09 04:31:45,808 INFO L87 Difference]: Start difference. First operand 1048 states and 1061 transitions. Second operand 58 states. [2018-12-09 04:31:46,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:46,849 INFO L93 Difference]: Finished difference Result 1178 states and 1192 transitions. [2018-12-09 04:31:46,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-12-09 04:31:46,850 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 841 [2018-12-09 04:31:46,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:46,851 INFO L225 Difference]: With dead ends: 1178 [2018-12-09 04:31:46,851 INFO L226 Difference]: Without dead ends: 1178 [2018-12-09 04:31:46,852 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 909 GetRequests, 820 SyntacticMatches, 0 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1541 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1813, Invalid=6377, Unknown=0, NotChecked=0, Total=8190 [2018-12-09 04:31:46,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1178 states. [2018-12-09 04:31:46,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1178 to 1144. [2018-12-09 04:31:46,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1144 states. [2018-12-09 04:31:46,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1144 states to 1144 states and 1158 transitions. [2018-12-09 04:31:46,861 INFO L78 Accepts]: Start accepts. Automaton has 1144 states and 1158 transitions. Word has length 841 [2018-12-09 04:31:46,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:46,862 INFO L480 AbstractCegarLoop]: Abstraction has 1144 states and 1158 transitions. [2018-12-09 04:31:46,862 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-12-09 04:31:46,862 INFO L276 IsEmpty]: Start isEmpty. Operand 1144 states and 1158 transitions. [2018-12-09 04:31:46,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 928 [2018-12-09 04:31:46,868 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:46,868 INFO L402 BasicCegarLoop]: trace histogram [151, 151, 150, 150, 150, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:46,869 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:46,869 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:46,869 INFO L82 PathProgramCache]: Analyzing trace with hash -519548770, now seen corresponding path program 30 times [2018-12-09 04:31:46,869 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:46,869 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:46,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:46,870 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:46,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:46,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:47,483 INFO L134 CoverageAnalysis]: Checked inductivity of 59790 backedges. 21156 proven. 2709 refuted. 0 times theorem prover too weak. 35925 trivial. 0 not checked. [2018-12-09 04:31:47,483 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:47,483 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:47,489 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:31:48,897 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 32 check-sat command(s) [2018-12-09 04:31:48,897 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:48,907 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:49,748 INFO L134 CoverageAnalysis]: Checked inductivity of 59790 backedges. 28329 proven. 1770 refuted. 0 times theorem prover too weak. 29691 trivial. 0 not checked. [2018-12-09 04:31:49,765 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:49,765 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 37] total 70 [2018-12-09 04:31:49,765 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-12-09 04:31:49,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-12-09 04:31:49,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=785, Invalid=4045, Unknown=0, NotChecked=0, Total=4830 [2018-12-09 04:31:49,766 INFO L87 Difference]: Start difference. First operand 1144 states and 1158 transitions. Second operand 70 states. [2018-12-09 04:31:51,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:51,327 INFO L93 Difference]: Finished difference Result 1183 states and 1194 transitions. [2018-12-09 04:31:51,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-12-09 04:31:51,327 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 927 [2018-12-09 04:31:51,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:51,329 INFO L225 Difference]: With dead ends: 1183 [2018-12-09 04:31:51,329 INFO L226 Difference]: Without dead ends: 1174 [2018-12-09 04:31:51,330 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1014 GetRequests, 897 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4160 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2436, Invalid=11606, Unknown=0, NotChecked=0, Total=14042 [2018-12-09 04:31:51,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1174 states. [2018-12-09 04:31:51,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1174 to 1144. [2018-12-09 04:31:51,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1144 states. [2018-12-09 04:31:51,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1144 states to 1144 states and 1155 transitions. [2018-12-09 04:31:51,336 INFO L78 Accepts]: Start accepts. Automaton has 1144 states and 1155 transitions. Word has length 927 [2018-12-09 04:31:51,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:51,337 INFO L480 AbstractCegarLoop]: Abstraction has 1144 states and 1155 transitions. [2018-12-09 04:31:51,337 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-12-09 04:31:51,337 INFO L276 IsEmpty]: Start isEmpty. Operand 1144 states and 1155 transitions. [2018-12-09 04:31:51,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 933 [2018-12-09 04:31:51,341 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:51,341 INFO L402 BasicCegarLoop]: trace histogram [152, 152, 151, 151, 151, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:51,341 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:51,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:51,341 INFO L82 PathProgramCache]: Analyzing trace with hash -426911351, now seen corresponding path program 31 times [2018-12-09 04:31:51,342 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:51,342 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:51,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:51,342 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:51,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:51,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:52,029 INFO L134 CoverageAnalysis]: Checked inductivity of 60558 backedges. 11475 proven. 648 refuted. 0 times theorem prover too weak. 48435 trivial. 0 not checked. [2018-12-09 04:31:52,030 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:52,030 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:52,035 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:52,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:52,181 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:52,183 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:31:52,185 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:31:52,188 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:31:52,188 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:31:52,193 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:31:52,202 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:31:52,202 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:31:53,424 INFO L134 CoverageAnalysis]: Checked inductivity of 60558 backedges. 11475 proven. 648 refuted. 0 times theorem prover too weak. 48435 trivial. 0 not checked. [2018-12-09 04:31:53,439 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:53,440 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 38 [2018-12-09 04:31:53,440 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-12-09 04:31:53,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-12-09 04:31:53,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=401, Invalid=1081, Unknown=0, NotChecked=0, Total=1482 [2018-12-09 04:31:53,441 INFO L87 Difference]: Start difference. First operand 1144 states and 1155 transitions. Second operand 39 states. [2018-12-09 04:31:54,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:54,244 INFO L93 Difference]: Finished difference Result 1178 states and 1190 transitions. [2018-12-09 04:31:54,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-12-09 04:31:54,244 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 932 [2018-12-09 04:31:54,245 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:54,246 INFO L225 Difference]: With dead ends: 1178 [2018-12-09 04:31:54,246 INFO L226 Difference]: Without dead ends: 1178 [2018-12-09 04:31:54,246 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 969 GetRequests, 883 SyntacticMatches, 32 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 881 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=655, Invalid=2425, Unknown=0, NotChecked=0, Total=3080 [2018-12-09 04:31:54,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1178 states. [2018-12-09 04:31:54,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1178 to 1149. [2018-12-09 04:31:54,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1149 states. [2018-12-09 04:31:54,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1149 states to 1149 states and 1161 transitions. [2018-12-09 04:31:54,255 INFO L78 Accepts]: Start accepts. Automaton has 1149 states and 1161 transitions. Word has length 932 [2018-12-09 04:31:54,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:54,255 INFO L480 AbstractCegarLoop]: Abstraction has 1149 states and 1161 transitions. [2018-12-09 04:31:54,255 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-12-09 04:31:54,255 INFO L276 IsEmpty]: Start isEmpty. Operand 1149 states and 1161 transitions. [2018-12-09 04:31:54,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 938 [2018-12-09 04:31:54,262 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:54,262 INFO L402 BasicCegarLoop]: trace histogram [153, 153, 152, 152, 152, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:54,262 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:54,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:54,263 INFO L82 PathProgramCache]: Analyzing trace with hash 1551487140, now seen corresponding path program 32 times [2018-12-09 04:31:54,263 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:54,263 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:54,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:54,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:31:54,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:54,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:54,877 INFO L134 CoverageAnalysis]: Checked inductivity of 61331 backedges. 12863 proven. 693 refuted. 0 times theorem prover too weak. 47775 trivial. 0 not checked. [2018-12-09 04:31:54,877 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:54,877 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:54,882 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:31:55,019 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:31:55,019 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:55,027 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:55,645 INFO L134 CoverageAnalysis]: Checked inductivity of 61331 backedges. 12896 proven. 660 refuted. 0 times theorem prover too weak. 47775 trivial. 0 not checked. [2018-12-09 04:31:55,660 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:55,661 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 37] total 57 [2018-12-09 04:31:55,661 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-12-09 04:31:55,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-12-09 04:31:55,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=742, Invalid=2450, Unknown=0, NotChecked=0, Total=3192 [2018-12-09 04:31:55,661 INFO L87 Difference]: Start difference. First operand 1149 states and 1161 transitions. Second operand 57 states. [2018-12-09 04:31:56,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:31:56,594 INFO L93 Difference]: Finished difference Result 1276 states and 1289 transitions. [2018-12-09 04:31:56,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-12-09 04:31:56,594 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 937 [2018-12-09 04:31:56,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:31:56,597 INFO L225 Difference]: With dead ends: 1276 [2018-12-09 04:31:56,597 INFO L226 Difference]: Without dead ends: 1276 [2018-12-09 04:31:56,597 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1007 GetRequests, 919 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1319 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2059, Invalid=5951, Unknown=0, NotChecked=0, Total=8010 [2018-12-09 04:31:56,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1276 states. [2018-12-09 04:31:56,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1276 to 1245. [2018-12-09 04:31:56,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1245 states. [2018-12-09 04:31:56,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1245 states to 1245 states and 1258 transitions. [2018-12-09 04:31:56,606 INFO L78 Accepts]: Start accepts. Automaton has 1245 states and 1258 transitions. Word has length 937 [2018-12-09 04:31:56,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:31:56,606 INFO L480 AbstractCegarLoop]: Abstraction has 1245 states and 1258 transitions. [2018-12-09 04:31:56,606 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-12-09 04:31:56,606 INFO L276 IsEmpty]: Start isEmpty. Operand 1245 states and 1258 transitions. [2018-12-09 04:31:56,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1029 [2018-12-09 04:31:56,612 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:31:56,612 INFO L402 BasicCegarLoop]: trace histogram [169, 169, 168, 168, 168, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:31:56,612 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:31:56,612 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:31:56,613 INFO L82 PathProgramCache]: Analyzing trace with hash -139595476, now seen corresponding path program 33 times [2018-12-09 04:31:56,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:31:56,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:31:56,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:56,613 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:31:56,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:31:56,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:31:57,381 INFO L134 CoverageAnalysis]: Checked inductivity of 74716 backedges. 13592 proven. 731 refuted. 0 times theorem prover too weak. 60393 trivial. 0 not checked. [2018-12-09 04:31:57,382 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:31:57,382 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:31:57,387 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:31:57,601 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-12-09 04:31:57,601 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:31:57,608 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:31:58,557 INFO L134 CoverageAnalysis]: Checked inductivity of 74716 backedges. 24256 proven. 2010 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-09 04:31:58,572 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:31:58,573 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 41] total 62 [2018-12-09 04:31:58,573 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-09 04:31:58,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-09 04:31:58,573 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=567, Invalid=3215, Unknown=0, NotChecked=0, Total=3782 [2018-12-09 04:31:58,574 INFO L87 Difference]: Start difference. First operand 1245 states and 1258 transitions. Second operand 62 states. [2018-12-09 04:32:00,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:00,910 INFO L93 Difference]: Finished difference Result 1388 states and 1403 transitions. [2018-12-09 04:32:00,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-12-09 04:32:00,910 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1028 [2018-12-09 04:32:00,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:00,913 INFO L225 Difference]: With dead ends: 1388 [2018-12-09 04:32:00,913 INFO L226 Difference]: Without dead ends: 1388 [2018-12-09 04:32:00,913 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1108 GetRequests, 989 SyntacticMatches, 0 SemanticMatches, 119 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3624 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=2783, Invalid=11737, Unknown=0, NotChecked=0, Total=14520 [2018-12-09 04:32:00,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1388 states. [2018-12-09 04:32:00,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1388 to 1256. [2018-12-09 04:32:00,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1256 states. [2018-12-09 04:32:00,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1256 states to 1256 states and 1270 transitions. [2018-12-09 04:32:00,921 INFO L78 Accepts]: Start accepts. Automaton has 1256 states and 1270 transitions. Word has length 1028 [2018-12-09 04:32:00,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:00,921 INFO L480 AbstractCegarLoop]: Abstraction has 1256 states and 1270 transitions. [2018-12-09 04:32:00,921 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-09 04:32:00,921 INFO L276 IsEmpty]: Start isEmpty. Operand 1256 states and 1270 transitions. [2018-12-09 04:32:00,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1039 [2018-12-09 04:32:00,927 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:00,927 INFO L402 BasicCegarLoop]: trace histogram [171, 171, 170, 170, 170, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:00,927 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:00,927 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:00,927 INFO L82 PathProgramCache]: Analyzing trace with hash -1792127834, now seen corresponding path program 34 times [2018-12-09 04:32:00,927 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:00,928 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:00,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:00,928 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:00,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:00,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:01,732 INFO L134 CoverageAnalysis]: Checked inductivity of 76439 backedges. 14456 proven. 819 refuted. 0 times theorem prover too weak. 61164 trivial. 0 not checked. [2018-12-09 04:32:01,732 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:01,732 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:01,738 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:32:01,872 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:32:01,872 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:01,880 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:02,853 INFO L134 CoverageAnalysis]: Checked inductivity of 76439 backedges. 15106 proven. 2668 refuted. 0 times theorem prover too weak. 58665 trivial. 0 not checked. [2018-12-09 04:32:02,869 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:02,869 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 43] total 65 [2018-12-09 04:32:02,869 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-12-09 04:32:02,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-12-09 04:32:02,870 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=611, Invalid=3549, Unknown=0, NotChecked=0, Total=4160 [2018-12-09 04:32:02,870 INFO L87 Difference]: Start difference. First operand 1256 states and 1270 transitions. Second operand 65 states. [2018-12-09 04:32:05,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:05,466 INFO L93 Difference]: Finished difference Result 1513 states and 1533 transitions. [2018-12-09 04:32:05,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-12-09 04:32:05,466 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 1038 [2018-12-09 04:32:05,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:05,468 INFO L225 Difference]: With dead ends: 1513 [2018-12-09 04:32:05,468 INFO L226 Difference]: Without dead ends: 1513 [2018-12-09 04:32:05,469 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1140 GetRequests, 1014 SyntacticMatches, 0 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4141 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=2334, Invalid=13922, Unknown=0, NotChecked=0, Total=16256 [2018-12-09 04:32:05,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1513 states. [2018-12-09 04:32:05,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1513 to 1470. [2018-12-09 04:32:05,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1470 states. [2018-12-09 04:32:05,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1470 states to 1470 states and 1490 transitions. [2018-12-09 04:32:05,477 INFO L78 Accepts]: Start accepts. Automaton has 1470 states and 1490 transitions. Word has length 1038 [2018-12-09 04:32:05,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:05,477 INFO L480 AbstractCegarLoop]: Abstraction has 1470 states and 1490 transitions. [2018-12-09 04:32:05,477 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-12-09 04:32:05,477 INFO L276 IsEmpty]: Start isEmpty. Operand 1470 states and 1490 transitions. [2018-12-09 04:32:05,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1135 [2018-12-09 04:32:05,483 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:05,483 INFO L402 BasicCegarLoop]: trace histogram [188, 188, 187, 187, 187, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:05,483 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:05,483 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:05,483 INFO L82 PathProgramCache]: Analyzing trace with hash 1853652527, now seen corresponding path program 35 times [2018-12-09 04:32:05,483 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:05,484 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:05,484 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:05,484 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:05,484 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:05,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:06,279 INFO L134 CoverageAnalysis]: Checked inductivity of 92259 backedges. 28678 proven. 4740 refuted. 0 times theorem prover too weak. 58841 trivial. 0 not checked. [2018-12-09 04:32:06,279 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:06,279 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:06,287 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:32:07,418 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 41 check-sat command(s) [2018-12-09 04:32:07,418 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:07,429 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:08,353 INFO L134 CoverageAnalysis]: Checked inductivity of 92259 backedges. 44737 proven. 4771 refuted. 0 times theorem prover too weak. 42751 trivial. 0 not checked. [2018-12-09 04:32:08,371 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:08,371 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 71 [2018-12-09 04:32:08,371 INFO L459 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-12-09 04:32:08,372 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-12-09 04:32:08,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=816, Invalid=4154, Unknown=0, NotChecked=0, Total=4970 [2018-12-09 04:32:08,372 INFO L87 Difference]: Start difference. First operand 1470 states and 1490 transitions. Second operand 71 states. [2018-12-09 04:32:09,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:09,835 INFO L93 Difference]: Finished difference Result 1419 states and 1438 transitions. [2018-12-09 04:32:09,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-09 04:32:09,835 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 1134 [2018-12-09 04:32:09,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:09,838 INFO L225 Difference]: With dead ends: 1419 [2018-12-09 04:32:09,838 INFO L226 Difference]: Without dead ends: 1372 [2018-12-09 04:32:09,839 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1223 GetRequests, 1105 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4231 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2569, Invalid=11711, Unknown=0, NotChecked=0, Total=14280 [2018-12-09 04:32:09,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states. [2018-12-09 04:32:09,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1351. [2018-12-09 04:32:09,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1351 states. [2018-12-09 04:32:09,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1351 states to 1351 states and 1364 transitions. [2018-12-09 04:32:09,852 INFO L78 Accepts]: Start accepts. Automaton has 1351 states and 1364 transitions. Word has length 1134 [2018-12-09 04:32:09,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:09,853 INFO L480 AbstractCegarLoop]: Abstraction has 1351 states and 1364 transitions. [2018-12-09 04:32:09,853 INFO L481 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-12-09 04:32:09,853 INFO L276 IsEmpty]: Start isEmpty. Operand 1351 states and 1364 transitions. [2018-12-09 04:32:09,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1140 [2018-12-09 04:32:09,858 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:09,859 INFO L402 BasicCegarLoop]: trace histogram [189, 189, 188, 188, 188, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:09,859 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:09,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:09,859 INFO L82 PathProgramCache]: Analyzing trace with hash -1047165046, now seen corresponding path program 36 times [2018-12-09 04:32:09,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:09,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:09,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:09,860 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:09,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:09,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:10,716 INFO L134 CoverageAnalysis]: Checked inductivity of 93214 backedges. 30939 proven. 3440 refuted. 0 times theorem prover too weak. 58835 trivial. 0 not checked. [2018-12-09 04:32:10,717 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:10,717 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:10,722 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:32:11,722 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-12-09 04:32:11,722 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:11,733 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:11,736 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:32:11,738 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:32:11,744 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:32:11,744 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:32:11,749 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:32:11,755 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:32:11,756 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:32:14,273 INFO L134 CoverageAnalysis]: Checked inductivity of 93214 backedges. 28739 proven. 2421 refuted. 0 times theorem prover too weak. 62054 trivial. 0 not checked. [2018-12-09 04:32:14,290 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:14,290 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 28] total 69 [2018-12-09 04:32:14,291 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-12-09 04:32:14,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-12-09 04:32:14,291 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=765, Invalid=3927, Unknown=0, NotChecked=0, Total=4692 [2018-12-09 04:32:14,291 INFO L87 Difference]: Start difference. First operand 1351 states and 1364 transitions. Second operand 69 states. [2018-12-09 04:32:17,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:17,831 INFO L93 Difference]: Finished difference Result 1382 states and 1393 transitions. [2018-12-09 04:32:17,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-12-09 04:32:17,831 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1139 [2018-12-09 04:32:17,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:17,833 INFO L225 Difference]: With dead ends: 1382 [2018-12-09 04:32:17,833 INFO L226 Difference]: Without dead ends: 1376 [2018-12-09 04:32:17,835 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1275 GetRequests, 1082 SyntacticMatches, 32 SemanticMatches, 161 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9838 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=4256, Invalid=22150, Unknown=0, NotChecked=0, Total=26406 [2018-12-09 04:32:17,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1376 states. [2018-12-09 04:32:17,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1376 to 1351. [2018-12-09 04:32:17,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1351 states. [2018-12-09 04:32:17,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1351 states to 1351 states and 1362 transitions. [2018-12-09 04:32:17,842 INFO L78 Accepts]: Start accepts. Automaton has 1351 states and 1362 transitions. Word has length 1139 [2018-12-09 04:32:17,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:17,843 INFO L480 AbstractCegarLoop]: Abstraction has 1351 states and 1362 transitions. [2018-12-09 04:32:17,843 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-12-09 04:32:17,843 INFO L276 IsEmpty]: Start isEmpty. Operand 1351 states and 1362 transitions. [2018-12-09 04:32:17,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1145 [2018-12-09 04:32:17,848 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:17,848 INFO L402 BasicCegarLoop]: trace histogram [190, 190, 189, 189, 189, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:17,848 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:17,848 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:17,849 INFO L82 PathProgramCache]: Analyzing trace with hash 7672105, now seen corresponding path program 37 times [2018-12-09 04:32:17,849 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:17,849 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:17,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:17,849 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:17,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:17,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:18,637 INFO L134 CoverageAnalysis]: Checked inductivity of 94174 backedges. 17892 proven. 887 refuted. 0 times theorem prover too weak. 75395 trivial. 0 not checked. [2018-12-09 04:32:18,637 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:18,637 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:18,643 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:32:18,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:18,813 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:19,627 INFO L134 CoverageAnalysis]: Checked inductivity of 94174 backedges. 17929 proven. 850 refuted. 0 times theorem prover too weak. 75395 trivial. 0 not checked. [2018-12-09 04:32:19,642 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:19,642 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 41] total 63 [2018-12-09 04:32:19,643 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-12-09 04:32:19,643 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-12-09 04:32:19,643 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=904, Invalid=3002, Unknown=0, NotChecked=0, Total=3906 [2018-12-09 04:32:19,643 INFO L87 Difference]: Start difference. First operand 1351 states and 1362 transitions. Second operand 63 states. [2018-12-09 04:32:20,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:20,723 INFO L93 Difference]: Finished difference Result 1485 states and 1497 transitions. [2018-12-09 04:32:20,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-12-09 04:32:20,723 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1144 [2018-12-09 04:32:20,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:20,726 INFO L225 Difference]: With dead ends: 1485 [2018-12-09 04:32:20,726 INFO L226 Difference]: Without dead ends: 1485 [2018-12-09 04:32:20,727 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1222 GetRequests, 1124 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1646 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2529, Invalid=7371, Unknown=0, NotChecked=0, Total=9900 [2018-12-09 04:32:20,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1485 states. [2018-12-09 04:32:20,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1485 to 1457. [2018-12-09 04:32:20,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1457 states. [2018-12-09 04:32:20,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1457 states to 1457 states and 1469 transitions. [2018-12-09 04:32:20,735 INFO L78 Accepts]: Start accepts. Automaton has 1457 states and 1469 transitions. Word has length 1144 [2018-12-09 04:32:20,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:20,736 INFO L480 AbstractCegarLoop]: Abstraction has 1457 states and 1469 transitions. [2018-12-09 04:32:20,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-12-09 04:32:20,736 INFO L276 IsEmpty]: Start isEmpty. Operand 1457 states and 1469 transitions. [2018-12-09 04:32:20,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1246 [2018-12-09 04:32:20,743 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:20,743 INFO L402 BasicCegarLoop]: trace histogram [208, 208, 207, 207, 207, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:20,744 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:20,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:20,744 INFO L82 PathProgramCache]: Analyzing trace with hash -700055321, now seen corresponding path program 38 times [2018-12-09 04:32:20,744 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:20,744 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:20,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:20,745 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:32:20,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:20,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:21,718 INFO L134 CoverageAnalysis]: Checked inductivity of 112707 backedges. 48036 proven. 2562 refuted. 0 times theorem prover too weak. 62109 trivial. 0 not checked. [2018-12-09 04:32:21,718 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:21,718 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:21,724 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:32:21,907 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:32:21,908 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:21,917 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:22,941 INFO L134 CoverageAnalysis]: Checked inductivity of 112707 backedges. 35600 proven. 783 refuted. 0 times theorem prover too weak. 76324 trivial. 0 not checked. [2018-12-09 04:32:22,957 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:22,957 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 40] total 79 [2018-12-09 04:32:22,957 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-12-09 04:32:22,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-12-09 04:32:22,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1011, Invalid=5151, Unknown=0, NotChecked=0, Total=6162 [2018-12-09 04:32:22,958 INFO L87 Difference]: Start difference. First operand 1457 states and 1469 transitions. Second operand 79 states. [2018-12-09 04:32:26,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:26,267 INFO L93 Difference]: Finished difference Result 1486 states and 1496 transitions. [2018-12-09 04:32:26,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-12-09 04:32:26,267 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1245 [2018-12-09 04:32:26,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:26,270 INFO L225 Difference]: With dead ends: 1486 [2018-12-09 04:32:26,270 INFO L226 Difference]: Without dead ends: 1480 [2018-12-09 04:32:26,271 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1344 GetRequests, 1212 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5834 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=2881, Invalid=14941, Unknown=0, NotChecked=0, Total=17822 [2018-12-09 04:32:26,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1480 states. [2018-12-09 04:32:26,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1480 to 1457. [2018-12-09 04:32:26,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1457 states. [2018-12-09 04:32:26,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1457 states to 1457 states and 1467 transitions. [2018-12-09 04:32:26,281 INFO L78 Accepts]: Start accepts. Automaton has 1457 states and 1467 transitions. Word has length 1245 [2018-12-09 04:32:26,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:26,282 INFO L480 AbstractCegarLoop]: Abstraction has 1457 states and 1467 transitions. [2018-12-09 04:32:26,282 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-12-09 04:32:26,282 INFO L276 IsEmpty]: Start isEmpty. Operand 1457 states and 1467 transitions. [2018-12-09 04:32:26,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1251 [2018-12-09 04:32:26,289 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:26,289 INFO L402 BasicCegarLoop]: trace histogram [209, 209, 208, 208, 208, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:26,289 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:26,290 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:26,290 INFO L82 PathProgramCache]: Analyzing trace with hash 1926949356, now seen corresponding path program 39 times [2018-12-09 04:32:26,290 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:26,290 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:26,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:26,290 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:26,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:26,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:27,305 INFO L134 CoverageAnalysis]: Checked inductivity of 113763 backedges. 18900 proven. 912 refuted. 0 times theorem prover too weak. 93951 trivial. 0 not checked. [2018-12-09 04:32:27,306 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:27,306 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:27,311 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:32:27,667 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-12-09 04:32:27,668 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:27,677 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:27,679 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:32:27,681 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:32:27,685 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:32:27,685 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:32:27,690 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:32:27,698 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:32:27,698 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:32:29,548 INFO L134 CoverageAnalysis]: Checked inductivity of 113763 backedges. 18900 proven. 912 refuted. 0 times theorem prover too weak. 93951 trivial. 0 not checked. [2018-12-09 04:32:29,564 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:29,564 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25] total 26 [2018-12-09 04:32:29,565 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-09 04:32:29,565 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-09 04:32:29,565 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=287, Invalid=415, Unknown=0, NotChecked=0, Total=702 [2018-12-09 04:32:29,565 INFO L87 Difference]: Start difference. First operand 1457 states and 1467 transitions. Second operand 27 states. [2018-12-09 04:32:30,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:30,064 INFO L93 Difference]: Finished difference Result 1488 states and 1499 transitions. [2018-12-09 04:32:30,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-12-09 04:32:30,064 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 1250 [2018-12-09 04:32:30,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:30,067 INFO L225 Difference]: With dead ends: 1488 [2018-12-09 04:32:30,067 INFO L226 Difference]: Without dead ends: 1488 [2018-12-09 04:32:30,068 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1293 GetRequests, 1210 SyntacticMatches, 38 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 341 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=788, Invalid=1374, Unknown=0, NotChecked=0, Total=2162 [2018-12-09 04:32:30,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states. [2018-12-09 04:32:30,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1462. [2018-12-09 04:32:30,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1462 states. [2018-12-09 04:32:30,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1462 states to 1462 states and 1473 transitions. [2018-12-09 04:32:30,078 INFO L78 Accepts]: Start accepts. Automaton has 1462 states and 1473 transitions. Word has length 1250 [2018-12-09 04:32:30,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:30,079 INFO L480 AbstractCegarLoop]: Abstraction has 1462 states and 1473 transitions. [2018-12-09 04:32:30,079 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-09 04:32:30,079 INFO L276 IsEmpty]: Start isEmpty. Operand 1462 states and 1473 transitions. [2018-12-09 04:32:30,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1256 [2018-12-09 04:32:30,091 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:30,092 INFO L402 BasicCegarLoop]: trace histogram [210, 210, 209, 209, 209, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:30,092 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:30,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:30,092 INFO L82 PathProgramCache]: Analyzing trace with hash 1858504225, now seen corresponding path program 40 times [2018-12-09 04:32:30,092 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:30,092 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:30,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:30,093 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:30,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:30,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:31,015 INFO L134 CoverageAnalysis]: Checked inductivity of 114824 backedges. 20834 proven. 993 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2018-12-09 04:32:31,016 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:31,016 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:31,021 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:32:31,193 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:32:31,193 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:31,203 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:32,231 INFO L134 CoverageAnalysis]: Checked inductivity of 114824 backedges. 20686 proven. 3307 refuted. 0 times theorem prover too weak. 90831 trivial. 0 not checked. [2018-12-09 04:32:32,246 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:32,247 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 47] total 70 [2018-12-09 04:32:32,247 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-12-09 04:32:32,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-12-09 04:32:32,247 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1003, Invalid=3827, Unknown=0, NotChecked=0, Total=4830 [2018-12-09 04:32:32,248 INFO L87 Difference]: Start difference. First operand 1462 states and 1473 transitions. Second operand 70 states. [2018-12-09 04:32:33,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:33,508 INFO L93 Difference]: Finished difference Result 1601 states and 1613 transitions. [2018-12-09 04:32:33,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-09 04:32:33,509 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1255 [2018-12-09 04:32:33,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:33,511 INFO L225 Difference]: With dead ends: 1601 [2018-12-09 04:32:33,511 INFO L226 Difference]: Without dead ends: 1601 [2018-12-09 04:32:33,512 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1339 GetRequests, 1230 SyntacticMatches, 0 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2291 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=2733, Invalid=9477, Unknown=0, NotChecked=0, Total=12210 [2018-12-09 04:32:33,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1601 states. [2018-12-09 04:32:33,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1601 to 1573. [2018-12-09 04:32:33,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1573 states. [2018-12-09 04:32:33,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1573 states to 1573 states and 1585 transitions. [2018-12-09 04:32:33,522 INFO L78 Accepts]: Start accepts. Automaton has 1573 states and 1585 transitions. Word has length 1255 [2018-12-09 04:32:33,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:33,522 INFO L480 AbstractCegarLoop]: Abstraction has 1573 states and 1585 transitions. [2018-12-09 04:32:33,522 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-12-09 04:32:33,522 INFO L276 IsEmpty]: Start isEmpty. Operand 1573 states and 1585 transitions. [2018-12-09 04:32:33,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1362 [2018-12-09 04:32:33,530 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:33,530 INFO L402 BasicCegarLoop]: trace histogram [229, 229, 228, 228, 228, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:33,530 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:33,530 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:33,530 INFO L82 PathProgramCache]: Analyzing trace with hash 945394430, now seen corresponding path program 41 times [2018-12-09 04:32:33,530 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:33,530 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:33,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:33,531 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:33,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:33,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:34,578 INFO L134 CoverageAnalysis]: Checked inductivity of 136363 backedges. 41194 proven. 4255 refuted. 0 times theorem prover too weak. 90914 trivial. 0 not checked. [2018-12-09 04:32:34,578 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:34,578 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:34,584 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:32:36,445 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2018-12-09 04:32:36,445 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:36,464 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:37,429 INFO L134 CoverageAnalysis]: Checked inductivity of 136363 backedges. 41186 proven. 5197 refuted. 0 times theorem prover too weak. 89980 trivial. 0 not checked. [2018-12-09 04:32:37,449 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:37,449 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 71 [2018-12-09 04:32:37,449 INFO L459 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-12-09 04:32:37,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-12-09 04:32:37,450 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=924, Invalid=4046, Unknown=0, NotChecked=0, Total=4970 [2018-12-09 04:32:37,450 INFO L87 Difference]: Start difference. First operand 1573 states and 1585 transitions. Second operand 71 states. [2018-12-09 04:32:38,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:38,685 INFO L93 Difference]: Finished difference Result 1602 states and 1612 transitions. [2018-12-09 04:32:38,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-12-09 04:32:38,685 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 1361 [2018-12-09 04:32:38,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:38,688 INFO L225 Difference]: With dead ends: 1602 [2018-12-09 04:32:38,688 INFO L226 Difference]: Without dead ends: 1596 [2018-12-09 04:32:38,689 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1451 GetRequests, 1338 SyntacticMatches, 0 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4088 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2818, Invalid=10292, Unknown=0, NotChecked=0, Total=13110 [2018-12-09 04:32:38,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1596 states. [2018-12-09 04:32:38,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1596 to 1573. [2018-12-09 04:32:38,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1573 states. [2018-12-09 04:32:38,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1573 states to 1573 states and 1583 transitions. [2018-12-09 04:32:38,696 INFO L78 Accepts]: Start accepts. Automaton has 1573 states and 1583 transitions. Word has length 1361 [2018-12-09 04:32:38,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:38,697 INFO L480 AbstractCegarLoop]: Abstraction has 1573 states and 1583 transitions. [2018-12-09 04:32:38,697 INFO L481 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-12-09 04:32:38,697 INFO L276 IsEmpty]: Start isEmpty. Operand 1573 states and 1583 transitions. [2018-12-09 04:32:38,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1367 [2018-12-09 04:32:38,706 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:38,706 INFO L402 BasicCegarLoop]: trace histogram [230, 230, 229, 229, 229, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:38,706 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:38,706 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:38,707 INFO L82 PathProgramCache]: Analyzing trace with hash -1625873879, now seen corresponding path program 42 times [2018-12-09 04:32:38,707 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:38,707 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:38,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:38,707 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:38,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:38,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:39,859 INFO L134 CoverageAnalysis]: Checked inductivity of 137525 backedges. 21945 proven. 1010 refuted. 0 times theorem prover too weak. 114570 trivial. 0 not checked. [2018-12-09 04:32:39,859 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:39,859 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:39,866 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:32:40,956 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 41 check-sat command(s) [2018-12-09 04:32:40,956 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:40,968 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:40,971 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:32:40,973 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:32:40,979 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:32:40,979 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:32:40,985 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:32:40,997 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:32:40,997 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:32:43,131 INFO L134 CoverageAnalysis]: Checked inductivity of 137525 backedges. 21945 proven. 1010 refuted. 0 times theorem prover too weak. 114570 trivial. 0 not checked. [2018-12-09 04:32:43,148 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:43,148 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26] total 27 [2018-12-09 04:32:43,149 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-09 04:32:43,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-09 04:32:43,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=445, Unknown=0, NotChecked=0, Total=756 [2018-12-09 04:32:43,149 INFO L87 Difference]: Start difference. First operand 1573 states and 1583 transitions. Second operand 28 states. [2018-12-09 04:32:43,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:43,660 INFO L93 Difference]: Finished difference Result 1604 states and 1615 transitions. [2018-12-09 04:32:43,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-12-09 04:32:43,660 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 1366 [2018-12-09 04:32:43,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:43,662 INFO L225 Difference]: With dead ends: 1604 [2018-12-09 04:32:43,662 INFO L226 Difference]: Without dead ends: 1604 [2018-12-09 04:32:43,662 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1411 GetRequests, 1324 SyntacticMatches, 40 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 369 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=858, Invalid=1494, Unknown=0, NotChecked=0, Total=2352 [2018-12-09 04:32:43,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1604 states. [2018-12-09 04:32:43,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1604 to 1578. [2018-12-09 04:32:43,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1578 states. [2018-12-09 04:32:43,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 1589 transitions. [2018-12-09 04:32:43,669 INFO L78 Accepts]: Start accepts. Automaton has 1578 states and 1589 transitions. Word has length 1366 [2018-12-09 04:32:43,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:43,670 INFO L480 AbstractCegarLoop]: Abstraction has 1578 states and 1589 transitions. [2018-12-09 04:32:43,670 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-09 04:32:43,670 INFO L276 IsEmpty]: Start isEmpty. Operand 1578 states and 1589 transitions. [2018-12-09 04:32:43,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1372 [2018-12-09 04:32:43,677 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:43,677 INFO L402 BasicCegarLoop]: trace histogram [231, 231, 230, 230, 230, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:43,677 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:43,677 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:43,677 INFO L82 PathProgramCache]: Analyzing trace with hash 2139417604, now seen corresponding path program 43 times [2018-12-09 04:32:43,677 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:43,677 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:43,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:43,678 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:43,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:43,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:44,681 INFO L134 CoverageAnalysis]: Checked inductivity of 138692 backedges. 24081 proven. 1105 refuted. 0 times theorem prover too weak. 113506 trivial. 0 not checked. [2018-12-09 04:32:44,681 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:44,681 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:44,687 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:32:44,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:44,889 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:45,908 INFO L134 CoverageAnalysis]: Checked inductivity of 138692 backedges. 24122 proven. 1064 refuted. 0 times theorem prover too weak. 113506 trivial. 0 not checked. [2018-12-09 04:32:45,923 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:45,924 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 45] total 69 [2018-12-09 04:32:45,924 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-12-09 04:32:45,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-12-09 04:32:45,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1082, Invalid=3610, Unknown=0, NotChecked=0, Total=4692 [2018-12-09 04:32:45,925 INFO L87 Difference]: Start difference. First operand 1578 states and 1589 transitions. Second operand 69 states. [2018-12-09 04:32:47,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:47,237 INFO L93 Difference]: Finished difference Result 1722 states and 1734 transitions. [2018-12-09 04:32:47,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-12-09 04:32:47,237 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1371 [2018-12-09 04:32:47,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:47,241 INFO L225 Difference]: With dead ends: 1722 [2018-12-09 04:32:47,241 INFO L226 Difference]: Without dead ends: 1722 [2018-12-09 04:32:47,242 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1457 GetRequests, 1349 SyntacticMatches, 0 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2009 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3047, Invalid=8943, Unknown=0, NotChecked=0, Total=11990 [2018-12-09 04:32:47,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1722 states. [2018-12-09 04:32:47,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1722 to 1694. [2018-12-09 04:32:47,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1694 states. [2018-12-09 04:32:47,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1694 states to 1694 states and 1706 transitions. [2018-12-09 04:32:47,251 INFO L78 Accepts]: Start accepts. Automaton has 1694 states and 1706 transitions. Word has length 1371 [2018-12-09 04:32:47,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:47,252 INFO L480 AbstractCegarLoop]: Abstraction has 1694 states and 1706 transitions. [2018-12-09 04:32:47,252 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-12-09 04:32:47,252 INFO L276 IsEmpty]: Start isEmpty. Operand 1694 states and 1706 transitions. [2018-12-09 04:32:47,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1483 [2018-12-09 04:32:47,261 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:47,262 INFO L402 BasicCegarLoop]: trace histogram [251, 251, 250, 250, 250, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:47,262 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:47,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:47,262 INFO L82 PathProgramCache]: Analyzing trace with hash 781243404, now seen corresponding path program 44 times [2018-12-09 04:32:47,263 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:47,263 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:47,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:47,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:32:47,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:47,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:48,503 INFO L134 CoverageAnalysis]: Checked inductivity of 163545 backedges. 65297 proven. 3147 refuted. 0 times theorem prover too weak. 95101 trivial. 0 not checked. [2018-12-09 04:32:48,503 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:48,503 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:48,509 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:32:48,725 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:32:48,725 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:48,737 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:49,988 INFO L134 CoverageAnalysis]: Checked inductivity of 163545 backedges. 47937 proven. 970 refuted. 0 times theorem prover too weak. 114638 trivial. 0 not checked. [2018-12-09 04:32:50,003 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:50,004 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 44] total 87 [2018-12-09 04:32:50,004 INFO L459 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-12-09 04:32:50,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-12-09 04:32:50,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1222, Invalid=6260, Unknown=0, NotChecked=0, Total=7482 [2018-12-09 04:32:50,005 INFO L87 Difference]: Start difference. First operand 1694 states and 1706 transitions. Second operand 87 states. [2018-12-09 04:32:52,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:52,696 INFO L93 Difference]: Finished difference Result 1723 states and 1733 transitions. [2018-12-09 04:32:52,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-12-09 04:32:52,696 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 1482 [2018-12-09 04:32:52,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:52,698 INFO L225 Difference]: With dead ends: 1723 [2018-12-09 04:32:52,698 INFO L226 Difference]: Without dead ends: 1717 [2018-12-09 04:32:52,699 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1591 GetRequests, 1445 SyntacticMatches, 0 SemanticMatches, 146 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7223 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3479, Invalid=18277, Unknown=0, NotChecked=0, Total=21756 [2018-12-09 04:32:52,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1717 states. [2018-12-09 04:32:52,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1717 to 1694. [2018-12-09 04:32:52,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1694 states. [2018-12-09 04:32:52,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1694 states to 1694 states and 1704 transitions. [2018-12-09 04:32:52,706 INFO L78 Accepts]: Start accepts. Automaton has 1694 states and 1704 transitions. Word has length 1482 [2018-12-09 04:32:52,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:52,707 INFO L480 AbstractCegarLoop]: Abstraction has 1694 states and 1704 transitions. [2018-12-09 04:32:52,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-12-09 04:32:52,707 INFO L276 IsEmpty]: Start isEmpty. Operand 1694 states and 1704 transitions. [2018-12-09 04:32:52,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1488 [2018-12-09 04:32:52,716 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:52,716 INFO L402 BasicCegarLoop]: trace histogram [252, 252, 251, 251, 251, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:52,716 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:52,716 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:52,716 INFO L82 PathProgramCache]: Analyzing trace with hash 303144551, now seen corresponding path program 45 times [2018-12-09 04:32:52,716 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:52,716 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:52,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:52,717 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:52,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:52,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:54,029 INFO L134 CoverageAnalysis]: Checked inductivity of 164818 backedges. 25300 proven. 1113 refuted. 0 times theorem prover too weak. 138405 trivial. 0 not checked. [2018-12-09 04:32:54,029 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:54,029 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:54,035 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:32:54,480 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-12-09 04:32:54,480 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:54,491 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:32:54,492 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:32:54,497 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:32:54,510 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:32:54,510 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:32:54,515 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:32:54,521 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:32:54,521 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:32:57,010 INFO L134 CoverageAnalysis]: Checked inductivity of 164818 backedges. 25300 proven. 1113 refuted. 0 times theorem prover too weak. 138405 trivial. 0 not checked. [2018-12-09 04:32:57,026 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:32:57,026 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27] total 28 [2018-12-09 04:32:57,026 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-09 04:32:57,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-09 04:32:57,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=336, Invalid=476, Unknown=0, NotChecked=0, Total=812 [2018-12-09 04:32:57,027 INFO L87 Difference]: Start difference. First operand 1694 states and 1704 transitions. Second operand 29 states. [2018-12-09 04:32:57,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:32:57,563 INFO L93 Difference]: Finished difference Result 1725 states and 1736 transitions. [2018-12-09 04:32:57,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-09 04:32:57,563 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 1487 [2018-12-09 04:32:57,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:32:57,565 INFO L225 Difference]: With dead ends: 1725 [2018-12-09 04:32:57,565 INFO L226 Difference]: Without dead ends: 1725 [2018-12-09 04:32:57,566 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1534 GetRequests, 1443 SyntacticMatches, 42 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 398 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=931, Invalid=1619, Unknown=0, NotChecked=0, Total=2550 [2018-12-09 04:32:57,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1725 states. [2018-12-09 04:32:57,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1725 to 1699. [2018-12-09 04:32:57,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1699 states. [2018-12-09 04:32:57,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1699 states to 1699 states and 1710 transitions. [2018-12-09 04:32:57,574 INFO L78 Accepts]: Start accepts. Automaton has 1699 states and 1710 transitions. Word has length 1487 [2018-12-09 04:32:57,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:32:57,575 INFO L480 AbstractCegarLoop]: Abstraction has 1699 states and 1710 transitions. [2018-12-09 04:32:57,575 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-09 04:32:57,575 INFO L276 IsEmpty]: Start isEmpty. Operand 1699 states and 1710 transitions. [2018-12-09 04:32:57,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1493 [2018-12-09 04:32:57,583 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:32:57,584 INFO L402 BasicCegarLoop]: trace histogram [253, 253, 252, 252, 252, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:32:57,584 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:32:57,584 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:32:57,584 INFO L82 PathProgramCache]: Analyzing trace with hash -612079994, now seen corresponding path program 46 times [2018-12-09 04:32:57,584 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:32:57,584 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:32:57,584 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:57,584 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:32:57,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:32:57,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:32:58,724 INFO L134 CoverageAnalysis]: Checked inductivity of 166096 backedges. 27648 proven. 1223 refuted. 0 times theorem prover too weak. 137225 trivial. 0 not checked. [2018-12-09 04:32:58,724 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:32:58,724 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:32:58,730 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:32:58,918 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:32:58,918 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:32:58,930 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:33:00,180 INFO L134 CoverageAnalysis]: Checked inductivity of 166096 backedges. 27486 proven. 4014 refuted. 0 times theorem prover too weak. 134596 trivial. 0 not checked. [2018-12-09 04:33:00,196 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:33:00,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 51] total 76 [2018-12-09 04:33:00,197 INFO L459 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-12-09 04:33:00,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-12-09 04:33:00,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1189, Invalid=4511, Unknown=0, NotChecked=0, Total=5700 [2018-12-09 04:33:00,198 INFO L87 Difference]: Start difference. First operand 1699 states and 1710 transitions. Second operand 76 states. [2018-12-09 04:33:01,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:33:01,851 INFO L93 Difference]: Finished difference Result 1848 states and 1860 transitions. [2018-12-09 04:33:01,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-12-09 04:33:01,851 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1492 [2018-12-09 04:33:01,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:33:01,854 INFO L225 Difference]: With dead ends: 1848 [2018-12-09 04:33:01,854 INFO L226 Difference]: Without dead ends: 1848 [2018-12-09 04:33:01,855 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1584 GetRequests, 1465 SyntacticMatches, 0 SemanticMatches, 119 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2720 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3265, Invalid=11255, Unknown=0, NotChecked=0, Total=14520 [2018-12-09 04:33:01,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1848 states. [2018-12-09 04:33:01,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1848 to 1820. [2018-12-09 04:33:01,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1820 states. [2018-12-09 04:33:01,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1820 states to 1820 states and 1832 transitions. [2018-12-09 04:33:01,863 INFO L78 Accepts]: Start accepts. Automaton has 1820 states and 1832 transitions. Word has length 1492 [2018-12-09 04:33:01,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:33:01,863 INFO L480 AbstractCegarLoop]: Abstraction has 1820 states and 1832 transitions. [2018-12-09 04:33:01,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-12-09 04:33:01,863 INFO L276 IsEmpty]: Start isEmpty. Operand 1820 states and 1832 transitions. [2018-12-09 04:33:01,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1609 [2018-12-09 04:33:01,873 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:33:01,873 INFO L402 BasicCegarLoop]: trace histogram [274, 274, 273, 273, 273, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:33:01,873 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:33:01,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:33:01,874 INFO L82 PathProgramCache]: Analyzing trace with hash 1669692803, now seen corresponding path program 47 times [2018-12-09 04:33:01,874 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:33:01,874 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:33:01,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:01,874 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:33:01,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:01,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:03,256 INFO L134 CoverageAnalysis]: Checked inductivity of 194586 backedges. 54747 proven. 5154 refuted. 0 times theorem prover too weak. 134685 trivial. 0 not checked. [2018-12-09 04:33:03,256 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:33:03,256 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:33:03,263 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:33:07,382 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 49 check-sat command(s) [2018-12-09 04:33:07,382 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:33:07,407 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:33:08,606 INFO L134 CoverageAnalysis]: Checked inductivity of 194586 backedges. 54729 proven. 6313 refuted. 0 times theorem prover too weak. 133544 trivial. 0 not checked. [2018-12-09 04:33:08,627 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:33:08,627 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 77 [2018-12-09 04:33:08,628 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-12-09 04:33:08,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-12-09 04:33:08,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1100, Invalid=4752, Unknown=0, NotChecked=0, Total=5852 [2018-12-09 04:33:08,628 INFO L87 Difference]: Start difference. First operand 1820 states and 1832 transitions. Second operand 77 states. [2018-12-09 04:33:10,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:33:10,585 INFO L93 Difference]: Finished difference Result 1849 states and 1859 transitions. [2018-12-09 04:33:10,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-12-09 04:33:10,586 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1608 [2018-12-09 04:33:10,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:33:10,591 INFO L225 Difference]: With dead ends: 1849 [2018-12-09 04:33:10,591 INFO L226 Difference]: Without dead ends: 1843 [2018-12-09 04:33:10,593 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1706 GetRequests, 1583 SyntacticMatches, 0 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4915 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3335, Invalid=12165, Unknown=0, NotChecked=0, Total=15500 [2018-12-09 04:33:10,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1843 states. [2018-12-09 04:33:10,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1843 to 1820. [2018-12-09 04:33:10,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1820 states. [2018-12-09 04:33:10,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1820 states to 1820 states and 1830 transitions. [2018-12-09 04:33:10,612 INFO L78 Accepts]: Start accepts. Automaton has 1820 states and 1830 transitions. Word has length 1608 [2018-12-09 04:33:10,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:33:10,613 INFO L480 AbstractCegarLoop]: Abstraction has 1820 states and 1830 transitions. [2018-12-09 04:33:10,613 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-12-09 04:33:10,613 INFO L276 IsEmpty]: Start isEmpty. Operand 1820 states and 1830 transitions. [2018-12-09 04:33:10,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1614 [2018-12-09 04:33:10,633 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:33:10,633 INFO L402 BasicCegarLoop]: trace histogram [275, 275, 274, 274, 274, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:33:10,633 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:33:10,633 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:33:10,633 INFO L82 PathProgramCache]: Analyzing trace with hash 1280506436, now seen corresponding path program 48 times [2018-12-09 04:33:10,634 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:33:10,634 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:33:10,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:10,634 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:33:10,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:10,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:12,108 INFO L134 CoverageAnalysis]: Checked inductivity of 195975 backedges. 28980 proven. 1221 refuted. 0 times theorem prover too weak. 165774 trivial. 0 not checked. [2018-12-09 04:33:12,108 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:33:12,108 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:33:12,115 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:33:14,607 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 45 check-sat command(s) [2018-12-09 04:33:14,607 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:33:14,624 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:33:14,626 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:33:14,629 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:33:14,633 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:33:14,633 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:33:14,641 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:33:14,650 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:33:14,650 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:33:17,440 INFO L134 CoverageAnalysis]: Checked inductivity of 195975 backedges. 28980 proven. 1221 refuted. 0 times theorem prover too weak. 165774 trivial. 0 not checked. [2018-12-09 04:33:17,459 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:33:17,459 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28] total 29 [2018-12-09 04:33:17,459 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-09 04:33:17,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-09 04:33:17,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=508, Unknown=0, NotChecked=0, Total=870 [2018-12-09 04:33:17,460 INFO L87 Difference]: Start difference. First operand 1820 states and 1830 transitions. Second operand 30 states. [2018-12-09 04:33:18,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:33:18,025 INFO L93 Difference]: Finished difference Result 1851 states and 1862 transitions. [2018-12-09 04:33:18,025 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-12-09 04:33:18,025 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 1613 [2018-12-09 04:33:18,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:33:18,028 INFO L225 Difference]: With dead ends: 1851 [2018-12-09 04:33:18,029 INFO L226 Difference]: Without dead ends: 1851 [2018-12-09 04:33:18,029 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1662 GetRequests, 1567 SyntacticMatches, 44 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 428 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1007, Invalid=1749, Unknown=0, NotChecked=0, Total=2756 [2018-12-09 04:33:18,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1851 states. [2018-12-09 04:33:18,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1851 to 1825. [2018-12-09 04:33:18,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1825 states. [2018-12-09 04:33:18,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1825 states to 1825 states and 1836 transitions. [2018-12-09 04:33:18,038 INFO L78 Accepts]: Start accepts. Automaton has 1825 states and 1836 transitions. Word has length 1613 [2018-12-09 04:33:18,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:33:18,039 INFO L480 AbstractCegarLoop]: Abstraction has 1825 states and 1836 transitions. [2018-12-09 04:33:18,039 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-09 04:33:18,039 INFO L276 IsEmpty]: Start isEmpty. Operand 1825 states and 1836 transitions. [2018-12-09 04:33:18,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1619 [2018-12-09 04:33:18,050 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:33:18,051 INFO L402 BasicCegarLoop]: trace histogram [276, 276, 275, 275, 275, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:33:18,051 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:33:18,051 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:33:18,051 INFO L82 PathProgramCache]: Analyzing trace with hash -1543312183, now seen corresponding path program 49 times [2018-12-09 04:33:18,051 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:33:18,051 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:33:18,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:18,052 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:33:18,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:18,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:19,358 INFO L134 CoverageAnalysis]: Checked inductivity of 197369 backedges. 31550 proven. 1347 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2018-12-09 04:33:19,358 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:33:19,358 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:33:19,364 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:33:19,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:19,602 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:33:20,928 INFO L134 CoverageAnalysis]: Checked inductivity of 197369 backedges. 31595 proven. 1302 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2018-12-09 04:33:20,944 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:33:20,944 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49] total 75 [2018-12-09 04:33:20,945 INFO L459 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-12-09 04:33:20,945 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-12-09 04:33:20,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1276, Invalid=4274, Unknown=0, NotChecked=0, Total=5550 [2018-12-09 04:33:20,945 INFO L87 Difference]: Start difference. First operand 1825 states and 1836 transitions. Second operand 75 states. [2018-12-09 04:33:22,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:33:22,280 INFO L93 Difference]: Finished difference Result 1979 states and 1991 transitions. [2018-12-09 04:33:22,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-12-09 04:33:22,280 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 1618 [2018-12-09 04:33:22,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:33:22,283 INFO L225 Difference]: With dead ends: 1979 [2018-12-09 04:33:22,283 INFO L226 Difference]: Without dead ends: 1979 [2018-12-09 04:33:22,283 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1712 GetRequests, 1594 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2408 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3613, Invalid=10667, Unknown=0, NotChecked=0, Total=14280 [2018-12-09 04:33:22,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1979 states. [2018-12-09 04:33:22,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1979 to 1951. [2018-12-09 04:33:22,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1951 states. [2018-12-09 04:33:22,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1951 states to 1951 states and 1963 transitions. [2018-12-09 04:33:22,291 INFO L78 Accepts]: Start accepts. Automaton has 1951 states and 1963 transitions. Word has length 1618 [2018-12-09 04:33:22,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:33:22,292 INFO L480 AbstractCegarLoop]: Abstraction has 1951 states and 1963 transitions. [2018-12-09 04:33:22,292 INFO L481 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-12-09 04:33:22,292 INFO L276 IsEmpty]: Start isEmpty. Operand 1951 states and 1963 transitions. [2018-12-09 04:33:22,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1740 [2018-12-09 04:33:22,303 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:33:22,303 INFO L402 BasicCegarLoop]: trace histogram [298, 298, 297, 297, 297, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:33:22,303 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:33:22,303 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:33:22,304 INFO L82 PathProgramCache]: Analyzing trace with hash -389187577, now seen corresponding path program 50 times [2018-12-09 04:33:22,304 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:33:22,304 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:33:22,304 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:22,304 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:33:22,304 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:22,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:23,921 INFO L134 CoverageAnalysis]: Checked inductivity of 229834 backedges. 86262 proven. 3792 refuted. 0 times theorem prover too weak. 139780 trivial. 0 not checked. [2018-12-09 04:33:23,921 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:33:23,921 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:33:23,927 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:33:24,184 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:33:24,184 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:33:24,198 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:33:25,831 INFO L134 CoverageAnalysis]: Checked inductivity of 229834 backedges. 62830 proven. 1177 refuted. 0 times theorem prover too weak. 165827 trivial. 0 not checked. [2018-12-09 04:33:25,847 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:33:25,847 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 48] total 95 [2018-12-09 04:33:25,848 INFO L459 AbstractCegarLoop]: Interpolant automaton has 95 states [2018-12-09 04:33:25,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2018-12-09 04:33:25,848 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1453, Invalid=7477, Unknown=0, NotChecked=0, Total=8930 [2018-12-09 04:33:25,849 INFO L87 Difference]: Start difference. First operand 1951 states and 1963 transitions. Second operand 95 states. [2018-12-09 04:33:28,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:33:28,509 INFO L93 Difference]: Finished difference Result 1980 states and 1990 transitions. [2018-12-09 04:33:28,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-12-09 04:33:28,509 INFO L78 Accepts]: Start accepts. Automaton has 95 states. Word has length 1739 [2018-12-09 04:33:28,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:33:28,511 INFO L225 Difference]: With dead ends: 1980 [2018-12-09 04:33:28,511 INFO L226 Difference]: Without dead ends: 1974 [2018-12-09 04:33:28,513 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1858 GetRequests, 1698 SyntacticMatches, 0 SemanticMatches, 160 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8760 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=4133, Invalid=21949, Unknown=0, NotChecked=0, Total=26082 [2018-12-09 04:33:28,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1974 states. [2018-12-09 04:33:28,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1974 to 1951. [2018-12-09 04:33:28,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1951 states. [2018-12-09 04:33:28,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1951 states to 1951 states and 1961 transitions. [2018-12-09 04:33:28,524 INFO L78 Accepts]: Start accepts. Automaton has 1951 states and 1961 transitions. Word has length 1739 [2018-12-09 04:33:28,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:33:28,524 INFO L480 AbstractCegarLoop]: Abstraction has 1951 states and 1961 transitions. [2018-12-09 04:33:28,524 INFO L481 AbstractCegarLoop]: Interpolant automaton has 95 states. [2018-12-09 04:33:28,524 INFO L276 IsEmpty]: Start isEmpty. Operand 1951 states and 1961 transitions. [2018-12-09 04:33:28,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1745 [2018-12-09 04:33:28,535 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:33:28,535 INFO L402 BasicCegarLoop]: trace histogram [299, 299, 298, 298, 298, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:33:28,536 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:33:28,536 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:33:28,536 INFO L82 PathProgramCache]: Analyzing trace with hash 2087778252, now seen corresponding path program 51 times [2018-12-09 04:33:28,536 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:33:28,536 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:33:28,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:28,536 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:33:28,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:28,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:30,183 INFO L134 CoverageAnalysis]: Checked inductivity of 231344 backedges. 33000 proven. 1334 refuted. 0 times theorem prover too weak. 197010 trivial. 0 not checked. [2018-12-09 04:33:30,183 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:33:30,183 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:33:30,191 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:33:30,967 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-12-09 04:33:30,967 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:33:30,980 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:33:30,983 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:33:30,985 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:33:30,991 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:33:30,991 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:33:30,996 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:33:31,015 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:33:31,015 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:33:34,374 INFO L134 CoverageAnalysis]: Checked inductivity of 231344 backedges. 33000 proven. 1334 refuted. 0 times theorem prover too weak. 197010 trivial. 0 not checked. [2018-12-09 04:33:34,390 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:33:34,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29] total 30 [2018-12-09 04:33:34,391 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-09 04:33:34,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-09 04:33:34,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=389, Invalid=541, Unknown=0, NotChecked=0, Total=930 [2018-12-09 04:33:34,391 INFO L87 Difference]: Start difference. First operand 1951 states and 1961 transitions. Second operand 31 states. [2018-12-09 04:33:34,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:33:34,984 INFO L93 Difference]: Finished difference Result 1982 states and 1993 transitions. [2018-12-09 04:33:34,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-09 04:33:34,985 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 1744 [2018-12-09 04:33:34,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:33:34,987 INFO L225 Difference]: With dead ends: 1982 [2018-12-09 04:33:34,987 INFO L226 Difference]: Without dead ends: 1982 [2018-12-09 04:33:34,987 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1795 GetRequests, 1696 SyntacticMatches, 46 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 459 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1086, Invalid=1884, Unknown=0, NotChecked=0, Total=2970 [2018-12-09 04:33:34,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1982 states. [2018-12-09 04:33:34,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1982 to 1956. [2018-12-09 04:33:34,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1956 states. [2018-12-09 04:33:34,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1956 states to 1956 states and 1967 transitions. [2018-12-09 04:33:34,995 INFO L78 Accepts]: Start accepts. Automaton has 1956 states and 1967 transitions. Word has length 1744 [2018-12-09 04:33:34,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:33:34,996 INFO L480 AbstractCegarLoop]: Abstraction has 1956 states and 1967 transitions. [2018-12-09 04:33:34,996 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-09 04:33:34,996 INFO L276 IsEmpty]: Start isEmpty. Operand 1956 states and 1967 transitions. [2018-12-09 04:33:35,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1750 [2018-12-09 04:33:35,007 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:33:35,007 INFO L402 BasicCegarLoop]: trace histogram [300, 300, 299, 299, 299, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:33:35,007 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:33:35,007 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:33:35,008 INFO L82 PathProgramCache]: Analyzing trace with hash -1607588799, now seen corresponding path program 52 times [2018-12-09 04:33:35,008 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:33:35,008 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:33:35,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:35,008 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:33:35,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:35,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:36,446 INFO L134 CoverageAnalysis]: Checked inductivity of 232859 backedges. 35802 proven. 1477 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2018-12-09 04:33:36,446 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:33:36,446 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:33:36,453 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:33:36,674 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:33:36,674 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:33:36,688 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:33:38,247 INFO L134 CoverageAnalysis]: Checked inductivity of 232859 backedges. 35626 proven. 4789 refuted. 0 times theorem prover too weak. 192444 trivial. 0 not checked. [2018-12-09 04:33:38,264 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:33:38,264 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 55] total 82 [2018-12-09 04:33:38,264 INFO L459 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-12-09 04:33:38,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-12-09 04:33:38,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1391, Invalid=5251, Unknown=0, NotChecked=0, Total=6642 [2018-12-09 04:33:38,265 INFO L87 Difference]: Start difference. First operand 1956 states and 1967 transitions. Second operand 82 states. [2018-12-09 04:33:39,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:33:39,697 INFO L93 Difference]: Finished difference Result 2115 states and 2127 transitions. [2018-12-09 04:33:39,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-12-09 04:33:39,697 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 1749 [2018-12-09 04:33:39,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:33:39,700 INFO L225 Difference]: With dead ends: 2115 [2018-12-09 04:33:39,700 INFO L226 Difference]: Without dead ends: 2115 [2018-12-09 04:33:39,701 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1849 GetRequests, 1720 SyntacticMatches, 0 SemanticMatches, 129 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3185 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3845, Invalid=13185, Unknown=0, NotChecked=0, Total=17030 [2018-12-09 04:33:39,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2115 states. [2018-12-09 04:33:39,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2115 to 2087. [2018-12-09 04:33:39,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2087 states. [2018-12-09 04:33:39,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2087 states to 2087 states and 2099 transitions. [2018-12-09 04:33:39,710 INFO L78 Accepts]: Start accepts. Automaton has 2087 states and 2099 transitions. Word has length 1749 [2018-12-09 04:33:39,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:33:39,711 INFO L480 AbstractCegarLoop]: Abstraction has 2087 states and 2099 transitions. [2018-12-09 04:33:39,711 INFO L481 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-12-09 04:33:39,711 INFO L276 IsEmpty]: Start isEmpty. Operand 2087 states and 2099 transitions. [2018-12-09 04:33:39,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1876 [2018-12-09 04:33:39,724 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:33:39,724 INFO L402 BasicCegarLoop]: trace histogram [323, 323, 322, 322, 322, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:33:39,725 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:33:39,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:33:39,725 INFO L82 PathProgramCache]: Analyzing trace with hash 1904395870, now seen corresponding path program 53 times [2018-12-09 04:33:39,725 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:33:39,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:33:39,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:39,725 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:33:39,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:39,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:41,403 INFO L134 CoverageAnalysis]: Checked inductivity of 269652 backedges. 70976 proven. 6137 refuted. 0 times theorem prover too weak. 192539 trivial. 0 not checked. [2018-12-09 04:33:41,403 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:33:41,403 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:33:41,410 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:33:45,905 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 52 check-sat command(s) [2018-12-09 04:33:45,906 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:33:45,944 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:33:47,446 INFO L134 CoverageAnalysis]: Checked inductivity of 269652 backedges. 70948 proven. 7533 refuted. 0 times theorem prover too weak. 191171 trivial. 0 not checked. [2018-12-09 04:33:47,468 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:33:47,469 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 83 [2018-12-09 04:33:47,469 INFO L459 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-12-09 04:33:47,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-12-09 04:33:47,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1292, Invalid=5514, Unknown=0, NotChecked=0, Total=6806 [2018-12-09 04:33:47,470 INFO L87 Difference]: Start difference. First operand 2087 states and 2099 transitions. Second operand 83 states. [2018-12-09 04:33:49,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:33:49,008 INFO L93 Difference]: Finished difference Result 2116 states and 2126 transitions. [2018-12-09 04:33:49,009 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-09 04:33:49,009 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 1875 [2018-12-09 04:33:49,009 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:33:49,011 INFO L225 Difference]: With dead ends: 2116 [2018-12-09 04:33:49,011 INFO L226 Difference]: Without dead ends: 2110 [2018-12-09 04:33:49,012 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1981 GetRequests, 1848 SyntacticMatches, 0 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5818 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3896, Invalid=14194, Unknown=0, NotChecked=0, Total=18090 [2018-12-09 04:33:49,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2110 states. [2018-12-09 04:33:49,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2110 to 2087. [2018-12-09 04:33:49,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2087 states. [2018-12-09 04:33:49,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2087 states to 2087 states and 2097 transitions. [2018-12-09 04:33:49,023 INFO L78 Accepts]: Start accepts. Automaton has 2087 states and 2097 transitions. Word has length 1875 [2018-12-09 04:33:49,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:33:49,024 INFO L480 AbstractCegarLoop]: Abstraction has 2087 states and 2097 transitions. [2018-12-09 04:33:49,024 INFO L481 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-12-09 04:33:49,024 INFO L276 IsEmpty]: Start isEmpty. Operand 2087 states and 2097 transitions. [2018-12-09 04:33:49,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1881 [2018-12-09 04:33:49,043 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:33:49,043 INFO L402 BasicCegarLoop]: trace histogram [324, 324, 323, 323, 323, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:33:49,043 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:33:49,043 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:33:49,044 INFO L82 PathProgramCache]: Analyzing trace with hash -763782711, now seen corresponding path program 54 times [2018-12-09 04:33:49,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:33:49,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:33:49,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:49,044 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:33:49,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:33:49,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:33:50,876 INFO L134 CoverageAnalysis]: Checked inductivity of 271288 backedges. 37375 proven. 1452 refuted. 0 times theorem prover too weak. 232461 trivial. 0 not checked. [2018-12-09 04:33:50,877 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:33:50,877 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:33:50,883 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:34:19,438 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-12-09 04:34:19,438 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:34:19,480 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:34:19,482 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:34:19,487 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:34:19,499 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:34:19,499 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:34:19,508 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:34:19,515 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:34:19,515 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:34:24,423 INFO L134 CoverageAnalysis]: Checked inductivity of 271288 backedges. 68387 proven. 5213 refuted. 0 times theorem prover too weak. 197688 trivial. 0 not checked. [2018-12-09 04:34:24,446 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:34:24,446 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 43] total 68 [2018-12-09 04:34:24,447 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-12-09 04:34:24,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-12-09 04:34:24,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1150, Invalid=3542, Unknown=0, NotChecked=0, Total=4692 [2018-12-09 04:34:24,447 INFO L87 Difference]: Start difference. First operand 2087 states and 2097 transitions. Second operand 69 states. [2018-12-09 04:34:28,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:34:28,228 INFO L93 Difference]: Finished difference Result 2125 states and 2137 transitions. [2018-12-09 04:34:28,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-12-09 04:34:28,228 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1880 [2018-12-09 04:34:28,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:34:28,231 INFO L225 Difference]: With dead ends: 2125 [2018-12-09 04:34:28,231 INFO L226 Difference]: Without dead ends: 2125 [2018-12-09 04:34:28,232 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1965 GetRequests, 1797 SyntacticMatches, 46 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5393 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=4070, Invalid=11182, Unknown=0, NotChecked=0, Total=15252 [2018-12-09 04:34:28,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2125 states. [2018-12-09 04:34:28,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2125 to 2092. [2018-12-09 04:34:28,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2092 states. [2018-12-09 04:34:28,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2092 states to 2092 states and 2103 transitions. [2018-12-09 04:34:28,241 INFO L78 Accepts]: Start accepts. Automaton has 2092 states and 2103 transitions. Word has length 1880 [2018-12-09 04:34:28,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:34:28,242 INFO L480 AbstractCegarLoop]: Abstraction has 2092 states and 2103 transitions. [2018-12-09 04:34:28,243 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-12-09 04:34:28,243 INFO L276 IsEmpty]: Start isEmpty. Operand 2092 states and 2103 transitions. [2018-12-09 04:34:28,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1886 [2018-12-09 04:34:28,256 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:34:28,257 INFO L402 BasicCegarLoop]: trace histogram [325, 325, 324, 324, 324, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:34:28,257 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:34:28,257 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:34:28,257 INFO L82 PathProgramCache]: Analyzing trace with hash 991705188, now seen corresponding path program 55 times [2018-12-09 04:34:28,257 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:34:28,257 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:34:28,258 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:28,258 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:34:28,258 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:28,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:34:29,893 INFO L134 CoverageAnalysis]: Checked inductivity of 272929 backedges. 40419 proven. 1613 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2018-12-09 04:34:29,893 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:34:29,893 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:34:29,899 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:34:30,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:34:30,183 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:34:31,812 INFO L134 CoverageAnalysis]: Checked inductivity of 272929 backedges. 40468 proven. 1564 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2018-12-09 04:34:31,828 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:34:31,829 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53] total 81 [2018-12-09 04:34:31,829 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-12-09 04:34:31,829 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-12-09 04:34:31,830 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1486, Invalid=4994, Unknown=0, NotChecked=0, Total=6480 [2018-12-09 04:34:31,830 INFO L87 Difference]: Start difference. First operand 2092 states and 2103 transitions. Second operand 81 states. [2018-12-09 04:34:33,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:34:33,613 INFO L93 Difference]: Finished difference Result 2256 states and 2268 transitions. [2018-12-09 04:34:33,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-09 04:34:33,614 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 1885 [2018-12-09 04:34:33,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:34:33,617 INFO L225 Difference]: With dead ends: 2256 [2018-12-09 04:34:33,617 INFO L226 Difference]: Without dead ends: 2256 [2018-12-09 04:34:33,618 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1987 GetRequests, 1859 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2843 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=4227, Invalid=12543, Unknown=0, NotChecked=0, Total=16770 [2018-12-09 04:34:33,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2256 states. [2018-12-09 04:34:33,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2256 to 2228. [2018-12-09 04:34:33,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2228 states. [2018-12-09 04:34:33,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2228 states to 2228 states and 2240 transitions. [2018-12-09 04:34:33,628 INFO L78 Accepts]: Start accepts. Automaton has 2228 states and 2240 transitions. Word has length 1885 [2018-12-09 04:34:33,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:34:33,629 INFO L480 AbstractCegarLoop]: Abstraction has 2228 states and 2240 transitions. [2018-12-09 04:34:33,629 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-12-09 04:34:33,629 INFO L276 IsEmpty]: Start isEmpty. Operand 2228 states and 2240 transitions. [2018-12-09 04:34:33,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2017 [2018-12-09 04:34:33,644 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:34:33,645 INFO L402 BasicCegarLoop]: trace histogram [349, 349, 348, 348, 348, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:34:33,645 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:34:33,645 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:34:33,646 INFO L82 PathProgramCache]: Analyzing trace with hash 924657132, now seen corresponding path program 56 times [2018-12-09 04:34:33,646 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:34:33,646 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:34:33,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:33,646 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:34:33,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:33,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:34:35,713 INFO L134 CoverageAnalysis]: Checked inductivity of 314418 backedges. 41992 proven. 1575 refuted. 0 times theorem prover too weak. 270851 trivial. 0 not checked. [2018-12-09 04:34:35,714 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:34:35,714 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:34:35,719 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:34:36,049 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:34:36,049 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:34:36,066 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:34:38,069 INFO L134 CoverageAnalysis]: Checked inductivity of 314418 backedges. 80519 proven. 1404 refuted. 0 times theorem prover too weak. 232495 trivial. 0 not checked. [2018-12-09 04:34:38,085 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:34:38,085 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 52] total 81 [2018-12-09 04:34:38,086 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-12-09 04:34:38,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-12-09 04:34:38,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1062, Invalid=5418, Unknown=0, NotChecked=0, Total=6480 [2018-12-09 04:34:38,086 INFO L87 Difference]: Start difference. First operand 2228 states and 2240 transitions. Second operand 81 states. [2018-12-09 04:34:42,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:34:42,325 INFO L93 Difference]: Finished difference Result 2265 states and 2276 transitions. [2018-12-09 04:34:42,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-12-09 04:34:42,326 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 2016 [2018-12-09 04:34:42,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:34:42,330 INFO L225 Difference]: With dead ends: 2265 [2018-12-09 04:34:42,330 INFO L226 Difference]: Without dead ends: 2259 [2018-12-09 04:34:42,332 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2118 GetRequests, 1966 SyntacticMatches, 0 SemanticMatches, 152 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6005 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=4057, Invalid=19505, Unknown=0, NotChecked=0, Total=23562 [2018-12-09 04:34:42,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2259 states. [2018-12-09 04:34:42,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2259 to 2233. [2018-12-09 04:34:42,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2233 states. [2018-12-09 04:34:42,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2233 states to 2233 states and 2244 transitions. [2018-12-09 04:34:42,349 INFO L78 Accepts]: Start accepts. Automaton has 2233 states and 2244 transitions. Word has length 2016 [2018-12-09 04:34:42,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:34:42,350 INFO L480 AbstractCegarLoop]: Abstraction has 2233 states and 2244 transitions. [2018-12-09 04:34:42,351 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-12-09 04:34:42,351 INFO L276 IsEmpty]: Start isEmpty. Operand 2233 states and 2244 transitions. [2018-12-09 04:34:42,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2027 [2018-12-09 04:34:42,370 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:34:42,370 INFO L402 BasicCegarLoop]: trace histogram [351, 351, 350, 350, 350, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:34:42,370 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:34:42,370 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:34:42,371 INFO L82 PathProgramCache]: Analyzing trace with hash -1291341978, now seen corresponding path program 57 times [2018-12-09 04:34:42,371 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:34:42,371 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:34:42,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:42,371 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:34:42,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:42,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:34:44,510 INFO L134 CoverageAnalysis]: Checked inductivity of 317957 backedges. 43764 proven. 1703 refuted. 0 times theorem prover too weak. 272490 trivial. 0 not checked. [2018-12-09 04:34:44,510 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:34:44,510 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:34:44,516 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:34:46,040 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-12-09 04:34:46,040 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:34:46,056 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:34:48,485 INFO L134 CoverageAnalysis]: Checked inductivity of 317957 backedges. 76455 proven. 7634 refuted. 0 times theorem prover too weak. 233868 trivial. 0 not checked. [2018-12-09 04:34:48,502 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:34:48,503 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 59] total 89 [2018-12-09 04:34:48,503 INFO L459 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-12-09 04:34:48,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-12-09 04:34:48,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1183, Invalid=6649, Unknown=0, NotChecked=0, Total=7832 [2018-12-09 04:34:48,504 INFO L87 Difference]: Start difference. First operand 2233 states and 2244 transitions. Second operand 89 states. [2018-12-09 04:34:53,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:34:53,164 INFO L93 Difference]: Finished difference Result 2415 states and 2428 transitions. [2018-12-09 04:34:53,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-12-09 04:34:53,164 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 2026 [2018-12-09 04:34:53,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:34:53,167 INFO L225 Difference]: With dead ends: 2415 [2018-12-09 04:34:53,167 INFO L226 Difference]: Without dead ends: 2415 [2018-12-09 04:34:53,169 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2142 GetRequests, 1969 SyntacticMatches, 0 SemanticMatches, 173 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7933 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=5739, Invalid=24711, Unknown=0, NotChecked=0, Total=30450 [2018-12-09 04:34:53,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2415 states. [2018-12-09 04:34:53,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2415 to 2379. [2018-12-09 04:34:53,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2379 states. [2018-12-09 04:34:53,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2379 states to 2379 states and 2392 transitions. [2018-12-09 04:34:53,180 INFO L78 Accepts]: Start accepts. Automaton has 2379 states and 2392 transitions. Word has length 2026 [2018-12-09 04:34:53,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:34:53,181 INFO L480 AbstractCegarLoop]: Abstraction has 2379 states and 2392 transitions. [2018-12-09 04:34:53,181 INFO L481 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-12-09 04:34:53,181 INFO L276 IsEmpty]: Start isEmpty. Operand 2379 states and 2392 transitions. [2018-12-09 04:34:53,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2168 [2018-12-09 04:34:53,199 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:34:53,199 INFO L402 BasicCegarLoop]: trace histogram [377, 377, 376, 376, 376, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:34:53,199 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:34:53,199 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:34:53,200 INFO L82 PathProgramCache]: Analyzing trace with hash 515644234, now seen corresponding path program 58 times [2018-12-09 04:34:53,200 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:34:53,200 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:34:53,200 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:53,200 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:34:53,200 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:53,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:34:55,318 INFO L134 CoverageAnalysis]: Checked inductivity of 366428 backedges. 91891 proven. 7204 refuted. 0 times theorem prover too weak. 267333 trivial. 0 not checked. [2018-12-09 04:34:55,318 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:34:55,318 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:34:55,333 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:34:55,632 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:34:55,632 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:34:55,648 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:34:57,461 INFO L134 CoverageAnalysis]: Checked inductivity of 366428 backedges. 91977 proven. 5492 refuted. 0 times theorem prover too weak. 268959 trivial. 0 not checked. [2018-12-09 04:34:57,478 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:34:57,478 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 57] total 88 [2018-12-09 04:34:57,479 INFO L459 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-12-09 04:34:57,479 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-12-09 04:34:57,479 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1509, Invalid=6147, Unknown=0, NotChecked=0, Total=7656 [2018-12-09 04:34:57,480 INFO L87 Difference]: Start difference. First operand 2379 states and 2392 transitions. Second operand 88 states. [2018-12-09 04:34:59,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:34:59,631 INFO L93 Difference]: Finished difference Result 2406 states and 2417 transitions. [2018-12-09 04:34:59,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-12-09 04:34:59,631 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2167 [2018-12-09 04:34:59,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:34:59,633 INFO L225 Difference]: With dead ends: 2406 [2018-12-09 04:34:59,633 INFO L226 Difference]: Without dead ends: 2400 [2018-12-09 04:34:59,634 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2279 GetRequests, 2139 SyntacticMatches, 0 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6603 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=4369, Invalid=15653, Unknown=0, NotChecked=0, Total=20022 [2018-12-09 04:34:59,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2400 states. [2018-12-09 04:34:59,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2400 to 2379. [2018-12-09 04:34:59,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2379 states. [2018-12-09 04:34:59,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2379 states to 2379 states and 2390 transitions. [2018-12-09 04:34:59,644 INFO L78 Accepts]: Start accepts. Automaton has 2379 states and 2390 transitions. Word has length 2167 [2018-12-09 04:34:59,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:34:59,644 INFO L480 AbstractCegarLoop]: Abstraction has 2379 states and 2390 transitions. [2018-12-09 04:34:59,645 INFO L481 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-12-09 04:34:59,645 INFO L276 IsEmpty]: Start isEmpty. Operand 2379 states and 2390 transitions. [2018-12-09 04:34:59,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2173 [2018-12-09 04:34:59,661 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:34:59,662 INFO L402 BasicCegarLoop]: trace histogram [378, 378, 377, 377, 377, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:34:59,662 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:34:59,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:34:59,662 INFO L82 PathProgramCache]: Analyzing trace with hash 1279424361, now seen corresponding path program 59 times [2018-12-09 04:34:59,662 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:34:59,662 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:34:59,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:59,662 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:34:59,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:34:59,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:35:01,694 INFO L134 CoverageAnalysis]: Checked inductivity of 368336 backedges. 50808 proven. 1903 refuted. 0 times theorem prover too weak. 315625 trivial. 0 not checked. [2018-12-09 04:35:01,695 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:35:01,695 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:35:01,700 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:35:18,658 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2018-12-09 04:35:18,658 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:35:18,703 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:35:20,827 INFO L134 CoverageAnalysis]: Checked inductivity of 368336 backedges. 50611 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2018-12-09 04:35:20,854 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:35:20,854 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 62] total 91 [2018-12-09 04:35:20,855 INFO L459 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-12-09 04:35:20,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-12-09 04:35:20,856 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1724, Invalid=6466, Unknown=0, NotChecked=0, Total=8190 [2018-12-09 04:35:20,856 INFO L87 Difference]: Start difference. First operand 2379 states and 2390 transitions. Second operand 91 states. [2018-12-09 04:35:23,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:35:23,093 INFO L93 Difference]: Finished difference Result 2553 states and 2565 transitions. [2018-12-09 04:35:23,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-12-09 04:35:23,093 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2172 [2018-12-09 04:35:23,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:35:23,096 INFO L225 Difference]: With dead ends: 2553 [2018-12-09 04:35:23,096 INFO L226 Difference]: Without dead ends: 2553 [2018-12-09 04:35:23,097 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2284 GetRequests, 2140 SyntacticMatches, 0 SemanticMatches, 144 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3950 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4805, Invalid=16365, Unknown=0, NotChecked=0, Total=21170 [2018-12-09 04:35:23,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2553 states. [2018-12-09 04:35:23,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2553 to 2525. [2018-12-09 04:35:23,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2525 states. [2018-12-09 04:35:23,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2525 states to 2525 states and 2537 transitions. [2018-12-09 04:35:23,107 INFO L78 Accepts]: Start accepts. Automaton has 2525 states and 2537 transitions. Word has length 2172 [2018-12-09 04:35:23,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:35:23,108 INFO L480 AbstractCegarLoop]: Abstraction has 2525 states and 2537 transitions. [2018-12-09 04:35:23,108 INFO L481 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-12-09 04:35:23,108 INFO L276 IsEmpty]: Start isEmpty. Operand 2525 states and 2537 transitions. [2018-12-09 04:35:23,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2314 [2018-12-09 04:35:23,126 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:35:23,126 INFO L402 BasicCegarLoop]: trace histogram [404, 404, 403, 403, 403, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:35:23,126 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:35:23,126 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:35:23,126 INFO L82 PathProgramCache]: Analyzing trace with hash -1921720281, now seen corresponding path program 60 times [2018-12-09 04:35:23,126 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:35:23,126 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:35:23,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:35:23,127 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:35:23,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:35:23,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:35:25,575 INFO L134 CoverageAnalysis]: Checked inductivity of 420381 backedges. 140744 proven. 5262 refuted. 0 times theorem prover too weak. 274375 trivial. 0 not checked. [2018-12-09 04:35:25,575 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:35:25,575 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:35:25,580 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:35:37,153 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-12-09 04:35:37,153 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:35:37,187 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:35:37,188 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:35:37,194 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:35:37,197 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:35:37,198 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:35:37,205 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:35:37,212 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:35:37,212 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-12-09 04:35:44,809 INFO L134 CoverageAnalysis]: Checked inductivity of 420381 backedges. 96007 proven. 5672 refuted. 0 times theorem prover too weak. 318702 trivial. 0 not checked. [2018-12-09 04:35:44,831 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:35:44,832 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 39] total 98 [2018-12-09 04:35:44,832 INFO L459 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-12-09 04:35:44,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-12-09 04:35:44,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1274, Invalid=8232, Unknown=0, NotChecked=0, Total=9506 [2018-12-09 04:35:44,833 INFO L87 Difference]: Start difference. First operand 2525 states and 2537 transitions. Second operand 98 states. [2018-12-09 04:35:59,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:35:59,449 INFO L93 Difference]: Finished difference Result 2555 states and 2558 transitions. [2018-12-09 04:35:59,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2018-12-09 04:35:59,449 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 2313 [2018-12-09 04:35:59,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:35:59,451 INFO L225 Difference]: With dead ends: 2555 [2018-12-09 04:35:59,451 INFO L226 Difference]: Without dead ends: 2482 [2018-12-09 04:35:59,453 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2497 GetRequests, 2226 SyntacticMatches, 51 SemanticMatches, 220 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15337 ImplicationChecksByTransitivity, 13.1s TimeCoverageRelationStatistics Valid=6312, Invalid=42750, Unknown=0, NotChecked=0, Total=49062 [2018-12-09 04:35:59,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2482 states. [2018-12-09 04:35:59,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2482 to 2468. [2018-12-09 04:35:59,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2468 states. [2018-12-09 04:35:59,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2468 states to 2468 states and 2470 transitions. [2018-12-09 04:35:59,462 INFO L78 Accepts]: Start accepts. Automaton has 2468 states and 2470 transitions. Word has length 2313 [2018-12-09 04:35:59,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:35:59,463 INFO L480 AbstractCegarLoop]: Abstraction has 2468 states and 2470 transitions. [2018-12-09 04:35:59,463 INFO L481 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-12-09 04:35:59,463 INFO L276 IsEmpty]: Start isEmpty. Operand 2468 states and 2470 transitions. [2018-12-09 04:35:59,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2465 [2018-12-09 04:35:59,483 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:35:59,484 INFO L402 BasicCegarLoop]: trace histogram [432, 432, 431, 431, 431, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:35:59,484 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:35:59,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:35:59,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1209734959, now seen corresponding path program 61 times [2018-12-09 04:35:59,484 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:35:59,484 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:35:59,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:35:59,485 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:35:59,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:35:59,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:36:02,076 INFO L134 CoverageAnalysis]: Checked inductivity of 480224 backedges. 110375 proven. 8355 refuted. 0 times theorem prover too weak. 361494 trivial. 0 not checked. [2018-12-09 04:36:02,076 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:36:02,076 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:36:02,082 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:36:02,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:36:02,494 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:36:04,627 INFO L134 CoverageAnalysis]: Checked inductivity of 480224 backedges. 110773 proven. 1782 refuted. 0 times theorem prover too weak. 367669 trivial. 0 not checked. [2018-12-09 04:36:04,644 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:36:04,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 58] total 91 [2018-12-09 04:36:04,645 INFO L459 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-12-09 04:36:04,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-12-09 04:36:04,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1722, Invalid=6468, Unknown=0, NotChecked=0, Total=8190 [2018-12-09 04:36:04,645 INFO L87 Difference]: Start difference. First operand 2468 states and 2470 transitions. Second operand 91 states. [2018-12-09 04:36:07,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:36:07,825 INFO L93 Difference]: Finished difference Result 2491 states and 2493 transitions. [2018-12-09 04:36:07,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-12-09 04:36:07,825 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2464 [2018-12-09 04:36:07,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:36:07,829 INFO L225 Difference]: With dead ends: 2491 [2018-12-09 04:36:07,829 INFO L226 Difference]: Without dead ends: 2485 [2018-12-09 04:36:07,830 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2585 GetRequests, 2438 SyntacticMatches, 0 SemanticMatches, 147 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7394 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=4825, Invalid=17227, Unknown=0, NotChecked=0, Total=22052 [2018-12-09 04:36:07,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2485 states. [2018-12-09 04:36:07,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2485 to 2476. [2018-12-09 04:36:07,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2476 states. [2018-12-09 04:36:07,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2476 states to 2476 states and 2478 transitions. [2018-12-09 04:36:07,843 INFO L78 Accepts]: Start accepts. Automaton has 2476 states and 2478 transitions. Word has length 2464 [2018-12-09 04:36:07,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:36:07,843 INFO L480 AbstractCegarLoop]: Abstraction has 2476 states and 2478 transitions. [2018-12-09 04:36:07,844 INFO L481 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-12-09 04:36:07,844 INFO L276 IsEmpty]: Start isEmpty. Operand 2476 states and 2478 transitions. [2018-12-09 04:36:07,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2470 [2018-12-09 04:36:07,864 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:36:07,864 INFO L402 BasicCegarLoop]: trace histogram [433, 433, 432, 432, 432, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:36:07,865 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:36:07,865 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:36:07,865 INFO L82 PathProgramCache]: Analyzing trace with hash 617489060, now seen corresponding path program 62 times [2018-12-09 04:36:07,865 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:36:07,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:36:07,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:36:07,865 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:36:07,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:36:08,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:36:10,628 INFO L134 CoverageAnalysis]: Checked inductivity of 482409 backedges. 56673 proven. 1836 refuted. 0 times theorem prover too weak. 423900 trivial. 0 not checked. [2018-12-09 04:36:10,628 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:36:10,628 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:36:10,633 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:36:11,008 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:36:11,009 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:36:11,029 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:36:11,031 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:36:11,033 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:36:11,044 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:36:11,044 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:36:11,050 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:36:11,058 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:36:11,059 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:36:17,453 INFO L134 CoverageAnalysis]: Checked inductivity of 482409 backedges. 56673 proven. 1836 refuted. 0 times theorem prover too weak. 423900 trivial. 0 not checked. [2018-12-09 04:36:17,471 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:36:17,471 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 60 [2018-12-09 04:36:17,471 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-12-09 04:36:17,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-12-09 04:36:17,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=962, Invalid=2698, Unknown=0, NotChecked=0, Total=3660 [2018-12-09 04:36:17,472 INFO L87 Difference]: Start difference. First operand 2476 states and 2478 transitions. Second operand 61 states. [2018-12-09 04:36:19,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:36:19,511 INFO L93 Difference]: Finished difference Result 2484 states and 2486 transitions. [2018-12-09 04:36:19,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-09 04:36:19,511 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 2469 [2018-12-09 04:36:19,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:36:19,515 INFO L225 Difference]: With dead ends: 2484 [2018-12-09 04:36:19,515 INFO L226 Difference]: Without dead ends: 2484 [2018-12-09 04:36:19,516 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2528 GetRequests, 2385 SyntacticMatches, 56 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2380 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1535, Invalid=6297, Unknown=0, NotChecked=0, Total=7832 [2018-12-09 04:36:19,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2484 states. [2018-12-09 04:36:19,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2484 to 2478. [2018-12-09 04:36:19,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2478 states. [2018-12-09 04:36:19,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2478 states to 2478 states and 2480 transitions. [2018-12-09 04:36:19,526 INFO L78 Accepts]: Start accepts. Automaton has 2478 states and 2480 transitions. Word has length 2469 [2018-12-09 04:36:19,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:36:19,528 INFO L480 AbstractCegarLoop]: Abstraction has 2478 states and 2480 transitions. [2018-12-09 04:36:19,528 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-12-09 04:36:19,528 INFO L276 IsEmpty]: Start isEmpty. Operand 2478 states and 2480 transitions. [2018-12-09 04:36:19,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2475 [2018-12-09 04:36:19,550 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:36:19,550 INFO L402 BasicCegarLoop]: trace histogram [434, 434, 433, 433, 433, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:36:19,550 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:36:19,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:36:19,551 INFO L82 PathProgramCache]: Analyzing trace with hash -971898775, now seen corresponding path program 63 times [2018-12-09 04:36:19,551 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:36:19,551 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:36:19,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:36:19,552 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:36:19,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:36:19,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:36:22,381 INFO L134 CoverageAnalysis]: Checked inductivity of 484599 backedges. 58725 proven. 1974 refuted. 0 times theorem prover too weak. 423900 trivial. 0 not checked. [2018-12-09 04:36:22,381 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:36:22,381 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:36:22,386 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:36:25,454 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-12-09 04:36:25,454 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:36:25,472 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:36:25,474 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:36:25,477 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:36:25,482 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:36:25,482 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:36:25,498 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:36:25,504 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:36:25,504 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:36:31,739 INFO L134 CoverageAnalysis]: Checked inductivity of 484599 backedges. 58725 proven. 1974 refuted. 0 times theorem prover too weak. 423900 trivial. 0 not checked. [2018-12-09 04:36:31,756 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:36:31,757 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 34] total 35 [2018-12-09 04:36:31,758 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-12-09 04:36:31,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-12-09 04:36:31,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=539, Invalid=721, Unknown=0, NotChecked=0, Total=1260 [2018-12-09 04:36:31,758 INFO L87 Difference]: Start difference. First operand 2478 states and 2480 transitions. Second operand 36 states. [2018-12-09 04:36:32,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:36:32,520 INFO L93 Difference]: Finished difference Result 2500 states and 2504 transitions. [2018-12-09 04:36:32,520 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-12-09 04:36:32,520 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 2474 [2018-12-09 04:36:32,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:36:32,523 INFO L225 Difference]: With dead ends: 2500 [2018-12-09 04:36:32,523 INFO L226 Difference]: Without dead ends: 2500 [2018-12-09 04:36:32,523 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2535 GetRequests, 2416 SyntacticMatches, 56 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 629 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1526, Invalid=2634, Unknown=0, NotChecked=0, Total=4160 [2018-12-09 04:36:32,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2500 states. [2018-12-09 04:36:32,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2500 to 2483. [2018-12-09 04:36:32,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2483 states. [2018-12-09 04:36:32,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2483 states to 2483 states and 2486 transitions. [2018-12-09 04:36:32,532 INFO L78 Accepts]: Start accepts. Automaton has 2483 states and 2486 transitions. Word has length 2474 [2018-12-09 04:36:32,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:36:32,533 INFO L480 AbstractCegarLoop]: Abstraction has 2483 states and 2486 transitions. [2018-12-09 04:36:32,533 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-12-09 04:36:32,533 INFO L276 IsEmpty]: Start isEmpty. Operand 2483 states and 2486 transitions. [2018-12-09 04:36:32,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2480 [2018-12-09 04:36:32,553 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:36:32,554 INFO L402 BasicCegarLoop]: trace histogram [435, 435, 434, 434, 434, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:36:32,554 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:36:32,554 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:36:32,554 INFO L82 PathProgramCache]: Analyzing trace with hash -438635068, now seen corresponding path program 64 times [2018-12-09 04:36:32,554 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:36:32,554 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:36:32,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:36:32,555 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:36:32,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:36:32,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:36:35,071 INFO L134 CoverageAnalysis]: Checked inductivity of 486794 backedges. 62837 proven. 2217 refuted. 0 times theorem prover too weak. 421740 trivial. 0 not checked. [2018-12-09 04:36:35,072 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:36:35,072 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:36:35,078 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:36:35,392 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:36:35,392 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:36:35,411 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:36:38,029 INFO L134 CoverageAnalysis]: Checked inductivity of 486794 backedges. 62626 proven. 7024 refuted. 0 times theorem prover too weak. 417144 trivial. 0 not checked. [2018-12-09 04:36:38,046 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:36:38,046 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 65] total 97 [2018-12-09 04:36:38,047 INFO L459 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-12-09 04:36:38,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-12-09 04:36:38,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1966, Invalid=7346, Unknown=0, NotChecked=0, Total=9312 [2018-12-09 04:36:38,048 INFO L87 Difference]: Start difference. First operand 2483 states and 2486 transitions. Second operand 97 states. [2018-12-09 04:36:40,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:36:40,454 INFO L93 Difference]: Finished difference Result 2654 states and 2658 transitions. [2018-12-09 04:36:40,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-12-09 04:36:40,454 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 2479 [2018-12-09 04:36:40,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:36:40,458 INFO L225 Difference]: With dead ends: 2654 [2018-12-09 04:36:40,458 INFO L226 Difference]: Without dead ends: 2654 [2018-12-09 04:36:40,459 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2599 GetRequests, 2445 SyntacticMatches, 0 SemanticMatches, 154 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4505 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=5505, Invalid=18675, Unknown=0, NotChecked=0, Total=24180 [2018-12-09 04:36:40,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2654 states. [2018-12-09 04:36:40,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2654 to 2644. [2018-12-09 04:36:40,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2644 states. [2018-12-09 04:36:40,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2644 states to 2644 states and 2648 transitions. [2018-12-09 04:36:40,470 INFO L78 Accepts]: Start accepts. Automaton has 2644 states and 2648 transitions. Word has length 2479 [2018-12-09 04:36:40,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:36:40,471 INFO L480 AbstractCegarLoop]: Abstraction has 2644 states and 2648 transitions. [2018-12-09 04:36:40,471 INFO L481 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-12-09 04:36:40,471 INFO L276 IsEmpty]: Start isEmpty. Operand 2644 states and 2648 transitions. [2018-12-09 04:36:40,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2631 [2018-12-09 04:36:40,494 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:36:40,494 INFO L402 BasicCegarLoop]: trace histogram [463, 463, 462, 462, 462, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:36:40,495 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:36:40,495 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:36:40,495 INFO L82 PathProgramCache]: Analyzing trace with hash 1393501900, now seen corresponding path program 65 times [2018-12-09 04:36:40,495 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:36:40,495 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:36:40,495 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:36:40,496 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:36:40,496 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:36:40,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:36:43,562 INFO L134 CoverageAnalysis]: Checked inductivity of 551047 backedges. 174981 proven. 6087 refuted. 0 times theorem prover too weak. 369979 trivial. 0 not checked. [2018-12-09 04:36:43,562 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:36:43,562 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:36:43,569 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:37:02,785 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 72 check-sat command(s) [2018-12-09 04:37:02,785 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:37:02,836 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:37:06,028 INFO L134 CoverageAnalysis]: Checked inductivity of 551047 backedges. 124779 proven. 13049 refuted. 0 times theorem prover too weak. 413219 trivial. 0 not checked. [2018-12-09 04:37:06,057 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:37:06,058 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64] total 122 [2018-12-09 04:37:06,058 INFO L459 AbstractCegarLoop]: Interpolant automaton has 122 states [2018-12-09 04:37:06,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 122 interpolants. [2018-12-09 04:37:06,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2225, Invalid=12537, Unknown=0, NotChecked=0, Total=14762 [2018-12-09 04:37:06,059 INFO L87 Difference]: Start difference. First operand 2644 states and 2648 transitions. Second operand 122 states. [2018-12-09 04:37:11,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:37:11,590 INFO L93 Difference]: Finished difference Result 2655 states and 2657 transitions. [2018-12-09 04:37:11,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 119 states. [2018-12-09 04:37:11,590 INFO L78 Accepts]: Start accepts. Automaton has 122 states. Word has length 2630 [2018-12-09 04:37:11,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:37:11,593 INFO L225 Difference]: With dead ends: 2655 [2018-12-09 04:37:11,593 INFO L226 Difference]: Without dead ends: 2649 [2018-12-09 04:37:11,595 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2784 GetRequests, 2574 SyntacticMatches, 0 SemanticMatches, 210 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14999 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=7199, Invalid=37533, Unknown=0, NotChecked=0, Total=44732 [2018-12-09 04:37:11,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2649 states. [2018-12-09 04:37:11,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2649 to 2644. [2018-12-09 04:37:11,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2644 states. [2018-12-09 04:37:11,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2644 states to 2644 states and 2646 transitions. [2018-12-09 04:37:11,606 INFO L78 Accepts]: Start accepts. Automaton has 2644 states and 2646 transitions. Word has length 2630 [2018-12-09 04:37:11,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:37:11,607 INFO L480 AbstractCegarLoop]: Abstraction has 2644 states and 2646 transitions. [2018-12-09 04:37:11,607 INFO L481 AbstractCegarLoop]: Interpolant automaton has 122 states. [2018-12-09 04:37:11,607 INFO L276 IsEmpty]: Start isEmpty. Operand 2644 states and 2646 transitions. [2018-12-09 04:37:11,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2636 [2018-12-09 04:37:11,630 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:37:11,630 INFO L402 BasicCegarLoop]: trace histogram [464, 464, 463, 463, 463, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:37:11,630 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:37:11,630 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:37:11,631 INFO L82 PathProgramCache]: Analyzing trace with hash 1734616487, now seen corresponding path program 66 times [2018-12-09 04:37:11,631 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:37:11,631 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:37:11,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:37:11,631 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:37:11,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:37:11,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:37:14,889 INFO L134 CoverageAnalysis]: Checked inductivity of 553388 backedges. 65100 proven. 2117 refuted. 0 times theorem prover too weak. 486171 trivial. 0 not checked. [2018-12-09 04:37:14,889 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:37:14,889 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:37:14,895 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:37:42,856 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-12-09 04:37:42,856 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:37:42,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:37:42,894 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:37:42,896 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:37:42,900 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:37:42,901 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:37:42,906 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:37:42,913 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:37:42,913 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:37:50,170 INFO L134 CoverageAnalysis]: Checked inductivity of 553388 backedges. 65100 proven. 2117 refuted. 0 times theorem prover too weak. 486171 trivial. 0 not checked. [2018-12-09 04:37:50,193 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:37:50,194 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 35] total 36 [2018-12-09 04:37:50,194 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-12-09 04:37:50,194 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-12-09 04:37:50,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=572, Invalid=760, Unknown=0, NotChecked=0, Total=1332 [2018-12-09 04:37:50,195 INFO L87 Difference]: Start difference. First operand 2644 states and 2646 transitions. Second operand 37 states. [2018-12-09 04:37:50,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:37:50,984 INFO L93 Difference]: Finished difference Result 2657 states and 2660 transitions. [2018-12-09 04:37:50,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-12-09 04:37:50,984 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 2635 [2018-12-09 04:37:50,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:37:50,987 INFO L225 Difference]: With dead ends: 2657 [2018-12-09 04:37:50,988 INFO L226 Difference]: Without dead ends: 2657 [2018-12-09 04:37:50,988 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2698 GetRequests, 2575 SyntacticMatches, 58 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 666 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1623, Invalid=2799, Unknown=0, NotChecked=0, Total=4422 [2018-12-09 04:37:50,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2657 states. [2018-12-09 04:37:50,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2657 to 2649. [2018-12-09 04:37:50,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2649 states. [2018-12-09 04:37:51,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2649 states to 2649 states and 2652 transitions. [2018-12-09 04:37:51,001 INFO L78 Accepts]: Start accepts. Automaton has 2649 states and 2652 transitions. Word has length 2635 [2018-12-09 04:37:51,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:37:51,003 INFO L480 AbstractCegarLoop]: Abstraction has 2649 states and 2652 transitions. [2018-12-09 04:37:51,003 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-12-09 04:37:51,003 INFO L276 IsEmpty]: Start isEmpty. Operand 2649 states and 2652 transitions. [2018-12-09 04:37:51,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2641 [2018-12-09 04:37:51,027 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:37:51,027 INFO L402 BasicCegarLoop]: trace histogram [465, 465, 464, 464, 464, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:37:51,027 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:37:51,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:37:51,028 INFO L82 PathProgramCache]: Analyzing trace with hash -723228858, now seen corresponding path program 67 times [2018-12-09 04:37:51,028 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:37:51,028 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:37:51,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:37:51,028 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:37:51,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:37:51,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:37:53,856 INFO L134 CoverageAnalysis]: Checked inductivity of 555734 backedges. 69504 proven. 2383 refuted. 0 times theorem prover too weak. 483847 trivial. 0 not checked. [2018-12-09 04:37:53,856 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:37:53,856 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:37:53,864 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:37:54,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:37:54,259 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:37:57,010 INFO L134 CoverageAnalysis]: Checked inductivity of 555734 backedges. 69563 proven. 2324 refuted. 0 times theorem prover too weak. 483847 trivial. 0 not checked. [2018-12-09 04:37:57,028 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:37:57,028 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 63] total 96 [2018-12-09 04:37:57,029 INFO L459 AbstractCegarLoop]: Interpolant automaton has 96 states [2018-12-09 04:37:57,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2018-12-09 04:37:57,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2081, Invalid=7039, Unknown=0, NotChecked=0, Total=9120 [2018-12-09 04:37:57,030 INFO L87 Difference]: Start difference. First operand 2649 states and 2652 transitions. Second operand 96 states. [2018-12-09 04:37:59,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:37:59,020 INFO L93 Difference]: Finished difference Result 2820 states and 2824 transitions. [2018-12-09 04:37:59,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-12-09 04:37:59,021 INFO L78 Accepts]: Start accepts. Automaton has 96 states. Word has length 2640 [2018-12-09 04:37:59,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:37:59,024 INFO L225 Difference]: With dead ends: 2820 [2018-12-09 04:37:59,024 INFO L226 Difference]: Without dead ends: 2820 [2018-12-09 04:37:59,025 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2762 GetRequests, 2609 SyntacticMatches, 0 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4088 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=5972, Invalid=17898, Unknown=0, NotChecked=0, Total=23870 [2018-12-09 04:37:59,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2820 states. [2018-12-09 04:37:59,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2820 to 2810. [2018-12-09 04:37:59,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2810 states. [2018-12-09 04:37:59,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2810 states to 2810 states and 2814 transitions. [2018-12-09 04:37:59,035 INFO L78 Accepts]: Start accepts. Automaton has 2810 states and 2814 transitions. Word has length 2640 [2018-12-09 04:37:59,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:37:59,036 INFO L480 AbstractCegarLoop]: Abstraction has 2810 states and 2814 transitions. [2018-12-09 04:37:59,036 INFO L481 AbstractCegarLoop]: Interpolant automaton has 96 states. [2018-12-09 04:37:59,036 INFO L276 IsEmpty]: Start isEmpty. Operand 2810 states and 2814 transitions. [2018-12-09 04:37:59,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2797 [2018-12-09 04:37:59,062 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:37:59,062 INFO L402 BasicCegarLoop]: trace histogram [494, 494, 493, 493, 493, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:37:59,062 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:37:59,062 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:37:59,062 INFO L82 PathProgramCache]: Analyzing trace with hash -748474429, now seen corresponding path program 68 times [2018-12-09 04:37:59,062 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:37:59,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:37:59,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:37:59,063 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:37:59,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:37:59,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:38:02,282 INFO L134 CoverageAnalysis]: Checked inductivity of 626748 backedges. 138119 proven. 9590 refuted. 0 times theorem prover too weak. 479039 trivial. 0 not checked. [2018-12-09 04:38:02,282 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:38:02,282 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:38:02,288 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:38:02,746 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:38:02,746 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:38:02,767 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:38:05,430 INFO L134 CoverageAnalysis]: Checked inductivity of 626748 backedges. 138549 proven. 2059 refuted. 0 times theorem prover too weak. 486140 trivial. 0 not checked. [2018-12-09 04:38:05,447 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:38:05,448 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 62] total 97 [2018-12-09 04:38:05,448 INFO L459 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-12-09 04:38:05,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-12-09 04:38:05,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1964, Invalid=7348, Unknown=0, NotChecked=0, Total=9312 [2018-12-09 04:38:05,449 INFO L87 Difference]: Start difference. First operand 2810 states and 2814 transitions. Second operand 97 states. [2018-12-09 04:38:07,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:38:07,718 INFO L93 Difference]: Finished difference Result 2821 states and 2823 transitions. [2018-12-09 04:38:07,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2018-12-09 04:38:07,718 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 2796 [2018-12-09 04:38:07,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:38:07,724 INFO L225 Difference]: With dead ends: 2821 [2018-12-09 04:38:07,724 INFO L226 Difference]: Without dead ends: 2815 [2018-12-09 04:38:07,725 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2924 GetRequests, 2767 SyntacticMatches, 0 SemanticMatches, 157 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8493 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=5498, Invalid=19624, Unknown=0, NotChecked=0, Total=25122 [2018-12-09 04:38:07,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2815 states. [2018-12-09 04:38:07,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2815 to 2810. [2018-12-09 04:38:07,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2810 states. [2018-12-09 04:38:07,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2810 states to 2810 states and 2812 transitions. [2018-12-09 04:38:07,742 INFO L78 Accepts]: Start accepts. Automaton has 2810 states and 2812 transitions. Word has length 2796 [2018-12-09 04:38:07,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:38:07,743 INFO L480 AbstractCegarLoop]: Abstraction has 2810 states and 2812 transitions. [2018-12-09 04:38:07,743 INFO L481 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-12-09 04:38:07,743 INFO L276 IsEmpty]: Start isEmpty. Operand 2810 states and 2812 transitions. [2018-12-09 04:38:07,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2802 [2018-12-09 04:38:07,770 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:38:07,770 INFO L402 BasicCegarLoop]: trace histogram [495, 495, 494, 494, 494, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:38:07,770 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:38:07,771 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:38:07,771 INFO L82 PathProgramCache]: Analyzing trace with hash 1476709892, now seen corresponding path program 69 times [2018-12-09 04:38:07,771 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:38:07,771 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:38:07,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:38:07,771 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:38:07,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:38:07,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:38:11,270 INFO L134 CoverageAnalysis]: Checked inductivity of 629245 backedges. 71920 proven. 2265 refuted. 0 times theorem prover too weak. 555060 trivial. 0 not checked. [2018-12-09 04:38:11,270 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:38:11,270 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:38:11,276 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 04:38:13,388 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-12-09 04:38:13,388 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:38:13,409 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:38:13,412 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:38:13,414 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:38:13,420 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:38:13,420 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:38:13,428 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:38:13,435 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:38:13,435 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:38:21,461 INFO L134 CoverageAnalysis]: Checked inductivity of 629245 backedges. 71920 proven. 2265 refuted. 0 times theorem prover too weak. 555060 trivial. 0 not checked. [2018-12-09 04:38:21,479 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:38:21,479 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 36] total 37 [2018-12-09 04:38:21,480 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-12-09 04:38:21,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-12-09 04:38:21,480 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=606, Invalid=800, Unknown=0, NotChecked=0, Total=1406 [2018-12-09 04:38:21,480 INFO L87 Difference]: Start difference. First operand 2810 states and 2812 transitions. Second operand 38 states. [2018-12-09 04:38:22,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:38:22,397 INFO L93 Difference]: Finished difference Result 2823 states and 2826 transitions. [2018-12-09 04:38:22,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-09 04:38:22,397 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 2801 [2018-12-09 04:38:22,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:38:22,401 INFO L225 Difference]: With dead ends: 2823 [2018-12-09 04:38:22,401 INFO L226 Difference]: Without dead ends: 2823 [2018-12-09 04:38:22,402 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2866 GetRequests, 2739 SyntacticMatches, 60 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 704 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1723, Invalid=2969, Unknown=0, NotChecked=0, Total=4692 [2018-12-09 04:38:22,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2823 states. [2018-12-09 04:38:22,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2823 to 2815. [2018-12-09 04:38:22,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2815 states. [2018-12-09 04:38:22,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2815 states to 2815 states and 2818 transitions. [2018-12-09 04:38:22,414 INFO L78 Accepts]: Start accepts. Automaton has 2815 states and 2818 transitions. Word has length 2801 [2018-12-09 04:38:22,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:38:22,415 INFO L480 AbstractCegarLoop]: Abstraction has 2815 states and 2818 transitions. [2018-12-09 04:38:22,415 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-12-09 04:38:22,415 INFO L276 IsEmpty]: Start isEmpty. Operand 2815 states and 2818 transitions. [2018-12-09 04:38:22,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2807 [2018-12-09 04:38:22,441 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:38:22,441 INFO L402 BasicCegarLoop]: trace histogram [496, 496, 495, 495, 495, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:38:22,441 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:38:22,441 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:38:22,442 INFO L82 PathProgramCache]: Analyzing trace with hash -1793101559, now seen corresponding path program 70 times [2018-12-09 04:38:22,442 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:38:22,442 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:38:22,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:38:22,442 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:38:22,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:38:22,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:38:25,575 INFO L134 CoverageAnalysis]: Checked inductivity of 631747 backedges. 76626 proven. 2555 refuted. 0 times theorem prover too weak. 552566 trivial. 0 not checked. [2018-12-09 04:38:25,575 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:38:25,575 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:38:25,581 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 04:38:25,944 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 04:38:25,944 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:38:25,966 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:38:29,197 INFO L134 CoverageAnalysis]: Checked inductivity of 631747 backedges. 76401 proven. 8037 refuted. 0 times theorem prover too weak. 547309 trivial. 0 not checked. [2018-12-09 04:38:29,215 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:38:29,215 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 69] total 103 [2018-12-09 04:38:29,216 INFO L459 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-12-09 04:38:29,216 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-12-09 04:38:29,216 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2224, Invalid=8282, Unknown=0, NotChecked=0, Total=10506 [2018-12-09 04:38:29,217 INFO L87 Difference]: Start difference. First operand 2815 states and 2818 transitions. Second operand 103 states. [2018-12-09 04:38:31,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:38:31,626 INFO L93 Difference]: Finished difference Result 2991 states and 2995 transitions. [2018-12-09 04:38:31,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-12-09 04:38:31,626 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 2806 [2018-12-09 04:38:31,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:38:31,629 INFO L225 Difference]: With dead ends: 2991 [2018-12-09 04:38:31,629 INFO L226 Difference]: Without dead ends: 2991 [2018-12-09 04:38:31,630 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2934 GetRequests, 2770 SyntacticMatches, 0 SemanticMatches, 164 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5096 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=6253, Invalid=21137, Unknown=0, NotChecked=0, Total=27390 [2018-12-09 04:38:31,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2991 states. [2018-12-09 04:38:31,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2991 to 2981. [2018-12-09 04:38:31,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2981 states. [2018-12-09 04:38:31,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2981 states to 2981 states and 2985 transitions. [2018-12-09 04:38:31,642 INFO L78 Accepts]: Start accepts. Automaton has 2981 states and 2985 transitions. Word has length 2806 [2018-12-09 04:38:31,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:38:31,643 INFO L480 AbstractCegarLoop]: Abstraction has 2981 states and 2985 transitions. [2018-12-09 04:38:31,643 INFO L481 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-12-09 04:38:31,643 INFO L276 IsEmpty]: Start isEmpty. Operand 2981 states and 2985 transitions. [2018-12-09 04:38:31,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2968 [2018-12-09 04:38:31,671 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:38:31,671 INFO L402 BasicCegarLoop]: trace histogram [526, 526, 525, 525, 525, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:38:31,671 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:38:31,671 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:38:31,672 INFO L82 PathProgramCache]: Analyzing trace with hash 1530460487, now seen corresponding path program 71 times [2018-12-09 04:38:31,672 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:38:31,672 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:38:31,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:38:31,672 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:38:31,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:38:31,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:38:35,414 INFO L134 CoverageAnalysis]: Checked inductivity of 709980 backedges. 214362 proven. 6972 refuted. 0 times theorem prover too weak. 488646 trivial. 0 not checked. [2018-12-09 04:38:35,414 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:38:35,414 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:38:35,420 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 04:38:55,088 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 79 check-sat command(s) [2018-12-09 04:38:55,088 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:38:55,144 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:38:58,978 INFO L134 CoverageAnalysis]: Checked inductivity of 709980 backedges. 152244 proven. 14940 refuted. 0 times theorem prover too weak. 542796 trivial. 0 not checked. [2018-12-09 04:38:59,011 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:38:59,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68] total 130 [2018-12-09 04:38:59,012 INFO L459 AbstractCegarLoop]: Interpolant automaton has 130 states [2018-12-09 04:38:59,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 130 interpolants. [2018-12-09 04:38:59,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2530, Invalid=14240, Unknown=0, NotChecked=0, Total=16770 [2018-12-09 04:38:59,013 INFO L87 Difference]: Start difference. First operand 2981 states and 2985 transitions. Second operand 130 states. [2018-12-09 04:39:04,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:39:04,378 INFO L93 Difference]: Finished difference Result 2992 states and 2994 transitions. [2018-12-09 04:39:04,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 127 states. [2018-12-09 04:39:04,378 INFO L78 Accepts]: Start accepts. Automaton has 130 states. Word has length 2967 [2018-12-09 04:39:04,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:39:04,382 INFO L225 Difference]: With dead ends: 2992 [2018-12-09 04:39:04,382 INFO L226 Difference]: Without dead ends: 2986 [2018-12-09 04:39:04,385 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3131 GetRequests, 2907 SyntacticMatches, 0 SemanticMatches, 224 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17184 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=8127, Invalid=42723, Unknown=0, NotChecked=0, Total=50850 [2018-12-09 04:39:04,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2986 states. [2018-12-09 04:39:04,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2986 to 2981. [2018-12-09 04:39:04,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2981 states. [2018-12-09 04:39:04,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2981 states to 2981 states and 2983 transitions. [2018-12-09 04:39:04,398 INFO L78 Accepts]: Start accepts. Automaton has 2981 states and 2983 transitions. Word has length 2967 [2018-12-09 04:39:04,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:39:04,400 INFO L480 AbstractCegarLoop]: Abstraction has 2981 states and 2983 transitions. [2018-12-09 04:39:04,400 INFO L481 AbstractCegarLoop]: Interpolant automaton has 130 states. [2018-12-09 04:39:04,400 INFO L276 IsEmpty]: Start isEmpty. Operand 2981 states and 2983 transitions. [2018-12-09 04:39:04,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2973 [2018-12-09 04:39:04,434 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:39:04,434 INFO L402 BasicCegarLoop]: trace histogram [527, 527, 526, 526, 526, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:39:04,434 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:39:04,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:39:04,435 INFO L82 PathProgramCache]: Analyzing trace with hash 390914188, now seen corresponding path program 72 times [2018-12-09 04:39:04,435 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:39:04,435 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:39:04,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:39:04,435 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:39:04,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:39:04,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:39:08,314 INFO L134 CoverageAnalysis]: Checked inductivity of 712638 backedges. 79200 proven. 2418 refuted. 0 times theorem prover too weak. 631020 trivial. 0 not checked. [2018-12-09 04:39:08,314 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:39:08,315 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:39:08,321 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 04:39:23,249 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 63 check-sat command(s) [2018-12-09 04:39:23,249 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:39:23,283 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:39:23,285 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 04:39:23,289 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 04:39:23,293 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-12-09 04:39:23,293 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-12-09 04:39:23,299 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-12-09 04:39:23,306 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-12-09 04:39:23,306 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-12-09 04:39:34,003 INFO L134 CoverageAnalysis]: Checked inductivity of 712638 backedges. 147905 proven. 7439 refuted. 0 times theorem prover too weak. 557294 trivial. 0 not checked. [2018-12-09 04:39:34,026 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:39:34,026 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 45] total 77 [2018-12-09 04:39:34,027 INFO L459 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-12-09 04:39:34,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-12-09 04:39:34,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1755, Invalid=4251, Unknown=0, NotChecked=0, Total=6006 [2018-12-09 04:39:34,027 INFO L87 Difference]: Start difference. First operand 2981 states and 2983 transitions. Second operand 78 states. [2018-12-09 04:39:42,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:39:42,467 INFO L93 Difference]: Finished difference Result 2994 states and 2997 transitions. [2018-12-09 04:39:42,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2018-12-09 04:39:42,468 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 2972 [2018-12-09 04:39:42,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:39:42,474 INFO L225 Difference]: With dead ends: 2994 [2018-12-09 04:39:42,474 INFO L226 Difference]: Without dead ends: 2994 [2018-12-09 04:39:42,476 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3111 GetRequests, 2871 SyntacticMatches, 61 SemanticMatches, 179 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10786 ImplicationChecksByTransitivity, 9.9s TimeCoverageRelationStatistics Valid=8848, Invalid=23732, Unknown=0, NotChecked=0, Total=32580 [2018-12-09 04:39:42,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2994 states. [2018-12-09 04:39:42,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2994 to 2986. [2018-12-09 04:39:42,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2986 states. [2018-12-09 04:39:42,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2986 states to 2986 states and 2989 transitions. [2018-12-09 04:39:42,496 INFO L78 Accepts]: Start accepts. Automaton has 2986 states and 2989 transitions. Word has length 2972 [2018-12-09 04:39:42,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:39:42,497 INFO L480 AbstractCegarLoop]: Abstraction has 2986 states and 2989 transitions. [2018-12-09 04:39:42,497 INFO L481 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-12-09 04:39:42,497 INFO L276 IsEmpty]: Start isEmpty. Operand 2986 states and 2989 transitions. [2018-12-09 04:39:42,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2978 [2018-12-09 04:39:42,543 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:39:42,543 INFO L402 BasicCegarLoop]: trace histogram [528, 528, 527, 527, 527, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:39:42,543 INFO L423 AbstractCegarLoop]: === Iteration 85 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:39:42,543 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:39:42,543 INFO L82 PathProgramCache]: Analyzing trace with hash -1037716607, now seen corresponding path program 73 times [2018-12-09 04:39:42,543 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:39:42,543 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:39:42,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:39:42,544 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:39:42,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:39:42,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:39:46,011 INFO L134 CoverageAnalysis]: Checked inductivity of 715301 backedges. 84218 proven. 2733 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2018-12-09 04:39:46,011 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:39:46,011 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:39:46,017 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:39:46,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:39:46,491 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:39:49,820 INFO L134 CoverageAnalysis]: Checked inductivity of 715301 backedges. 84281 proven. 2670 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2018-12-09 04:39:49,838 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:39:49,838 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 67] total 102 [2018-12-09 04:39:49,839 INFO L459 AbstractCegarLoop]: Interpolant automaton has 102 states [2018-12-09 04:39:49,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2018-12-09 04:39:49,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2347, Invalid=7955, Unknown=0, NotChecked=0, Total=10302 [2018-12-09 04:39:49,839 INFO L87 Difference]: Start difference. First operand 2986 states and 2989 transitions. Second operand 102 states. [2018-12-09 04:39:51,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:39:51,884 INFO L93 Difference]: Finished difference Result 3167 states and 3171 transitions. [2018-12-09 04:39:51,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-12-09 04:39:51,884 INFO L78 Accepts]: Start accepts. Automaton has 102 states. Word has length 2977 [2018-12-09 04:39:51,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:39:51,887 INFO L225 Difference]: With dead ends: 3167 [2018-12-09 04:39:51,887 INFO L226 Difference]: Without dead ends: 3167 [2018-12-09 04:39:51,888 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3107 GetRequests, 2944 SyntacticMatches, 0 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4649 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=6754, Invalid=20306, Unknown=0, NotChecked=0, Total=27060 [2018-12-09 04:39:51,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3167 states. [2018-12-09 04:39:51,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3167 to 3157. [2018-12-09 04:39:51,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3157 states. [2018-12-09 04:39:51,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3157 states to 3157 states and 3161 transitions. [2018-12-09 04:39:51,903 INFO L78 Accepts]: Start accepts. Automaton has 3157 states and 3161 transitions. Word has length 2977 [2018-12-09 04:39:51,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:39:51,904 INFO L480 AbstractCegarLoop]: Abstraction has 3157 states and 3161 transitions. [2018-12-09 04:39:51,904 INFO L481 AbstractCegarLoop]: Interpolant automaton has 102 states. [2018-12-09 04:39:51,904 INFO L276 IsEmpty]: Start isEmpty. Operand 3157 states and 3161 transitions. [2018-12-09 04:39:51,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3144 [2018-12-09 04:39:51,937 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:39:51,937 INFO L402 BasicCegarLoop]: trace histogram [559, 559, 558, 558, 558, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:39:51,937 INFO L423 AbstractCegarLoop]: === Iteration 86 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:39:51,937 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:39:51,937 INFO L82 PathProgramCache]: Analyzing trace with hash -2065956834, now seen corresponding path program 74 times [2018-12-09 04:39:51,938 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:39:51,938 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:39:51,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:39:51,938 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 04:39:51,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:39:52,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 04:39:55,849 INFO L134 CoverageAnalysis]: Checked inductivity of 801226 backedges. 167452 proven. 10909 refuted. 0 times theorem prover too weak. 622865 trivial. 0 not checked. [2018-12-09 04:39:55,849 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 04:39:55,850 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 04:39:55,855 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 04:39:56,346 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 04:39:56,346 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 04:39:56,370 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 04:39:59,615 INFO L134 CoverageAnalysis]: Checked inductivity of 801226 backedges. 167914 proven. 2356 refuted. 0 times theorem prover too weak. 630956 trivial. 0 not checked. [2018-12-09 04:39:59,633 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 04:39:59,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 66] total 103 [2018-12-09 04:39:59,634 INFO L459 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-12-09 04:39:59,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-12-09 04:39:59,635 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2222, Invalid=8284, Unknown=0, NotChecked=0, Total=10506 [2018-12-09 04:39:59,635 INFO L87 Difference]: Start difference. First operand 3157 states and 3161 transitions. Second operand 103 states. [2018-12-09 04:40:02,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 04:40:02,115 INFO L93 Difference]: Finished difference Result 3168 states and 3170 transitions. [2018-12-09 04:40:02,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2018-12-09 04:40:02,116 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 3143 [2018-12-09 04:40:02,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 04:40:02,124 INFO L225 Difference]: With dead ends: 3168 [2018-12-09 04:40:02,125 INFO L226 Difference]: Without dead ends: 3162 [2018-12-09 04:40:02,128 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3279 GetRequests, 3112 SyntacticMatches, 0 SemanticMatches, 167 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9668 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=6215, Invalid=22177, Unknown=0, NotChecked=0, Total=28392 [2018-12-09 04:40:02,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3162 states. [2018-12-09 04:40:02,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3162 to 3157. [2018-12-09 04:40:02,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3157 states. [2018-12-09 04:40:02,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3157 states to 3157 states and 3159 transitions. [2018-12-09 04:40:02,151 INFO L78 Accepts]: Start accepts. Automaton has 3157 states and 3159 transitions. Word has length 3143 [2018-12-09 04:40:02,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 04:40:02,152 INFO L480 AbstractCegarLoop]: Abstraction has 3157 states and 3159 transitions. [2018-12-09 04:40:02,152 INFO L481 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-12-09 04:40:02,153 INFO L276 IsEmpty]: Start isEmpty. Operand 3157 states and 3159 transitions. [2018-12-09 04:40:02,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3149 [2018-12-09 04:40:02,187 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 04:40:02,188 INFO L402 BasicCegarLoop]: trace histogram [560, 560, 559, 559, 559, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 04:40:02,188 INFO L423 AbstractCegarLoop]: === Iteration 87 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-12-09 04:40:02,188 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 04:40:02,188 INFO L82 PathProgramCache]: Analyzing trace with hash 2091587081, now seen corresponding path program 75 times [2018-12-09 04:40:02,189 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 04:40:02,189 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 04:40:02,189 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:40:02,189 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 04:40:02,189 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 04:40:03,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 04:40:04,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 04:40:04,458 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 04:40:04,691 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 04:40:04 BoogieIcfgContainer [2018-12-09 04:40:04,691 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 04:40:04,692 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 04:40:04,692 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 04:40:04,692 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 04:40:04,692 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 04:30:53" (3/4) ... [2018-12-09 04:40:04,694 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-09 04:40:04,888 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_98d1e647-d78f-493f-a313-05e1f9b41499/bin-2019/uautomizer/witness.graphml [2018-12-09 04:40:04,889 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 04:40:04,890 INFO L168 Benchmark]: Toolchain (without parser) took 551766.82 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 954.4 MB in the beginning and 669.3 MB in the end (delta: 285.1 MB). Peak memory consumption was 4.3 GB. Max. memory is 11.5 GB. [2018-12-09 04:40:04,891 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 04:40:04,891 INFO L168 Benchmark]: CACSL2BoogieTranslator took 123.20 ms. Allocated memory is still 1.0 GB. Free memory was 954.4 MB in the beginning and 943.6 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-12-09 04:40:04,891 INFO L168 Benchmark]: Boogie Preprocessor took 20.60 ms. Allocated memory is still 1.0 GB. Free memory was 943.6 MB in the beginning and 941.0 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-09 04:40:04,891 INFO L168 Benchmark]: RCFGBuilder took 194.96 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 92.8 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -132.7 MB). Peak memory consumption was 13.3 MB. Max. memory is 11.5 GB. [2018-12-09 04:40:04,892 INFO L168 Benchmark]: TraceAbstraction took 551228.22 ms. Allocated memory was 1.1 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 752.4 MB in the end (delta: 321.2 MB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2018-12-09 04:40:04,892 INFO L168 Benchmark]: Witness Printer took 197.08 ms. Allocated memory is still 5.0 GB. Free memory was 752.4 MB in the beginning and 669.3 MB in the end (delta: 83.1 MB). Peak memory consumption was 83.1 MB. Max. memory is 11.5 GB. [2018-12-09 04:40:04,893 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 979.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 123.20 ms. Allocated memory is still 1.0 GB. Free memory was 954.4 MB in the beginning and 943.6 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 20.60 ms. Allocated memory is still 1.0 GB. Free memory was 943.6 MB in the beginning and 941.0 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 194.96 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 92.8 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -132.7 MB). Peak memory consumption was 13.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 551228.22 ms. Allocated memory was 1.1 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 752.4 MB in the end (delta: 321.2 MB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. * Witness Printer took 197.08 ms. Allocated memory is still 5.0 GB. Free memory was 752.4 MB in the beginning and 669.3 MB in the end (delta: 83.1 MB). Peak memory consumption was 83.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: pointer dereference may fail pointer dereference may fail We found a FailurePath: [L24] int i, b[32]; [L25] char mask[32]; [L26] i = 0 VAL [b={157:0}, i=0, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=0, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=0, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=0, b={140:0}, b={140:0}, i=0, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={140:0}, b={140:0}, i=0, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={140:0}, b={140:0}, i=0, size=0] [L18] EXPR b[i] VAL [\old(size)=0, b={140:0}, b={140:0}, b[i]=148, i=0, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={140:0}, b={140:0}, i=1, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={140:0}, b={140:0}, i=1, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={140:0}, b={140:0}, i=1, size=0] [L18] EXPR b[i] VAL [\old(size)=0, b={140:0}, b={140:0}, b[i]=162, i=1, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={140:0}, b={140:0}, i=2, size=0] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=0, b={140:0}, b={140:0}, i=2, size=0] [L20] return i; VAL [\old(size)=0, \result=2, b={140:0}, b={140:0}, i=2, size=0] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=2, i=0, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=2, i=0, mask={140:0}] [L26] i++ VAL [b={157:0}, i=1, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=1, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=1, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=148, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=162, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=143, i=2, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=3, size=1] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=1, b={140:0}, b={140:0}, i=3, size=1] [L20] return i; VAL [\old(size)=1, \result=3, b={140:0}, b={140:0}, i=3, size=1] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=3, i=1, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=3, i=1, mask={140:0}] [L26] i++ VAL [b={157:0}, i=2, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=2, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=2, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=148, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=162, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=143, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=131, i=3, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=4, size=2] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=2, b={140:0}, b={140:0}, i=4, size=2] [L20] return i; VAL [\old(size)=2, \result=4, b={140:0}, b={140:0}, i=4, size=2] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=4, i=2, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=4, i=2, mask={140:0}] [L26] i++ VAL [b={157:0}, i=3, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=3, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=3, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=148, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=162, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=143, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=131, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=130, i=4, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=5, size=3] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=3, b={140:0}, b={140:0}, i=5, size=3] [L20] return i; VAL [\old(size)=3, \result=5, b={140:0}, b={140:0}, i=5, size=3] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=5, i=3, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=5, i=3, mask={140:0}] [L26] i++ VAL [b={157:0}, i=4, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=4, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=4, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=148, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=162, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=143, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=131, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=130, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=139, i=5, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=6, size=4] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=4, b={140:0}, b={140:0}, i=6, size=4] [L20] return i; VAL [\old(size)=4, \result=6, b={140:0}, b={140:0}, i=6, size=4] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=6, i=4, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=6, i=4, mask={140:0}] [L26] i++ VAL [b={157:0}, i=5, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=5, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=5, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=148, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=162, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=143, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=131, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=130, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=139, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=129, i=6, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=7, size=5] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=5, b={140:0}, b={140:0}, i=7, size=5] [L20] return i; VAL [\old(size)=5, \result=7, b={140:0}, b={140:0}, i=7, size=5] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=7, i=5, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=7, i=5, mask={140:0}] [L26] i++ VAL [b={157:0}, i=6, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=6, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=6, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=148, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=162, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=143, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=131, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=130, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=139, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=129, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=149, i=7, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=8, size=6] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=6, b={140:0}, b={140:0}, i=8, size=6] [L20] return i; VAL [\old(size)=6, \result=8, b={140:0}, b={140:0}, i=8, size=6] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=8, i=6, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=8, i=6, mask={140:0}] [L26] i++ VAL [b={157:0}, i=7, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=7, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=7, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=148, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=162, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=143, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=131, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=130, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=139, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=129, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=149, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=155, i=8, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=9, size=7] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=7, b={140:0}, b={140:0}, i=9, size=7] [L20] return i; VAL [\old(size)=7, \result=9, b={140:0}, b={140:0}, i=9, size=7] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=9, i=7, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=9, i=7, mask={140:0}] [L26] i++ VAL [b={157:0}, i=8, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=8, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=8, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=148, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=162, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=143, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=131, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=130, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=139, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=129, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=149, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=155, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=135, i=9, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=10, size=8] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=8, b={140:0}, b={140:0}, i=10, size=8] [L20] return i; VAL [\old(size)=8, \result=10, b={140:0}, b={140:0}, i=10, size=8] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=10, i=8, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=10, i=8, mask={140:0}] [L26] i++ VAL [b={157:0}, i=9, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=9, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=9, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=148, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=162, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=143, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=131, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=130, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=139, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=129, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=149, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=155, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=135, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=150, i=10, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=11, size=9] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=9, b={140:0}, b={140:0}, i=11, size=9] [L20] return i; VAL [\old(size)=9, \result=11, b={140:0}, b={140:0}, i=11, size=9] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=11, i=9, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=11, i=9, mask={140:0}] [L26] i++ VAL [b={157:0}, i=10, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=10, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=10, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=148, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=162, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=143, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=131, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=130, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=139, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=129, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=149, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=155, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=135, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=146, i=11, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=12, size=10] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=10, b={140:0}, b={140:0}, i=12, size=10] [L20] return i; VAL [\old(size)=10, \result=12, b={140:0}, b={140:0}, i=12, size=10] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=12, i=10, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=12, i=10, mask={140:0}] [L26] i++ VAL [b={157:0}, i=11, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=11, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=11, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=148, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=162, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=143, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=131, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=130, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=139, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=129, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=149, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=155, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=135, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=146, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=151, i=12, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=13, size=11] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=11, b={140:0}, b={140:0}, i=13, size=11] [L20] return i; VAL [\old(size)=11, \result=13, b={140:0}, b={140:0}, i=13, size=11] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=13, i=11, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=13, i=11, mask={140:0}] [L26] i++ VAL [b={157:0}, i=12, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=12, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=12, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=148, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=162, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=143, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=131, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=130, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=139, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=129, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=149, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=155, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=135, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=146, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=151, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=158, i=13, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=14, size=12] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=12, b={140:0}, b={140:0}, i=14, size=12] [L20] return i; VAL [\old(size)=12, \result=14, b={140:0}, b={140:0}, i=14, size=12] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=14, i=12, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=14, i=12, mask={140:0}] [L26] i++ VAL [b={157:0}, i=13, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=13, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=13, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=148, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=162, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=143, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=131, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=130, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=139, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=129, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=149, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=155, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=135, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=146, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=151, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=158, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=154, i=14, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=15, size=13] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=13, b={140:0}, b={140:0}, i=15, size=13] [L20] return i; VAL [\old(size)=13, \result=15, b={140:0}, b={140:0}, i=15, size=13] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=15, i=13, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=15, i=13, mask={140:0}] [L26] i++ VAL [b={157:0}, i=14, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=14, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=14, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=148, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=162, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=143, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=131, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=130, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=139, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=129, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=149, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=155, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=135, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=146, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=151, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=158, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=154, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=136, i=15, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=16, size=14] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=14, b={140:0}, b={140:0}, i=16, size=14] [L20] return i; VAL [\old(size)=14, \result=16, b={140:0}, b={140:0}, i=16, size=14] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=16, i=14, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=16, i=14, mask={140:0}] [L26] i++ VAL [b={157:0}, i=15, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=15, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=15, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=148, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=162, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=143, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=131, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=130, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=139, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=129, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=149, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=155, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=135, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=146, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=151, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=158, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=154, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=136, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=138, i=16, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=17, size=15] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=15, b={140:0}, b={140:0}, i=17, size=15] [L20] return i; VAL [\old(size)=15, \result=17, b={140:0}, b={140:0}, i=17, size=15] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=17, i=15, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=17, i=15, mask={140:0}] [L26] i++ VAL [b={157:0}, i=16, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=16, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=16, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=148, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=162, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=143, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=131, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=130, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=139, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=129, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=149, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=155, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=135, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=146, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=151, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=158, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=154, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=136, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=138, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=152, i=17, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=18, size=16] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=16, b={140:0}, b={140:0}, i=18, size=16] [L20] return i; VAL [\old(size)=16, \result=18, b={140:0}, b={140:0}, i=18, size=16] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=18, i=16, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=18, i=16, mask={140:0}] [L26] i++ VAL [b={157:0}, i=17, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=17, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=17, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=148, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=162, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=143, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=131, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=130, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=139, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=129, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=149, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=155, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=135, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=146, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=151, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=158, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=154, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=136, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=138, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=152, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=141, i=18, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=19, size=17] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=17, b={140:0}, b={140:0}, i=19, size=17] [L20] return i; VAL [\old(size)=17, \result=19, b={140:0}, b={140:0}, i=19, size=17] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=19, i=17, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=19, i=17, mask={140:0}] [L26] i++ VAL [b={157:0}, i=18, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=18, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=18, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=148, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=162, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=143, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=131, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=130, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=139, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=129, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=149, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=155, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=135, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=146, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=151, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=158, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=154, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=136, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=138, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=152, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=141, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=132, i=19, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=20, size=18] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=18, b={140:0}, b={140:0}, i=20, size=18] [L20] return i; VAL [\old(size)=18, \result=20, b={140:0}, b={140:0}, i=20, size=18] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=20, i=18, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=20, i=18, mask={140:0}] [L26] i++ VAL [b={157:0}, i=19, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=19, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=19, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=148, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=162, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=143, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=131, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=130, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=139, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=129, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=149, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=155, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=135, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=146, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=151, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=158, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=154, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=136, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=138, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=152, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=141, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=132, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=133, i=20, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=21, size=19] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=19, b={140:0}, b={140:0}, i=21, size=19] [L20] return i; VAL [\old(size)=19, \result=21, b={140:0}, b={140:0}, i=21, size=19] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=21, i=19, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=21, i=19, mask={140:0}] [L26] i++ VAL [b={157:0}, i=20, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=20, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=20, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=148, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=162, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=143, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=131, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=130, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=139, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=129, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=149, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=155, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=135, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=146, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=151, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=158, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=154, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=136, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=138, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=152, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=141, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=132, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=133, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=137, i=21, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=22, size=20] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=20, b={140:0}, b={140:0}, i=22, size=20] [L20] return i; VAL [\old(size)=20, \result=22, b={140:0}, b={140:0}, i=22, size=20] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=22, i=20, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=22, i=20, mask={140:0}] [L26] i++ VAL [b={157:0}, i=21, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=21, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=21, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=148, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=162, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=143, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=131, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=130, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=139, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=129, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=149, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=155, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=135, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=146, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=151, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=158, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=154, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=136, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=138, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=152, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=141, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=132, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=133, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=137, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=159, i=22, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=23, size=21] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=21, b={140:0}, b={140:0}, i=23, size=21] [L20] return i; VAL [\old(size)=21, \result=23, b={140:0}, b={140:0}, i=23, size=21] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=23, i=21, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=23, i=21, mask={140:0}] [L26] i++ VAL [b={157:0}, i=22, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=22, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=22, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=148, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=162, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=143, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=131, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=130, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=139, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=129, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=149, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=155, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=135, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=146, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=151, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=158, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=154, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=136, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=138, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=152, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=141, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=132, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=133, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=137, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=159, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=163, i=23, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=24, size=22] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=22, b={140:0}, b={140:0}, i=24, size=22] [L20] return i; VAL [\old(size)=22, \result=24, b={140:0}, b={140:0}, i=24, size=22] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=24, i=22, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=24, i=22, mask={140:0}] [L26] i++ VAL [b={157:0}, i=23, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=23, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=23, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=148, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=162, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=143, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=131, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=130, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=139, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=129, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=149, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=155, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=135, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=146, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=151, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=158, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=154, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=136, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=138, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=152, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=141, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=132, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=133, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=137, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=159, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=163, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=144, i=24, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=25, size=23] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=23, b={140:0}, b={140:0}, i=25, size=23] [L20] return i; VAL [\old(size)=23, \result=25, b={140:0}, b={140:0}, i=25, size=23] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=25, i=23, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=25, i=23, mask={140:0}] [L26] i++ VAL [b={157:0}, i=24, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=24, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=24, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=148, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=162, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=143, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=131, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=130, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=139, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=129, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=149, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=155, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=135, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=146, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=151, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=158, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=154, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=136, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=138, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=152, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=141, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=132, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=133, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=137, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=159, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=163, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=144, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=153, i=25, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=26, size=24] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=24, b={140:0}, b={140:0}, i=26, size=24] [L20] return i; VAL [\old(size)=24, \result=26, b={140:0}, b={140:0}, i=26, size=24] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=26, i=24, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=26, i=24, mask={140:0}] [L26] i++ VAL [b={157:0}, i=25, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=25, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=25, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=148, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=162, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=143, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=131, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=130, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=139, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=129, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=149, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=155, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=135, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=146, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=151, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=158, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=154, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=136, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=138, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=152, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=141, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=132, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=133, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=137, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=159, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=163, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=144, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=153, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=145, i=26, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=27, size=25] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=25, b={140:0}, b={140:0}, i=27, size=25] [L20] return i; VAL [\old(size)=25, \result=27, b={140:0}, b={140:0}, i=27, size=25] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=27, i=25, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=27, i=25, mask={140:0}] [L26] i++ VAL [b={157:0}, i=26, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=26, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=26, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=148, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=162, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=143, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=131, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=130, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=139, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=129, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=149, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=155, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=135, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=146, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=151, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=158, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=154, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=136, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=138, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=152, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=141, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=132, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=133, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=137, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=159, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=163, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=144, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=153, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=145, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=164, i=27, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=28, size=26] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=26, b={140:0}, b={140:0}, i=28, size=26] [L20] return i; VAL [\old(size)=26, \result=28, b={140:0}, b={140:0}, i=28, size=26] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=28, i=26, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=28, i=26, mask={140:0}] [L26] i++ VAL [b={157:0}, i=27, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=27, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=27, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=148, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=162, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=143, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=131, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=130, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=139, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=129, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=149, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=155, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=135, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=146, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=151, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=158, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=154, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=136, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=138, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=152, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=141, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=132, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=133, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=137, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=159, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=163, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=144, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=153, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=145, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=164, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=160, i=28, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=29, size=27] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=27, b={140:0}, b={140:0}, i=29, size=27] [L20] return i; VAL [\old(size)=27, \result=29, b={140:0}, b={140:0}, i=29, size=27] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=29, i=27, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=29, i=27, mask={140:0}] [L26] i++ VAL [b={157:0}, i=28, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=28, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=28, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=148, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=162, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=143, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=131, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=130, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=139, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=129, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=149, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=155, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=135, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=146, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=151, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=158, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=154, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=136, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=138, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=152, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=141, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=132, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=133, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=137, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=159, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=163, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=144, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=153, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=145, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=164, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=160, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=142, i=29, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=30, size=28] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=28, b={140:0}, b={140:0}, i=30, size=28] [L20] return i; VAL [\old(size)=28, \result=30, b={140:0}, b={140:0}, i=30, size=28] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=30, i=28, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=30, i=28, mask={140:0}] [L26] i++ VAL [b={157:0}, i=29, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=29, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=29, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=148, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=162, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=143, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=131, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=130, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=139, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=129, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=149, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=155, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=135, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=146, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=151, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=158, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=154, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=136, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=138, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=152, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=141, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=132, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=133, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=137, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=159, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=163, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=144, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=153, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=145, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=164, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=160, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=142, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=161, i=30, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=31, size=29] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=29, b={140:0}, b={140:0}, i=31, size=29] [L20] return i; VAL [\old(size)=29, \result=31, b={140:0}, b={140:0}, i=31, size=29] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=31, i=29, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=31, i=29, mask={140:0}] [L26] i++ VAL [b={157:0}, i=30, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=30, mask={140:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=30, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=148, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=162, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=143, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=131, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=130, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=139, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=129, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=149, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=155, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=135, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=146, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=151, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=158, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=154, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=136, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=138, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=152, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=141, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=132, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=133, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=137, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=159, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=163, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=144, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=153, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=145, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=164, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=160, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=142, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=161, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=134, i=31, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=32, size=30] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=30, b={140:0}, b={140:0}, i=32, size=30] [L20] return i; VAL [\old(size)=30, \result=32, b={140:0}, b={140:0}, i=32, size=30] [L27] RET, EXPR foo(mask, i) VAL [b={157:0}, foo(mask, i)=32, i=30, mask={140:0}] [L27] b[i] = foo(mask, i) VAL [b={157:0}, foo(mask, i)=32, i=30, mask={140:0}] [L26] i++ VAL [b={157:0}, i=31, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=31, mask={140:0}] [L27] CALL foo(mask, i) VAL [\old(size)=31, b={140:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=148, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=162, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=143, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=131, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=130, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=139, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=129, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=149, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=155, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=135, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=146, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=151, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=158, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=154, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=136, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=138, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=152, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=141, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=132, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=133, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=137, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=159, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=163, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=144, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=153, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=145, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=164, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=160, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=142, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=161, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=134, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L18] a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L18] b[i] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 40 locations, 8 error locations. UNSAFE Result, 551.1s OverallTime, 87 OverallIterations, 560 TraceHistogramMax, 138.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3109 SDtfs, 44489 SDslu, 40350 SDs, 0 SdLazy, 169191 SolverSat, 5912 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 52.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 103537 GetRequests, 95279 SyntacticMatches, 879 SemanticMatches, 7379 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 255142 ImplicationChecksByTransitivity, 140.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3157occurred in iteration=85, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 86 MinimizatonAttempts, 2372 StatesRemovedByMinimization, 84 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 3.6s SsaConstructionTime, 179.0s SatisfiabilityAnalysisTime, 171.7s InterpolantComputationTime, 198719 NumberOfCodeBlocks, 183961 NumberOfCodeBlocksAsserted, 1310 NumberOfCheckSat, 195405 ConstructedInterpolants, 27136 QuantifiedInterpolants, 946626682 SizeOfPredicates, 333 NumberOfNonLiveVariables, 210227 ConjunctsInSsa, 3142 ConjunctsInUnsatCore, 166 InterpolantComputations, 7 PerfectInterpolantSequences, 28900419/29226346 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...