./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-09 15:44:04,067 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 15:44:04,068 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 15:44:04,076 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 15:44:04,076 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 15:44:04,077 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 15:44:04,078 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 15:44:04,079 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 15:44:04,080 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 15:44:04,080 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 15:44:04,081 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 15:44:04,081 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 15:44:04,082 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 15:44:04,083 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 15:44:04,083 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 15:44:04,084 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 15:44:04,085 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 15:44:04,086 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 15:44:04,087 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 15:44:04,088 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 15:44:04,089 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 15:44:04,090 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 15:44:04,091 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 15:44:04,091 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 15:44:04,092 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 15:44:04,092 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 15:44:04,093 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 15:44:04,094 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 15:44:04,094 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 15:44:04,095 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 15:44:04,095 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 15:44:04,096 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 15:44:04,096 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 15:44:04,096 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 15:44:04,096 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 15:44:04,097 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 15:44:04,097 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-12-09 15:44:04,107 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 15:44:04,107 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 15:44:04,107 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 15:44:04,107 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 15:44:04,108 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-09 15:44:04,108 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-09 15:44:04,108 INFO L133 SettingsManager]: * Use SBE=true [2018-12-09 15:44:04,108 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 15:44:04,108 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-09 15:44:04,109 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-09 15:44:04,110 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 15:44:04,110 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 15:44:04,110 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 15:44:04,110 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 15:44:04,110 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 15:44:04,110 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 15:44:04,110 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 15:44:04,110 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-09 15:44:04,110 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 15:44:04,111 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 [2018-12-09 15:44:04,132 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 15:44:04,139 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 15:44:04,141 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 15:44:04,142 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 15:44:04,143 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 15:44:04,143 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-09 15:44:04,180 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/data/1963f0905/70e94aaf76614d0e8f41ca35f6b8be0a/FLAG54d56cea4 [2018-12-09 15:44:04,611 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 15:44:04,611 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-09 15:44:04,615 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/data/1963f0905/70e94aaf76614d0e8f41ca35f6b8be0a/FLAG54d56cea4 [2018-12-09 15:44:04,622 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/data/1963f0905/70e94aaf76614d0e8f41ca35f6b8be0a [2018-12-09 15:44:04,624 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 15:44:04,625 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-12-09 15:44:04,625 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 15:44:04,625 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 15:44:04,627 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 15:44:04,628 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,629 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5080051a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04, skipping insertion in model container [2018-12-09 15:44:04,629 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,633 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 15:44:04,642 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 15:44:04,723 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 15:44:04,729 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 15:44:04,738 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 15:44:04,747 INFO L195 MainTranslator]: Completed translation [2018-12-09 15:44:04,747 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04 WrapperNode [2018-12-09 15:44:04,747 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 15:44:04,748 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 15:44:04,748 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 15:44:04,748 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 15:44:04,755 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,755 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,760 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,760 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,792 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,796 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,797 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (1/1) ... [2018-12-09 15:44:04,798 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 15:44:04,799 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 15:44:04,799 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 15:44:04,799 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 15:44:04,800 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 15:44:04,832 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 15:44:04,832 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 15:44:04,832 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-12-09 15:44:04,832 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 15:44:04,832 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-12-09 15:44:04,832 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-09 15:44:04,832 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 15:44:04,832 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-09 15:44:04,833 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-09 15:44:04,833 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-09 15:44:04,833 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 15:44:04,833 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 15:44:04,959 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 15:44:04,959 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-12-09 15:44:04,959 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 03:44:04 BoogieIcfgContainer [2018-12-09 15:44:04,959 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 15:44:04,960 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 15:44:04,960 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 15:44:04,961 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 15:44:04,962 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 03:44:04" (1/3) ... [2018-12-09 15:44:04,962 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5e07eb78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 03:44:04, skipping insertion in model container [2018-12-09 15:44:04,962 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 03:44:04" (2/3) ... [2018-12-09 15:44:04,962 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5e07eb78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 03:44:04, skipping insertion in model container [2018-12-09 15:44:04,962 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 03:44:04" (3/3) ... [2018-12-09 15:44:04,963 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-12-09 15:44:04,969 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 15:44:04,974 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-12-09 15:44:04,984 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-12-09 15:44:04,998 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-09 15:44:04,999 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 15:44:04,999 INFO L383 AbstractCegarLoop]: Hoare is false [2018-12-09 15:44:04,999 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 15:44:04,999 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 15:44:04,999 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 15:44:04,999 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 15:44:04,999 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 15:44:04,999 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 15:44:05,009 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states. [2018-12-09 15:44:05,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-12-09 15:44:05,015 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,015 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,016 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,021 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,022 INFO L82 PathProgramCache]: Analyzing trace with hash 1909189377, now seen corresponding path program 1 times [2018-12-09 15:44:05,023 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,023 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,051 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,052 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,114 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 15:44:05,115 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 15:44:05,117 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 15:44:05,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 15:44:05,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 15:44:05,127 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 3 states. [2018-12-09 15:44:05,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:05,167 INFO L93 Difference]: Finished difference Result 58 states and 63 transitions. [2018-12-09 15:44:05,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 15:44:05,169 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 10 [2018-12-09 15:44:05,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:05,174 INFO L225 Difference]: With dead ends: 58 [2018-12-09 15:44:05,174 INFO L226 Difference]: Without dead ends: 54 [2018-12-09 15:44:05,175 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 15:44:05,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-12-09 15:44:05,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 39. [2018-12-09 15:44:05,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-12-09 15:44:05,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 42 transitions. [2018-12-09 15:44:05,199 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 42 transitions. Word has length 10 [2018-12-09 15:44:05,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:05,199 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 42 transitions. [2018-12-09 15:44:05,200 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 15:44:05,200 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 42 transitions. [2018-12-09 15:44:05,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-12-09 15:44:05,200 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,200 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,200 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,201 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,201 INFO L82 PathProgramCache]: Analyzing trace with hash -941983064, now seen corresponding path program 1 times [2018-12-09 15:44:05,201 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,201 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,222 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 15:44:05,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-09 15:44:05,223 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 15:44:05,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 15:44:05,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 15:44:05,223 INFO L87 Difference]: Start difference. First operand 39 states and 42 transitions. Second operand 3 states. [2018-12-09 15:44:05,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:05,249 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-12-09 15:44:05,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 15:44:05,250 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-12-09 15:44:05,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:05,252 INFO L225 Difference]: With dead ends: 49 [2018-12-09 15:44:05,252 INFO L226 Difference]: Without dead ends: 49 [2018-12-09 15:44:05,252 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 15:44:05,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-12-09 15:44:05,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 41. [2018-12-09 15:44:05,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-12-09 15:44:05,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2018-12-09 15:44:05,256 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 11 [2018-12-09 15:44:05,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:05,257 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2018-12-09 15:44:05,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 15:44:05,257 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2018-12-09 15:44:05,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-09 15:44:05,257 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,257 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,258 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,258 INFO L82 PathProgramCache]: Analyzing trace with hash 863296133, now seen corresponding path program 1 times [2018-12-09 15:44:05,258 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,258 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,295 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 15:44:05,295 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 15:44:05,295 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 15:44:05,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 15:44:05,296 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 15:44:05,296 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 5 states. [2018-12-09 15:44:05,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:05,337 INFO L93 Difference]: Finished difference Result 40 states and 44 transitions. [2018-12-09 15:44:05,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 15:44:05,337 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 12 [2018-12-09 15:44:05,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:05,338 INFO L225 Difference]: With dead ends: 40 [2018-12-09 15:44:05,338 INFO L226 Difference]: Without dead ends: 40 [2018-12-09 15:44:05,338 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 15:44:05,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-12-09 15:44:05,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-12-09 15:44:05,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-12-09 15:44:05,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2018-12-09 15:44:05,340 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 12 [2018-12-09 15:44:05,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:05,341 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2018-12-09 15:44:05,341 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 15:44:05,341 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2018-12-09 15:44:05,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-12-09 15:44:05,341 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,341 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,341 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,341 INFO L82 PathProgramCache]: Analyzing trace with hash 863296134, now seen corresponding path program 1 times [2018-12-09 15:44:05,342 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,342 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,342 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,405 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 15:44:05,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 15:44:05,405 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 15:44:05,405 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 15:44:05,405 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-09 15:44:05,405 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 6 states. [2018-12-09 15:44:05,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:05,458 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-12-09 15:44:05,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 15:44:05,458 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 12 [2018-12-09 15:44:05,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:05,459 INFO L225 Difference]: With dead ends: 42 [2018-12-09 15:44:05,459 INFO L226 Difference]: Without dead ends: 42 [2018-12-09 15:44:05,459 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-12-09 15:44:05,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-12-09 15:44:05,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 39. [2018-12-09 15:44:05,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-12-09 15:44:05,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 43 transitions. [2018-12-09 15:44:05,461 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 43 transitions. Word has length 12 [2018-12-09 15:44:05,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:05,461 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 43 transitions. [2018-12-09 15:44:05,461 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 15:44:05,462 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 43 transitions. [2018-12-09 15:44:05,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-12-09 15:44:05,462 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,462 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,462 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,462 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,462 INFO L82 PathProgramCache]: Analyzing trace with hash 143250926, now seen corresponding path program 1 times [2018-12-09 15:44:05,462 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,462 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,463 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,491 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 15:44:05,491 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-09 15:44:05,491 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 15:44:05,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 15:44:05,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 15:44:05,492 INFO L87 Difference]: Start difference. First operand 39 states and 43 transitions. Second operand 3 states. [2018-12-09 15:44:05,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:05,503 INFO L93 Difference]: Finished difference Result 37 states and 41 transitions. [2018-12-09 15:44:05,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 15:44:05,503 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-12-09 15:44:05,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:05,504 INFO L225 Difference]: With dead ends: 37 [2018-12-09 15:44:05,504 INFO L226 Difference]: Without dead ends: 37 [2018-12-09 15:44:05,504 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 15:44:05,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-12-09 15:44:05,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2018-12-09 15:44:05,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-12-09 15:44:05,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 41 transitions. [2018-12-09 15:44:05,506 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 41 transitions. Word has length 15 [2018-12-09 15:44:05,506 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:05,506 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 41 transitions. [2018-12-09 15:44:05,506 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 15:44:05,507 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 41 transitions. [2018-12-09 15:44:05,507 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-12-09 15:44:05,507 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,507 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,507 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,507 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,507 INFO L82 PathProgramCache]: Analyzing trace with hash 143250927, now seen corresponding path program 1 times [2018-12-09 15:44:05,507 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,508 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,508 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,537 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 15:44:05,537 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 15:44:05,537 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 15:44:05,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 15:44:05,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-09 15:44:05,537 INFO L87 Difference]: Start difference. First operand 37 states and 41 transitions. Second operand 6 states. [2018-12-09 15:44:05,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:05,591 INFO L93 Difference]: Finished difference Result 56 states and 61 transitions. [2018-12-09 15:44:05,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 15:44:05,592 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2018-12-09 15:44:05,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:05,592 INFO L225 Difference]: With dead ends: 56 [2018-12-09 15:44:05,592 INFO L226 Difference]: Without dead ends: 56 [2018-12-09 15:44:05,592 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 15:44:05,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-12-09 15:44:05,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 41. [2018-12-09 15:44:05,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-12-09 15:44:05,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 46 transitions. [2018-12-09 15:44:05,595 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 46 transitions. Word has length 15 [2018-12-09 15:44:05,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:05,595 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 46 transitions. [2018-12-09 15:44:05,595 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 15:44:05,595 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 46 transitions. [2018-12-09 15:44:05,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-12-09 15:44:05,596 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,596 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,596 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,596 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,596 INFO L82 PathProgramCache]: Analyzing trace with hash 1623425863, now seen corresponding path program 1 times [2018-12-09 15:44:05,596 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,596 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,597 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,615 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,616 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:05,616 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:05,622 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,635 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:05,652 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,666 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:05,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2018-12-09 15:44:05,666 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 15:44:05,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 15:44:05,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 15:44:05,667 INFO L87 Difference]: Start difference. First operand 41 states and 46 transitions. Second operand 4 states. [2018-12-09 15:44:05,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:05,685 INFO L93 Difference]: Finished difference Result 52 states and 59 transitions. [2018-12-09 15:44:05,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 15:44:05,685 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-12-09 15:44:05,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:05,686 INFO L225 Difference]: With dead ends: 52 [2018-12-09 15:44:05,686 INFO L226 Difference]: Without dead ends: 52 [2018-12-09 15:44:05,686 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 14 SyntacticMatches, 3 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 15:44:05,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-12-09 15:44:05,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 46. [2018-12-09 15:44:05,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-12-09 15:44:05,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2018-12-09 15:44:05,689 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 16 [2018-12-09 15:44:05,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:05,689 INFO L480 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2018-12-09 15:44:05,690 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 15:44:05,690 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2018-12-09 15:44:05,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-12-09 15:44:05,690 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,690 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,690 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,690 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,690 INFO L82 PathProgramCache]: Analyzing trace with hash 2121234190, now seen corresponding path program 1 times [2018-12-09 15:44:05,691 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,691 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,691 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,729 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,729 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:05,729 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:05,735 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,746 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:05,774 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,788 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:05,789 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 9 [2018-12-09 15:44:05,789 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-09 15:44:05,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-09 15:44:05,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2018-12-09 15:44:05,789 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand 9 states. [2018-12-09 15:44:05,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:05,866 INFO L93 Difference]: Finished difference Result 64 states and 68 transitions. [2018-12-09 15:44:05,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-09 15:44:05,867 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 20 [2018-12-09 15:44:05,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:05,867 INFO L225 Difference]: With dead ends: 64 [2018-12-09 15:44:05,867 INFO L226 Difference]: Without dead ends: 58 [2018-12-09 15:44:05,868 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 17 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-12-09 15:44:05,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-12-09 15:44:05,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 42. [2018-12-09 15:44:05,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-12-09 15:44:05,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 45 transitions. [2018-12-09 15:44:05,871 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 45 transitions. Word has length 20 [2018-12-09 15:44:05,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:05,871 INFO L480 AbstractCegarLoop]: Abstraction has 42 states and 45 transitions. [2018-12-09 15:44:05,872 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-09 15:44:05,872 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 45 transitions. [2018-12-09 15:44:05,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-12-09 15:44:05,872 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:05,872 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:05,873 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:05,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:05,873 INFO L82 PathProgramCache]: Analyzing trace with hash -1483602424, now seen corresponding path program 2 times [2018-12-09 15:44:05,873 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:05,873 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:05,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,874 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:05,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:05,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:05,939 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 15:44:05,939 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:05,939 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:05,945 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:44:05,955 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:44:05,955 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:05,956 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:05,987 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-09 15:44:06,001 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:06,001 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 12 [2018-12-09 15:44:06,002 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-09 15:44:06,002 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-09 15:44:06,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2018-12-09 15:44:06,002 INFO L87 Difference]: Start difference. First operand 42 states and 45 transitions. Second operand 12 states. [2018-12-09 15:44:06,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:06,107 INFO L93 Difference]: Finished difference Result 70 states and 73 transitions. [2018-12-09 15:44:06,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-09 15:44:06,107 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 21 [2018-12-09 15:44:06,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:06,108 INFO L225 Difference]: With dead ends: 70 [2018-12-09 15:44:06,108 INFO L226 Difference]: Without dead ends: 70 [2018-12-09 15:44:06,108 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=68, Invalid=172, Unknown=0, NotChecked=0, Total=240 [2018-12-09 15:44:06,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-12-09 15:44:06,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 58. [2018-12-09 15:44:06,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-12-09 15:44:06,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 61 transitions. [2018-12-09 15:44:06,111 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 61 transitions. Word has length 21 [2018-12-09 15:44:06,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:06,111 INFO L480 AbstractCegarLoop]: Abstraction has 58 states and 61 transitions. [2018-12-09 15:44:06,111 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-09 15:44:06,112 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 61 transitions. [2018-12-09 15:44:06,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-12-09 15:44:06,112 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:06,112 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:06,113 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:06,113 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:06,113 INFO L82 PathProgramCache]: Analyzing trace with hash -523456177, now seen corresponding path program 2 times [2018-12-09 15:44:06,113 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:06,113 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:06,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,114 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:06,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:06,134 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 15:44:06,135 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 15:44:06,135 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-09 15:44:06,135 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 15:44:06,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 15:44:06,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 15:44:06,135 INFO L87 Difference]: Start difference. First operand 58 states and 61 transitions. Second operand 3 states. [2018-12-09 15:44:06,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:06,154 INFO L93 Difference]: Finished difference Result 62 states and 65 transitions. [2018-12-09 15:44:06,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 15:44:06,155 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-12-09 15:44:06,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:06,155 INFO L225 Difference]: With dead ends: 62 [2018-12-09 15:44:06,155 INFO L226 Difference]: Without dead ends: 62 [2018-12-09 15:44:06,156 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 15:44:06,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-12-09 15:44:06,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 60. [2018-12-09 15:44:06,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-12-09 15:44:06,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 63 transitions. [2018-12-09 15:44:06,159 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 63 transitions. Word has length 25 [2018-12-09 15:44:06,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:06,159 INFO L480 AbstractCegarLoop]: Abstraction has 60 states and 63 transitions. [2018-12-09 15:44:06,159 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 15:44:06,160 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 63 transitions. [2018-12-09 15:44:06,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-12-09 15:44:06,160 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:06,160 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:06,161 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:06,161 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:06,161 INFO L82 PathProgramCache]: Analyzing trace with hash 2020089664, now seen corresponding path program 1 times [2018-12-09 15:44:06,161 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:06,161 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:06,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,162 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:06,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:06,208 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-09 15:44:06,208 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:06,208 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:06,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:06,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:06,228 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:06,248 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 15:44:06,268 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:06,268 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 4] total 10 [2018-12-09 15:44:06,268 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-09 15:44:06,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-09 15:44:06,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-12-09 15:44:06,269 INFO L87 Difference]: Start difference. First operand 60 states and 63 transitions. Second operand 10 states. [2018-12-09 15:44:06,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:06,343 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2018-12-09 15:44:06,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-09 15:44:06,343 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 31 [2018-12-09 15:44:06,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:06,344 INFO L225 Difference]: With dead ends: 74 [2018-12-09 15:44:06,344 INFO L226 Difference]: Without dead ends: 74 [2018-12-09 15:44:06,344 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 32 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-12-09 15:44:06,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-12-09 15:44:06,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 49. [2018-12-09 15:44:06,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-12-09 15:44:06,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2018-12-09 15:44:06,346 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 50 transitions. Word has length 31 [2018-12-09 15:44:06,346 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:06,346 INFO L480 AbstractCegarLoop]: Abstraction has 49 states and 50 transitions. [2018-12-09 15:44:06,346 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-09 15:44:06,346 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 50 transitions. [2018-12-09 15:44:06,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-12-09 15:44:06,347 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:06,347 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:06,347 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:06,347 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:06,347 INFO L82 PathProgramCache]: Analyzing trace with hash -1710006518, now seen corresponding path program 1 times [2018-12-09 15:44:06,347 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:06,347 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:06,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,348 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:06,348 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:06,397 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-12-09 15:44:06,397 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:06,397 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:06,408 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:06,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:06,421 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:06,438 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-12-09 15:44:06,452 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:06,452 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-12-09 15:44:06,452 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 15:44:06,452 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 15:44:06,453 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 15:44:06,453 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. Second operand 5 states. [2018-12-09 15:44:06,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:06,485 INFO L93 Difference]: Finished difference Result 60 states and 62 transitions. [2018-12-09 15:44:06,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 15:44:06,485 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-12-09 15:44:06,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:06,485 INFO L225 Difference]: With dead ends: 60 [2018-12-09 15:44:06,485 INFO L226 Difference]: Without dead ends: 60 [2018-12-09 15:44:06,486 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 40 SyntacticMatches, 3 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 15:44:06,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-12-09 15:44:06,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 54. [2018-12-09 15:44:06,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-12-09 15:44:06,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 56 transitions. [2018-12-09 15:44:06,487 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 56 transitions. Word has length 42 [2018-12-09 15:44:06,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:06,488 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 56 transitions. [2018-12-09 15:44:06,488 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 15:44:06,488 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 56 transitions. [2018-12-09 15:44:06,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-12-09 15:44:06,488 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:06,488 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:06,488 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:06,488 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:06,489 INFO L82 PathProgramCache]: Analyzing trace with hash -1860847279, now seen corresponding path program 1 times [2018-12-09 15:44:06,489 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:06,489 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:06,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,489 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:06,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:06,567 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 4 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-12-09 15:44:06,567 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:06,567 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:06,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:06,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:06,586 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:06,623 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 15:44:06,637 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:06,637 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8] total 15 [2018-12-09 15:44:06,637 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-09 15:44:06,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-09 15:44:06,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=167, Unknown=0, NotChecked=0, Total=210 [2018-12-09 15:44:06,637 INFO L87 Difference]: Start difference. First operand 54 states and 56 transitions. Second operand 15 states. [2018-12-09 15:44:06,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:06,748 INFO L93 Difference]: Finished difference Result 62 states and 63 transitions. [2018-12-09 15:44:06,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-12-09 15:44:06,748 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 46 [2018-12-09 15:44:06,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:06,749 INFO L225 Difference]: With dead ends: 62 [2018-12-09 15:44:06,749 INFO L226 Difference]: Without dead ends: 59 [2018-12-09 15:44:06,749 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=92, Invalid=288, Unknown=0, NotChecked=0, Total=380 [2018-12-09 15:44:06,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-12-09 15:44:06,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 54. [2018-12-09 15:44:06,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-12-09 15:44:06,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-12-09 15:44:06,751 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 46 [2018-12-09 15:44:06,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:06,751 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-12-09 15:44:06,751 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-09 15:44:06,751 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-12-09 15:44:06,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-09 15:44:06,752 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:06,752 INFO L402 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:06,752 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:06,752 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:06,752 INFO L82 PathProgramCache]: Analyzing trace with hash -374076379, now seen corresponding path program 2 times [2018-12-09 15:44:06,752 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:06,752 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:06,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:06,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:06,790 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 55 proven. 7 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 15:44:06,790 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:06,790 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:06,796 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:44:06,809 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:44:06,809 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:06,810 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:06,858 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 60 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-12-09 15:44:06,872 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:06,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 15 [2018-12-09 15:44:06,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-12-09 15:44:06,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-12-09 15:44:06,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-12-09 15:44:06,872 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 15 states. [2018-12-09 15:44:06,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:06,958 INFO L93 Difference]: Finished difference Result 83 states and 84 transitions. [2018-12-09 15:44:06,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-12-09 15:44:06,958 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 47 [2018-12-09 15:44:06,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:06,958 INFO L225 Difference]: With dead ends: 83 [2018-12-09 15:44:06,959 INFO L226 Difference]: Without dead ends: 83 [2018-12-09 15:44:06,959 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=113, Invalid=267, Unknown=0, NotChecked=0, Total=380 [2018-12-09 15:44:06,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-12-09 15:44:06,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 78. [2018-12-09 15:44:06,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-12-09 15:44:06,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 79 transitions. [2018-12-09 15:44:06,961 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 79 transitions. Word has length 47 [2018-12-09 15:44:06,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:06,961 INFO L480 AbstractCegarLoop]: Abstraction has 78 states and 79 transitions. [2018-12-09 15:44:06,961 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-12-09 15:44:06,961 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 79 transitions. [2018-12-09 15:44:06,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-12-09 15:44:06,962 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:06,962 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:06,962 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:06,962 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:06,962 INFO L82 PathProgramCache]: Analyzing trace with hash -1743494932, now seen corresponding path program 2 times [2018-12-09 15:44:06,962 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:06,962 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:06,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,963 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:06,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:06,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:07,002 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-09 15:44:07,002 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:07,002 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:07,009 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:44:07,022 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:44:07,022 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:07,024 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:07,053 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-12-09 15:44:07,053 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-12-09 15:44:07,062 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 15:44:07,064 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 15:44:07,064 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-12-09 15:44:07,065 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-09 15:44:07,068 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-09 15:44:07,077 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-12-09 15:44:07,077 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-12-09 15:44:07,174 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-12-09 15:44:07,189 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:07,190 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 7 [2018-12-09 15:44:07,190 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-09 15:44:07,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-09 15:44:07,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-09 15:44:07,190 INFO L87 Difference]: Start difference. First operand 78 states and 79 transitions. Second operand 8 states. [2018-12-09 15:44:07,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:07,284 INFO L93 Difference]: Finished difference Result 82 states and 83 transitions. [2018-12-09 15:44:07,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 15:44:07,284 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-12-09 15:44:07,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:07,285 INFO L225 Difference]: With dead ends: 82 [2018-12-09 15:44:07,285 INFO L226 Difference]: Without dead ends: 82 [2018-12-09 15:44:07,285 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 45 SyntacticMatches, 4 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-12-09 15:44:07,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-12-09 15:44:07,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 80. [2018-12-09 15:44:07,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-12-09 15:44:07,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 81 transitions. [2018-12-09 15:44:07,287 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 81 transitions. Word has length 51 [2018-12-09 15:44:07,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:07,288 INFO L480 AbstractCegarLoop]: Abstraction has 80 states and 81 transitions. [2018-12-09 15:44:07,288 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-09 15:44:07,288 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 81 transitions. [2018-12-09 15:44:07,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-09 15:44:07,289 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:07,289 INFO L402 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:07,289 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:07,289 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:07,289 INFO L82 PathProgramCache]: Analyzing trace with hash 1240037378, now seen corresponding path program 3 times [2018-12-09 15:44:07,289 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:07,289 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:07,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:07,290 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:07,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:07,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:07,353 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 104 proven. 13 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2018-12-09 15:44:07,353 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:07,353 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:07,359 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:44:07,373 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-12-09 15:44:07,374 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:07,375 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:07,399 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 104 proven. 13 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2018-12-09 15:44:07,422 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:07,422 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-12-09 15:44:07,422 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-12-09 15:44:07,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-12-09 15:44:07,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=82, Unknown=0, NotChecked=0, Total=110 [2018-12-09 15:44:07,423 INFO L87 Difference]: Start difference. First operand 80 states and 81 transitions. Second operand 11 states. [2018-12-09 15:44:07,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:07,476 INFO L93 Difference]: Finished difference Result 110 states and 112 transitions. [2018-12-09 15:44:07,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-09 15:44:07,477 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 73 [2018-12-09 15:44:07,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:07,477 INFO L225 Difference]: With dead ends: 110 [2018-12-09 15:44:07,477 INFO L226 Difference]: Without dead ends: 110 [2018-12-09 15:44:07,478 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 72 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-12-09 15:44:07,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-12-09 15:44:07,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 104. [2018-12-09 15:44:07,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-12-09 15:44:07,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 106 transitions. [2018-12-09 15:44:07,481 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 106 transitions. Word has length 73 [2018-12-09 15:44:07,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:07,481 INFO L480 AbstractCegarLoop]: Abstraction has 104 states and 106 transitions. [2018-12-09 15:44:07,481 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-12-09 15:44:07,481 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 106 transitions. [2018-12-09 15:44:07,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-12-09 15:44:07,482 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:07,482 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:07,482 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:07,483 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:07,483 INFO L82 PathProgramCache]: Analyzing trace with hash -976841143, now seen corresponding path program 3 times [2018-12-09 15:44:07,483 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:07,483 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:07,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:07,483 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:07,484 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:07,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:07,572 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 69 proven. 103 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 15:44:07,572 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:07,572 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:07,578 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:44:07,589 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-12-09 15:44:07,589 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:07,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:07,598 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-12-09 15:44:07,598 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-12-09 15:44:07,604 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-12-09 15:44:07,606 INFO L701 Elim1Store]: detected not equals via solver [2018-12-09 15:44:07,606 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-12-09 15:44:07,607 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-12-09 15:44:07,611 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-12-09 15:44:07,615 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-12-09 15:44:07,616 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2018-12-09 15:44:07,820 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 183 trivial. 0 not checked. [2018-12-09 15:44:07,835 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 15:44:07,835 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [14] total 19 [2018-12-09 15:44:07,835 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-12-09 15:44:07,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-12-09 15:44:07,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2018-12-09 15:44:07,836 INFO L87 Difference]: Start difference. First operand 104 states and 106 transitions. Second operand 19 states. [2018-12-09 15:44:08,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:08,061 INFO L93 Difference]: Finished difference Result 127 states and 129 transitions. [2018-12-09 15:44:08,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-12-09 15:44:08,061 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 77 [2018-12-09 15:44:08,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:08,062 INFO L225 Difference]: With dead ends: 127 [2018-12-09 15:44:08,062 INFO L226 Difference]: Without dead ends: 121 [2018-12-09 15:44:08,062 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 71 SyntacticMatches, 5 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 172 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=166, Invalid=646, Unknown=0, NotChecked=0, Total=812 [2018-12-09 15:44:08,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-12-09 15:44:08,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 112. [2018-12-09 15:44:08,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-12-09 15:44:08,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 114 transitions. [2018-12-09 15:44:08,065 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 114 transitions. Word has length 77 [2018-12-09 15:44:08,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:08,065 INFO L480 AbstractCegarLoop]: Abstraction has 112 states and 114 transitions. [2018-12-09 15:44:08,065 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-12-09 15:44:08,066 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 114 transitions. [2018-12-09 15:44:08,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-12-09 15:44:08,066 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:08,066 INFO L402 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:08,066 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:08,067 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:08,067 INFO L82 PathProgramCache]: Analyzing trace with hash -1811005430, now seen corresponding path program 4 times [2018-12-09 15:44:08,067 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:08,067 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:08,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:08,067 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:08,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:08,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:08,114 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 165 proven. 21 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-09 15:44:08,114 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:08,114 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:08,124 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:44:08,147 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:44:08,148 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:08,150 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:08,170 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 165 proven. 21 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-09 15:44:08,185 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:08,185 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 9 [2018-12-09 15:44:08,185 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-09 15:44:08,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-09 15:44:08,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-12-09 15:44:08,186 INFO L87 Difference]: Start difference. First operand 112 states and 114 transitions. Second operand 10 states. [2018-12-09 15:44:08,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:08,243 INFO L93 Difference]: Finished difference Result 120 states and 122 transitions. [2018-12-09 15:44:08,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 15:44:08,243 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 104 [2018-12-09 15:44:08,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:08,243 INFO L225 Difference]: With dead ends: 120 [2018-12-09 15:44:08,243 INFO L226 Difference]: Without dead ends: 120 [2018-12-09 15:44:08,244 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 100 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-12-09 15:44:08,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-12-09 15:44:08,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 113. [2018-12-09 15:44:08,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-12-09 15:44:08,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 115 transitions. [2018-12-09 15:44:08,246 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 115 transitions. Word has length 104 [2018-12-09 15:44:08,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:08,246 INFO L480 AbstractCegarLoop]: Abstraction has 113 states and 115 transitions. [2018-12-09 15:44:08,246 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-09 15:44:08,246 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 115 transitions. [2018-12-09 15:44:08,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-12-09 15:44:08,247 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:08,247 INFO L402 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:08,247 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:08,248 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:08,248 INFO L82 PathProgramCache]: Analyzing trace with hash 241027877, now seen corresponding path program 5 times [2018-12-09 15:44:08,248 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:08,248 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:08,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:08,248 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:08,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:08,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:08,360 INFO L134 CoverageAnalysis]: Checked inductivity of 500 backedges. 250 proven. 28 refuted. 0 times theorem prover too weak. 222 trivial. 0 not checked. [2018-12-09 15:44:08,360 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:08,360 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:08,366 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:44:08,396 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-12-09 15:44:08,396 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:08,398 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:08,444 INFO L134 CoverageAnalysis]: Checked inductivity of 500 backedges. 213 proven. 38 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-09 15:44:08,459 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:08,459 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 7] total 18 [2018-12-09 15:44:08,460 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-12-09 15:44:08,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-12-09 15:44:08,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-12-09 15:44:08,460 INFO L87 Difference]: Start difference. First operand 113 states and 115 transitions. Second operand 19 states. [2018-12-09 15:44:08,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:08,673 INFO L93 Difference]: Finished difference Result 175 states and 181 transitions. [2018-12-09 15:44:08,673 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-09 15:44:08,673 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 109 [2018-12-09 15:44:08,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:08,673 INFO L225 Difference]: With dead ends: 175 [2018-12-09 15:44:08,673 INFO L226 Difference]: Without dead ends: 175 [2018-12-09 15:44:08,674 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 104 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=118, Invalid=532, Unknown=0, NotChecked=0, Total=650 [2018-12-09 15:44:08,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-12-09 15:44:08,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 149. [2018-12-09 15:44:08,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-12-09 15:44:08,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 153 transitions. [2018-12-09 15:44:08,676 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 153 transitions. Word has length 109 [2018-12-09 15:44:08,676 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:08,676 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 153 transitions. [2018-12-09 15:44:08,676 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-12-09 15:44:08,676 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 153 transitions. [2018-12-09 15:44:08,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-12-09 15:44:08,677 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:08,677 INFO L402 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:08,677 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:08,677 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:08,677 INFO L82 PathProgramCache]: Analyzing trace with hash -937043486, now seen corresponding path program 6 times [2018-12-09 15:44:08,678 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:08,678 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:08,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:08,678 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:08,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:08,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:08,795 INFO L134 CoverageAnalysis]: Checked inductivity of 955 backedges. 553 proven. 153 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2018-12-09 15:44:08,796 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:08,796 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:08,804 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:44:08,834 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-12-09 15:44:08,835 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:08,837 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:08,921 INFO L134 CoverageAnalysis]: Checked inductivity of 955 backedges. 396 proven. 49 refuted. 0 times theorem prover too weak. 510 trivial. 0 not checked. [2018-12-09 15:44:08,937 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:08,937 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 11] total 26 [2018-12-09 15:44:08,937 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-12-09 15:44:08,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-12-09 15:44:08,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=558, Unknown=0, NotChecked=0, Total=650 [2018-12-09 15:44:08,937 INFO L87 Difference]: Start difference. First operand 149 states and 153 transitions. Second operand 26 states. [2018-12-09 15:44:09,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:09,545 INFO L93 Difference]: Finished difference Result 250 states and 256 transitions. [2018-12-09 15:44:09,545 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-12-09 15:44:09,545 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 145 [2018-12-09 15:44:09,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:09,546 INFO L225 Difference]: With dead ends: 250 [2018-12-09 15:44:09,546 INFO L226 Difference]: Without dead ends: 250 [2018-12-09 15:44:09,546 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 194 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 803 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=644, Invalid=2662, Unknown=0, NotChecked=0, Total=3306 [2018-12-09 15:44:09,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2018-12-09 15:44:09,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 204. [2018-12-09 15:44:09,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-12-09 15:44:09,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 209 transitions. [2018-12-09 15:44:09,550 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 209 transitions. Word has length 145 [2018-12-09 15:44:09,550 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:09,550 INFO L480 AbstractCegarLoop]: Abstraction has 204 states and 209 transitions. [2018-12-09 15:44:09,550 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-12-09 15:44:09,550 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 209 transitions. [2018-12-09 15:44:09,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-12-09 15:44:09,551 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:09,551 INFO L402 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:09,551 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:09,552 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:09,552 INFO L82 PathProgramCache]: Analyzing trace with hash 1055653604, now seen corresponding path program 7 times [2018-12-09 15:44:09,552 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:09,552 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:09,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:09,552 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:09,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:09,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:09,678 INFO L134 CoverageAnalysis]: Checked inductivity of 1678 backedges. 957 proven. 273 refuted. 0 times theorem prover too weak. 448 trivial. 0 not checked. [2018-12-09 15:44:09,678 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:09,678 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:09,684 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:09,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:09,716 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:09,798 INFO L134 CoverageAnalysis]: Checked inductivity of 1678 backedges. 1018 proven. 55 refuted. 0 times theorem prover too weak. 605 trivial. 0 not checked. [2018-12-09 15:44:09,813 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:09,813 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 14] total 24 [2018-12-09 15:44:09,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-12-09 15:44:09,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-12-09 15:44:09,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=440, Unknown=0, NotChecked=0, Total=552 [2018-12-09 15:44:09,814 INFO L87 Difference]: Start difference. First operand 204 states and 209 transitions. Second operand 24 states. [2018-12-09 15:44:10,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:10,078 INFO L93 Difference]: Finished difference Result 224 states and 226 transitions. [2018-12-09 15:44:10,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-12-09 15:44:10,079 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 186 [2018-12-09 15:44:10,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:10,079 INFO L225 Difference]: With dead ends: 224 [2018-12-09 15:44:10,080 INFO L226 Difference]: Without dead ends: 203 [2018-12-09 15:44:10,080 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 215 GetRequests, 182 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 267 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=278, Invalid=912, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 15:44:10,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states. [2018-12-09 15:44:10,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 200. [2018-12-09 15:44:10,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2018-12-09 15:44:10,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 201 transitions. [2018-12-09 15:44:10,084 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 201 transitions. Word has length 186 [2018-12-09 15:44:10,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:10,085 INFO L480 AbstractCegarLoop]: Abstraction has 200 states and 201 transitions. [2018-12-09 15:44:10,085 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-12-09 15:44:10,085 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 201 transitions. [2018-12-09 15:44:10,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2018-12-09 15:44:10,086 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:10,086 INFO L402 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:10,086 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:10,087 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:10,087 INFO L82 PathProgramCache]: Analyzing trace with hash 1146107562, now seen corresponding path program 8 times [2018-12-09 15:44:10,087 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:10,087 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:10,087 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:10,088 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:10,088 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:10,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:10,223 INFO L134 CoverageAnalysis]: Checked inductivity of 1937 backedges. 723 proven. 76 refuted. 0 times theorem prover too weak. 1138 trivial. 0 not checked. [2018-12-09 15:44:10,223 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:10,223 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:10,231 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:44:10,264 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:44:10,264 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:10,266 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:10,332 INFO L134 CoverageAnalysis]: Checked inductivity of 1937 backedges. 675 proven. 87 refuted. 0 times theorem prover too weak. 1175 trivial. 0 not checked. [2018-12-09 15:44:10,347 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:10,347 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8] total 20 [2018-12-09 15:44:10,347 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-12-09 15:44:10,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-12-09 15:44:10,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=355, Unknown=0, NotChecked=0, Total=420 [2018-12-09 15:44:10,348 INFO L87 Difference]: Start difference. First operand 200 states and 201 transitions. Second operand 21 states. [2018-12-09 15:44:10,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:10,629 INFO L93 Difference]: Finished difference Result 268 states and 272 transitions. [2018-12-09 15:44:10,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-09 15:44:10,630 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 196 [2018-12-09 15:44:10,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:10,630 INFO L225 Difference]: With dead ends: 268 [2018-12-09 15:44:10,630 INFO L226 Difference]: Without dead ends: 268 [2018-12-09 15:44:10,631 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=158, Invalid=772, Unknown=0, NotChecked=0, Total=930 [2018-12-09 15:44:10,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268 states. [2018-12-09 15:44:10,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268 to 246. [2018-12-09 15:44:10,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2018-12-09 15:44:10,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 249 transitions. [2018-12-09 15:44:10,634 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 249 transitions. Word has length 196 [2018-12-09 15:44:10,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:10,635 INFO L480 AbstractCegarLoop]: Abstraction has 246 states and 249 transitions. [2018-12-09 15:44:10,635 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-12-09 15:44:10,635 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 249 transitions. [2018-12-09 15:44:10,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 243 [2018-12-09 15:44:10,635 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:10,635 INFO L402 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 33, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:10,636 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:10,636 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:10,636 INFO L82 PathProgramCache]: Analyzing trace with hash 1428696967, now seen corresponding path program 9 times [2018-12-09 15:44:10,636 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:10,636 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:10,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:10,636 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:10,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:10,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:10,834 INFO L134 CoverageAnalysis]: Checked inductivity of 3093 backedges. 1600 proven. 318 refuted. 0 times theorem prover too weak. 1175 trivial. 0 not checked. [2018-12-09 15:44:10,834 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:10,834 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:10,842 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:44:10,897 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-12-09 15:44:10,898 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:10,900 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:11,027 INFO L134 CoverageAnalysis]: Checked inductivity of 3093 backedges. 1513 proven. 318 refuted. 0 times theorem prover too weak. 1262 trivial. 0 not checked. [2018-12-09 15:44:11,042 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:11,042 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 16] total 32 [2018-12-09 15:44:11,043 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 15:44:11,043 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 15:44:11,043 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=819, Unknown=0, NotChecked=0, Total=992 [2018-12-09 15:44:11,043 INFO L87 Difference]: Start difference. First operand 246 states and 249 transitions. Second operand 32 states. [2018-12-09 15:44:11,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:11,486 INFO L93 Difference]: Finished difference Result 310 states and 315 transitions. [2018-12-09 15:44:11,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 15:44:11,487 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 242 [2018-12-09 15:44:11,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:11,488 INFO L225 Difference]: With dead ends: 310 [2018-12-09 15:44:11,488 INFO L226 Difference]: Without dead ends: 310 [2018-12-09 15:44:11,488 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 285 GetRequests, 233 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 721 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=653, Invalid=2209, Unknown=0, NotChecked=0, Total=2862 [2018-12-09 15:44:11,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 310 states. [2018-12-09 15:44:11,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 310 to 303. [2018-12-09 15:44:11,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2018-12-09 15:44:11,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 308 transitions. [2018-12-09 15:44:11,492 INFO L78 Accepts]: Start accepts. Automaton has 303 states and 308 transitions. Word has length 242 [2018-12-09 15:44:11,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:11,492 INFO L480 AbstractCegarLoop]: Abstraction has 303 states and 308 transitions. [2018-12-09 15:44:11,493 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 15:44:11,493 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 308 transitions. [2018-12-09 15:44:11,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 248 [2018-12-09 15:44:11,493 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:11,494 INFO L402 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 34, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:11,494 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:11,494 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:11,494 INFO L82 PathProgramCache]: Analyzing trace with hash -300291550, now seen corresponding path program 10 times [2018-12-09 15:44:11,494 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:11,494 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:11,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:11,494 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:11,495 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:11,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:11,596 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1078 proven. 109 refuted. 0 times theorem prover too weak. 2079 trivial. 0 not checked. [2018-12-09 15:44:11,596 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:11,596 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:11,602 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:44:11,657 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:44:11,658 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:11,661 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:11,771 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1047 proven. 119 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2018-12-09 15:44:11,787 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:11,787 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9] total 21 [2018-12-09 15:44:11,787 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-12-09 15:44:11,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-12-09 15:44:11,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=390, Unknown=0, NotChecked=0, Total=462 [2018-12-09 15:44:11,787 INFO L87 Difference]: Start difference. First operand 303 states and 308 transitions. Second operand 22 states. [2018-12-09 15:44:12,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:12,184 INFO L93 Difference]: Finished difference Result 429 states and 440 transitions. [2018-12-09 15:44:12,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 15:44:12,184 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 247 [2018-12-09 15:44:12,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:12,185 INFO L225 Difference]: With dead ends: 429 [2018-12-09 15:44:12,185 INFO L226 Difference]: Without dead ends: 429 [2018-12-09 15:44:12,185 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 271 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 175 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=178, Invalid=944, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 15:44:12,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states. [2018-12-09 15:44:12,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 403. [2018-12-09 15:44:12,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 403 states. [2018-12-09 15:44:12,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 413 transitions. [2018-12-09 15:44:12,190 INFO L78 Accepts]: Start accepts. Automaton has 403 states and 413 transitions. Word has length 247 [2018-12-09 15:44:12,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:12,191 INFO L480 AbstractCegarLoop]: Abstraction has 403 states and 413 transitions. [2018-12-09 15:44:12,191 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-12-09 15:44:12,191 INFO L276 IsEmpty]: Start isEmpty. Operand 403 states and 413 transitions. [2018-12-09 15:44:12,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-12-09 15:44:12,192 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:12,192 INFO L402 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 41, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:12,192 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:12,192 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:12,192 INFO L82 PathProgramCache]: Analyzing trace with hash -1077850677, now seen corresponding path program 11 times [2018-12-09 15:44:12,192 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:12,192 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:12,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:12,193 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:12,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:12,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:12,395 INFO L134 CoverageAnalysis]: Checked inductivity of 4728 backedges. 2076 proven. 584 refuted. 0 times theorem prover too weak. 2068 trivial. 0 not checked. [2018-12-09 15:44:12,395 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:12,395 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:12,401 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:44:12,511 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-12-09 15:44:12,511 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:12,515 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:12,751 INFO L134 CoverageAnalysis]: Checked inductivity of 4728 backedges. 2905 proven. 456 refuted. 0 times theorem prover too weak. 1367 trivial. 0 not checked. [2018-12-09 15:44:12,767 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:12,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 20] total 41 [2018-12-09 15:44:12,767 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-09 15:44:12,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-09 15:44:12,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=1429, Unknown=0, NotChecked=0, Total=1640 [2018-12-09 15:44:12,768 INFO L87 Difference]: Start difference. First operand 403 states and 413 transitions. Second operand 41 states. [2018-12-09 15:44:13,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:13,611 INFO L93 Difference]: Finished difference Result 320 states and 323 transitions. [2018-12-09 15:44:13,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-12-09 15:44:13,612 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 293 [2018-12-09 15:44:13,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:13,613 INFO L225 Difference]: With dead ends: 320 [2018-12-09 15:44:13,613 INFO L226 Difference]: Without dead ends: 311 [2018-12-09 15:44:13,613 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 356 GetRequests, 278 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1758 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=970, Invalid=5350, Unknown=0, NotChecked=0, Total=6320 [2018-12-09 15:44:13,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 311 states. [2018-12-09 15:44:13,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 311 to 307. [2018-12-09 15:44:13,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2018-12-09 15:44:13,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 310 transitions. [2018-12-09 15:44:13,617 INFO L78 Accepts]: Start accepts. Automaton has 307 states and 310 transitions. Word has length 293 [2018-12-09 15:44:13,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:13,617 INFO L480 AbstractCegarLoop]: Abstraction has 307 states and 310 transitions. [2018-12-09 15:44:13,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-09 15:44:13,617 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 310 transitions. [2018-12-09 15:44:13,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2018-12-09 15:44:13,618 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:13,618 INFO L402 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 42, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:13,618 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:13,618 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:13,618 INFO L82 PathProgramCache]: Analyzing trace with hash -1652634800, now seen corresponding path program 12 times [2018-12-09 15:44:13,618 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:13,618 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:13,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:13,619 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:13,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:13,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:13,838 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 2419 proven. 423 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2018-12-09 15:44:13,838 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:13,838 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:13,844 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:44:13,949 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2018-12-09 15:44:13,949 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:13,952 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:14,100 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 1527 proven. 148 refuted. 0 times theorem prover too weak. 3267 trivial. 0 not checked. [2018-12-09 15:44:14,124 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:14,124 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 14] total 35 [2018-12-09 15:44:14,124 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-09 15:44:14,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-09 15:44:14,125 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=1023, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 15:44:14,125 INFO L87 Difference]: Start difference. First operand 307 states and 310 transitions. Second operand 35 states. [2018-12-09 15:44:15,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:15,171 INFO L93 Difference]: Finished difference Result 433 states and 439 transitions. [2018-12-09 15:44:15,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-12-09 15:44:15,171 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 298 [2018-12-09 15:44:15,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:15,178 INFO L225 Difference]: With dead ends: 433 [2018-12-09 15:44:15,178 INFO L226 Difference]: Without dead ends: 433 [2018-12-09 15:44:15,180 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 374 GetRequests, 288 SyntacticMatches, 0 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2201 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1334, Invalid=6322, Unknown=0, NotChecked=0, Total=7656 [2018-12-09 15:44:15,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 433 states. [2018-12-09 15:44:15,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 433 to 372. [2018-12-09 15:44:15,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 372 states. [2018-12-09 15:44:15,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 372 states to 372 states and 377 transitions. [2018-12-09 15:44:15,186 INFO L78 Accepts]: Start accepts. Automaton has 372 states and 377 transitions. Word has length 298 [2018-12-09 15:44:15,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:15,186 INFO L480 AbstractCegarLoop]: Abstraction has 372 states and 377 transitions. [2018-12-09 15:44:15,186 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-09 15:44:15,187 INFO L276 IsEmpty]: Start isEmpty. Operand 372 states and 377 transitions. [2018-12-09 15:44:15,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 355 [2018-12-09 15:44:15,188 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:15,188 INFO L402 BasicCegarLoop]: trace histogram [52, 51, 51, 51, 51, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:15,188 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:15,189 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:15,189 INFO L82 PathProgramCache]: Analyzing trace with hash -197186291, now seen corresponding path program 13 times [2018-12-09 15:44:15,189 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:15,189 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:15,189 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:15,189 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:15,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:15,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:15,436 INFO L134 CoverageAnalysis]: Checked inductivity of 7225 backedges. 3495 proven. 648 refuted. 0 times theorem prover too weak. 3082 trivial. 0 not checked. [2018-12-09 15:44:15,436 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:15,436 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:15,442 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:15,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:15,498 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:15,644 INFO L134 CoverageAnalysis]: Checked inductivity of 7225 backedges. 3589 proven. 148 refuted. 0 times theorem prover too weak. 3488 trivial. 0 not checked. [2018-12-09 15:44:15,660 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:15,660 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 20] total 33 [2018-12-09 15:44:15,660 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-09 15:44:15,660 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-09 15:44:15,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=217, Invalid=839, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 15:44:15,661 INFO L87 Difference]: Start difference. First operand 372 states and 377 transitions. Second operand 33 states. [2018-12-09 15:44:16,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:16,123 INFO L93 Difference]: Finished difference Result 392 states and 394 transitions. [2018-12-09 15:44:16,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-09 15:44:16,124 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 354 [2018-12-09 15:44:16,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:16,125 INFO L225 Difference]: With dead ends: 392 [2018-12-09 15:44:16,125 INFO L226 Difference]: Without dead ends: 371 [2018-12-09 15:44:16,125 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 395 GetRequests, 347 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 657 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=563, Invalid=1887, Unknown=0, NotChecked=0, Total=2450 [2018-12-09 15:44:16,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 371 states. [2018-12-09 15:44:16,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 371 to 368. [2018-12-09 15:44:16,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-12-09 15:44:16,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 369 transitions. [2018-12-09 15:44:16,129 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 369 transitions. Word has length 354 [2018-12-09 15:44:16,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:16,130 INFO L480 AbstractCegarLoop]: Abstraction has 368 states and 369 transitions. [2018-12-09 15:44:16,130 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-09 15:44:16,130 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 369 transitions. [2018-12-09 15:44:16,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 365 [2018-12-09 15:44:16,131 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:16,131 INFO L402 BasicCegarLoop]: trace histogram [54, 53, 53, 53, 53, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:16,131 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:16,131 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:16,132 INFO L82 PathProgramCache]: Analyzing trace with hash -1526039033, now seen corresponding path program 14 times [2018-12-09 15:44:16,132 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:16,132 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:16,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:16,132 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:16,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:16,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:16,275 INFO L134 CoverageAnalysis]: Checked inductivity of 7760 backedges. 2189 proven. 193 refuted. 0 times theorem prover too weak. 5378 trivial. 0 not checked. [2018-12-09 15:44:16,275 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:16,275 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:16,282 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:44:16,350 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:44:16,350 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:16,354 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:16,476 INFO L134 CoverageAnalysis]: Checked inductivity of 7760 backedges. 2148 proven. 198 refuted. 0 times theorem prover too weak. 5414 trivial. 0 not checked. [2018-12-09 15:44:16,492 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:16,492 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11] total 25 [2018-12-09 15:44:16,492 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-12-09 15:44:16,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-12-09 15:44:16,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=553, Unknown=0, NotChecked=0, Total=650 [2018-12-09 15:44:16,493 INFO L87 Difference]: Start difference. First operand 368 states and 369 transitions. Second operand 26 states. [2018-12-09 15:44:17,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:17,038 INFO L93 Difference]: Finished difference Result 451 states and 455 transitions. [2018-12-09 15:44:17,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-12-09 15:44:17,039 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 364 [2018-12-09 15:44:17,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:17,040 INFO L225 Difference]: With dead ends: 451 [2018-12-09 15:44:17,040 INFO L226 Difference]: Without dead ends: 451 [2018-12-09 15:44:17,040 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 391 GetRequests, 354 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 237 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=215, Invalid=1267, Unknown=0, NotChecked=0, Total=1482 [2018-12-09 15:44:17,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states. [2018-12-09 15:44:17,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 429. [2018-12-09 15:44:17,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 429 states. [2018-12-09 15:44:17,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 429 states to 429 states and 432 transitions. [2018-12-09 15:44:17,044 INFO L78 Accepts]: Start accepts. Automaton has 429 states and 432 transitions. Word has length 364 [2018-12-09 15:44:17,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:17,044 INFO L480 AbstractCegarLoop]: Abstraction has 429 states and 432 transitions. [2018-12-09 15:44:17,044 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-12-09 15:44:17,044 INFO L276 IsEmpty]: Start isEmpty. Operand 429 states and 432 transitions. [2018-12-09 15:44:17,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 426 [2018-12-09 15:44:17,045 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:17,045 INFO L402 BasicCegarLoop]: trace histogram [64, 63, 63, 63, 63, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:17,045 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:17,046 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:17,046 INFO L82 PathProgramCache]: Analyzing trace with hash 321506027, now seen corresponding path program 15 times [2018-12-09 15:44:17,046 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:17,046 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:17,046 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:17,046 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:17,046 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:17,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:17,336 INFO L134 CoverageAnalysis]: Checked inductivity of 10890 backedges. 4798 proven. 678 refuted. 0 times theorem prover too weak. 5414 trivial. 0 not checked. [2018-12-09 15:44:17,336 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:17,336 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:17,342 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:44:17,439 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-12-09 15:44:17,440 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:17,445 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:17,690 INFO L134 CoverageAnalysis]: Checked inductivity of 10890 backedges. 4600 proven. 678 refuted. 0 times theorem prover too weak. 5612 trivial. 0 not checked. [2018-12-09 15:44:17,706 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:17,706 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 19] total 41 [2018-12-09 15:44:17,706 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-12-09 15:44:17,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-12-09 15:44:17,707 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=296, Invalid=1344, Unknown=0, NotChecked=0, Total=1640 [2018-12-09 15:44:17,707 INFO L87 Difference]: Start difference. First operand 429 states and 432 transitions. Second operand 41 states. [2018-12-09 15:44:18,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:18,361 INFO L93 Difference]: Finished difference Result 508 states and 513 transitions. [2018-12-09 15:44:18,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-12-09 15:44:18,361 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 425 [2018-12-09 15:44:18,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:18,363 INFO L225 Difference]: With dead ends: 508 [2018-12-09 15:44:18,363 INFO L226 Difference]: Without dead ends: 508 [2018-12-09 15:44:18,364 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 483 GetRequests, 413 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1393 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1184, Invalid=3928, Unknown=0, NotChecked=0, Total=5112 [2018-12-09 15:44:18,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 508 states. [2018-12-09 15:44:18,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 508 to 501. [2018-12-09 15:44:18,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 501 states. [2018-12-09 15:44:18,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 501 states to 501 states and 506 transitions. [2018-12-09 15:44:18,371 INFO L78 Accepts]: Start accepts. Automaton has 501 states and 506 transitions. Word has length 425 [2018-12-09 15:44:18,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:18,371 INFO L480 AbstractCegarLoop]: Abstraction has 501 states and 506 transitions. [2018-12-09 15:44:18,371 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-12-09 15:44:18,372 INFO L276 IsEmpty]: Start isEmpty. Operand 501 states and 506 transitions. [2018-12-09 15:44:18,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2018-12-09 15:44:18,374 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:18,374 INFO L402 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 64, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:18,374 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:18,374 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:18,374 INFO L82 PathProgramCache]: Analyzing trace with hash -867500726, now seen corresponding path program 16 times [2018-12-09 15:44:18,374 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:18,375 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:18,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:18,375 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:18,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:18,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:18,558 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2995 proven. 244 refuted. 0 times theorem prover too weak. 7977 trivial. 0 not checked. [2018-12-09 15:44:18,559 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:18,559 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:18,565 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:44:18,667 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:44:18,667 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:18,672 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:18,823 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2907 proven. 245 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-09 15:44:18,839 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:18,839 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 12] total 28 [2018-12-09 15:44:18,839 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-09 15:44:18,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-09 15:44:18,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=697, Unknown=0, NotChecked=0, Total=812 [2018-12-09 15:44:18,840 INFO L87 Difference]: Start difference. First operand 501 states and 506 transitions. Second operand 29 states. [2018-12-09 15:44:19,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:19,539 INFO L93 Difference]: Finished difference Result 657 states and 668 transitions. [2018-12-09 15:44:19,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-12-09 15:44:19,539 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 430 [2018-12-09 15:44:19,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:19,541 INFO L225 Difference]: With dead ends: 657 [2018-12-09 15:44:19,541 INFO L226 Difference]: Without dead ends: 657 [2018-12-09 15:44:19,541 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 461 GetRequests, 419 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 321 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=261, Invalid=1631, Unknown=0, NotChecked=0, Total=1892 [2018-12-09 15:44:19,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2018-12-09 15:44:19,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 631. [2018-12-09 15:44:19,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 631 states. [2018-12-09 15:44:19,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 631 states to 631 states and 641 transitions. [2018-12-09 15:44:19,547 INFO L78 Accepts]: Start accepts. Automaton has 631 states and 641 transitions. Word has length 430 [2018-12-09 15:44:19,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:19,547 INFO L480 AbstractCegarLoop]: Abstraction has 631 states and 641 transitions. [2018-12-09 15:44:19,547 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-09 15:44:19,547 INFO L276 IsEmpty]: Start isEmpty. Operand 631 states and 641 transitions. [2018-12-09 15:44:19,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 492 [2018-12-09 15:44:19,549 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:19,549 INFO L402 BasicCegarLoop]: trace histogram [75, 74, 74, 74, 74, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:19,549 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:19,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:19,549 INFO L82 PathProgramCache]: Analyzing trace with hash -666277688, now seen corresponding path program 17 times [2018-12-09 15:44:19,549 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:19,549 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:19,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:19,550 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:19,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:19,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:19,896 INFO L134 CoverageAnalysis]: Checked inductivity of 14928 backedges. 5709 proven. 1205 refuted. 0 times theorem prover too weak. 8014 trivial. 0 not checked. [2018-12-09 15:44:19,896 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:19,896 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:19,902 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:44:20,109 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2018-12-09 15:44:20,109 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:20,114 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:20,530 INFO L134 CoverageAnalysis]: Checked inductivity of 14928 backedges. 9196 proven. 987 refuted. 0 times theorem prover too weak. 4745 trivial. 0 not checked. [2018-12-09 15:44:20,546 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:20,546 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 26] total 53 [2018-12-09 15:44:20,547 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-12-09 15:44:20,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-12-09 15:44:20,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=366, Invalid=2390, Unknown=0, NotChecked=0, Total=2756 [2018-12-09 15:44:20,547 INFO L87 Difference]: Start difference. First operand 631 states and 641 transitions. Second operand 53 states. [2018-12-09 15:44:21,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:21,919 INFO L93 Difference]: Finished difference Result 518 states and 521 transitions. [2018-12-09 15:44:21,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-12-09 15:44:21,920 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 491 [2018-12-09 15:44:21,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:21,921 INFO L225 Difference]: With dead ends: 518 [2018-12-09 15:44:21,921 INFO L226 Difference]: Without dead ends: 509 [2018-12-09 15:44:21,923 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 570 GetRequests, 470 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2895 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1619, Invalid=8683, Unknown=0, NotChecked=0, Total=10302 [2018-12-09 15:44:21,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 509 states. [2018-12-09 15:44:21,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 509 to 505. [2018-12-09 15:44:21,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 505 states. [2018-12-09 15:44:21,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 505 states to 505 states and 508 transitions. [2018-12-09 15:44:21,928 INFO L78 Accepts]: Start accepts. Automaton has 505 states and 508 transitions. Word has length 491 [2018-12-09 15:44:21,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:21,928 INFO L480 AbstractCegarLoop]: Abstraction has 505 states and 508 transitions. [2018-12-09 15:44:21,928 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-12-09 15:44:21,929 INFO L276 IsEmpty]: Start isEmpty. Operand 505 states and 508 transitions. [2018-12-09 15:44:21,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2018-12-09 15:44:21,931 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:21,931 INFO L402 BasicCegarLoop]: trace histogram [76, 75, 75, 75, 75, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:21,932 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:21,932 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:21,932 INFO L82 PathProgramCache]: Analyzing trace with hash -1675425945, now seen corresponding path program 18 times [2018-12-09 15:44:21,932 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:21,932 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:21,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:21,933 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:21,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:21,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:22,246 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6418 proven. 828 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2018-12-09 15:44:22,247 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:22,247 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:22,252 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:44:22,542 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-12-09 15:44:22,542 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:22,547 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:22,791 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 3819 proven. 301 refuted. 0 times theorem prover too weak. 11190 trivial. 0 not checked. [2018-12-09 15:44:22,807 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:22,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 17] total 44 [2018-12-09 15:44:22,807 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-12-09 15:44:22,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-12-09 15:44:22,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=269, Invalid=1623, Unknown=0, NotChecked=0, Total=1892 [2018-12-09 15:44:22,808 INFO L87 Difference]: Start difference. First operand 505 states and 508 transitions. Second operand 44 states. [2018-12-09 15:44:24,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:24,209 INFO L93 Difference]: Finished difference Result 661 states and 667 transitions. [2018-12-09 15:44:24,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-12-09 15:44:24,209 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 496 [2018-12-09 15:44:24,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:24,211 INFO L225 Difference]: With dead ends: 661 [2018-12-09 15:44:24,211 INFO L226 Difference]: Without dead ends: 661 [2018-12-09 15:44:24,211 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 599 GetRequests, 483 SyntacticMatches, 0 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4274 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2222, Invalid=11584, Unknown=0, NotChecked=0, Total=13806 [2018-12-09 15:44:24,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 661 states. [2018-12-09 15:44:24,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 661 to 585. [2018-12-09 15:44:24,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 585 states. [2018-12-09 15:44:24,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 585 states to 585 states and 590 transitions. [2018-12-09 15:44:24,216 INFO L78 Accepts]: Start accepts. Automaton has 585 states and 590 transitions. Word has length 496 [2018-12-09 15:44:24,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:24,216 INFO L480 AbstractCegarLoop]: Abstraction has 585 states and 590 transitions. [2018-12-09 15:44:24,216 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-12-09 15:44:24,216 INFO L276 IsEmpty]: Start isEmpty. Operand 585 states and 590 transitions. [2018-12-09 15:44:24,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 568 [2018-12-09 15:44:24,218 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:24,218 INFO L402 BasicCegarLoop]: trace histogram [88, 87, 87, 87, 87, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:24,218 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:24,218 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:24,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1497007777, now seen corresponding path program 19 times [2018-12-09 15:44:24,218 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:24,218 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:24,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:24,219 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:24,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:24,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:24,560 INFO L134 CoverageAnalysis]: Checked inductivity of 20485 backedges. 8490 proven. 1167 refuted. 0 times theorem prover too weak. 10828 trivial. 0 not checked. [2018-12-09 15:44:24,560 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:24,560 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:24,566 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:24,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:24,651 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:24,934 INFO L134 CoverageAnalysis]: Checked inductivity of 20485 backedges. 8617 proven. 286 refuted. 0 times theorem prover too weak. 11582 trivial. 0 not checked. [2018-12-09 15:44:24,949 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:24,949 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 26] total 42 [2018-12-09 15:44:24,949 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-12-09 15:44:24,950 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-12-09 15:44:24,950 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=1364, Unknown=0, NotChecked=0, Total=1722 [2018-12-09 15:44:24,950 INFO L87 Difference]: Start difference. First operand 585 states and 590 transitions. Second operand 42 states. [2018-12-09 15:44:25,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:25,389 INFO L93 Difference]: Finished difference Result 605 states and 607 transitions. [2018-12-09 15:44:25,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-12-09 15:44:25,389 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 567 [2018-12-09 15:44:25,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:25,390 INFO L225 Difference]: With dead ends: 605 [2018-12-09 15:44:25,390 INFO L226 Difference]: Without dead ends: 584 [2018-12-09 15:44:25,390 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 620 GetRequests, 557 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1218 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=947, Invalid=3213, Unknown=0, NotChecked=0, Total=4160 [2018-12-09 15:44:25,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 584 states. [2018-12-09 15:44:25,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 584 to 581. [2018-12-09 15:44:25,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 581 states. [2018-12-09 15:44:25,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 582 transitions. [2018-12-09 15:44:25,398 INFO L78 Accepts]: Start accepts. Automaton has 581 states and 582 transitions. Word has length 567 [2018-12-09 15:44:25,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:25,399 INFO L480 AbstractCegarLoop]: Abstraction has 581 states and 582 transitions. [2018-12-09 15:44:25,399 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-12-09 15:44:25,399 INFO L276 IsEmpty]: Start isEmpty. Operand 581 states and 582 transitions. [2018-12-09 15:44:25,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 578 [2018-12-09 15:44:25,402 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:25,402 INFO L402 BasicCegarLoop]: trace histogram [90, 89, 89, 89, 89, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:25,403 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:25,403 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:25,403 INFO L82 PathProgramCache]: Analyzing trace with hash 35953893, now seen corresponding path program 20 times [2018-12-09 15:44:25,403 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:25,403 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:25,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:25,404 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:25,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:25,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:25,715 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 5114 proven. 364 refuted. 0 times theorem prover too weak. 15908 trivial. 0 not checked. [2018-12-09 15:44:25,715 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:25,715 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:25,721 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:44:25,815 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:44:25,815 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:25,820 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:26,049 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 4917 proven. 354 refuted. 0 times theorem prover too weak. 16115 trivial. 0 not checked. [2018-12-09 15:44:26,064 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:26,064 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 14] total 34 [2018-12-09 15:44:26,064 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-12-09 15:44:26,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-12-09 15:44:26,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=157, Invalid=1033, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 15:44:26,065 INFO L87 Difference]: Start difference. First operand 581 states and 582 transitions. Second operand 35 states. [2018-12-09 15:44:26,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:26,951 INFO L93 Difference]: Finished difference Result 679 states and 683 transitions. [2018-12-09 15:44:26,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-12-09 15:44:26,951 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 577 [2018-12-09 15:44:26,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:26,952 INFO L225 Difference]: With dead ends: 679 [2018-12-09 15:44:26,952 INFO L226 Difference]: Without dead ends: 679 [2018-12-09 15:44:26,953 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 613 GetRequests, 564 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 471 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=335, Invalid=2215, Unknown=0, NotChecked=0, Total=2550 [2018-12-09 15:44:26,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 679 states. [2018-12-09 15:44:26,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 679 to 657. [2018-12-09 15:44:26,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 657 states. [2018-12-09 15:44:26,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 657 states and 660 transitions. [2018-12-09 15:44:26,957 INFO L78 Accepts]: Start accepts. Automaton has 657 states and 660 transitions. Word has length 577 [2018-12-09 15:44:26,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:26,957 INFO L480 AbstractCegarLoop]: Abstraction has 657 states and 660 transitions. [2018-12-09 15:44:26,957 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-12-09 15:44:26,957 INFO L276 IsEmpty]: Start isEmpty. Operand 657 states and 660 transitions. [2018-12-09 15:44:26,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 654 [2018-12-09 15:44:26,960 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:26,960 INFO L402 BasicCegarLoop]: trace histogram [103, 102, 102, 102, 102, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:26,960 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:26,960 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:26,960 INFO L82 PathProgramCache]: Analyzing trace with hash -1741773022, now seen corresponding path program 21 times [2018-12-09 15:44:26,960 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:26,960 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:26,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:26,961 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:26,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:26,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:27,418 INFO L134 CoverageAnalysis]: Checked inductivity of 27957 backedges. 10669 proven. 1173 refuted. 0 times theorem prover too weak. 16115 trivial. 0 not checked. [2018-12-09 15:44:27,418 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:27,418 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:27,424 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:44:27,543 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-12-09 15:44:27,543 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:27,547 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:27,883 INFO L134 CoverageAnalysis]: Checked inductivity of 27957 backedges. 10315 proven. 1173 refuted. 0 times theorem prover too weak. 16469 trivial. 0 not checked. [2018-12-09 15:44:27,898 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:27,898 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 22] total 50 [2018-12-09 15:44:27,899 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-12-09 15:44:27,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-12-09 15:44:27,899 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=455, Invalid=1995, Unknown=0, NotChecked=0, Total=2450 [2018-12-09 15:44:27,899 INFO L87 Difference]: Start difference. First operand 657 states and 660 transitions. Second operand 50 states. [2018-12-09 15:44:28,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:28,872 INFO L93 Difference]: Finished difference Result 751 states and 756 transitions. [2018-12-09 15:44:28,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-09 15:44:28,873 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 653 [2018-12-09 15:44:28,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:28,874 INFO L225 Difference]: With dead ends: 751 [2018-12-09 15:44:28,874 INFO L226 Difference]: Without dead ends: 751 [2018-12-09 15:44:28,874 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 726 GetRequests, 638 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2281 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1877, Invalid=6133, Unknown=0, NotChecked=0, Total=8010 [2018-12-09 15:44:28,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 751 states. [2018-12-09 15:44:28,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 751 to 744. [2018-12-09 15:44:28,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 744 states. [2018-12-09 15:44:28,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 744 states to 744 states and 749 transitions. [2018-12-09 15:44:28,879 INFO L78 Accepts]: Start accepts. Automaton has 744 states and 749 transitions. Word has length 653 [2018-12-09 15:44:28,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:28,879 INFO L480 AbstractCegarLoop]: Abstraction has 744 states and 749 transitions. [2018-12-09 15:44:28,879 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-12-09 15:44:28,879 INFO L276 IsEmpty]: Start isEmpty. Operand 744 states and 749 transitions. [2018-12-09 15:44:28,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 659 [2018-12-09 15:44:28,882 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:28,882 INFO L402 BasicCegarLoop]: trace histogram [104, 103, 103, 103, 103, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:28,882 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:28,882 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:28,882 INFO L82 PathProgramCache]: Analyzing trace with hash 1104503271, now seen corresponding path program 22 times [2018-12-09 15:44:28,882 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:28,882 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:28,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:28,883 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:28,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:28,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:29,177 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6259 proven. 433 refuted. 0 times theorem prover too weak. 21789 trivial. 0 not checked. [2018-12-09 15:44:29,177 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:29,177 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:29,184 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:44:29,338 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:44:29,339 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:29,345 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:29,600 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6198 proven. 416 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2018-12-09 15:44:29,616 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:29,617 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 15] total 33 [2018-12-09 15:44:29,617 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-12-09 15:44:29,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-12-09 15:44:29,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=159, Invalid=963, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 15:44:29,617 INFO L87 Difference]: Start difference. First operand 744 states and 749 transitions. Second operand 34 states. [2018-12-09 15:44:30,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:30,509 INFO L93 Difference]: Finished difference Result 930 states and 941 transitions. [2018-12-09 15:44:30,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-09 15:44:30,509 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 658 [2018-12-09 15:44:30,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:30,511 INFO L225 Difference]: With dead ends: 930 [2018-12-09 15:44:30,511 INFO L226 Difference]: Without dead ends: 930 [2018-12-09 15:44:30,511 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 694 GetRequests, 644 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 436 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=325, Invalid=2327, Unknown=0, NotChecked=0, Total=2652 [2018-12-09 15:44:30,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 930 states. [2018-12-09 15:44:30,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 930 to 904. [2018-12-09 15:44:30,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 904 states. [2018-12-09 15:44:30,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 904 states to 904 states and 914 transitions. [2018-12-09 15:44:30,517 INFO L78 Accepts]: Start accepts. Automaton has 904 states and 914 transitions. Word has length 658 [2018-12-09 15:44:30,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:30,517 INFO L480 AbstractCegarLoop]: Abstraction has 904 states and 914 transitions. [2018-12-09 15:44:30,517 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-12-09 15:44:30,517 INFO L276 IsEmpty]: Start isEmpty. Operand 904 states and 914 transitions. [2018-12-09 15:44:30,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 735 [2018-12-09 15:44:30,520 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:30,520 INFO L402 BasicCegarLoop]: trace histogram [117, 116, 116, 116, 116, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:30,520 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:30,520 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:30,520 INFO L82 PathProgramCache]: Analyzing trace with hash -402943376, now seen corresponding path program 23 times [2018-12-09 15:44:30,520 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:30,521 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:30,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:30,521 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:30,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:30,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:31,045 INFO L134 CoverageAnalysis]: Checked inductivity of 36000 backedges. 12150 proven. 2051 refuted. 0 times theorem prover too weak. 21799 trivial. 0 not checked. [2018-12-09 15:44:31,045 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:31,045 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:31,051 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:44:31,487 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-12-09 15:44:31,487 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:31,495 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:32,115 INFO L134 CoverageAnalysis]: Checked inductivity of 36000 backedges. 17896 proven. 1767 refuted. 0 times theorem prover too weak. 16337 trivial. 0 not checked. [2018-12-09 15:44:32,131 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:32,131 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 32] total 65 [2018-12-09 15:44:32,132 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-12-09 15:44:32,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-12-09 15:44:32,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=556, Invalid=3604, Unknown=0, NotChecked=0, Total=4160 [2018-12-09 15:44:32,133 INFO L87 Difference]: Start difference. First operand 904 states and 914 transitions. Second operand 65 states. [2018-12-09 15:44:33,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:33,936 INFO L93 Difference]: Finished difference Result 761 states and 764 transitions. [2018-12-09 15:44:33,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-09 15:44:33,936 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 734 [2018-12-09 15:44:33,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:33,937 INFO L225 Difference]: With dead ends: 761 [2018-12-09 15:44:33,937 INFO L226 Difference]: Without dead ends: 752 [2018-12-09 15:44:33,938 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 839 GetRequests, 707 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5595 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2644, Invalid=15178, Unknown=0, NotChecked=0, Total=17822 [2018-12-09 15:44:33,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 752 states. [2018-12-09 15:44:33,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 752 to 748. [2018-12-09 15:44:33,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 748 states. [2018-12-09 15:44:33,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 748 states and 751 transitions. [2018-12-09 15:44:33,942 INFO L78 Accepts]: Start accepts. Automaton has 748 states and 751 transitions. Word has length 734 [2018-12-09 15:44:33,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:33,943 INFO L480 AbstractCegarLoop]: Abstraction has 748 states and 751 transitions. [2018-12-09 15:44:33,943 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-12-09 15:44:33,943 INFO L276 IsEmpty]: Start isEmpty. Operand 748 states and 751 transitions. [2018-12-09 15:44:33,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 740 [2018-12-09 15:44:33,945 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:33,946 INFO L402 BasicCegarLoop]: trace histogram [118, 117, 117, 117, 117, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:33,946 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:33,946 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:33,946 INFO L82 PathProgramCache]: Analyzing trace with hash 79086155, now seen corresponding path program 24 times [2018-12-09 15:44:33,946 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:33,946 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:33,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:33,946 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:33,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:33,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:34,461 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 13360 proven. 1368 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2018-12-09 15:44:34,461 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:34,461 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:34,467 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:44:35,167 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-12-09 15:44:35,167 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:35,174 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:35,538 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 7677 proven. 508 refuted. 0 times theorem prover too weak. 28410 trivial. 0 not checked. [2018-12-09 15:44:35,554 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:35,555 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 20] total 53 [2018-12-09 15:44:35,555 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-12-09 15:44:35,556 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-12-09 15:44:35,556 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=398, Invalid=2358, Unknown=0, NotChecked=0, Total=2756 [2018-12-09 15:44:35,556 INFO L87 Difference]: Start difference. First operand 748 states and 751 transitions. Second operand 53 states. [2018-12-09 15:44:38,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:38,177 INFO L93 Difference]: Finished difference Result 934 states and 940 transitions. [2018-12-09 15:44:38,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2018-12-09 15:44:38,177 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 739 [2018-12-09 15:44:38,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:38,179 INFO L225 Difference]: With dead ends: 934 [2018-12-09 15:44:38,179 INFO L226 Difference]: Without dead ends: 934 [2018-12-09 15:44:38,180 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 869 GetRequests, 723 SyntacticMatches, 0 SemanticMatches, 146 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7022 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=3308, Invalid=18448, Unknown=0, NotChecked=0, Total=21756 [2018-12-09 15:44:38,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 934 states. [2018-12-09 15:44:38,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 934 to 843. [2018-12-09 15:44:38,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 843 states. [2018-12-09 15:44:38,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 848 transitions. [2018-12-09 15:44:38,186 INFO L78 Accepts]: Start accepts. Automaton has 843 states and 848 transitions. Word has length 739 [2018-12-09 15:44:38,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:38,187 INFO L480 AbstractCegarLoop]: Abstraction has 843 states and 848 transitions. [2018-12-09 15:44:38,187 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-12-09 15:44:38,187 INFO L276 IsEmpty]: Start isEmpty. Operand 843 states and 848 transitions. [2018-12-09 15:44:38,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 826 [2018-12-09 15:44:38,197 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:38,197 INFO L402 BasicCegarLoop]: trace histogram [133, 132, 132, 132, 132, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:38,197 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:38,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:38,198 INFO L82 PathProgramCache]: Analyzing trace with hash -1645932632, now seen corresponding path program 25 times [2018-12-09 15:44:38,198 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:38,198 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:38,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:38,198 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:38,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:38,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:38,733 INFO L134 CoverageAnalysis]: Checked inductivity of 46399 backedges. 16752 proven. 1830 refuted. 0 times theorem prover too weak. 27817 trivial. 0 not checked. [2018-12-09 15:44:38,734 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:38,734 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:38,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:38,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:38,861 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:39,250 INFO L134 CoverageAnalysis]: Checked inductivity of 46399 backedges. 16912 proven. 469 refuted. 0 times theorem prover too weak. 29018 trivial. 0 not checked. [2018-12-09 15:44:39,265 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:39,265 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 32] total 51 [2018-12-09 15:44:39,266 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-12-09 15:44:39,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-12-09 15:44:39,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=535, Invalid=2015, Unknown=0, NotChecked=0, Total=2550 [2018-12-09 15:44:39,266 INFO L87 Difference]: Start difference. First operand 843 states and 848 transitions. Second operand 51 states. [2018-12-09 15:44:40,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:40,217 INFO L93 Difference]: Finished difference Result 863 states and 865 transitions. [2018-12-09 15:44:40,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-12-09 15:44:40,217 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 825 [2018-12-09 15:44:40,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:40,220 INFO L225 Difference]: With dead ends: 863 [2018-12-09 15:44:40,220 INFO L226 Difference]: Without dead ends: 842 [2018-12-09 15:44:40,221 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 890 GetRequests, 812 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1950 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1430, Invalid=4890, Unknown=0, NotChecked=0, Total=6320 [2018-12-09 15:44:40,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 842 states. [2018-12-09 15:44:40,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 842 to 839. [2018-12-09 15:44:40,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 839 states. [2018-12-09 15:44:40,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 839 states to 839 states and 840 transitions. [2018-12-09 15:44:40,227 INFO L78 Accepts]: Start accepts. Automaton has 839 states and 840 transitions. Word has length 825 [2018-12-09 15:44:40,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:40,228 INFO L480 AbstractCegarLoop]: Abstraction has 839 states and 840 transitions. [2018-12-09 15:44:40,228 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-12-09 15:44:40,228 INFO L276 IsEmpty]: Start isEmpty. Operand 839 states and 840 transitions. [2018-12-09 15:44:40,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 836 [2018-12-09 15:44:40,233 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:40,233 INFO L402 BasicCegarLoop]: trace histogram [135, 134, 134, 134, 134, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:40,233 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:40,234 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:40,234 INFO L82 PathProgramCache]: Analyzing trace with hash 1746428258, now seen corresponding path program 26 times [2018-12-09 15:44:40,234 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:40,234 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:40,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:40,235 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:40,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:40,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:40,585 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9458 proven. 589 refuted. 0 times theorem prover too weak. 37709 trivial. 0 not checked. [2018-12-09 15:44:40,585 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:40,585 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:40,591 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:44:40,714 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:44:40,714 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:40,721 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:41,050 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9387 proven. 555 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2018-12-09 15:44:41,065 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:41,065 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 17] total 37 [2018-12-09 15:44:41,065 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-12-09 15:44:41,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-12-09 15:44:41,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=196, Invalid=1210, Unknown=0, NotChecked=0, Total=1406 [2018-12-09 15:44:41,066 INFO L87 Difference]: Start difference. First operand 839 states and 840 transitions. Second operand 38 states. [2018-12-09 15:44:42,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:42,291 INFO L93 Difference]: Finished difference Result 952 states and 956 transitions. [2018-12-09 15:44:42,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-12-09 15:44:42,291 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 835 [2018-12-09 15:44:42,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:42,293 INFO L225 Difference]: With dead ends: 952 [2018-12-09 15:44:42,293 INFO L226 Difference]: Without dead ends: 952 [2018-12-09 15:44:42,293 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 874 GetRequests, 819 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 528 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=374, Invalid=2818, Unknown=0, NotChecked=0, Total=3192 [2018-12-09 15:44:42,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states. [2018-12-09 15:44:42,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 930. [2018-12-09 15:44:42,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 930 states. [2018-12-09 15:44:42,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 930 states to 930 states and 933 transitions. [2018-12-09 15:44:42,298 INFO L78 Accepts]: Start accepts. Automaton has 930 states and 933 transitions. Word has length 835 [2018-12-09 15:44:42,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:42,299 INFO L480 AbstractCegarLoop]: Abstraction has 930 states and 933 transitions. [2018-12-09 15:44:42,299 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-12-09 15:44:42,299 INFO L276 IsEmpty]: Start isEmpty. Operand 930 states and 933 transitions. [2018-12-09 15:44:42,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 927 [2018-12-09 15:44:42,303 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:42,304 INFO L402 BasicCegarLoop]: trace histogram [151, 150, 150, 150, 150, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:42,304 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:42,304 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:42,304 INFO L82 PathProgramCache]: Analyzing trace with hash -848043632, now seen corresponding path program 27 times [2018-12-09 15:44:42,304 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:42,304 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:42,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:42,305 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:42,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:42,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:42,951 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 20023 proven. 1803 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2018-12-09 15:44:42,951 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:42,951 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:42,958 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:44:43,148 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-12-09 15:44:43,149 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:43,154 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:43,673 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 19468 proven. 1803 refuted. 0 times theorem prover too weak. 38369 trivial. 0 not checked. [2018-12-09 15:44:43,688 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:43,688 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 25] total 59 [2018-12-09 15:44:43,688 INFO L459 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-12-09 15:44:43,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-12-09 15:44:43,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=650, Invalid=2772, Unknown=0, NotChecked=0, Total=3422 [2018-12-09 15:44:43,689 INFO L87 Difference]: Start difference. First operand 930 states and 933 transitions. Second operand 59 states. [2018-12-09 15:44:44,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:44,816 INFO L93 Difference]: Finished difference Result 1039 states and 1044 transitions. [2018-12-09 15:44:44,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-12-09 15:44:44,816 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 926 [2018-12-09 15:44:44,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:44,818 INFO L225 Difference]: With dead ends: 1039 [2018-12-09 15:44:44,818 INFO L226 Difference]: Without dead ends: 1039 [2018-12-09 15:44:44,818 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1014 GetRequests, 908 SyntacticMatches, 0 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3385 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2732, Invalid=8824, Unknown=0, NotChecked=0, Total=11556 [2018-12-09 15:44:44,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1039 states. [2018-12-09 15:44:44,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1039 to 1032. [2018-12-09 15:44:44,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1032 states. [2018-12-09 15:44:44,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1032 states to 1032 states and 1037 transitions. [2018-12-09 15:44:44,824 INFO L78 Accepts]: Start accepts. Automaton has 1032 states and 1037 transitions. Word has length 926 [2018-12-09 15:44:44,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:44,824 INFO L480 AbstractCegarLoop]: Abstraction has 1032 states and 1037 transitions. [2018-12-09 15:44:44,824 INFO L481 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-12-09 15:44:44,824 INFO L276 IsEmpty]: Start isEmpty. Operand 1032 states and 1037 transitions. [2018-12-09 15:44:44,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 932 [2018-12-09 15:44:44,828 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:44,828 INFO L402 BasicCegarLoop]: trace histogram [152, 151, 151, 151, 151, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:44,828 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:44,828 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:44,828 INFO L82 PathProgramCache]: Analyzing trace with hash 401870661, now seen corresponding path program 28 times [2018-12-09 15:44:44,828 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:44,828 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:44,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:44,829 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:44,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:44,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:45,458 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11956 proven. 676 refuted. 0 times theorem prover too weak. 47775 trivial. 0 not checked. [2018-12-09 15:44:45,459 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:45,459 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:45,464 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:44:45,815 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:44:45,816 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:45,825 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:46,265 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11325 proven. 632 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-09 15:44:46,282 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:46,282 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 18] total 53 [2018-12-09 15:44:46,283 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-12-09 15:44:46,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-12-09 15:44:46,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=2484, Unknown=0, NotChecked=0, Total=2862 [2018-12-09 15:44:46,283 INFO L87 Difference]: Start difference. First operand 1032 states and 1037 transitions. Second operand 54 states. [2018-12-09 15:44:47,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:47,762 INFO L93 Difference]: Finished difference Result 1244 states and 1255 transitions. [2018-12-09 15:44:47,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-12-09 15:44:47,763 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 931 [2018-12-09 15:44:47,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:47,764 INFO L225 Difference]: With dead ends: 1244 [2018-12-09 15:44:47,764 INFO L226 Difference]: Without dead ends: 1244 [2018-12-09 15:44:47,765 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 987 GetRequests, 914 SyntacticMatches, 1 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1171 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=681, Invalid=4721, Unknown=0, NotChecked=0, Total=5402 [2018-12-09 15:44:47,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1244 states. [2018-12-09 15:44:47,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1244 to 1222. [2018-12-09 15:44:47,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1222 states. [2018-12-09 15:44:47,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1232 transitions. [2018-12-09 15:44:47,772 INFO L78 Accepts]: Start accepts. Automaton has 1222 states and 1232 transitions. Word has length 931 [2018-12-09 15:44:47,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:47,772 INFO L480 AbstractCegarLoop]: Abstraction has 1222 states and 1232 transitions. [2018-12-09 15:44:47,772 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-12-09 15:44:47,772 INFO L276 IsEmpty]: Start isEmpty. Operand 1222 states and 1232 transitions. [2018-12-09 15:44:47,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1023 [2018-12-09 15:44:47,776 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:47,777 INFO L402 BasicCegarLoop]: trace histogram [168, 167, 167, 167, 167, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:47,777 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:47,777 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:47,777 INFO L82 PathProgramCache]: Analyzing trace with hash -1689975411, now seen corresponding path program 29 times [2018-12-09 15:44:47,777 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:47,777 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:47,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:47,777 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:47,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:47,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:48,513 INFO L134 CoverageAnalysis]: Checked inductivity of 73695 backedges. 22209 proven. 3122 refuted. 0 times theorem prover too weak. 48364 trivial. 0 not checked. [2018-12-09 15:44:48,513 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:48,513 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:48,519 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:44:49,409 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-12-09 15:44:49,409 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:49,420 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:50,414 INFO L134 CoverageAnalysis]: Checked inductivity of 73695 backedges. 37420 proven. 3556 refuted. 0 times theorem prover too weak. 32719 trivial. 0 not checked. [2018-12-09 15:44:50,432 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:50,432 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 38] total 77 [2018-12-09 15:44:50,432 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-12-09 15:44:50,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-12-09 15:44:50,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=796, Invalid=5056, Unknown=0, NotChecked=0, Total=5852 [2018-12-09 15:44:50,433 INFO L87 Difference]: Start difference. First operand 1222 states and 1232 transitions. Second operand 77 states. [2018-12-09 15:44:52,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:52,362 INFO L93 Difference]: Finished difference Result 1049 states and 1052 transitions. [2018-12-09 15:44:52,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2018-12-09 15:44:52,362 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1022 [2018-12-09 15:44:52,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:52,364 INFO L225 Difference]: With dead ends: 1049 [2018-12-09 15:44:52,364 INFO L226 Difference]: Without dead ends: 1040 [2018-12-09 15:44:52,365 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1138 GetRequests, 989 SyntacticMatches, 0 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6784 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3510, Invalid=19140, Unknown=0, NotChecked=0, Total=22650 [2018-12-09 15:44:52,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1040 states. [2018-12-09 15:44:52,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1040 to 1036. [2018-12-09 15:44:52,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1036 states. [2018-12-09 15:44:52,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1036 states to 1036 states and 1039 transitions. [2018-12-09 15:44:52,370 INFO L78 Accepts]: Start accepts. Automaton has 1036 states and 1039 transitions. Word has length 1022 [2018-12-09 15:44:52,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:52,371 INFO L480 AbstractCegarLoop]: Abstraction has 1036 states and 1039 transitions. [2018-12-09 15:44:52,371 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-12-09 15:44:52,371 INFO L276 IsEmpty]: Start isEmpty. Operand 1036 states and 1039 transitions. [2018-12-09 15:44:52,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1028 [2018-12-09 15:44:52,376 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:52,376 INFO L402 BasicCegarLoop]: trace histogram [169, 168, 168, 168, 168, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:52,376 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:52,376 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:52,376 INFO L82 PathProgramCache]: Analyzing trace with hash -697239742, now seen corresponding path program 30 times [2018-12-09 15:44:52,376 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:52,376 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:52,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:52,377 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:52,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:52,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:53,127 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 24055 proven. 2043 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2018-12-09 15:44:53,127 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:53,127 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:53,133 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:44:54,575 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 35 check-sat command(s) [2018-12-09 15:44:54,575 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:54,585 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:55,193 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 23423 proven. 2043 refuted. 0 times theorem prover too weak. 49082 trivial. 0 not checked. [2018-12-09 15:44:55,210 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:55,210 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 26] total 62 [2018-12-09 15:44:55,211 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-09 15:44:55,211 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-09 15:44:55,211 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=723, Invalid=3059, Unknown=0, NotChecked=0, Total=3782 [2018-12-09 15:44:55,211 INFO L87 Difference]: Start difference. First operand 1036 states and 1039 transitions. Second operand 62 states. [2018-12-09 15:44:56,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:56,410 INFO L93 Difference]: Finished difference Result 1145 states and 1150 transitions. [2018-12-09 15:44:56,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-12-09 15:44:56,411 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1027 [2018-12-09 15:44:56,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:56,413 INFO L225 Difference]: With dead ends: 1145 [2018-12-09 15:44:56,413 INFO L226 Difference]: Without dead ends: 1145 [2018-12-09 15:44:56,413 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1120 GetRequests, 1008 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3801 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=3053, Invalid=9829, Unknown=0, NotChecked=0, Total=12882 [2018-12-09 15:44:56,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1145 states. [2018-12-09 15:44:56,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1145 to 1138. [2018-12-09 15:44:56,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1138 states. [2018-12-09 15:44:56,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1138 states to 1138 states and 1143 transitions. [2018-12-09 15:44:56,419 INFO L78 Accepts]: Start accepts. Automaton has 1138 states and 1143 transitions. Word has length 1027 [2018-12-09 15:44:56,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:56,420 INFO L480 AbstractCegarLoop]: Abstraction has 1138 states and 1143 transitions. [2018-12-09 15:44:56,420 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-09 15:44:56,420 INFO L276 IsEmpty]: Start isEmpty. Operand 1138 states and 1143 transitions. [2018-12-09 15:44:56,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1033 [2018-12-09 15:44:56,425 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:56,425 INFO L402 BasicCegarLoop]: trace histogram [170, 169, 169, 169, 169, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:56,425 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:56,425 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:56,425 INFO L82 PathProgramCache]: Analyzing trace with hash 548287687, now seen corresponding path program 31 times [2018-12-09 15:44:56,425 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:56,425 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:56,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:56,426 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:44:56,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:56,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:56,921 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13593 proven. 769 refuted. 0 times theorem prover too weak. 61044 trivial. 0 not checked. [2018-12-09 15:44:56,922 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:56,922 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:56,927 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:57,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:57,083 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:44:57,531 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13512 proven. 714 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2018-12-09 15:44:57,546 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:44:57,546 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 19] total 41 [2018-12-09 15:44:57,547 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-12-09 15:44:57,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-12-09 15:44:57,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=237, Invalid=1485, Unknown=0, NotChecked=0, Total=1722 [2018-12-09 15:44:57,547 INFO L87 Difference]: Start difference. First operand 1138 states and 1143 transitions. Second operand 42 states. [2018-12-09 15:44:58,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:44:58,865 INFO L93 Difference]: Finished difference Result 1364 states and 1375 transitions. [2018-12-09 15:44:58,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-12-09 15:44:58,865 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 1032 [2018-12-09 15:44:58,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:44:58,867 INFO L225 Difference]: With dead ends: 1364 [2018-12-09 15:44:58,868 INFO L226 Difference]: Without dead ends: 1364 [2018-12-09 15:44:58,868 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1076 GetRequests, 1014 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 670 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=443, Invalid=3589, Unknown=0, NotChecked=0, Total=4032 [2018-12-09 15:44:58,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1364 states. [2018-12-09 15:44:58,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1364 to 1338. [2018-12-09 15:44:58,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1338 states. [2018-12-09 15:44:58,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1338 states to 1338 states and 1348 transitions. [2018-12-09 15:44:58,875 INFO L78 Accepts]: Start accepts. Automaton has 1338 states and 1348 transitions. Word has length 1032 [2018-12-09 15:44:58,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:44:58,875 INFO L480 AbstractCegarLoop]: Abstraction has 1338 states and 1348 transitions. [2018-12-09 15:44:58,875 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-12-09 15:44:58,875 INFO L276 IsEmpty]: Start isEmpty. Operand 1338 states and 1348 transitions. [2018-12-09 15:44:58,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1129 [2018-12-09 15:44:58,883 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:44:58,883 INFO L402 BasicCegarLoop]: trace histogram [187, 186, 186, 186, 186, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:44:58,883 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:44:58,883 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:44:58,883 INFO L82 PathProgramCache]: Analyzing trace with hash 1455325456, now seen corresponding path program 32 times [2018-12-09 15:44:58,883 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:44:58,884 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:44:58,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:58,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:44:58,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:44:58,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:44:59,737 INFO L134 CoverageAnalysis]: Checked inductivity of 91123 backedges. 26506 proven. 3529 refuted. 0 times theorem prover too weak. 61088 trivial. 0 not checked. [2018-12-09 15:44:59,737 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:44:59,737 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:44:59,743 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:44:59,912 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:44:59,912 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:44:59,921 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:00,856 INFO L134 CoverageAnalysis]: Checked inductivity of 91123 backedges. 39629 proven. 616 refuted. 0 times theorem prover too weak. 50878 trivial. 0 not checked. [2018-12-09 15:45:00,872 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:00,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 36] total 77 [2018-12-09 15:45:00,873 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-12-09 15:45:00,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-12-09 15:45:00,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=887, Invalid=4965, Unknown=0, NotChecked=0, Total=5852 [2018-12-09 15:45:00,873 INFO L87 Difference]: Start difference. First operand 1338 states and 1348 transitions. Second operand 77 states. [2018-12-09 15:45:02,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:02,658 INFO L93 Difference]: Finished difference Result 1155 states and 1158 transitions. [2018-12-09 15:45:02,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2018-12-09 15:45:02,658 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1128 [2018-12-09 15:45:02,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:02,660 INFO L225 Difference]: With dead ends: 1155 [2018-12-09 15:45:02,660 INFO L226 Difference]: Without dead ends: 1146 [2018-12-09 15:45:02,661 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1239 GetRequests, 1096 SyntacticMatches, 0 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6478 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3173, Invalid=17707, Unknown=0, NotChecked=0, Total=20880 [2018-12-09 15:45:02,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1146 states. [2018-12-09 15:45:02,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1146 to 1142. [2018-12-09 15:45:02,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1142 states. [2018-12-09 15:45:02,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1142 states to 1142 states and 1145 transitions. [2018-12-09 15:45:02,667 INFO L78 Accepts]: Start accepts. Automaton has 1142 states and 1145 transitions. Word has length 1128 [2018-12-09 15:45:02,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:02,668 INFO L480 AbstractCegarLoop]: Abstraction has 1142 states and 1145 transitions. [2018-12-09 15:45:02,668 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-12-09 15:45:02,668 INFO L276 IsEmpty]: Start isEmpty. Operand 1142 states and 1145 transitions. [2018-12-09 15:45:02,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1134 [2018-12-09 15:45:02,674 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:02,674 INFO L402 BasicCegarLoop]: trace histogram [188, 187, 187, 187, 187, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:02,674 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:02,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:02,675 INFO L82 PathProgramCache]: Analyzing trace with hash -1908118869, now seen corresponding path program 33 times [2018-12-09 15:45:02,675 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:02,675 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:02,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:02,676 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:02,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:02,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:03,541 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 28594 proven. 2298 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2018-12-09 15:45:03,541 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:03,541 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:03,546 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:45:03,791 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2018-12-09 15:45:03,792 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:03,798 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:04,492 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 27880 proven. 2298 refuted. 0 times theorem prover too weak. 61894 trivial. 0 not checked. [2018-12-09 15:45:04,507 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:04,517 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 27] total 65 [2018-12-09 15:45:04,518 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-12-09 15:45:04,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-12-09 15:45:04,518 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=800, Invalid=3360, Unknown=0, NotChecked=0, Total=4160 [2018-12-09 15:45:04,518 INFO L87 Difference]: Start difference. First operand 1142 states and 1145 transitions. Second operand 65 states. [2018-12-09 15:45:05,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:05,781 INFO L93 Difference]: Finished difference Result 1256 states and 1261 transitions. [2018-12-09 15:45:05,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-12-09 15:45:05,782 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 1133 [2018-12-09 15:45:05,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:05,784 INFO L225 Difference]: With dead ends: 1256 [2018-12-09 15:45:05,784 INFO L226 Difference]: Without dead ends: 1256 [2018-12-09 15:45:05,784 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1231 GetRequests, 1113 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4241 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3392, Invalid=10888, Unknown=0, NotChecked=0, Total=14280 [2018-12-09 15:45:05,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1256 states. [2018-12-09 15:45:05,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1256 to 1249. [2018-12-09 15:45:05,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1249 states. [2018-12-09 15:45:05,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1249 states to 1249 states and 1254 transitions. [2018-12-09 15:45:05,791 INFO L78 Accepts]: Start accepts. Automaton has 1249 states and 1254 transitions. Word has length 1133 [2018-12-09 15:45:05,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:05,791 INFO L480 AbstractCegarLoop]: Abstraction has 1249 states and 1254 transitions. [2018-12-09 15:45:05,791 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-12-09 15:45:05,791 INFO L276 IsEmpty]: Start isEmpty. Operand 1249 states and 1254 transitions. [2018-12-09 15:45:05,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1139 [2018-12-09 15:45:05,797 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:05,797 INFO L402 BasicCegarLoop]: trace histogram [189, 188, 188, 188, 188, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:05,797 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:05,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:05,797 INFO L82 PathProgramCache]: Analyzing trace with hash -1485351030, now seen corresponding path program 34 times [2018-12-09 15:45:05,797 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:05,797 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:05,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:05,798 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:05,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:05,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:06,394 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 16131 proven. 868 refuted. 0 times theorem prover too weak. 76027 trivial. 0 not checked. [2018-12-09 15:45:06,394 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:06,394 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:06,400 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:45:07,014 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:45:07,015 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:07,027 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:07,556 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 15963 proven. 801 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-09 15:45:07,574 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:07,574 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 20] total 44 [2018-12-09 15:45:07,575 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-12-09 15:45:07,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-12-09 15:45:07,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=263, Invalid=1717, Unknown=0, NotChecked=0, Total=1980 [2018-12-09 15:45:07,575 INFO L87 Difference]: Start difference. First operand 1249 states and 1254 transitions. Second operand 45 states. [2018-12-09 15:45:09,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:09,096 INFO L93 Difference]: Finished difference Result 1485 states and 1496 transitions. [2018-12-09 15:45:09,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-12-09 15:45:09,096 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 1138 [2018-12-09 15:45:09,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:09,098 INFO L225 Difference]: With dead ends: 1485 [2018-12-09 15:45:09,098 INFO L226 Difference]: Without dead ends: 1485 [2018-12-09 15:45:09,099 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1185 GetRequests, 1119 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 789 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=497, Invalid=4059, Unknown=0, NotChecked=0, Total=4556 [2018-12-09 15:45:09,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1485 states. [2018-12-09 15:45:09,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1485 to 1459. [2018-12-09 15:45:09,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1459 states. [2018-12-09 15:45:09,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1459 states to 1459 states and 1469 transitions. [2018-12-09 15:45:09,106 INFO L78 Accepts]: Start accepts. Automaton has 1459 states and 1469 transitions. Word has length 1138 [2018-12-09 15:45:09,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:09,107 INFO L480 AbstractCegarLoop]: Abstraction has 1459 states and 1469 transitions. [2018-12-09 15:45:09,107 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-12-09 15:45:09,107 INFO L276 IsEmpty]: Start isEmpty. Operand 1459 states and 1469 transitions. [2018-12-09 15:45:09,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1240 [2018-12-09 15:45:09,113 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:09,113 INFO L402 BasicCegarLoop]: trace histogram [207, 206, 206, 206, 206, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:09,113 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:09,113 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:09,113 INFO L82 PathProgramCache]: Analyzing trace with hash 775919112, now seen corresponding path program 35 times [2018-12-09 15:45:09,113 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:09,114 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:09,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:09,114 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:09,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:09,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:10,101 INFO L134 CoverageAnalysis]: Checked inductivity of 111450 backedges. 31325 proven. 3961 refuted. 0 times theorem prover too weak. 76164 trivial. 0 not checked. [2018-12-09 15:45:10,101 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:10,101 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:10,107 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:45:11,547 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 45 check-sat command(s) [2018-12-09 15:45:11,547 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:11,562 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:12,818 INFO L134 CoverageAnalysis]: Checked inductivity of 111450 backedges. 50996 proven. 6057 refuted. 0 times theorem prover too weak. 54397 trivial. 0 not checked. [2018-12-09 15:45:12,836 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:12,836 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 42] total 85 [2018-12-09 15:45:12,837 INFO L459 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-12-09 15:45:12,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-12-09 15:45:12,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=961, Invalid=6179, Unknown=0, NotChecked=0, Total=7140 [2018-12-09 15:45:12,837 INFO L87 Difference]: Start difference. First operand 1459 states and 1469 transitions. Second operand 85 states. [2018-12-09 15:45:17,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:17,860 INFO L93 Difference]: Finished difference Result 1266 states and 1269 transitions. [2018-12-09 15:45:17,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-12-09 15:45:17,860 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1239 [2018-12-09 15:45:17,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:17,866 INFO L225 Difference]: With dead ends: 1266 [2018-12-09 15:45:17,867 INFO L226 Difference]: Without dead ends: 1257 [2018-12-09 15:45:17,870 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1369 GetRequests, 1202 SyntacticMatches, 0 SemanticMatches, 167 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8749 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=4284, Invalid=24108, Unknown=0, NotChecked=0, Total=28392 [2018-12-09 15:45:17,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1257 states. [2018-12-09 15:45:17,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1257 to 1253. [2018-12-09 15:45:17,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1253 states. [2018-12-09 15:45:17,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 1253 states and 1256 transitions. [2018-12-09 15:45:17,889 INFO L78 Accepts]: Start accepts. Automaton has 1253 states and 1256 transitions. Word has length 1239 [2018-12-09 15:45:17,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:17,890 INFO L480 AbstractCegarLoop]: Abstraction has 1253 states and 1256 transitions. [2018-12-09 15:45:17,890 INFO L481 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-12-09 15:45:17,890 INFO L276 IsEmpty]: Start isEmpty. Operand 1253 states and 1256 transitions. [2018-12-09 15:45:17,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1245 [2018-12-09 15:45:17,900 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:17,901 INFO L402 BasicCegarLoop]: trace histogram [208, 207, 207, 207, 207, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:17,901 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:17,901 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:17,901 INFO L82 PathProgramCache]: Analyzing trace with hash -1962245081, now seen corresponding path program 36 times [2018-12-09 15:45:17,901 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:17,901 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:17,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:17,902 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:17,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:17,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:18,863 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 33670 proven. 2568 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2018-12-09 15:45:18,863 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:18,863 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:18,869 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:45:19,661 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 39 check-sat command(s) [2018-12-09 15:45:19,661 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:19,671 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:20,465 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 18596 proven. 893 refuted. 0 times theorem prover too weak. 93011 trivial. 0 not checked. [2018-12-09 15:45:20,482 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:20,482 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 22] total 67 [2018-12-09 15:45:20,483 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-12-09 15:45:20,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-12-09 15:45:20,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=686, Invalid=3736, Unknown=0, NotChecked=0, Total=4422 [2018-12-09 15:45:20,483 INFO L87 Difference]: Start difference. First operand 1253 states and 1256 transitions. Second operand 67 states. [2018-12-09 15:45:22,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:22,195 INFO L93 Difference]: Finished difference Result 1380 states and 1386 transitions. [2018-12-09 15:45:22,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-09 15:45:22,195 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1244 [2018-12-09 15:45:22,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:22,197 INFO L225 Difference]: With dead ends: 1380 [2018-12-09 15:45:22,197 INFO L226 Difference]: Without dead ends: 1380 [2018-12-09 15:45:22,198 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1348 GetRequests, 1224 SyntacticMatches, 0 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3743 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3576, Invalid=12174, Unknown=0, NotChecked=0, Total=15750 [2018-12-09 15:45:22,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1380 states. [2018-12-09 15:45:22,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1380 to 1370. [2018-12-09 15:45:22,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1370 states. [2018-12-09 15:45:22,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1370 states to 1370 states and 1376 transitions. [2018-12-09 15:45:22,204 INFO L78 Accepts]: Start accepts. Automaton has 1370 states and 1376 transitions. Word has length 1244 [2018-12-09 15:45:22,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:22,204 INFO L480 AbstractCegarLoop]: Abstraction has 1370 states and 1376 transitions. [2018-12-09 15:45:22,205 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-12-09 15:45:22,205 INFO L276 IsEmpty]: Start isEmpty. Operand 1370 states and 1376 transitions. [2018-12-09 15:45:22,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1255 [2018-12-09 15:45:22,211 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:22,211 INFO L402 BasicCegarLoop]: trace histogram [210, 209, 209, 209, 209, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:22,211 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:22,211 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:22,211 INFO L82 PathProgramCache]: Analyzing trace with hash 1445425069, now seen corresponding path program 37 times [2018-12-09 15:45:22,211 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:22,212 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:22,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:22,212 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:22,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:22,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:23,103 INFO L134 CoverageAnalysis]: Checked inductivity of 114615 backedges. 20625 proven. 993 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2018-12-09 15:45:23,103 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:23,104 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:23,110 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:45:23,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:23,299 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:24,207 INFO L134 CoverageAnalysis]: Checked inductivity of 114615 backedges. 20664 proven. 954 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2018-12-09 15:45:24,222 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:24,223 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 43] total 66 [2018-12-09 15:45:24,223 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-12-09 15:45:24,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-12-09 15:45:24,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=991, Invalid=3299, Unknown=0, NotChecked=0, Total=4290 [2018-12-09 15:45:24,224 INFO L87 Difference]: Start difference. First operand 1370 states and 1376 transitions. Second operand 66 states. [2018-12-09 15:45:25,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:25,374 INFO L93 Difference]: Finished difference Result 1601 states and 1611 transitions. [2018-12-09 15:45:25,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-12-09 15:45:25,374 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 1254 [2018-12-09 15:45:25,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:25,376 INFO L225 Difference]: With dead ends: 1601 [2018-12-09 15:45:25,376 INFO L226 Difference]: Without dead ends: 1601 [2018-12-09 15:45:25,377 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1336 GetRequests, 1233 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1823 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2782, Invalid=8138, Unknown=0, NotChecked=0, Total=10920 [2018-12-09 15:45:25,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1601 states. [2018-12-09 15:45:25,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1601 to 1590. [2018-12-09 15:45:25,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1590 states. [2018-12-09 15:45:25,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1590 states to 1590 states and 1600 transitions. [2018-12-09 15:45:25,385 INFO L78 Accepts]: Start accepts. Automaton has 1590 states and 1600 transitions. Word has length 1254 [2018-12-09 15:45:25,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:25,385 INFO L480 AbstractCegarLoop]: Abstraction has 1590 states and 1600 transitions. [2018-12-09 15:45:25,385 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-12-09 15:45:25,385 INFO L276 IsEmpty]: Start isEmpty. Operand 1590 states and 1600 transitions. [2018-12-09 15:45:25,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1356 [2018-12-09 15:45:25,393 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:25,393 INFO L402 BasicCegarLoop]: trace histogram [228, 227, 227, 227, 227, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:25,393 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:25,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:25,393 INFO L82 PathProgramCache]: Analyzing trace with hash -862088469, now seen corresponding path program 38 times [2018-12-09 15:45:25,393 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:25,393 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:25,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:25,394 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:45:25,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:25,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:26,495 INFO L134 CoverageAnalysis]: Checked inductivity of 134979 backedges. 36696 proven. 4418 refuted. 0 times theorem prover too weak. 93865 trivial. 0 not checked. [2018-12-09 15:45:26,495 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:26,495 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:26,501 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:45:26,697 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:45:26,697 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:26,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:27,902 INFO L134 CoverageAnalysis]: Checked inductivity of 134979 backedges. 54954 proven. 783 refuted. 0 times theorem prover too weak. 79242 trivial. 0 not checked. [2018-12-09 15:45:27,918 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:27,919 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 40] total 85 [2018-12-09 15:45:27,919 INFO L459 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-12-09 15:45:27,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-12-09 15:45:27,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1084, Invalid=6056, Unknown=0, NotChecked=0, Total=7140 [2018-12-09 15:45:27,920 INFO L87 Difference]: Start difference. First operand 1590 states and 1600 transitions. Second operand 85 states. [2018-12-09 15:45:30,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:30,719 INFO L93 Difference]: Finished difference Result 1382 states and 1385 transitions. [2018-12-09 15:45:30,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-12-09 15:45:30,720 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1355 [2018-12-09 15:45:30,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:30,722 INFO L225 Difference]: With dead ends: 1382 [2018-12-09 15:45:30,722 INFO L226 Difference]: Without dead ends: 1373 [2018-12-09 15:45:30,723 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1478 GetRequests, 1319 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8078 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3902, Invalid=21858, Unknown=0, NotChecked=0, Total=25760 [2018-12-09 15:45:30,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1373 states. [2018-12-09 15:45:30,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1373 to 1369. [2018-12-09 15:45:30,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1369 states. [2018-12-09 15:45:30,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1369 states to 1369 states and 1372 transitions. [2018-12-09 15:45:30,731 INFO L78 Accepts]: Start accepts. Automaton has 1369 states and 1372 transitions. Word has length 1355 [2018-12-09 15:45:30,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:30,731 INFO L480 AbstractCegarLoop]: Abstraction has 1369 states and 1372 transitions. [2018-12-09 15:45:30,731 INFO L481 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-12-09 15:45:30,731 INFO L276 IsEmpty]: Start isEmpty. Operand 1369 states and 1372 transitions. [2018-12-09 15:45:30,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1361 [2018-12-09 15:45:30,740 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:30,740 INFO L402 BasicCegarLoop]: trace histogram [229, 228, 228, 228, 228, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:30,740 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:30,740 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:30,741 INFO L82 PathProgramCache]: Analyzing trace with hash -1077882064, now seen corresponding path program 39 times [2018-12-09 15:45:30,741 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:30,741 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:30,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:30,741 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:30,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:30,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:31,865 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 39313 proven. 2853 refuted. 0 times theorem prover too weak. 93969 trivial. 0 not checked. [2018-12-09 15:45:31,865 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:31,865 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:31,872 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:45:32,251 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-12-09 15:45:32,251 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:32,260 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:33,134 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 38420 proven. 2853 refuted. 0 times theorem prover too weak. 94862 trivial. 0 not checked. [2018-12-09 15:45:33,150 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:33,151 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 29] total 71 [2018-12-09 15:45:33,151 INFO L459 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-12-09 15:45:33,152 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-12-09 15:45:33,152 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=966, Invalid=4004, Unknown=0, NotChecked=0, Total=4970 [2018-12-09 15:45:33,152 INFO L87 Difference]: Start difference. First operand 1369 states and 1372 transitions. Second operand 71 states. [2018-12-09 15:45:34,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:34,889 INFO L93 Difference]: Finished difference Result 1493 states and 1498 transitions. [2018-12-09 15:45:34,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-12-09 15:45:34,889 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 1360 [2018-12-09 15:45:34,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:34,891 INFO L225 Difference]: With dead ends: 1493 [2018-12-09 15:45:34,891 INFO L226 Difference]: Without dead ends: 1493 [2018-12-09 15:45:34,892 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1468 GetRequests, 1338 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5193 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=4124, Invalid=13168, Unknown=0, NotChecked=0, Total=17292 [2018-12-09 15:45:34,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1493 states. [2018-12-09 15:45:34,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1493 to 1486. [2018-12-09 15:45:34,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1486 states. [2018-12-09 15:45:34,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1486 states to 1486 states and 1491 transitions. [2018-12-09 15:45:34,899 INFO L78 Accepts]: Start accepts. Automaton has 1486 states and 1491 transitions. Word has length 1360 [2018-12-09 15:45:34,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:34,899 INFO L480 AbstractCegarLoop]: Abstraction has 1486 states and 1491 transitions. [2018-12-09 15:45:34,900 INFO L481 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-12-09 15:45:34,900 INFO L276 IsEmpty]: Start isEmpty. Operand 1486 states and 1491 transitions. [2018-12-09 15:45:34,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1366 [2018-12-09 15:45:34,907 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:34,907 INFO L402 BasicCegarLoop]: trace histogram [230, 229, 229, 229, 229, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:34,908 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:34,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:34,908 INFO L82 PathProgramCache]: Analyzing trace with hash -1160826203, now seen corresponding path program 40 times [2018-12-09 15:45:34,908 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:34,908 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:34,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:34,909 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:34,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:34,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:35,702 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 22074 proven. 1084 refuted. 0 times theorem prover too weak. 114138 trivial. 0 not checked. [2018-12-09 15:45:35,702 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:35,702 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:35,708 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:45:36,472 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:45:36,472 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:36,486 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:37,183 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 21717 proven. 990 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-09 15:45:37,202 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:37,203 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 22] total 50 [2018-12-09 15:45:37,203 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-12-09 15:45:37,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-12-09 15:45:37,204 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=2229, Unknown=0, NotChecked=0, Total=2550 [2018-12-09 15:45:37,204 INFO L87 Difference]: Start difference. First operand 1486 states and 1491 transitions. Second operand 51 states. [2018-12-09 15:45:38,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:38,609 INFO L93 Difference]: Finished difference Result 1742 states and 1753 transitions. [2018-12-09 15:45:38,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-12-09 15:45:38,610 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 1365 [2018-12-09 15:45:38,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:38,613 INFO L225 Difference]: With dead ends: 1742 [2018-12-09 15:45:38,613 INFO L226 Difference]: Without dead ends: 1742 [2018-12-09 15:45:38,613 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1418 GetRequests, 1344 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1051 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=614, Invalid=5086, Unknown=0, NotChecked=0, Total=5700 [2018-12-09 15:45:38,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1742 states. [2018-12-09 15:45:38,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1742 to 1716. [2018-12-09 15:45:38,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1716 states. [2018-12-09 15:45:38,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1716 states to 1716 states and 1726 transitions. [2018-12-09 15:45:38,623 INFO L78 Accepts]: Start accepts. Automaton has 1716 states and 1726 transitions. Word has length 1365 [2018-12-09 15:45:38,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:38,624 INFO L480 AbstractCegarLoop]: Abstraction has 1716 states and 1726 transitions. [2018-12-09 15:45:38,624 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-12-09 15:45:38,624 INFO L276 IsEmpty]: Start isEmpty. Operand 1716 states and 1726 transitions. [2018-12-09 15:45:38,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1477 [2018-12-09 15:45:38,632 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:38,633 INFO L402 BasicCegarLoop]: trace histogram [250, 249, 249, 249, 249, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:38,633 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:38,633 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:38,633 INFO L82 PathProgramCache]: Analyzing trace with hash 1797808493, now seen corresponding path program 41 times [2018-12-09 15:45:38,633 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:38,633 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:38,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:38,633 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:38,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:38,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:39,874 INFO L134 CoverageAnalysis]: Checked inductivity of 162028 backedges. 42649 proven. 4900 refuted. 0 times theorem prover too weak. 114479 trivial. 0 not checked. [2018-12-09 15:45:39,874 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:39,875 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:39,880 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:45:43,579 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2018-12-09 15:45:43,579 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:43,601 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:45,142 INFO L134 CoverageAnalysis]: Checked inductivity of 162028 backedges. 67896 proven. 8842 refuted. 0 times theorem prover too weak. 85290 trivial. 0 not checked. [2018-12-09 15:45:45,163 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:45,163 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 46] total 93 [2018-12-09 15:45:45,164 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-12-09 15:45:45,164 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-12-09 15:45:45,164 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1146, Invalid=7410, Unknown=0, NotChecked=0, Total=8556 [2018-12-09 15:45:45,164 INFO L87 Difference]: Start difference. First operand 1716 states and 1726 transitions. Second operand 93 states. [2018-12-09 15:45:50,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:50,095 INFO L93 Difference]: Finished difference Result 1503 states and 1506 transitions. [2018-12-09 15:45:50,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2018-12-09 15:45:50,096 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1476 [2018-12-09 15:45:50,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:50,103 INFO L225 Difference]: With dead ends: 1503 [2018-12-09 15:45:50,103 INFO L226 Difference]: Without dead ends: 1494 [2018-12-09 15:45:50,106 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1620 GetRequests, 1435 SyntacticMatches, 0 SemanticMatches, 185 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10950 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=5154, Invalid=29628, Unknown=0, NotChecked=0, Total=34782 [2018-12-09 15:45:50,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2018-12-09 15:45:50,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1490. [2018-12-09 15:45:50,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1490 states. [2018-12-09 15:45:50,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1490 states to 1490 states and 1493 transitions. [2018-12-09 15:45:50,122 INFO L78 Accepts]: Start accepts. Automaton has 1490 states and 1493 transitions. Word has length 1476 [2018-12-09 15:45:50,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:50,123 INFO L480 AbstractCegarLoop]: Abstraction has 1490 states and 1493 transitions. [2018-12-09 15:45:50,123 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-12-09 15:45:50,123 INFO L276 IsEmpty]: Start isEmpty. Operand 1490 states and 1493 transitions. [2018-12-09 15:45:50,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1482 [2018-12-09 15:45:50,135 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:50,135 INFO L402 BasicCegarLoop]: trace histogram [251, 250, 250, 250, 250, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:50,135 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:50,135 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:50,136 INFO L82 PathProgramCache]: Analyzing trace with hash -667535262, now seen corresponding path program 42 times [2018-12-09 15:45:50,136 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:50,136 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:50,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:50,136 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:50,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:50,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:51,393 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 45553 proven. 3153 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2018-12-09 15:45:51,393 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:51,393 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:51,399 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:45:52,929 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-12-09 15:45:52,929 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:45:52,942 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:53,935 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 44563 proven. 3153 refuted. 0 times theorem prover too weak. 115579 trivial. 0 not checked. [2018-12-09 15:45:53,953 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:53,953 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 30] total 74 [2018-12-09 15:45:53,954 INFO L459 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-12-09 15:45:53,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-12-09 15:45:53,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1055, Invalid=4347, Unknown=0, NotChecked=0, Total=5402 [2018-12-09 15:45:53,954 INFO L87 Difference]: Start difference. First operand 1490 states and 1493 transitions. Second operand 74 states. [2018-12-09 15:45:55,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:55,612 INFO L93 Difference]: Finished difference Result 1619 states and 1624 transitions. [2018-12-09 15:45:55,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-12-09 15:45:55,612 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1481 [2018-12-09 15:45:55,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:55,615 INFO L225 Difference]: With dead ends: 1619 [2018-12-09 15:45:55,615 INFO L226 Difference]: Without dead ends: 1619 [2018-12-09 15:45:55,616 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1594 GetRequests, 1458 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5705 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=4517, Invalid=14389, Unknown=0, NotChecked=0, Total=18906 [2018-12-09 15:45:55,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1619 states. [2018-12-09 15:45:55,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1619 to 1612. [2018-12-09 15:45:55,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1612 states. [2018-12-09 15:45:55,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1612 states to 1612 states and 1617 transitions. [2018-12-09 15:45:55,623 INFO L78 Accepts]: Start accepts. Automaton has 1612 states and 1617 transitions. Word has length 1481 [2018-12-09 15:45:55,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:55,623 INFO L480 AbstractCegarLoop]: Abstraction has 1612 states and 1617 transitions. [2018-12-09 15:45:55,623 INFO L481 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-12-09 15:45:55,623 INFO L276 IsEmpty]: Start isEmpty. Operand 1612 states and 1617 transitions. [2018-12-09 15:45:55,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1487 [2018-12-09 15:45:55,632 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:55,632 INFO L402 BasicCegarLoop]: trace histogram [252, 251, 251, 251, 251, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:55,632 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:55,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:55,632 INFO L82 PathProgramCache]: Analyzing trace with hash 9778855, now seen corresponding path program 43 times [2018-12-09 15:45:55,633 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:55,633 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:55,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:55,633 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:45:55,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:55,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:56,522 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25151 proven. 1201 refuted. 0 times theorem prover too weak. 138215 trivial. 0 not checked. [2018-12-09 15:45:56,522 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:45:56,522 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:45:56,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:45:56,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:45:56,753 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:45:57,553 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25050 proven. 1092 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-09 15:45:57,569 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:45:57,570 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 23] total 49 [2018-12-09 15:45:57,570 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-12-09 15:45:57,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-12-09 15:45:57,570 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=331, Invalid=2119, Unknown=0, NotChecked=0, Total=2450 [2018-12-09 15:45:57,571 INFO L87 Difference]: Start difference. First operand 1612 states and 1617 transitions. Second operand 50 states. [2018-12-09 15:45:59,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:45:59,066 INFO L93 Difference]: Finished difference Result 1878 states and 1889 transitions. [2018-12-09 15:45:59,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-12-09 15:45:59,066 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 1486 [2018-12-09 15:45:59,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:45:59,069 INFO L225 Difference]: With dead ends: 1878 [2018-12-09 15:45:59,069 INFO L226 Difference]: Without dead ends: 1878 [2018-12-09 15:45:59,069 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1538 GetRequests, 1464 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 952 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=577, Invalid=5123, Unknown=0, NotChecked=0, Total=5700 [2018-12-09 15:45:59,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1878 states. [2018-12-09 15:45:59,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1878 to 1852. [2018-12-09 15:45:59,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1852 states. [2018-12-09 15:45:59,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1852 states to 1852 states and 1862 transitions. [2018-12-09 15:45:59,078 INFO L78 Accepts]: Start accepts. Automaton has 1852 states and 1862 transitions. Word has length 1486 [2018-12-09 15:45:59,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:45:59,079 INFO L480 AbstractCegarLoop]: Abstraction has 1852 states and 1862 transitions. [2018-12-09 15:45:59,079 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-12-09 15:45:59,079 INFO L276 IsEmpty]: Start isEmpty. Operand 1852 states and 1862 transitions. [2018-12-09 15:45:59,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1603 [2018-12-09 15:45:59,089 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:45:59,089 INFO L402 BasicCegarLoop]: trace histogram [273, 272, 272, 272, 272, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:45:59,089 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:45:59,089 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:45:59,089 INFO L82 PathProgramCache]: Analyzing trace with hash 1962499760, now seen corresponding path program 44 times [2018-12-09 15:45:59,089 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:45:59,089 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:45:59,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:59,090 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:45:59,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:45:59,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:00,488 INFO L134 CoverageAnalysis]: Checked inductivity of 192930 backedges. 49214 proven. 5407 refuted. 0 times theorem prover too weak. 138309 trivial. 0 not checked. [2018-12-09 15:46:00,488 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:00,488 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:00,494 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:46:00,742 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:46:00,743 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:46:00,755 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:02,278 INFO L134 CoverageAnalysis]: Checked inductivity of 192930 backedges. 73783 proven. 970 refuted. 0 times theorem prover too weak. 118177 trivial. 0 not checked. [2018-12-09 15:46:02,294 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:02,294 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 44] total 93 [2018-12-09 15:46:02,295 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-12-09 15:46:02,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-12-09 15:46:02,296 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1301, Invalid=7255, Unknown=0, NotChecked=0, Total=8556 [2018-12-09 15:46:02,296 INFO L87 Difference]: Start difference. First operand 1852 states and 1862 transitions. Second operand 93 states. [2018-12-09 15:46:04,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:04,736 INFO L93 Difference]: Finished difference Result 1629 states and 1632 transitions. [2018-12-09 15:46:04,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2018-12-09 15:46:04,736 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1602 [2018-12-09 15:46:04,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:04,739 INFO L225 Difference]: With dead ends: 1629 [2018-12-09 15:46:04,739 INFO L226 Difference]: Without dead ends: 1620 [2018-12-09 15:46:04,740 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1737 GetRequests, 1562 SyntacticMatches, 0 SemanticMatches, 175 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9854 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=4707, Invalid=26445, Unknown=0, NotChecked=0, Total=31152 [2018-12-09 15:46:04,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states. [2018-12-09 15:46:04,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 1616. [2018-12-09 15:46:04,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1616 states. [2018-12-09 15:46:04,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1616 states to 1616 states and 1619 transitions. [2018-12-09 15:46:04,747 INFO L78 Accepts]: Start accepts. Automaton has 1616 states and 1619 transitions. Word has length 1602 [2018-12-09 15:46:04,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:04,748 INFO L480 AbstractCegarLoop]: Abstraction has 1616 states and 1619 transitions. [2018-12-09 15:46:04,748 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-12-09 15:46:04,748 INFO L276 IsEmpty]: Start isEmpty. Operand 1616 states and 1619 transitions. [2018-12-09 15:46:04,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1608 [2018-12-09 15:46:04,758 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:04,758 INFO L402 BasicCegarLoop]: trace histogram [274, 273, 273, 273, 273, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:04,758 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:04,758 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:04,758 INFO L82 PathProgramCache]: Analyzing trace with hash -1747254261, now seen corresponding path program 45 times [2018-12-09 15:46:04,758 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:04,758 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:04,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:04,759 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:46:04,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:04,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:06,213 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 52420 proven. 3468 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2018-12-09 15:46:06,213 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:06,213 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:06,219 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:46:06,774 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-12-09 15:46:06,775 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:46:06,784 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:07,860 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 28595 proven. 1199 refuted. 0 times theorem prover too weak. 164519 trivial. 0 not checked. [2018-12-09 15:46:07,876 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:07,876 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 25] total 76 [2018-12-09 15:46:07,876 INFO L459 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-12-09 15:46:07,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-12-09 15:46:07,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=890, Invalid=4810, Unknown=0, NotChecked=0, Total=5700 [2018-12-09 15:46:07,877 INFO L87 Difference]: Start difference. First operand 1616 states and 1619 transitions. Second operand 76 states. [2018-12-09 15:46:10,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:10,019 INFO L93 Difference]: Finished difference Result 1758 states and 1764 transitions. [2018-12-09 15:46:10,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-09 15:46:10,019 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1607 [2018-12-09 15:46:10,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:10,021 INFO L225 Difference]: With dead ends: 1758 [2018-12-09 15:46:10,021 INFO L226 Difference]: Without dead ends: 1758 [2018-12-09 15:46:10,022 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1726 GetRequests, 1584 SyntacticMatches, 0 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4961 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=4695, Invalid=15897, Unknown=0, NotChecked=0, Total=20592 [2018-12-09 15:46:10,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1758 states. [2018-12-09 15:46:10,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1758 to 1748. [2018-12-09 15:46:10,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1748 states. [2018-12-09 15:46:10,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1748 states to 1748 states and 1754 transitions. [2018-12-09 15:46:10,029 INFO L78 Accepts]: Start accepts. Automaton has 1748 states and 1754 transitions. Word has length 1607 [2018-12-09 15:46:10,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:10,029 INFO L480 AbstractCegarLoop]: Abstraction has 1748 states and 1754 transitions. [2018-12-09 15:46:10,029 INFO L481 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-12-09 15:46:10,029 INFO L276 IsEmpty]: Start isEmpty. Operand 1748 states and 1754 transitions. [2018-12-09 15:46:10,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1618 [2018-12-09 15:46:10,039 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:10,039 INFO L402 BasicCegarLoop]: trace histogram [276, 275, 275, 275, 275, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:10,039 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:10,040 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:10,040 INFO L82 PathProgramCache]: Analyzing trace with hash -1712352251, now seen corresponding path program 46 times [2018-12-09 15:46:10,040 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:10,040 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:10,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:10,040 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:46:10,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:10,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:11,345 INFO L134 CoverageAnalysis]: Checked inductivity of 197094 backedges. 31275 proven. 1347 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2018-12-09 15:46:11,345 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:11,345 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:11,353 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:46:11,559 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:46:11,560 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:46:11,573 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:12,970 INFO L134 CoverageAnalysis]: Checked inductivity of 197094 backedges. 31106 proven. 4393 refuted. 0 times theorem prover too weak. 161595 trivial. 0 not checked. [2018-12-09 15:46:12,986 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:12,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 53] total 79 [2018-12-09 15:46:12,987 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-12-09 15:46:12,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-12-09 15:46:12,987 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1288, Invalid=4874, Unknown=0, NotChecked=0, Total=6162 [2018-12-09 15:46:12,988 INFO L87 Difference]: Start difference. First operand 1748 states and 1754 transitions. Second operand 79 states. [2018-12-09 15:46:14,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:14,811 INFO L93 Difference]: Finished difference Result 2009 states and 2019 transitions. [2018-12-09 15:46:14,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-12-09 15:46:14,811 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1617 [2018-12-09 15:46:14,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:14,815 INFO L225 Difference]: With dead ends: 2009 [2018-12-09 15:46:14,815 INFO L226 Difference]: Without dead ends: 2009 [2018-12-09 15:46:14,816 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1713 GetRequests, 1589 SyntacticMatches, 0 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2948 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3549, Invalid=12201, Unknown=0, NotChecked=0, Total=15750 [2018-12-09 15:46:14,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2009 states. [2018-12-09 15:46:14,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2009 to 1998. [2018-12-09 15:46:14,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1998 states. [2018-12-09 15:46:14,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1998 states to 1998 states and 2008 transitions. [2018-12-09 15:46:14,832 INFO L78 Accepts]: Start accepts. Automaton has 1998 states and 2008 transitions. Word has length 1617 [2018-12-09 15:46:14,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:14,833 INFO L480 AbstractCegarLoop]: Abstraction has 1998 states and 2008 transitions. [2018-12-09 15:46:14,833 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-12-09 15:46:14,833 INFO L276 IsEmpty]: Start isEmpty. Operand 1998 states and 2008 transitions. [2018-12-09 15:46:14,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1734 [2018-12-09 15:46:14,855 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:14,855 INFO L402 BasicCegarLoop]: trace histogram [297, 296, 296, 296, 296, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:14,855 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:14,855 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:14,855 INFO L82 PathProgramCache]: Analyzing trace with hash -1388841432, now seen corresponding path program 47 times [2018-12-09 15:46:14,855 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:14,856 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:14,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:14,856 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:46:14,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:14,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:16,461 INFO L134 CoverageAnalysis]: Checked inductivity of 228033 backedges. 56421 proven. 5939 refuted. 0 times theorem prover too weak. 165673 trivial. 0 not checked. [2018-12-09 15:46:16,462 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:16,462 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:16,467 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:46:20,089 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 49 check-sat command(s) [2018-12-09 15:46:20,090 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:46:20,114 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:22,025 INFO L134 CoverageAnalysis]: Checked inductivity of 228033 backedges. 84304 proven. 6313 refuted. 0 times theorem prover too weak. 137416 trivial. 0 not checked. [2018-12-09 15:46:22,045 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:22,046 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 50] total 101 [2018-12-09 15:46:22,046 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-12-09 15:46:22,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-12-09 15:46:22,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1396, Invalid=8704, Unknown=0, NotChecked=0, Total=10100 [2018-12-09 15:46:22,047 INFO L87 Difference]: Start difference. First operand 1998 states and 2008 transitions. Second operand 101 states. [2018-12-09 15:46:25,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:25,242 INFO L93 Difference]: Finished difference Result 1760 states and 1763 transitions. [2018-12-09 15:46:25,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-12-09 15:46:25,242 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 1733 [2018-12-09 15:46:25,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:25,245 INFO L225 Difference]: With dead ends: 1760 [2018-12-09 15:46:25,245 INFO L226 Difference]: Without dead ends: 1751 [2018-12-09 15:46:25,248 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1900 GetRequests, 1688 SyntacticMatches, 0 SemanticMatches, 212 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15151 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=6669, Invalid=38913, Unknown=0, NotChecked=0, Total=45582 [2018-12-09 15:46:25,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1751 states. [2018-12-09 15:46:25,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1751 to 1747. [2018-12-09 15:46:25,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1747 states. [2018-12-09 15:46:25,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1747 states to 1747 states and 1750 transitions. [2018-12-09 15:46:25,260 INFO L78 Accepts]: Start accepts. Automaton has 1747 states and 1750 transitions. Word has length 1733 [2018-12-09 15:46:25,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:25,261 INFO L480 AbstractCegarLoop]: Abstraction has 1747 states and 1750 transitions. [2018-12-09 15:46:25,261 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-12-09 15:46:25,261 INFO L276 IsEmpty]: Start isEmpty. Operand 1747 states and 1750 transitions. [2018-12-09 15:46:25,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1739 [2018-12-09 15:46:25,276 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:25,276 INFO L402 BasicCegarLoop]: trace histogram [298, 297, 297, 297, 297, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:25,277 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:25,277 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:25,277 INFO L82 PathProgramCache]: Analyzing trace with hash -1675122425, now seen corresponding path program 48 times [2018-12-09 15:46:25,277 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:25,277 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:25,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:25,277 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:46:25,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:25,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:26,839 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 59944 proven. 3798 refuted. 0 times theorem prover too weak. 165795 trivial. 0 not checked. [2018-12-09 15:46:26,839 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:26,839 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:26,846 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:46:30,343 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 47 check-sat command(s) [2018-12-09 15:46:30,343 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:46:30,360 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:31,543 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 32586 proven. 1311 refuted. 0 times theorem prover too weak. 195640 trivial. 0 not checked. [2018-12-09 15:46:31,562 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:31,563 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 26] total 79 [2018-12-09 15:46:31,563 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-12-09 15:46:31,563 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-12-09 15:46:31,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=964, Invalid=5198, Unknown=0, NotChecked=0, Total=6162 [2018-12-09 15:46:31,564 INFO L87 Difference]: Start difference. First operand 1747 states and 1750 transitions. Second operand 79 states. [2018-12-09 15:46:33,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:33,731 INFO L93 Difference]: Finished difference Result 1894 states and 1900 transitions. [2018-12-09 15:46:33,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-12-09 15:46:33,731 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1738 [2018-12-09 15:46:33,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:33,734 INFO L225 Difference]: With dead ends: 1894 [2018-12-09 15:46:33,734 INFO L226 Difference]: Without dead ends: 1894 [2018-12-09 15:46:33,735 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1862 GetRequests, 1714 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5405 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=5102, Invalid=17248, Unknown=0, NotChecked=0, Total=22350 [2018-12-09 15:46:33,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1894 states. [2018-12-09 15:46:33,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1894 to 1884. [2018-12-09 15:46:33,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1884 states. [2018-12-09 15:46:33,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1884 states to 1884 states and 1890 transitions. [2018-12-09 15:46:33,744 INFO L78 Accepts]: Start accepts. Automaton has 1884 states and 1890 transitions. Word has length 1738 [2018-12-09 15:46:33,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:33,745 INFO L480 AbstractCegarLoop]: Abstraction has 1884 states and 1890 transitions. [2018-12-09 15:46:33,745 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-12-09 15:46:33,745 INFO L276 IsEmpty]: Start isEmpty. Operand 1884 states and 1890 transitions. [2018-12-09 15:46:33,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1749 [2018-12-09 15:46:33,756 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:33,757 INFO L402 BasicCegarLoop]: trace histogram [300, 299, 299, 299, 299, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:33,757 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:33,757 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:33,757 INFO L82 PathProgramCache]: Analyzing trace with hash 1749257613, now seen corresponding path program 49 times [2018-12-09 15:46:33,757 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:33,757 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:33,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:33,758 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:46:33,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:33,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:35,233 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35503 proven. 1477 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2018-12-09 15:46:35,233 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:35,233 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:35,239 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:46:35,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:35,502 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:36,932 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35550 proven. 1430 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2018-12-09 15:46:36,948 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:36,948 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 51] total 78 [2018-12-09 15:46:36,949 INFO L459 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-12-09 15:46:36,949 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-12-09 15:46:36,949 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1379, Invalid=4627, Unknown=0, NotChecked=0, Total=6006 [2018-12-09 15:46:36,949 INFO L87 Difference]: Start difference. First operand 1884 states and 1890 transitions. Second operand 78 states. [2018-12-09 15:46:38,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:38,411 INFO L93 Difference]: Finished difference Result 2155 states and 2165 transitions. [2018-12-09 15:46:38,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-12-09 15:46:38,411 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1748 [2018-12-09 15:46:38,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:38,414 INFO L225 Difference]: With dead ends: 2155 [2018-12-09 15:46:38,414 INFO L226 Difference]: Without dead ends: 2155 [2018-12-09 15:46:38,415 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1846 GetRequests, 1723 SyntacticMatches, 0 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2621 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3914, Invalid=11586, Unknown=0, NotChecked=0, Total=15500 [2018-12-09 15:46:38,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2155 states. [2018-12-09 15:46:38,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2155 to 2144. [2018-12-09 15:46:38,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2144 states. [2018-12-09 15:46:38,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2144 states to 2144 states and 2154 transitions. [2018-12-09 15:46:38,425 INFO L78 Accepts]: Start accepts. Automaton has 2144 states and 2154 transitions. Word has length 1748 [2018-12-09 15:46:38,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:38,425 INFO L480 AbstractCegarLoop]: Abstraction has 2144 states and 2154 transitions. [2018-12-09 15:46:38,425 INFO L481 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-12-09 15:46:38,425 INFO L276 IsEmpty]: Start isEmpty. Operand 2144 states and 2154 transitions. [2018-12-09 15:46:38,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1870 [2018-12-09 15:46:38,438 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:38,439 INFO L402 BasicCegarLoop]: trace histogram [322, 321, 321, 321, 321, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:38,439 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:38,439 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:38,439 INFO L82 PathProgramCache]: Analyzing trace with hash -299998901, now seen corresponding path program 50 times [2018-12-09 15:46:38,439 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:38,439 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:38,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:38,440 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:46:38,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:38,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:40,202 INFO L134 CoverageAnalysis]: Checked inductivity of 267700 backedges. 64300 proven. 6496 refuted. 0 times theorem prover too weak. 196904 trivial. 0 not checked. [2018-12-09 15:46:40,202 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:40,202 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:40,208 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:46:40,479 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:46:40,480 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:46:40,494 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:42,463 INFO L134 CoverageAnalysis]: Checked inductivity of 267700 backedges. 96476 proven. 1177 refuted. 0 times theorem prover too weak. 170047 trivial. 0 not checked. [2018-12-09 15:46:42,480 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:42,480 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 48] total 101 [2018-12-09 15:46:42,481 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-12-09 15:46:42,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-12-09 15:46:42,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1538, Invalid=8562, Unknown=0, NotChecked=0, Total=10100 [2018-12-09 15:46:42,481 INFO L87 Difference]: Start difference. First operand 2144 states and 2154 transitions. Second operand 101 states. [2018-12-09 15:46:45,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:45,170 INFO L93 Difference]: Finished difference Result 1896 states and 1899 transitions. [2018-12-09 15:46:45,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-12-09 15:46:45,170 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 1869 [2018-12-09 15:46:45,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:45,173 INFO L225 Difference]: With dead ends: 1896 [2018-12-09 15:46:45,173 INFO L226 Difference]: Without dead ends: 1887 [2018-12-09 15:46:45,174 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2016 GetRequests, 1825 SyntacticMatches, 0 SemanticMatches, 191 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11806 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=5588, Invalid=31468, Unknown=0, NotChecked=0, Total=37056 [2018-12-09 15:46:45,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1887 states. [2018-12-09 15:46:45,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1887 to 1883. [2018-12-09 15:46:45,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1883 states. [2018-12-09 15:46:45,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1883 states to 1883 states and 1886 transitions. [2018-12-09 15:46:45,183 INFO L78 Accepts]: Start accepts. Automaton has 1883 states and 1886 transitions. Word has length 1869 [2018-12-09 15:46:45,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:45,183 INFO L480 AbstractCegarLoop]: Abstraction has 1883 states and 1886 transitions. [2018-12-09 15:46:45,183 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-12-09 15:46:45,183 INFO L276 IsEmpty]: Start isEmpty. Operand 1883 states and 1886 transitions. [2018-12-09 15:46:45,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1875 [2018-12-09 15:46:45,196 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:45,197 INFO L402 BasicCegarLoop]: trace histogram [323, 322, 322, 322, 322, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:45,197 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:45,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:45,197 INFO L82 PathProgramCache]: Analyzing trace with hash 754168784, now seen corresponding path program 51 times [2018-12-09 15:46:45,197 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:45,197 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:45,197 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:45,198 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:46:45,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:45,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:47,041 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 68155 proven. 4143 refuted. 0 times theorem prover too weak. 197032 trivial. 0 not checked. [2018-12-09 15:46:47,042 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:47,042 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:47,047 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:46:47,736 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-12-09 15:46:47,736 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:46:47,748 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:49,141 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 36931 proven. 1428 refuted. 0 times theorem prover too weak. 230971 trivial. 0 not checked. [2018-12-09 15:46:49,158 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:49,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 27] total 82 [2018-12-09 15:46:49,158 INFO L459 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-12-09 15:46:49,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-12-09 15:46:49,159 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1041, Invalid=5601, Unknown=0, NotChecked=0, Total=6642 [2018-12-09 15:46:49,159 INFO L87 Difference]: Start difference. First operand 1883 states and 1886 transitions. Second operand 82 states. [2018-12-09 15:46:51,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:51,502 INFO L93 Difference]: Finished difference Result 2035 states and 2041 transitions. [2018-12-09 15:46:51,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-12-09 15:46:51,503 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 1874 [2018-12-09 15:46:51,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:51,506 INFO L225 Difference]: With dead ends: 2035 [2018-12-09 15:46:51,506 INFO L226 Difference]: Without dead ends: 2035 [2018-12-09 15:46:51,507 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2003 GetRequests, 1849 SyntacticMatches, 0 SemanticMatches, 154 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5868 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=5526, Invalid=18654, Unknown=0, NotChecked=0, Total=24180 [2018-12-09 15:46:51,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2035 states. [2018-12-09 15:46:51,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2035 to 2025. [2018-12-09 15:46:51,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2025 states. [2018-12-09 15:46:51,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2025 states to 2025 states and 2031 transitions. [2018-12-09 15:46:51,516 INFO L78 Accepts]: Start accepts. Automaton has 2025 states and 2031 transitions. Word has length 1874 [2018-12-09 15:46:51,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:51,517 INFO L480 AbstractCegarLoop]: Abstraction has 2025 states and 2031 transitions. [2018-12-09 15:46:51,518 INFO L481 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-12-09 15:46:51,518 INFO L276 IsEmpty]: Start isEmpty. Operand 2025 states and 2031 transitions. [2018-12-09 15:46:51,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1885 [2018-12-09 15:46:51,532 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:51,532 INFO L402 BasicCegarLoop]: trace histogram [325, 324, 324, 324, 324, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:51,532 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:51,532 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:51,533 INFO L82 PathProgramCache]: Analyzing trace with hash 1694558474, now seen corresponding path program 52 times [2018-12-09 15:46:51,533 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:51,533 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:51,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:51,533 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:46:51,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:51,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:53,213 INFO L134 CoverageAnalysis]: Checked inductivity of 272605 backedges. 40095 proven. 1613 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2018-12-09 15:46:53,213 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:53,213 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:53,220 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:46:53,465 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:46:53,465 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:46:53,481 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:46:55,298 INFO L134 CoverageAnalysis]: Checked inductivity of 272605 backedges. 39912 proven. 5202 refuted. 0 times theorem prover too weak. 227491 trivial. 0 not checked. [2018-12-09 15:46:55,314 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:46:55,314 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 57] total 85 [2018-12-09 15:46:55,315 INFO L459 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-12-09 15:46:55,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-12-09 15:46:55,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1498, Invalid=5642, Unknown=0, NotChecked=0, Total=7140 [2018-12-09 15:46:55,315 INFO L87 Difference]: Start difference. First operand 2025 states and 2031 transitions. Second operand 85 states. [2018-12-09 15:46:57,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:46:57,129 INFO L93 Difference]: Finished difference Result 2306 states and 2316 transitions. [2018-12-09 15:46:57,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-12-09 15:46:57,129 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1884 [2018-12-09 15:46:57,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:46:57,132 INFO L225 Difference]: With dead ends: 2306 [2018-12-09 15:46:57,132 INFO L226 Difference]: Without dead ends: 2306 [2018-12-09 15:46:57,133 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1988 GetRequests, 1854 SyntacticMatches, 0 SemanticMatches, 134 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3431 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=4153, Invalid=14207, Unknown=0, NotChecked=0, Total=18360 [2018-12-09 15:46:57,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2306 states. [2018-12-09 15:46:57,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2306 to 2295. [2018-12-09 15:46:57,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2295 states. [2018-12-09 15:46:57,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2295 states to 2295 states and 2305 transitions. [2018-12-09 15:46:57,144 INFO L78 Accepts]: Start accepts. Automaton has 2295 states and 2305 transitions. Word has length 1884 [2018-12-09 15:46:57,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:46:57,144 INFO L480 AbstractCegarLoop]: Abstraction has 2295 states and 2305 transitions. [2018-12-09 15:46:57,144 INFO L481 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-12-09 15:46:57,144 INFO L276 IsEmpty]: Start isEmpty. Operand 2295 states and 2305 transitions. [2018-12-09 15:46:57,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2011 [2018-12-09 15:46:57,159 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:46:57,159 INFO L402 BasicCegarLoop]: trace histogram [348, 347, 347, 347, 347, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:46:57,160 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:46:57,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:46:57,160 INFO L82 PathProgramCache]: Analyzing trace with hash -455283635, now seen corresponding path program 53 times [2018-12-09 15:46:57,160 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:46:57,160 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:46:57,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:57,160 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:46:57,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:46:57,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:46:59,177 INFO L134 CoverageAnalysis]: Checked inductivity of 312309 backedges. 72881 proven. 7078 refuted. 0 times theorem prover too weak. 232350 trivial. 0 not checked. [2018-12-09 15:46:59,177 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:46:59,177 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:46:59,184 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:47:17,605 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 52 check-sat command(s) [2018-12-09 15:47:17,605 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:47:17,649 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:47:20,025 INFO L134 CoverageAnalysis]: Checked inductivity of 312309 backedges. 109022 proven. 7533 refuted. 0 times theorem prover too weak. 195754 trivial. 0 not checked. [2018-12-09 15:47:20,051 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:47:20,051 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 54] total 109 [2018-12-09 15:47:20,052 INFO L459 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-12-09 15:47:20,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-12-09 15:47:20,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1639, Invalid=10133, Unknown=0, NotChecked=0, Total=11772 [2018-12-09 15:47:20,053 INFO L87 Difference]: Start difference. First operand 2295 states and 2305 transitions. Second operand 109 states. [2018-12-09 15:47:24,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:47:24,005 INFO L93 Difference]: Finished difference Result 2037 states and 2040 transitions. [2018-12-09 15:47:24,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-12-09 15:47:24,006 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 2010 [2018-12-09 15:47:24,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:47:24,008 INFO L225 Difference]: With dead ends: 2037 [2018-12-09 15:47:24,008 INFO L226 Difference]: Without dead ends: 2028 [2018-12-09 15:47:24,011 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2191 GetRequests, 1961 SyntacticMatches, 0 SemanticMatches, 230 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17950 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=7839, Invalid=45753, Unknown=0, NotChecked=0, Total=53592 [2018-12-09 15:47:24,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2028 states. [2018-12-09 15:47:24,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2028 to 2024. [2018-12-09 15:47:24,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2024 states. [2018-12-09 15:47:24,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2024 states to 2024 states and 2027 transitions. [2018-12-09 15:47:24,020 INFO L78 Accepts]: Start accepts. Automaton has 2024 states and 2027 transitions. Word has length 2010 [2018-12-09 15:47:24,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:47:24,021 INFO L480 AbstractCegarLoop]: Abstraction has 2024 states and 2027 transitions. [2018-12-09 15:47:24,021 INFO L481 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-12-09 15:47:24,021 INFO L276 IsEmpty]: Start isEmpty. Operand 2024 states and 2027 transitions. [2018-12-09 15:47:24,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2016 [2018-12-09 15:47:24,037 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:47:24,038 INFO L402 BasicCegarLoop]: trace histogram [349, 348, 348, 348, 348, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:47:24,038 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:47:24,038 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:47:24,038 INFO L82 PathProgramCache]: Analyzing trace with hash -2048382334, now seen corresponding path program 54 times [2018-12-09 15:47:24,038 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:47:24,038 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:47:24,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:47:24,039 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:47:24,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:47:24,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:47:26,029 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 77083 proven. 4503 refuted. 0 times theorem prover too weak. 232484 trivial. 0 not checked. [2018-12-09 15:47:26,029 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:47:26,029 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:47:26,035 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:47:43,075 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-12-09 15:47:43,075 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:47:43,107 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:47:45,195 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 99760 proven. 13372 refuted. 0 times theorem prover too weak. 200938 trivial. 0 not checked. [2018-12-09 15:47:45,217 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:47:45,217 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 41] total 96 [2018-12-09 15:47:45,218 INFO L459 AbstractCegarLoop]: Interpolant automaton has 96 states [2018-12-09 15:47:45,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2018-12-09 15:47:45,218 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1147, Invalid=7973, Unknown=0, NotChecked=0, Total=9120 [2018-12-09 15:47:45,218 INFO L87 Difference]: Start difference. First operand 2024 states and 2027 transitions. Second operand 96 states. [2018-12-09 15:47:50,567 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 19 [2018-12-09 15:47:51,495 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 19 [2018-12-09 15:47:52,000 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 19 [2018-12-09 15:48:04,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:48:04,215 INFO L93 Difference]: Finished difference Result 2325 states and 2337 transitions. [2018-12-09 15:48:04,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 291 states. [2018-12-09 15:48:04,216 INFO L78 Accepts]: Start accepts. Automaton has 96 states. Word has length 2015 [2018-12-09 15:48:04,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:48:04,220 INFO L225 Difference]: With dead ends: 2325 [2018-12-09 15:48:04,221 INFO L226 Difference]: Without dead ends: 2325 [2018-12-09 15:48:04,227 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2334 GetRequests, 1977 SyntacticMatches, 2 SemanticMatches, 355 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50388 ImplicationChecksByTransitivity, 16.3s TimeCoverageRelationStatistics Valid=19783, Invalid=107309, Unknown=0, NotChecked=0, Total=127092 [2018-12-09 15:48:04,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states. [2018-12-09 15:48:04,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2312. [2018-12-09 15:48:04,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2312 states. [2018-12-09 15:48:04,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2312 states to 2312 states and 2323 transitions. [2018-12-09 15:48:04,242 INFO L78 Accepts]: Start accepts. Automaton has 2312 states and 2323 transitions. Word has length 2015 [2018-12-09 15:48:04,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:48:04,242 INFO L480 AbstractCegarLoop]: Abstraction has 2312 states and 2323 transitions. [2018-12-09 15:48:04,243 INFO L481 AbstractCegarLoop]: Interpolant automaton has 96 states. [2018-12-09 15:48:04,243 INFO L276 IsEmpty]: Start isEmpty. Operand 2312 states and 2323 transitions. [2018-12-09 15:48:04,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2167 [2018-12-09 15:48:04,260 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:48:04,260 INFO L402 BasicCegarLoop]: trace histogram [377, 376, 376, 376, 376, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:48:04,260 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:48:04,260 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:48:04,260 INFO L82 PathProgramCache]: Analyzing trace with hash -1713476150, now seen corresponding path program 55 times [2018-12-09 15:48:04,260 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:48:04,260 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:48:04,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:04,261 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:48:04,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:04,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:48:05,903 INFO L134 CoverageAnalysis]: Checked inductivity of 366052 backedges. 47123 proven. 1876 refuted. 0 times theorem prover too weak. 317053 trivial. 0 not checked. [2018-12-09 15:48:05,903 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:48:05,903 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:48:05,909 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:48:06,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:48:06,235 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:48:07,678 INFO L134 CoverageAnalysis]: Checked inductivity of 366052 backedges. 46875 proven. 1677 refuted. 0 times theorem prover too weak. 317500 trivial. 0 not checked. [2018-12-09 15:48:07,695 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:48:07,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 28] total 60 [2018-12-09 15:48:07,696 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-12-09 15:48:07,697 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-12-09 15:48:07,697 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=475, Invalid=3185, Unknown=0, NotChecked=0, Total=3660 [2018-12-09 15:48:07,697 INFO L87 Difference]: Start difference. First operand 2312 states and 2323 transitions. Second operand 61 states. [2018-12-09 15:48:10,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:48:10,227 INFO L93 Difference]: Finished difference Result 2780 states and 2808 transitions. [2018-12-09 15:48:10,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-12-09 15:48:10,227 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 2166 [2018-12-09 15:48:10,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:48:10,232 INFO L225 Difference]: With dead ends: 2780 [2018-12-09 15:48:10,232 INFO L226 Difference]: Without dead ends: 2780 [2018-12-09 15:48:10,232 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2230 GetRequests, 2139 SyntacticMatches, 0 SemanticMatches, 91 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1480 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=806, Invalid=7750, Unknown=0, NotChecked=0, Total=8556 [2018-12-09 15:48:10,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2780 states. [2018-12-09 15:48:10,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2780 to 2750. [2018-12-09 15:48:10,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2750 states. [2018-12-09 15:48:10,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2750 states to 2750 states and 2777 transitions. [2018-12-09 15:48:10,247 INFO L78 Accepts]: Start accepts. Automaton has 2750 states and 2777 transitions. Word has length 2166 [2018-12-09 15:48:10,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:48:10,248 INFO L480 AbstractCegarLoop]: Abstraction has 2750 states and 2777 transitions. [2018-12-09 15:48:10,248 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-12-09 15:48:10,248 INFO L276 IsEmpty]: Start isEmpty. Operand 2750 states and 2777 transitions. [2018-12-09 15:48:10,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2303 [2018-12-09 15:48:10,268 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:48:10,269 INFO L402 BasicCegarLoop]: trace histogram [402, 401, 401, 401, 401, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:48:10,269 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:48:10,269 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:48:10,269 INFO L82 PathProgramCache]: Analyzing trace with hash -397294355, now seen corresponding path program 56 times [2018-12-09 15:48:10,270 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:48:10,270 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:48:10,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:10,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:48:10,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:10,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:48:12,717 INFO L134 CoverageAnalysis]: Checked inductivity of 415907 backedges. 87699 proven. 10994 refuted. 0 times theorem prover too weak. 317214 trivial. 0 not checked. [2018-12-09 15:48:12,717 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:48:12,717 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:48:12,724 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:48:13,057 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:48:13,057 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:48:13,075 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:48:15,628 INFO L134 CoverageAnalysis]: Checked inductivity of 415907 backedges. 168229 proven. 1404 refuted. 0 times theorem prover too weak. 246274 trivial. 0 not checked. [2018-12-09 15:48:15,645 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:48:15,645 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 52] total 111 [2018-12-09 15:48:15,646 INFO L459 AbstractCegarLoop]: Interpolant automaton has 111 states [2018-12-09 15:48:15,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 111 interpolants. [2018-12-09 15:48:15,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1829, Invalid=10381, Unknown=0, NotChecked=0, Total=12210 [2018-12-09 15:48:15,647 INFO L87 Difference]: Start difference. First operand 2750 states and 2777 transitions. Second operand 111 states. [2018-12-09 15:48:18,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:48:18,440 INFO L93 Difference]: Finished difference Result 2491 states and 2504 transitions. [2018-12-09 15:48:18,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 133 states. [2018-12-09 15:48:18,441 INFO L78 Accepts]: Start accepts. Automaton has 111 states. Word has length 2302 [2018-12-09 15:48:18,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:48:18,444 INFO L225 Difference]: With dead ends: 2491 [2018-12-09 15:48:18,444 INFO L226 Difference]: Without dead ends: 2482 [2018-12-09 15:48:18,446 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2465 GetRequests, 2254 SyntacticMatches, 0 SemanticMatches, 211 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14487 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=6741, Invalid=38415, Unknown=0, NotChecked=0, Total=45156 [2018-12-09 15:48:18,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2482 states. [2018-12-09 15:48:18,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2482 to 2474. [2018-12-09 15:48:18,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2018-12-09 15:48:18,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 2485 transitions. [2018-12-09 15:48:18,462 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 2485 transitions. Word has length 2302 [2018-12-09 15:48:18,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:48:18,464 INFO L480 AbstractCegarLoop]: Abstraction has 2474 states and 2485 transitions. [2018-12-09 15:48:18,464 INFO L481 AbstractCegarLoop]: Interpolant automaton has 111 states. [2018-12-09 15:48:18,464 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 2485 transitions. [2018-12-09 15:48:18,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2308 [2018-12-09 15:48:18,489 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:48:18,489 INFO L402 BasicCegarLoop]: trace histogram [403, 402, 402, 402, 402, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:48:18,489 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:48:18,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:48:18,490 INFO L82 PathProgramCache]: Analyzing trace with hash -706640056, now seen corresponding path program 57 times [2018-12-09 15:48:18,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:48:18,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:48:18,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:18,490 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:48:18,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:18,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:48:20,951 INFO L134 CoverageAnalysis]: Checked inductivity of 417940 backedges. 92269 proven. 8317 refuted. 0 times theorem prover too weak. 317354 trivial. 0 not checked. [2018-12-09 15:48:20,952 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:48:20,952 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:48:20,958 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:48:22,710 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-12-09 15:48:22,710 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:48:22,725 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:48:24,728 INFO L134 CoverageAnalysis]: Checked inductivity of 417940 backedges. 95265 proven. 5268 refuted. 0 times theorem prover too weak. 317407 trivial. 0 not checked. [2018-12-09 15:48:24,745 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:48:24,746 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 36] total 93 [2018-12-09 15:48:24,747 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-12-09 15:48:24,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-12-09 15:48:24,748 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1626, Invalid=6930, Unknown=0, NotChecked=0, Total=8556 [2018-12-09 15:48:24,748 INFO L87 Difference]: Start difference. First operand 2474 states and 2485 transitions. Second operand 93 states. [2018-12-09 15:48:31,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:48:31,637 INFO L93 Difference]: Finished difference Result 2633 states and 2648 transitions. [2018-12-09 15:48:31,637 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 118 states. [2018-12-09 15:48:31,637 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 2307 [2018-12-09 15:48:31,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:48:31,640 INFO L225 Difference]: With dead ends: 2633 [2018-12-09 15:48:31,640 INFO L226 Difference]: Without dead ends: 2633 [2018-12-09 15:48:31,642 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2476 GetRequests, 2277 SyntacticMatches, 0 SemanticMatches, 199 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12564 ImplicationChecksByTransitivity, 6.7s TimeCoverageRelationStatistics Valid=9174, Invalid=31026, Unknown=0, NotChecked=0, Total=40200 [2018-12-09 15:48:31,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2633 states. [2018-12-09 15:48:31,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2633 to 2626. [2018-12-09 15:48:31,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2626 states. [2018-12-09 15:48:31,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 2641 transitions. [2018-12-09 15:48:31,655 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 2641 transitions. Word has length 2307 [2018-12-09 15:48:31,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:48:31,656 INFO L480 AbstractCegarLoop]: Abstraction has 2626 states and 2641 transitions. [2018-12-09 15:48:31,656 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-12-09 15:48:31,656 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 2641 transitions. [2018-12-09 15:48:31,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2318 [2018-12-09 15:48:31,675 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:48:31,675 INFO L402 BasicCegarLoop]: trace histogram [405, 404, 404, 404, 404, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:48:31,675 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:48:31,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:48:31,676 INFO L82 PathProgramCache]: Analyzing trace with hash 1696940994, now seen corresponding path program 58 times [2018-12-09 15:48:31,676 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:48:31,676 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:48:31,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:31,676 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:48:31,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:31,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:48:33,498 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52508 proven. 2029 refuted. 0 times theorem prover too weak. 367484 trivial. 0 not checked. [2018-12-09 15:48:33,498 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:48:33,498 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:48:33,506 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:48:34,363 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:48:34,363 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:48:34,391 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:48:36,035 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52377 proven. 1809 refuted. 0 times theorem prover too weak. 367835 trivial. 0 not checked. [2018-12-09 15:48:36,057 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:48:36,058 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 29] total 61 [2018-12-09 15:48:36,059 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-09 15:48:36,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-09 15:48:36,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=502, Invalid=3280, Unknown=0, NotChecked=0, Total=3782 [2018-12-09 15:48:36,059 INFO L87 Difference]: Start difference. First operand 2626 states and 2641 transitions. Second operand 62 states. [2018-12-09 15:48:39,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:48:39,069 INFO L93 Difference]: Finished difference Result 3100 states and 3126 transitions. [2018-12-09 15:48:39,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2018-12-09 15:48:39,070 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 2317 [2018-12-09 15:48:39,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:48:39,073 INFO L225 Difference]: With dead ends: 3100 [2018-12-09 15:48:39,073 INFO L226 Difference]: Without dead ends: 3100 [2018-12-09 15:48:39,073 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2382 GetRequests, 2289 SyntacticMatches, 0 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1497 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=816, Invalid=8114, Unknown=0, NotChecked=0, Total=8930 [2018-12-09 15:48:39,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3100 states. [2018-12-09 15:48:39,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3100 to 3070. [2018-12-09 15:48:39,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3070 states. [2018-12-09 15:48:39,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3070 states to 3070 states and 3095 transitions. [2018-12-09 15:48:39,087 INFO L78 Accepts]: Start accepts. Automaton has 3070 states and 3095 transitions. Word has length 2317 [2018-12-09 15:48:39,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:48:39,088 INFO L480 AbstractCegarLoop]: Abstraction has 3070 states and 3095 transitions. [2018-12-09 15:48:39,088 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-09 15:48:39,088 INFO L276 IsEmpty]: Start isEmpty. Operand 3070 states and 3095 transitions. [2018-12-09 15:48:39,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2459 [2018-12-09 15:48:39,110 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:48:39,110 INFO L402 BasicCegarLoop]: trace histogram [431, 430, 430, 430, 430, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:48:39,110 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:48:39,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:48:39,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1469892906, now seen corresponding path program 59 times [2018-12-09 15:48:39,110 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:48:39,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:48:39,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:39,111 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:48:39,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:48:39,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:48:41,827 INFO L134 CoverageAnalysis]: Checked inductivity of 477614 backedges. 98189 proven. 11888 refuted. 0 times theorem prover too weak. 367537 trivial. 0 not checked. [2018-12-09 15:48:41,827 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:48:41,827 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:48:41,833 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:48:50,879 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 63 check-sat command(s) [2018-12-09 15:48:50,879 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:48:50,919 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:48:53,933 INFO L134 CoverageAnalysis]: Checked inductivity of 477614 backedges. 188324 proven. 8857 refuted. 0 times theorem prover too weak. 280433 trivial. 0 not checked. [2018-12-09 15:48:53,959 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:48:53,959 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 58] total 119 [2018-12-09 15:48:53,960 INFO L459 AbstractCegarLoop]: Interpolant automaton has 119 states [2018-12-09 15:48:53,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 119 interpolants. [2018-12-09 15:48:53,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1937, Invalid=12105, Unknown=0, NotChecked=0, Total=14042 [2018-12-09 15:48:53,960 INFO L87 Difference]: Start difference. First operand 3070 states and 3095 transitions. Second operand 119 states. [2018-12-09 15:49:07,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:49:07,770 INFO L93 Difference]: Finished difference Result 2795 states and 2808 transitions. [2018-12-09 15:49:07,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 143 states. [2018-12-09 15:49:07,770 INFO L78 Accepts]: Start accepts. Automaton has 119 states. Word has length 2458 [2018-12-09 15:49:07,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:49:07,773 INFO L225 Difference]: With dead ends: 2795 [2018-12-09 15:49:07,773 INFO L226 Difference]: Without dead ends: 2786 [2018-12-09 15:49:07,775 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2657 GetRequests, 2405 SyntacticMatches, 0 SemanticMatches, 252 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21655 ImplicationChecksByTransitivity, 9.1s TimeCoverageRelationStatistics Valid=9306, Invalid=54956, Unknown=0, NotChecked=0, Total=64262 [2018-12-09 15:49:07,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2786 states. [2018-12-09 15:49:07,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2786 to 2778. [2018-12-09 15:49:07,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2778 states. [2018-12-09 15:49:07,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2778 states to 2778 states and 2788 transitions. [2018-12-09 15:49:07,786 INFO L78 Accepts]: Start accepts. Automaton has 2778 states and 2788 transitions. Word has length 2458 [2018-12-09 15:49:07,787 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:49:07,787 INFO L480 AbstractCegarLoop]: Abstraction has 2778 states and 2788 transitions. [2018-12-09 15:49:07,787 INFO L481 AbstractCegarLoop]: Interpolant automaton has 119 states. [2018-12-09 15:49:07,787 INFO L276 IsEmpty]: Start isEmpty. Operand 2778 states and 2788 transitions. [2018-12-09 15:49:07,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2464 [2018-12-09 15:49:07,809 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:49:07,809 INFO L402 BasicCegarLoop]: trace histogram [432, 431, 431, 431, 431, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:49:07,809 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:49:07,810 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:49:07,810 INFO L82 PathProgramCache]: Analyzing trace with hash -1831952213, now seen corresponding path program 60 times [2018-12-09 15:49:07,810 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:49:07,810 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:49:07,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:49:07,810 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:49:07,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:49:07,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:49:10,543 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 103136 proven. 8974 refuted. 0 times theorem prover too weak. 367683 trivial. 0 not checked. [2018-12-09 15:49:10,543 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:49:10,544 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:49:10,551 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:49:34,649 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 52 check-sat command(s) [2018-12-09 15:49:34,649 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:49:34,684 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:49:36,768 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 58145 proven. 2188 refuted. 0 times theorem prover too weak. 419460 trivial. 0 not checked. [2018-12-09 15:49:36,790 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:49:36,790 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 34] total 94 [2018-12-09 15:49:36,791 INFO L459 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-12-09 15:49:36,791 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-12-09 15:49:36,791 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1328, Invalid=7414, Unknown=0, NotChecked=0, Total=8742 [2018-12-09 15:49:36,791 INFO L87 Difference]: Start difference. First operand 2778 states and 2788 transitions. Second operand 94 states. [2018-12-09 15:49:42,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:49:42,078 INFO L93 Difference]: Finished difference Result 3095 states and 3110 transitions. [2018-12-09 15:49:42,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 250 states. [2018-12-09 15:49:42,079 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2463 [2018-12-09 15:49:42,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:49:42,082 INFO L225 Difference]: With dead ends: 3095 [2018-12-09 15:49:42,082 INFO L226 Difference]: Without dead ends: 3095 [2018-12-09 15:49:42,085 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2716 GetRequests, 2434 SyntacticMatches, 0 SemanticMatches, 282 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27945 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=10795, Invalid=69577, Unknown=0, NotChecked=0, Total=80372 [2018-12-09 15:49:42,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3095 states. [2018-12-09 15:49:42,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3095 to 2791. [2018-12-09 15:49:42,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2791 states. [2018-12-09 15:49:42,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2791 states to 2791 states and 2802 transitions. [2018-12-09 15:49:42,097 INFO L78 Accepts]: Start accepts. Automaton has 2791 states and 2802 transitions. Word has length 2463 [2018-12-09 15:49:42,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:49:42,098 INFO L480 AbstractCegarLoop]: Abstraction has 2791 states and 2802 transitions. [2018-12-09 15:49:42,098 INFO L481 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-12-09 15:49:42,098 INFO L276 IsEmpty]: Start isEmpty. Operand 2791 states and 2802 transitions. [2018-12-09 15:49:42,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2615 [2018-12-09 15:49:42,121 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:49:42,122 INFO L402 BasicCegarLoop]: trace histogram [460, 459, 459, 459, 459, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:49:42,122 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:49:42,122 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:49:42,122 INFO L82 PathProgramCache]: Analyzing trace with hash 1196810675, now seen corresponding path program 61 times [2018-12-09 15:49:42,122 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:49:42,122 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:49:42,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:49:42,123 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:49:42,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:49:42,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:49:45,095 INFO L134 CoverageAnalysis]: Checked inductivity of 543595 backedges. 116042 proven. 5673 refuted. 0 times theorem prover too weak. 421880 trivial. 0 not checked. [2018-12-09 15:49:45,095 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:49:45,095 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:49:45,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:49:45,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:49:45,491 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:49:48,657 INFO L134 CoverageAnalysis]: Checked inductivity of 543595 backedges. 168382 proven. 1782 refuted. 0 times theorem prover too weak. 373431 trivial. 0 not checked. [2018-12-09 15:49:48,674 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:49:48,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 58] total 119 [2018-12-09 15:49:48,675 INFO L459 AbstractCegarLoop]: Interpolant automaton has 119 states [2018-12-09 15:49:48,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 119 interpolants. [2018-12-09 15:49:48,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2183, Invalid=11859, Unknown=0, NotChecked=0, Total=14042 [2018-12-09 15:49:48,676 INFO L87 Difference]: Start difference. First operand 2791 states and 2802 transitions. Second operand 119 states. [2018-12-09 15:49:52,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:49:52,649 INFO L93 Difference]: Finished difference Result 2657 states and 2659 transitions. [2018-12-09 15:49:52,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 144 states. [2018-12-09 15:49:52,649 INFO L78 Accepts]: Start accepts. Automaton has 119 states. Word has length 2614 [2018-12-09 15:49:52,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:49:52,653 INFO L225 Difference]: With dead ends: 2657 [2018-12-09 15:49:52,653 INFO L226 Difference]: Without dead ends: 2636 [2018-12-09 15:49:52,655 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2787 GetRequests, 2560 SyntacticMatches, 0 SemanticMatches, 227 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16846 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=7912, Invalid=44300, Unknown=0, NotChecked=0, Total=52212 [2018-12-09 15:49:52,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2636 states. [2018-12-09 15:49:52,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2636 to 2633. [2018-12-09 15:49:52,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2633 states. [2018-12-09 15:49:52,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2633 states to 2633 states and 2635 transitions. [2018-12-09 15:49:52,667 INFO L78 Accepts]: Start accepts. Automaton has 2633 states and 2635 transitions. Word has length 2614 [2018-12-09 15:49:52,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:49:52,668 INFO L480 AbstractCegarLoop]: Abstraction has 2633 states and 2635 transitions. [2018-12-09 15:49:52,668 INFO L481 AbstractCegarLoop]: Interpolant automaton has 119 states. [2018-12-09 15:49:52,668 INFO L276 IsEmpty]: Start isEmpty. Operand 2633 states and 2635 transitions. [2018-12-09 15:49:52,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2625 [2018-12-09 15:49:52,693 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:49:52,693 INFO L402 BasicCegarLoop]: trace histogram [462, 461, 461, 461, 461, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:49:52,693 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:49:52,693 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:49:52,694 INFO L82 PathProgramCache]: Analyzing trace with hash -1506860179, now seen corresponding path program 62 times [2018-12-09 15:49:52,694 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:49:52,694 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:49:52,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:49:52,694 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:49:52,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:49:52,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:49:55,615 INFO L134 CoverageAnalysis]: Checked inductivity of 548250 backedges. 122305 proven. 6828 refuted. 0 times theorem prover too weak. 419117 trivial. 0 not checked. [2018-12-09 15:49:55,615 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:49:55,615 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:49:55,621 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:49:56,013 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:49:56,013 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:49:56,033 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:49:58,417 INFO L134 CoverageAnalysis]: Checked inductivity of 548250 backedges. 122619 proven. 1918 refuted. 0 times theorem prover too weak. 423713 trivial. 0 not checked. [2018-12-09 15:49:58,435 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:49:58,435 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 60] total 93 [2018-12-09 15:49:58,436 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-12-09 15:49:58,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-12-09 15:49:58,436 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1837, Invalid=6719, Unknown=0, NotChecked=0, Total=8556 [2018-12-09 15:49:58,436 INFO L87 Difference]: Start difference. First operand 2633 states and 2635 transitions. Second operand 93 states. [2018-12-09 15:50:00,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:50:00,700 INFO L93 Difference]: Finished difference Result 2647 states and 2648 transitions. [2018-12-09 15:50:00,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-12-09 15:50:00,700 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 2624 [2018-12-09 15:50:00,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:50:00,704 INFO L225 Difference]: With dead ends: 2647 [2018-12-09 15:50:00,704 INFO L226 Difference]: Without dead ends: 2641 [2018-12-09 15:50:00,705 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2745 GetRequests, 2597 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7627 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4993, Invalid=17357, Unknown=0, NotChecked=0, Total=22350 [2018-12-09 15:50:00,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2641 states. [2018-12-09 15:50:00,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2641 to 2638. [2018-12-09 15:50:00,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2638 states. [2018-12-09 15:50:00,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2638 states to 2638 states and 2639 transitions. [2018-12-09 15:50:00,718 INFO L78 Accepts]: Start accepts. Automaton has 2638 states and 2639 transitions. Word has length 2624 [2018-12-09 15:50:00,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:50:00,719 INFO L480 AbstractCegarLoop]: Abstraction has 2638 states and 2639 transitions. [2018-12-09 15:50:00,719 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-12-09 15:50:00,719 INFO L276 IsEmpty]: Start isEmpty. Operand 2638 states and 2639 transitions. [2018-12-09 15:50:00,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2635 [2018-12-09 15:50:00,744 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:50:00,744 INFO L402 BasicCegarLoop]: trace histogram [464, 463, 463, 463, 463, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:50:00,744 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:50:00,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:50:00,745 INFO L82 PathProgramCache]: Analyzing trace with hash 2134165351, now seen corresponding path program 63 times [2018-12-09 15:50:00,745 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:50:00,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:50:00,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:50:00,745 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:50:00,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:50:00,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:50:03,037 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64779 proven. 2353 refuted. 0 times theorem prover too weak. 485793 trivial. 0 not checked. [2018-12-09 15:50:03,037 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:50:03,037 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:50:03,042 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:50:07,193 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-12-09 15:50:07,193 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:50:07,210 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:50:09,207 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64638 proven. 2088 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2018-12-09 15:50:09,226 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:50:09,226 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 32] total 65 [2018-12-09 15:50:09,226 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-12-09 15:50:09,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-12-09 15:50:09,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=945, Invalid=3345, Unknown=0, NotChecked=0, Total=4290 [2018-12-09 15:50:09,227 INFO L87 Difference]: Start difference. First operand 2638 states and 2639 transitions. Second operand 66 states. [2018-12-09 15:50:11,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:50:11,160 INFO L93 Difference]: Finished difference Result 2817 states and 2821 transitions. [2018-12-09 15:50:11,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2018-12-09 15:50:11,160 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 2634 [2018-12-09 15:50:11,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:50:11,162 INFO L225 Difference]: With dead ends: 2817 [2018-12-09 15:50:11,162 INFO L226 Difference]: Without dead ends: 2817 [2018-12-09 15:50:11,163 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2729 GetRequests, 2604 SyntacticMatches, 0 SemanticMatches, 125 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2961 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3428, Invalid=12574, Unknown=0, NotChecked=0, Total=16002 [2018-12-09 15:50:11,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2817 states. [2018-12-09 15:50:11,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2817 to 2799. [2018-12-09 15:50:11,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2799 states. [2018-12-09 15:50:11,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2799 states to 2799 states and 2802 transitions. [2018-12-09 15:50:11,174 INFO L78 Accepts]: Start accepts. Automaton has 2799 states and 2802 transitions. Word has length 2634 [2018-12-09 15:50:11,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:50:11,174 INFO L480 AbstractCegarLoop]: Abstraction has 2799 states and 2802 transitions. [2018-12-09 15:50:11,175 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-12-09 15:50:11,175 INFO L276 IsEmpty]: Start isEmpty. Operand 2799 states and 2802 transitions. [2018-12-09 15:50:11,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2796 [2018-12-09 15:50:11,201 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:50:11,202 INFO L402 BasicCegarLoop]: trace histogram [494, 493, 493, 493, 493, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:50:11,202 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:50:11,202 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:50:11,202 INFO L82 PathProgramCache]: Analyzing trace with hash 945686987, now seen corresponding path program 64 times [2018-12-09 15:50:11,202 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:50:11,202 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:50:11,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:50:11,203 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:50:11,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:50:11,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:50:14,589 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 133528 proven. 6528 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2018-12-09 15:50:14,589 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:50:14,589 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:50:14,595 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 15:50:14,945 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 15:50:14,945 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:50:14,964 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:50:18,781 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 137762 proven. 7304 refuted. 0 times theorem prover too weak. 481189 trivial. 0 not checked. [2018-12-09 15:50:18,798 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:50:18,799 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 65] total 130 [2018-12-09 15:50:18,799 INFO L459 AbstractCegarLoop]: Interpolant automaton has 130 states [2018-12-09 15:50:18,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 130 interpolants. [2018-12-09 15:50:18,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2495, Invalid=14275, Unknown=0, NotChecked=0, Total=16770 [2018-12-09 15:50:18,800 INFO L87 Difference]: Start difference. First operand 2799 states and 2802 transitions. Second operand 130 states. [2018-12-09 15:50:25,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:50:25,789 INFO L93 Difference]: Finished difference Result 2817 states and 2818 transitions. [2018-12-09 15:50:25,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 156 states. [2018-12-09 15:50:25,789 INFO L78 Accepts]: Start accepts. Automaton has 130 states. Word has length 2795 [2018-12-09 15:50:25,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:50:25,793 INFO L225 Difference]: With dead ends: 2817 [2018-12-09 15:50:25,793 INFO L226 Difference]: Without dead ends: 2811 [2018-12-09 15:50:25,796 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3015 GetRequests, 2735 SyntacticMatches, 0 SemanticMatches, 280 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27115 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=11883, Invalid=67359, Unknown=0, NotChecked=0, Total=79242 [2018-12-09 15:50:25,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2811 states. [2018-12-09 15:50:25,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2811 to 2804. [2018-12-09 15:50:25,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2804 states. [2018-12-09 15:50:25,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2804 states to 2804 states and 2805 transitions. [2018-12-09 15:50:25,807 INFO L78 Accepts]: Start accepts. Automaton has 2804 states and 2805 transitions. Word has length 2795 [2018-12-09 15:50:25,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:50:25,808 INFO L480 AbstractCegarLoop]: Abstraction has 2804 states and 2805 transitions. [2018-12-09 15:50:25,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 130 states. [2018-12-09 15:50:25,808 INFO L276 IsEmpty]: Start isEmpty. Operand 2804 states and 2805 transitions. [2018-12-09 15:50:25,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2801 [2018-12-09 15:50:25,835 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:50:25,836 INFO L402 BasicCegarLoop]: trace histogram [495, 494, 494, 494, 494, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:50:25,836 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:50:25,836 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:50:25,836 INFO L82 PathProgramCache]: Analyzing trace with hash 601825130, now seen corresponding path program 65 times [2018-12-09 15:50:25,836 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:50:25,836 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:50:25,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:50:25,837 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:50:25,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:50:26,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:50:28,409 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71715 proven. 2524 refuted. 0 times theorem prover too weak. 554512 trivial. 0 not checked. [2018-12-09 15:50:28,409 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:50:28,409 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:50:28,415 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-12-09 15:50:41,287 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 78 check-sat command(s) [2018-12-09 15:50:41,288 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:50:41,332 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:50:43,849 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71427 proven. 2235 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2018-12-09 15:50:43,878 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:50:43,879 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 33] total 69 [2018-12-09 15:50:43,879 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-12-09 15:50:43,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-12-09 15:50:43,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=608, Invalid=4222, Unknown=0, NotChecked=0, Total=4830 [2018-12-09 15:50:43,880 INFO L87 Difference]: Start difference. First operand 2804 states and 2805 transitions. Second operand 70 states. [2018-12-09 15:50:47,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:50:47,425 INFO L93 Difference]: Finished difference Result 2992 states and 2996 transitions. [2018-12-09 15:50:47,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-12-09 15:50:47,425 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 2800 [2018-12-09 15:50:47,426 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:50:47,428 INFO L225 Difference]: With dead ends: 2992 [2018-12-09 15:50:47,428 INFO L226 Difference]: Without dead ends: 2992 [2018-12-09 15:50:47,429 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2870 GetRequests, 2768 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1912 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=966, Invalid=9746, Unknown=0, NotChecked=0, Total=10712 [2018-12-09 15:50:47,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2992 states. [2018-12-09 15:50:47,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2992 to 2970. [2018-12-09 15:50:47,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2970 states. [2018-12-09 15:50:47,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2970 states to 2970 states and 2973 transitions. [2018-12-09 15:50:47,443 INFO L78 Accepts]: Start accepts. Automaton has 2970 states and 2973 transitions. Word has length 2800 [2018-12-09 15:50:47,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:50:47,444 INFO L480 AbstractCegarLoop]: Abstraction has 2970 states and 2973 transitions. [2018-12-09 15:50:47,444 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-12-09 15:50:47,444 INFO L276 IsEmpty]: Start isEmpty. Operand 2970 states and 2973 transitions. [2018-12-09 15:50:47,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2967 [2018-12-09 15:50:47,474 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:50:47,474 INFO L402 BasicCegarLoop]: trace histogram [526, 525, 525, 525, 525, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:50:47,474 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:50:47,474 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:50:47,474 INFO L82 PathProgramCache]: Analyzing trace with hash -643366969, now seen corresponding path program 66 times [2018-12-09 15:50:47,475 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:50:47,475 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:50:47,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:50:47,475 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:50:47,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:50:47,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:50:51,167 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 147388 proven. 6978 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2018-12-09 15:50:51,167 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:50:51,167 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:50:51,173 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-12-09 15:51:24,817 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 63 check-sat command(s) [2018-12-09 15:51:24,817 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:51:24,866 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:51:27,682 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 78518 proven. 2387 refuted. 0 times theorem prover too weak. 628550 trivial. 0 not checked. [2018-12-09 15:51:27,707 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:51:27,708 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 34] total 103 [2018-12-09 15:51:27,708 INFO L459 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-12-09 15:51:27,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-12-09 15:51:27,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1664, Invalid=8842, Unknown=0, NotChecked=0, Total=10506 [2018-12-09 15:51:27,709 INFO L87 Difference]: Start difference. First operand 2970 states and 2973 transitions. Second operand 103 states. [2018-12-09 15:51:33,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:51:33,523 INFO L93 Difference]: Finished difference Result 3162 states and 3168 transitions. [2018-12-09 15:51:33,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 104 states. [2018-12-09 15:51:33,524 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 2966 [2018-12-09 15:51:33,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:51:33,526 INFO L225 Difference]: With dead ends: 3162 [2018-12-09 15:51:33,527 INFO L226 Difference]: Without dead ends: 3162 [2018-12-09 15:51:33,528 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3130 GetRequests, 2934 SyntacticMatches, 0 SemanticMatches, 196 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9641 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=8970, Invalid=30036, Unknown=0, NotChecked=0, Total=39006 [2018-12-09 15:51:33,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3162 states. [2018-12-09 15:51:33,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3162 to 3152. [2018-12-09 15:51:33,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3152 states. [2018-12-09 15:51:33,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3152 states to 3152 states and 3158 transitions. [2018-12-09 15:51:33,540 INFO L78 Accepts]: Start accepts. Automaton has 3152 states and 3158 transitions. Word has length 2966 [2018-12-09 15:51:33,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:51:33,541 INFO L480 AbstractCegarLoop]: Abstraction has 3152 states and 3158 transitions. [2018-12-09 15:51:33,541 INFO L481 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-12-09 15:51:33,541 INFO L276 IsEmpty]: Start isEmpty. Operand 3152 states and 3158 transitions. [2018-12-09 15:51:33,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2977 [2018-12-09 15:51:33,571 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:51:33,571 INFO L402 BasicCegarLoop]: trace histogram [528, 527, 527, 527, 527, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:51:33,572 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:51:33,572 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:51:33,572 INFO L82 PathProgramCache]: Analyzing trace with hash -310569395, now seen corresponding path program 67 times [2018-12-09 15:51:33,572 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:51:33,572 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:51:33,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:51:33,573 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:51:33,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:51:33,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:51:37,051 INFO L134 CoverageAnalysis]: Checked inductivity of 714774 backedges. 83691 proven. 2733 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2018-12-09 15:51:37,051 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:51:37,052 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:51:37,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:51:37,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:51:37,518 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:51:40,829 INFO L134 CoverageAnalysis]: Checked inductivity of 714774 backedges. 83754 proven. 2670 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2018-12-09 15:51:40,847 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:51:40,848 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 67] total 102 [2018-12-09 15:51:40,848 INFO L459 AbstractCegarLoop]: Interpolant automaton has 102 states [2018-12-09 15:51:40,849 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2018-12-09 15:51:40,849 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2347, Invalid=7955, Unknown=0, NotChecked=0, Total=10302 [2018-12-09 15:51:40,849 INFO L87 Difference]: Start difference. First operand 3152 states and 3158 transitions. Second operand 102 states. [2018-12-09 15:51:43,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:51:43,071 INFO L93 Difference]: Finished difference Result 3503 states and 3513 transitions. [2018-12-09 15:51:43,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-12-09 15:51:43,071 INFO L78 Accepts]: Start accepts. Automaton has 102 states. Word has length 2976 [2018-12-09 15:51:43,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:51:43,075 INFO L225 Difference]: With dead ends: 3503 [2018-12-09 15:51:43,075 INFO L226 Difference]: Without dead ends: 3503 [2018-12-09 15:51:43,076 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3106 GetRequests, 2943 SyntacticMatches, 0 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4649 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=6754, Invalid=20306, Unknown=0, NotChecked=0, Total=27060 [2018-12-09 15:51:43,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3503 states. [2018-12-09 15:51:43,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3503 to 3492. [2018-12-09 15:51:43,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3492 states. [2018-12-09 15:51:43,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3492 states to 3492 states and 3502 transitions. [2018-12-09 15:51:43,090 INFO L78 Accepts]: Start accepts. Automaton has 3492 states and 3502 transitions. Word has length 2976 [2018-12-09 15:51:43,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:51:43,091 INFO L480 AbstractCegarLoop]: Abstraction has 3492 states and 3502 transitions. [2018-12-09 15:51:43,091 INFO L481 AbstractCegarLoop]: Interpolant automaton has 102 states. [2018-12-09 15:51:43,091 INFO L276 IsEmpty]: Start isEmpty. Operand 3492 states and 3502 transitions. [2018-12-09 15:51:43,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3138 [2018-12-09 15:51:43,125 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:51:43,125 INFO L402 BasicCegarLoop]: trace histogram [558, 557, 557, 557, 557, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:51:43,125 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:51:43,125 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:51:43,125 INFO L82 PathProgramCache]: Analyzing trace with hash -182742773, now seen corresponding path program 68 times [2018-12-09 15:51:43,125 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:51:43,125 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:51:43,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:51:43,126 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 15:51:43,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:51:43,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:51:47,181 INFO L134 CoverageAnalysis]: Checked inductivity of 797850 backedges. 155124 proven. 11852 refuted. 0 times theorem prover too weak. 630874 trivial. 0 not checked. [2018-12-09 15:51:47,181 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:51:47,181 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:51:47,187 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 15:51:47,670 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 15:51:47,670 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:51:47,695 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:51:52,444 INFO L134 CoverageAnalysis]: Checked inductivity of 797850 backedges. 233088 proven. 2205 refuted. 0 times theorem prover too weak. 562557 trivial. 0 not checked. [2018-12-09 15:51:52,462 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:51:52,463 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 64] total 133 [2018-12-09 15:51:52,464 INFO L459 AbstractCegarLoop]: Interpolant automaton has 133 states [2018-12-09 15:51:52,465 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 133 interpolants. [2018-12-09 15:51:52,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2686, Invalid=14870, Unknown=0, NotChecked=0, Total=17556 [2018-12-09 15:51:52,465 INFO L87 Difference]: Start difference. First operand 3492 states and 3502 transitions. Second operand 133 states. [2018-12-09 15:52:03,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:52:03,383 INFO L93 Difference]: Finished difference Result 3164 states and 3167 transitions. [2018-12-09 15:52:03,383 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2018-12-09 15:52:03,383 INFO L78 Accepts]: Start accepts. Automaton has 133 states. Word has length 3137 [2018-12-09 15:52:03,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:52:03,386 INFO L225 Difference]: With dead ends: 3164 [2018-12-09 15:52:03,386 INFO L226 Difference]: Without dead ends: 3155 [2018-12-09 15:52:03,389 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3332 GetRequests, 3077 SyntacticMatches, 0 SemanticMatches, 255 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21374 ImplicationChecksByTransitivity, 8.4s TimeCoverageRelationStatistics Valid=9872, Invalid=55920, Unknown=0, NotChecked=0, Total=65792 [2018-12-09 15:52:03,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3155 states. [2018-12-09 15:52:03,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3155 to 3151. [2018-12-09 15:52:03,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3151 states. [2018-12-09 15:52:03,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3151 states to 3151 states and 3154 transitions. [2018-12-09 15:52:03,401 INFO L78 Accepts]: Start accepts. Automaton has 3151 states and 3154 transitions. Word has length 3137 [2018-12-09 15:52:03,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:52:03,401 INFO L480 AbstractCegarLoop]: Abstraction has 3151 states and 3154 transitions. [2018-12-09 15:52:03,402 INFO L481 AbstractCegarLoop]: Interpolant automaton has 133 states. [2018-12-09 15:52:03,402 INFO L276 IsEmpty]: Start isEmpty. Operand 3151 states and 3154 transitions. [2018-12-09 15:52:03,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3143 [2018-12-09 15:52:03,435 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:52:03,435 INFO L402 BasicCegarLoop]: trace histogram [559, 558, 558, 558, 558, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:52:03,435 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:52:03,435 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:52:03,435 INFO L82 PathProgramCache]: Analyzing trace with hash -1867759088, now seen corresponding path program 69 times [2018-12-09 15:52:03,435 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:52:03,435 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:52:03,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:52:03,436 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:52:03,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:52:03,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 15:52:07,532 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 162175 proven. 7443 refuted. 0 times theorem prover too weak. 631050 trivial. 0 not checked. [2018-12-09 15:52:07,533 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 15:52:07,533 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 15:52:07,540 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 15:52:11,852 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-12-09 15:52:11,852 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 15:52:11,874 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 15:52:15,134 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 159788 proven. 7443 refuted. 0 times theorem prover too weak. 633437 trivial. 0 not checked. [2018-12-09 15:52:15,153 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-09 15:52:15,154 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 41] total 107 [2018-12-09 15:52:15,154 INFO L459 AbstractCegarLoop]: Interpolant automaton has 107 states [2018-12-09 15:52:15,155 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2018-12-09 15:52:15,155 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2298, Invalid=9044, Unknown=0, NotChecked=0, Total=11342 [2018-12-09 15:52:15,155 INFO L87 Difference]: Start difference. First operand 3151 states and 3154 transitions. Second operand 107 states. [2018-12-09 15:52:18,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 15:52:18,754 INFO L93 Difference]: Finished difference Result 3335 states and 3340 transitions. [2018-12-09 15:52:18,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 105 states. [2018-12-09 15:52:18,754 INFO L78 Accepts]: Start accepts. Automaton has 107 states. Word has length 3142 [2018-12-09 15:52:18,755 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 15:52:18,757 INFO L225 Difference]: With dead ends: 3335 [2018-12-09 15:52:18,757 INFO L226 Difference]: Without dead ends: 3335 [2018-12-09 15:52:18,759 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3310 GetRequests, 3108 SyntacticMatches, 0 SemanticMatches, 202 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12921 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=10028, Invalid=31384, Unknown=0, NotChecked=0, Total=41412 [2018-12-09 15:52:18,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3335 states. [2018-12-09 15:52:18,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3335 to 3328. [2018-12-09 15:52:18,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3328 states. [2018-12-09 15:52:18,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3328 states to 3328 states and 3333 transitions. [2018-12-09 15:52:18,773 INFO L78 Accepts]: Start accepts. Automaton has 3328 states and 3333 transitions. Word has length 3142 [2018-12-09 15:52:18,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 15:52:18,774 INFO L480 AbstractCegarLoop]: Abstraction has 3328 states and 3333 transitions. [2018-12-09 15:52:18,774 INFO L481 AbstractCegarLoop]: Interpolant automaton has 107 states. [2018-12-09 15:52:18,774 INFO L276 IsEmpty]: Start isEmpty. Operand 3328 states and 3333 transitions. [2018-12-09 15:52:18,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3148 [2018-12-09 15:52:18,814 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 15:52:18,814 INFO L402 BasicCegarLoop]: trace histogram [560, 559, 559, 559, 559, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 15:52:18,814 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr3REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-12-09 15:52:18,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 15:52:18,814 INFO L82 PathProgramCache]: Analyzing trace with hash -486718779, now seen corresponding path program 70 times [2018-12-09 15:52:18,814 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 15:52:18,815 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 15:52:18,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:52:18,815 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 15:52:18,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 15:52:19,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 15:52:20,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 15:52:20,869 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 15:52:21,150 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 03:52:21 BoogieIcfgContainer [2018-12-09 15:52:21,151 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 15:52:21,151 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 15:52:21,151 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 15:52:21,151 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 15:52:21,151 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 03:44:04" (3/4) ... [2018-12-09 15:52:21,153 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-09 15:52:21,349 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_9ae37d4f-c833-4f0a-8d37-b3582f124eab/bin-2019/uautomizer/witness.graphml [2018-12-09 15:52:21,350 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 15:52:21,350 INFO L168 Benchmark]: Toolchain (without parser) took 496726.00 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 956.0 MB in the beginning and 4.3 GB in the end (delta: -3.3 GB). Peak memory consumption was 641.8 MB. Max. memory is 11.5 GB. [2018-12-09 15:52:21,351 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 15:52:21,351 INFO L168 Benchmark]: CACSL2BoogieTranslator took 122.12 ms. Allocated memory is still 1.0 GB. Free memory was 956.0 MB in the beginning and 945.3 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-12-09 15:52:21,351 INFO L168 Benchmark]: Boogie Preprocessor took 50.90 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 85.5 MB). Free memory was 945.3 MB in the beginning and 1.1 GB in the end (delta: -135.6 MB). Peak memory consumption was 12.8 MB. Max. memory is 11.5 GB. [2018-12-09 15:52:21,351 INFO L168 Benchmark]: RCFGBuilder took 160.47 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 14.3 MB). Peak memory consumption was 14.3 MB. Max. memory is 11.5 GB. [2018-12-09 15:52:21,351 INFO L168 Benchmark]: TraceAbstraction took 496191.08 ms. Allocated memory was 1.1 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 4.4 GB in the end (delta: -3.3 GB). Peak memory consumption was 4.4 GB. Max. memory is 11.5 GB. [2018-12-09 15:52:21,352 INFO L168 Benchmark]: Witness Printer took 198.80 ms. Allocated memory is still 5.0 GB. Free memory was 4.4 GB in the beginning and 4.3 GB in the end (delta: 82.5 MB). Peak memory consumption was 82.5 MB. Max. memory is 11.5 GB. [2018-12-09 15:52:21,353 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 122.12 ms. Allocated memory is still 1.0 GB. Free memory was 956.0 MB in the beginning and 945.3 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 50.90 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 85.5 MB). Free memory was 945.3 MB in the beginning and 1.1 GB in the end (delta: -135.6 MB). Peak memory consumption was 12.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 160.47 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 14.3 MB). Peak memory consumption was 14.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 496191.08 ms. Allocated memory was 1.1 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 4.4 GB in the end (delta: -3.3 GB). Peak memory consumption was 4.4 GB. Max. memory is 11.5 GB. * Witness Printer took 198.80 ms. Allocated memory is still 5.0 GB. Free memory was 4.4 GB in the beginning and 4.3 GB in the end (delta: 82.5 MB). Peak memory consumption was 82.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] char mask[32]; [L26] i = 0 VAL [b={157:0}, i=0, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=0, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=0, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=148, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={140:0}, b={140:0}, i=1, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={140:0}, b={140:0}, b[i]=162, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={140:0}, b={140:0}, i=2, size=1] [L20] return i; VAL [\old(size)=1, \result=2, b={140:0}, b={140:0}, i=2, size=1] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=2, i=0, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=2, i=0, mask={140:0}] [L26] i++ VAL [b={157:0}, i=1, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=1, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=0, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=148, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=1, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=162, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={140:0}, b={140:0}, i=2, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={140:0}, b={140:0}, b[i]=143, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={140:0}, b={140:0}, i=3, size=2] [L20] return i; VAL [\old(size)=2, \result=3, b={140:0}, b={140:0}, i=3, size=2] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=3, i=1, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=3, i=1, mask={140:0}] [L26] i++ VAL [b={157:0}, i=2, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=2, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=0, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=148, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=1, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=162, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=2, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=143, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={140:0}, b={140:0}, i=3, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={140:0}, b={140:0}, b[i]=131, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={140:0}, b={140:0}, i=4, size=3] [L20] return i; VAL [\old(size)=3, \result=4, b={140:0}, b={140:0}, i=4, size=3] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=4, i=2, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=4, i=2, mask={140:0}] [L26] i++ VAL [b={157:0}, i=3, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=3, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=0, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=148, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=1, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=162, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=2, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=143, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=3, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=131, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={140:0}, b={140:0}, i=4, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={140:0}, b={140:0}, b[i]=130, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={140:0}, b={140:0}, i=5, size=4] [L20] return i; VAL [\old(size)=4, \result=5, b={140:0}, b={140:0}, i=5, size=4] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=5, i=3, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=5, i=3, mask={140:0}] [L26] i++ VAL [b={157:0}, i=4, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=4, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=0, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=148, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=1, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=162, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=2, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=143, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=3, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=131, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=4, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=130, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={140:0}, b={140:0}, i=5, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={140:0}, b={140:0}, b[i]=139, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={140:0}, b={140:0}, i=6, size=5] [L20] return i; VAL [\old(size)=5, \result=6, b={140:0}, b={140:0}, i=6, size=5] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=6, i=4, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=6, i=4, mask={140:0}] [L26] i++ VAL [b={157:0}, i=5, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=5, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=0, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=148, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=1, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=162, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=2, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=143, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=3, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=131, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=4, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=130, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=5, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=139, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={140:0}, b={140:0}, i=6, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={140:0}, b={140:0}, b[i]=129, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={140:0}, b={140:0}, i=7, size=6] [L20] return i; VAL [\old(size)=6, \result=7, b={140:0}, b={140:0}, i=7, size=6] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=7, i=5, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=7, i=5, mask={140:0}] [L26] i++ VAL [b={157:0}, i=6, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=6, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=0, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=148, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=1, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=162, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=2, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=143, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=3, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=131, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=4, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=130, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=5, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=139, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=6, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=129, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={140:0}, b={140:0}, i=7, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={140:0}, b={140:0}, b[i]=149, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={140:0}, b={140:0}, i=8, size=7] [L20] return i; VAL [\old(size)=7, \result=8, b={140:0}, b={140:0}, i=8, size=7] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=8, i=6, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=8, i=6, mask={140:0}] [L26] i++ VAL [b={157:0}, i=7, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=7, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=0, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=148, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=1, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=162, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=2, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=143, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=3, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=131, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=4, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=130, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=5, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=139, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=6, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=129, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=7, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=149, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={140:0}, b={140:0}, i=8, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={140:0}, b={140:0}, b[i]=155, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={140:0}, b={140:0}, i=9, size=8] [L20] return i; VAL [\old(size)=8, \result=9, b={140:0}, b={140:0}, i=9, size=8] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=9, i=7, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=9, i=7, mask={140:0}] [L26] i++ VAL [b={157:0}, i=8, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=8, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=0, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=148, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=1, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=162, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=2, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=143, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=3, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=131, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=4, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=130, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=5, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=139, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=6, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=129, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=7, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=149, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=8, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=155, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={140:0}, b={140:0}, i=9, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={140:0}, b={140:0}, b[i]=135, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={140:0}, b={140:0}, i=10, size=9] [L20] return i; VAL [\old(size)=9, \result=10, b={140:0}, b={140:0}, i=10, size=9] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=10, i=8, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=10, i=8, mask={140:0}] [L26] i++ VAL [b={157:0}, i=9, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=9, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=0, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=148, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=1, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=162, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=2, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=143, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=3, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=131, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=4, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=130, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=5, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=139, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=6, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=129, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=7, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=149, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=8, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=155, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=9, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=135, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={140:0}, b={140:0}, i=10, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={140:0}, b={140:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={140:0}, b={140:0}, i=11, size=10] [L20] return i; VAL [\old(size)=10, \result=11, b={140:0}, b={140:0}, i=11, size=10] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=11, i=9, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=11, i=9, mask={140:0}] [L26] i++ VAL [b={157:0}, i=10, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=10, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=0, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=148, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=1, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=162, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=2, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=143, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=3, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=131, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=4, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=130, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=5, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=139, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=6, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=129, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=7, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=149, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=8, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=155, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=9, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=135, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=10, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={140:0}, b={140:0}, i=11, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={140:0}, b={140:0}, b[i]=146, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={140:0}, b={140:0}, i=12, size=11] [L20] return i; VAL [\old(size)=11, \result=12, b={140:0}, b={140:0}, i=12, size=11] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=12, i=10, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=12, i=10, mask={140:0}] [L26] i++ VAL [b={157:0}, i=11, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=11, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=0, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=148, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=1, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=162, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=2, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=143, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=3, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=131, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=4, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=130, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=5, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=139, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=6, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=129, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=7, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=149, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=8, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=155, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=9, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=135, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=10, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=11, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=146, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={140:0}, b={140:0}, i=12, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={140:0}, b={140:0}, b[i]=151, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={140:0}, b={140:0}, i=13, size=12] [L20] return i; VAL [\old(size)=12, \result=13, b={140:0}, b={140:0}, i=13, size=12] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=13, i=11, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=13, i=11, mask={140:0}] [L26] i++ VAL [b={157:0}, i=12, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=12, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=0, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=148, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=1, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=162, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=2, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=143, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=3, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=131, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=4, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=130, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=5, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=139, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=6, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=129, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=7, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=149, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=8, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=155, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=9, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=135, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=10, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=11, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=146, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=12, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=151, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={140:0}, b={140:0}, i=13, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={140:0}, b={140:0}, b[i]=158, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={140:0}, b={140:0}, i=14, size=13] [L20] return i; VAL [\old(size)=13, \result=14, b={140:0}, b={140:0}, i=14, size=13] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=14, i=12, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=14, i=12, mask={140:0}] [L26] i++ VAL [b={157:0}, i=13, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=13, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=0, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=148, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=1, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=162, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=2, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=143, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=3, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=131, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=4, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=130, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=5, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=139, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=6, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=129, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=7, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=149, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=8, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=155, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=9, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=135, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=10, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=11, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=146, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=12, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=151, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=13, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=158, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={140:0}, b={140:0}, i=14, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={140:0}, b={140:0}, b[i]=154, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={140:0}, b={140:0}, i=15, size=14] [L20] return i; VAL [\old(size)=14, \result=15, b={140:0}, b={140:0}, i=15, size=14] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=15, i=13, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=15, i=13, mask={140:0}] [L26] i++ VAL [b={157:0}, i=14, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=14, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=0, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=148, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=1, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=162, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=2, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=143, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=3, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=131, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=4, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=130, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=5, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=139, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=6, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=129, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=7, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=149, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=8, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=155, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=9, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=135, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=10, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=11, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=146, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=12, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=151, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=13, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=158, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=14, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=154, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={140:0}, b={140:0}, i=15, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={140:0}, b={140:0}, b[i]=136, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={140:0}, b={140:0}, i=16, size=15] [L20] return i; VAL [\old(size)=15, \result=16, b={140:0}, b={140:0}, i=16, size=15] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=16, i=14, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=16, i=14, mask={140:0}] [L26] i++ VAL [b={157:0}, i=15, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=15, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=0, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=148, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=1, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=162, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=2, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=143, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=3, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=131, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=4, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=130, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=5, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=139, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=6, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=129, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=7, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=149, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=8, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=155, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=9, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=135, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=10, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=11, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=146, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=12, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=151, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=13, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=158, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=14, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=154, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=15, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=136, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={140:0}, b={140:0}, i=16, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={140:0}, b={140:0}, b[i]=138, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={140:0}, b={140:0}, i=17, size=16] [L20] return i; VAL [\old(size)=16, \result=17, b={140:0}, b={140:0}, i=17, size=16] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=17, i=15, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=17, i=15, mask={140:0}] [L26] i++ VAL [b={157:0}, i=16, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=16, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=0, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=148, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=1, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=162, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=2, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=143, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=3, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=131, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=4, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=130, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=5, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=139, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=6, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=129, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=7, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=149, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=8, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=155, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=9, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=135, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=10, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=11, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=146, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=12, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=151, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=13, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=158, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=14, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=154, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=15, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=136, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=16, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=138, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={140:0}, b={140:0}, i=17, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={140:0}, b={140:0}, b[i]=152, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={140:0}, b={140:0}, i=18, size=17] [L20] return i; VAL [\old(size)=17, \result=18, b={140:0}, b={140:0}, i=18, size=17] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=18, i=16, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=18, i=16, mask={140:0}] [L26] i++ VAL [b={157:0}, i=17, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=17, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=0, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=148, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=1, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=162, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=2, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=143, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=3, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=131, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=4, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=130, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=5, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=139, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=6, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=129, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=7, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=149, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=8, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=155, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=9, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=135, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=10, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=11, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=146, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=12, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=151, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=13, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=158, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=14, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=154, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=15, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=136, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=16, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=138, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=17, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=152, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={140:0}, b={140:0}, i=18, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={140:0}, b={140:0}, b[i]=141, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={140:0}, b={140:0}, i=19, size=18] [L20] return i; VAL [\old(size)=18, \result=19, b={140:0}, b={140:0}, i=19, size=18] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=19, i=17, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=19, i=17, mask={140:0}] [L26] i++ VAL [b={157:0}, i=18, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=18, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=0, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=148, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=1, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=162, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=2, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=143, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=3, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=131, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=4, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=130, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=5, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=139, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=6, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=129, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=7, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=149, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=8, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=155, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=9, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=135, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=10, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=11, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=146, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=12, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=151, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=13, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=158, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=14, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=154, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=15, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=136, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=16, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=138, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=17, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=152, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=18, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=141, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={140:0}, b={140:0}, i=19, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={140:0}, b={140:0}, b[i]=132, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={140:0}, b={140:0}, i=20, size=19] [L20] return i; VAL [\old(size)=19, \result=20, b={140:0}, b={140:0}, i=20, size=19] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=20, i=18, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=20, i=18, mask={140:0}] [L26] i++ VAL [b={157:0}, i=19, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=19, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=0, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=148, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=1, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=162, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=2, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=143, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=3, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=131, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=4, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=130, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=5, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=139, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=6, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=129, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=7, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=149, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=8, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=155, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=9, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=135, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=10, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=11, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=146, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=12, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=151, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=13, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=158, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=14, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=154, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=15, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=136, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=16, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=138, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=17, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=152, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=18, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=141, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=19, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=132, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={140:0}, b={140:0}, i=20, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={140:0}, b={140:0}, b[i]=133, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={140:0}, b={140:0}, i=21, size=20] [L20] return i; VAL [\old(size)=20, \result=21, b={140:0}, b={140:0}, i=21, size=20] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=21, i=19, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=21, i=19, mask={140:0}] [L26] i++ VAL [b={157:0}, i=20, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=20, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=0, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=148, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=1, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=162, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=2, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=143, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=3, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=131, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=4, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=130, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=5, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=139, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=6, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=129, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=7, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=149, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=8, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=155, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=9, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=135, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=10, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=11, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=146, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=12, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=151, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=13, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=158, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=14, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=154, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=15, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=136, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=16, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=138, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=17, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=152, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=18, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=141, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=19, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=132, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=20, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=133, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={140:0}, b={140:0}, i=21, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={140:0}, b={140:0}, b[i]=137, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={140:0}, b={140:0}, i=22, size=21] [L20] return i; VAL [\old(size)=21, \result=22, b={140:0}, b={140:0}, i=22, size=21] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=22, i=20, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=22, i=20, mask={140:0}] [L26] i++ VAL [b={157:0}, i=21, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=21, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=0, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=148, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=1, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=162, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=2, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=143, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=3, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=131, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=4, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=130, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=5, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=139, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=6, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=129, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=7, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=149, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=8, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=155, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=9, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=135, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=10, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=11, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=146, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=12, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=151, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=13, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=158, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=14, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=154, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=15, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=136, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=16, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=138, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=17, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=152, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=18, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=141, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=19, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=132, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=20, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=133, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=21, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=137, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={140:0}, b={140:0}, i=22, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={140:0}, b={140:0}, b[i]=159, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={140:0}, b={140:0}, i=23, size=22] [L20] return i; VAL [\old(size)=22, \result=23, b={140:0}, b={140:0}, i=23, size=22] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=23, i=21, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=23, i=21, mask={140:0}] [L26] i++ VAL [b={157:0}, i=22, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=22, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=0, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=148, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=1, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=162, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=2, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=143, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=3, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=131, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=4, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=130, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=5, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=139, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=6, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=129, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=7, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=149, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=8, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=155, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=9, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=135, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=10, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=11, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=146, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=12, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=151, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=13, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=158, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=14, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=154, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=15, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=136, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=16, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=138, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=17, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=152, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=18, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=141, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=19, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=132, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=20, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=133, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=21, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=137, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=22, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=159, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={140:0}, b={140:0}, i=23, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={140:0}, b={140:0}, b[i]=163, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={140:0}, b={140:0}, i=24, size=23] [L20] return i; VAL [\old(size)=23, \result=24, b={140:0}, b={140:0}, i=24, size=23] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=24, i=22, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=24, i=22, mask={140:0}] [L26] i++ VAL [b={157:0}, i=23, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=23, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=0, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=148, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=1, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=162, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=2, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=143, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=3, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=131, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=4, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=130, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=5, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=139, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=6, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=129, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=7, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=149, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=8, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=155, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=9, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=135, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=10, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=11, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=146, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=12, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=151, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=13, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=158, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=14, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=154, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=15, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=136, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=16, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=138, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=17, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=152, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=18, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=141, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=19, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=132, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=20, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=133, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=21, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=137, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=22, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=159, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=23, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=163, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={140:0}, b={140:0}, i=24, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={140:0}, b={140:0}, b[i]=144, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={140:0}, b={140:0}, i=25, size=24] [L20] return i; VAL [\old(size)=24, \result=25, b={140:0}, b={140:0}, i=25, size=24] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=25, i=23, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=25, i=23, mask={140:0}] [L26] i++ VAL [b={157:0}, i=24, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=24, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=0, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=148, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=1, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=162, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=2, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=143, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=3, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=131, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=4, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=130, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=5, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=139, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=6, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=129, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=7, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=149, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=8, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=155, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=9, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=135, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=10, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=11, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=146, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=12, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=151, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=13, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=158, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=14, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=154, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=15, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=136, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=16, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=138, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=17, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=152, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=18, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=141, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=19, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=132, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=20, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=133, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=21, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=137, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=22, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=159, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=23, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=163, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=24, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=144, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={140:0}, b={140:0}, i=25, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={140:0}, b={140:0}, b[i]=153, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={140:0}, b={140:0}, i=26, size=25] [L20] return i; VAL [\old(size)=25, \result=26, b={140:0}, b={140:0}, i=26, size=25] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=26, i=24, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=26, i=24, mask={140:0}] [L26] i++ VAL [b={157:0}, i=25, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=25, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=0, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=148, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=1, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=162, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=2, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=143, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=3, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=131, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=4, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=130, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=5, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=139, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=6, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=129, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=7, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=149, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=8, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=155, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=9, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=135, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=10, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=11, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=146, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=12, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=151, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=13, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=158, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=14, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=154, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=15, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=136, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=16, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=138, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=17, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=152, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=18, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=141, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=19, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=132, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=20, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=133, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=21, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=137, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=22, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=159, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=23, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=163, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=24, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=144, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=25, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=153, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={140:0}, b={140:0}, i=26, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={140:0}, b={140:0}, b[i]=145, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={140:0}, b={140:0}, i=27, size=26] [L20] return i; VAL [\old(size)=26, \result=27, b={140:0}, b={140:0}, i=27, size=26] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=27, i=25, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=27, i=25, mask={140:0}] [L26] i++ VAL [b={157:0}, i=26, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=26, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=0, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=148, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=1, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=162, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=2, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=143, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=3, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=131, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=4, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=130, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=5, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=139, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=6, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=129, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=7, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=149, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=8, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=155, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=9, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=135, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=10, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=11, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=146, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=12, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=151, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=13, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=158, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=14, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=154, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=15, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=136, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=16, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=138, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=17, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=152, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=18, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=141, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=19, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=132, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=20, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=133, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=21, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=137, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=22, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=159, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=23, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=163, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=24, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=144, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=25, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=153, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=26, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=145, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={140:0}, b={140:0}, i=27, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={140:0}, b={140:0}, b[i]=164, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={140:0}, b={140:0}, i=28, size=27] [L20] return i; VAL [\old(size)=27, \result=28, b={140:0}, b={140:0}, i=28, size=27] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=28, i=26, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=28, i=26, mask={140:0}] [L26] i++ VAL [b={157:0}, i=27, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=27, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=0, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=148, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=1, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=162, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=2, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=143, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=3, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=131, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=4, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=130, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=5, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=139, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=6, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=129, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=7, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=149, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=8, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=155, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=9, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=135, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=10, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=11, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=146, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=12, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=151, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=13, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=158, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=14, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=154, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=15, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=136, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=16, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=138, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=17, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=152, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=18, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=141, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=19, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=132, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=20, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=133, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=21, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=137, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=22, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=159, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=23, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=163, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=24, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=144, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=25, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=153, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=26, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=145, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=27, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=164, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={140:0}, b={140:0}, i=28, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={140:0}, b={140:0}, b[i]=160, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={140:0}, b={140:0}, i=29, size=28] [L20] return i; VAL [\old(size)=28, \result=29, b={140:0}, b={140:0}, i=29, size=28] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=29, i=27, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=29, i=27, mask={140:0}] [L26] i++ VAL [b={157:0}, i=28, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=28, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=0, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=148, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=1, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=162, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=2, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=143, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=3, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=131, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=4, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=130, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=5, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=139, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=6, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=129, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=7, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=149, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=8, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=155, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=9, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=135, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=10, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=11, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=146, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=12, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=151, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=13, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=158, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=14, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=154, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=15, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=136, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=16, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=138, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=17, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=152, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=18, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=141, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=19, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=132, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=20, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=133, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=21, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=137, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=22, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=159, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=23, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=163, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=24, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=144, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=25, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=153, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=26, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=145, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=27, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=164, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=28, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=160, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={140:0}, b={140:0}, i=29, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={140:0}, b={140:0}, b[i]=142, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={140:0}, b={140:0}, i=30, size=29] [L20] return i; VAL [\old(size)=29, \result=30, b={140:0}, b={140:0}, i=30, size=29] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=30, i=28, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=30, i=28, mask={140:0}] [L26] i++ VAL [b={157:0}, i=29, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=29, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=0, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=148, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=1, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=162, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=2, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=143, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=3, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=131, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=4, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=130, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=5, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=139, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=6, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=129, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=7, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=149, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=8, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=155, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=9, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=135, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=10, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=11, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=146, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=12, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=151, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=13, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=158, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=14, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=154, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=15, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=136, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=16, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=138, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=17, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=152, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=18, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=141, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=19, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=132, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=20, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=133, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=21, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=137, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=22, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=159, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=23, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=163, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=24, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=144, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=25, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=153, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=26, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=145, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=27, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=164, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=28, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=160, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=29, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=142, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={140:0}, b={140:0}, i=30, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={140:0}, b={140:0}, b[i]=161, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={140:0}, b={140:0}, i=31, size=30] [L20] return i; VAL [\old(size)=30, \result=31, b={140:0}, b={140:0}, i=31, size=30] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=31, i=29, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=31, i=29, mask={140:0}] [L26] i++ VAL [b={157:0}, i=30, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=30, mask={140:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=0, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=148, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=1, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=162, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=2, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=143, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=3, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=131, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=4, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=130, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=5, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=139, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=6, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=129, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=7, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=149, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=8, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=155, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=9, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=135, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=10, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=11, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=146, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=12, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=151, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=13, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=158, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=14, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=154, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=15, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=136, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=16, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=138, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=17, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=152, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=18, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=141, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=19, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=132, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=20, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=133, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=21, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=137, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=22, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=159, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=23, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=163, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=24, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=144, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=25, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=153, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=26, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=145, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=27, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=164, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=28, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=160, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=29, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=142, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=30, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=161, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={140:0}, b={140:0}, i=31, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={140:0}, b={140:0}, b[i]=134, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={140:0}, b={140:0}, i=32, size=31] [L20] return i; VAL [\old(size)=31, \result=32, b={140:0}, b={140:0}, i=32, size=31] [L27] RET, EXPR foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=32, i=30, mask={140:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={157:0}, foo(mask, i + 1)=32, i=30, mask={140:0}] [L26] i++ VAL [b={157:0}, i=31, mask={140:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={157:0}, i=31, mask={140:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={140:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=0, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=148, i=0, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=1, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=162, i=1, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=2, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=143, i=2, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=3, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=131, i=3, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=4, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=130, i=4, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=5, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=139, i=5, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=6, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=129, i=6, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=7, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=149, i=7, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=8, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=155, i=8, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=9, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=135, i=9, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=10, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=150, i=10, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=11, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=146, i=11, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=12, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=151, i=12, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=13, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=158, i=13, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=14, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=154, i=14, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=15, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=136, i=15, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=16, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=138, i=16, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=17, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=152, i=17, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=18, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=141, i=18, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=19, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=132, i=19, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=20, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=133, i=20, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=21, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=137, i=21, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=22, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=159, i=22, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=23, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=163, i=23, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=24, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=144, i=24, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=25, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=153, i=25, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=26, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=145, i=26, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=27, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=164, i=27, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=28, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=160, i=28, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=29, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=142, i=29, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=30, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=161, i=30, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=31, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={140:0}, b={140:0}, b[i]=134, i=31, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={140:0}, b={140:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 40 locations, 8 error locations. UNSAFE Result, 496.1s OverallTime, 84 OverallIterations, 560 TraceHistogramMax, 172.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2547 SDtfs, 76416 SDslu, 42350 SDs, 0 SdLazy, 204684 SolverSat, 12801 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 62.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 97164 GetRequests, 88735 SyntacticMatches, 21 SemanticMatches, 8408 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 424431 ImplicationChecksByTransitivity, 151.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3492occurred in iteration=81, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 83 MinimizatonAttempts, 1419 StatesRemovedByMinimization, 81 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 3.4s SsaConstructionTime, 158.1s SatisfiabilityAnalysisTime, 112.5s InterpolantComputationTime, 184021 NumberOfCodeBlocks, 170192 NumberOfCodeBlocksAsserted, 1219 NumberOfCheckSat, 180715 ConstructedInterpolants, 116 QuantifiedInterpolants, 503282699 SizeOfPredicates, 181 NumberOfNonLiveVariables, 193379 ConjunctsInSsa, 2469 ConjunctsInUnsatCore, 159 InterpolantComputations, 8 PerfectInterpolantSequences, 26506844/26847347 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...