./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 35aa81144c06555695e96f98f1b941f438431e9e ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-08 18:43:40,476 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-08 18:43:40,477 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-08 18:43:40,483 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-08 18:43:40,483 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-08 18:43:40,484 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-08 18:43:40,484 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-08 18:43:40,485 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-08 18:43:40,486 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-08 18:43:40,486 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-08 18:43:40,487 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-08 18:43:40,487 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-08 18:43:40,487 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-08 18:43:40,488 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-08 18:43:40,488 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-08 18:43:40,489 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-08 18:43:40,489 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-08 18:43:40,490 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-08 18:43:40,491 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-08 18:43:40,491 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-08 18:43:40,492 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-08 18:43:40,492 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-08 18:43:40,494 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-08 18:43:40,494 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-08 18:43:40,494 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-08 18:43:40,494 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-08 18:43:40,495 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-08 18:43:40,495 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-08 18:43:40,495 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-08 18:43:40,496 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-08 18:43:40,496 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-08 18:43:40,497 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-08 18:43:40,497 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-08 18:43:40,497 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-08 18:43:40,497 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-08 18:43:40,498 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-08 18:43:40,498 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-12-08 18:43:40,505 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-08 18:43:40,506 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-08 18:43:40,506 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-08 18:43:40,506 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-08 18:43:40,506 INFO L133 SettingsManager]: * Use SBE=true [2018-12-08 18:43:40,506 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * Use old map elimination=false [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-12-08 18:43:40,507 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-12-08 18:43:40,507 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-12-08 18:43:40,508 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-12-08 18:43:40,508 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-08 18:43:40,508 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-12-08 18:43:40,509 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-12-08 18:43:40,509 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 35aa81144c06555695e96f98f1b941f438431e9e [2018-12-08 18:43:40,526 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-08 18:43:40,536 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-08 18:43:40,539 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-08 18:43:40,540 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-08 18:43:40,540 INFO L276 PluginConnector]: CDTParser initialized [2018-12-08 18:43:40,541 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.07_true-unreach-call_false-termination.cil.c [2018-12-08 18:43:40,586 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/data/1ed1de5be/1e11b98accc64adab021074f0e947c12/FLAGaadd61f8d [2018-12-08 18:43:40,985 INFO L307 CDTParser]: Found 1 translation units. [2018-12-08 18:43:40,986 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/sv-benchmarks/c/systemc/token_ring.07_true-unreach-call_false-termination.cil.c [2018-12-08 18:43:40,991 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/data/1ed1de5be/1e11b98accc64adab021074f0e947c12/FLAGaadd61f8d [2018-12-08 18:43:41,350 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/data/1ed1de5be/1e11b98accc64adab021074f0e947c12 [2018-12-08 18:43:41,352 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-08 18:43:41,353 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-08 18:43:41,354 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-08 18:43:41,354 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-08 18:43:41,356 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-08 18:43:41,357 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,359 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58f41b83 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41, skipping insertion in model container [2018-12-08 18:43:41,359 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,366 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-08 18:43:41,400 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-08 18:43:41,541 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-08 18:43:41,545 INFO L191 MainTranslator]: Completed pre-run [2018-12-08 18:43:41,580 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-08 18:43:41,631 INFO L195 MainTranslator]: Completed translation [2018-12-08 18:43:41,631 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41 WrapperNode [2018-12-08 18:43:41,632 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-08 18:43:41,632 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-08 18:43:41,632 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-08 18:43:41,632 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-08 18:43:41,639 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,645 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,681 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-08 18:43:41,681 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-08 18:43:41,681 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-08 18:43:41,681 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-08 18:43:41,687 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,688 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,690 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,690 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,700 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,713 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,715 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... [2018-12-08 18:43:41,719 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-08 18:43:41,720 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-08 18:43:41,720 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-08 18:43:41,720 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-08 18:43:41,720 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:41,766 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-08 18:43:41,766 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-08 18:43:42,544 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-08 18:43:42,544 INFO L280 CfgBuilder]: Removed 278 assue(true) statements. [2018-12-08 18:43:42,545 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 06:43:42 BoogieIcfgContainer [2018-12-08 18:43:42,545 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-08 18:43:42,545 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-12-08 18:43:42,545 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-12-08 18:43:42,548 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-12-08 18:43:42,548 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-12-08 18:43:42,548 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.12 06:43:41" (1/3) ... [2018-12-08 18:43:42,549 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3ef46a25 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.12 06:43:42, skipping insertion in model container [2018-12-08 18:43:42,549 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-12-08 18:43:42,549 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 06:43:41" (2/3) ... [2018-12-08 18:43:42,550 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3ef46a25 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.12 06:43:42, skipping insertion in model container [2018-12-08 18:43:42,550 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-12-08 18:43:42,550 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 06:43:42" (3/3) ... [2018-12-08 18:43:42,551 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.07_true-unreach-call_false-termination.cil.c [2018-12-08 18:43:42,583 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-08 18:43:42,584 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-12-08 18:43:42,584 INFO L375 BuchiCegarLoop]: Hoare is false [2018-12-08 18:43:42,584 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-12-08 18:43:42,584 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-08 18:43:42,584 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-08 18:43:42,584 INFO L379 BuchiCegarLoop]: Difference is false [2018-12-08 18:43:42,584 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-08 18:43:42,584 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-12-08 18:43:42,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states. [2018-12-08 18:43:42,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 709 [2018-12-08 18:43:42,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:42,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:42,649 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:42,649 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:42,649 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-12-08 18:43:42,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 812 states. [2018-12-08 18:43:42,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 709 [2018-12-08 18:43:42,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:42,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:42,658 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:42,659 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:42,666 INFO L794 eck$LassoCheckResult]: Stem: 276#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 214#L-1true havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 793#L1131true havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 535#L519true assume !(1 == ~m_i~0);~m_st~0 := 2; 349#L526-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 172#L531-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 809#L536-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 536#L541-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 340#L546-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 136#L551-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 62#L556-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 696#L561-1true assume !(0 == ~M_E~0); 704#L759-1true assume 0 == ~T1_E~0;~T1_E~0 := 1; 402#L764-1true assume !(0 == ~T2_E~0); 241#L769-1true assume !(0 == ~T3_E~0); 43#L774-1true assume !(0 == ~T4_E~0); 779#L779-1true assume !(0 == ~T5_E~0); 594#L784-1true assume !(0 == ~T6_E~0); 386#L789-1true assume !(0 == ~T7_E~0); 103#L794-1true assume !(0 == ~E_M~0); 743#L799-1true assume 0 == ~E_1~0;~E_1~0 := 1; 646#L804-1true assume !(0 == ~E_2~0); 495#L809-1true assume !(0 == ~E_3~0); 308#L814-1true assume !(0 == ~E_4~0); 5#L819-1true assume !(0 == ~E_5~0); 621#L824-1true assume !(0 == ~E_6~0); 464#L829-1true assume !(0 == ~E_7~0); 355#L834-1true havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 577#L366true assume !(1 == ~m_pc~0); 580#L366-2true is_master_triggered_~__retres1~0 := 0; 156#L377true is_master_triggered_#res := is_master_triggered_~__retres1~0; 35#L378true activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 242#L945true assume !(0 != activate_threads_~tmp~1); 243#L945-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 686#L385true assume 1 == ~t1_pc~0; 550#L386true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 288#L396true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 125#L397true activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 749#L953true assume !(0 != activate_threads_~tmp___0~0); 750#L953-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 795#L404true assume !(1 == ~t2_pc~0); 800#L404-2true is_transmit2_triggered_~__retres1~2 := 0; 384#L415true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 350#L416true activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 564#L961true assume !(0 != activate_threads_~tmp___1~0); 567#L961-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 90#L423true assume 1 == ~t3_pc~0; 51#L424true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 520#L434true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 480#L435true activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 264#L969true assume !(0 != activate_threads_~tmp___2~0); 265#L969-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 102#L442true assume 1 == ~t4_pc~0; 175#L443true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 538#L453true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 588#L454true activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 783#L977true assume !(0 != activate_threads_~tmp___3~0); 786#L977-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 224#L461true assume !(1 == ~t5_pc~0); 226#L461-2true is_transmit5_triggered_~__retres1~5 := 0; 613#L472true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 681#L473true activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 499#L985true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 500#L985-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 341#L480true assume 1 == ~t6_pc~0; 381#L481true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 737#L491true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 810#L492true activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 198#L993true assume !(0 != activate_threads_~tmp___5~0); 201#L993-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 439#L499true assume !(1 == ~t7_pc~0); 443#L499-2true is_transmit7_triggered_~__retres1~7 := 0; 31#L510true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3#L511true activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 707#L1001true assume !(0 != activate_threads_~tmp___6~0); 708#L1001-2true assume !(1 == ~M_E~0); 699#L847-1true assume !(1 == ~T1_E~0); 399#L852-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 237#L857-1true assume !(1 == ~T3_E~0); 41#L862-1true assume !(1 == ~T4_E~0); 773#L867-1true assume !(1 == ~T5_E~0); 592#L872-1true assume !(1 == ~T6_E~0); 321#L877-1true assume !(1 == ~T7_E~0); 107#L882-1true assume !(1 == ~E_M~0); 751#L887-1true assume !(1 == ~E_1~0); 655#L892-1true assume 1 == ~E_2~0;~E_2~0 := 2; 503#L897-1true assume !(1 == ~E_3~0); 319#L902-1true assume !(1 == ~E_4~0); 11#L907-1true assume !(1 == ~E_5~0); 627#L912-1true assume !(1 == ~E_6~0); 460#L917-1true assume !(1 == ~E_7~0); 122#L1168-1true [2018-12-08 18:43:42,668 INFO L796 eck$LassoCheckResult]: Loop: 122#L1168-1true assume !false; 204#L1169true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 813#L734true assume false; 260#L749true start_simulation_~kernel_st~0 := 2; 537#L519-1true start_simulation_~kernel_st~0 := 3; 706#L759-2true assume 0 == ~M_E~0;~M_E~0 := 1; 693#L759-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 393#L764-3true assume !(0 == ~T2_E~0); 232#L769-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 37#L774-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 763#L779-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 590#L784-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 390#L789-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 105#L794-3true assume 0 == ~E_M~0;~E_M~0 := 1; 745#L799-3true assume 0 == ~E_1~0;~E_1~0 := 1; 649#L804-3true assume !(0 == ~E_2~0); 497#L809-3true assume 0 == ~E_3~0;~E_3~0 := 1; 310#L814-3true assume 0 == ~E_4~0;~E_4~0 := 1; 6#L819-3true assume 0 == ~E_5~0;~E_5~0 := 1; 622#L824-3true assume 0 == ~E_6~0;~E_6~0 := 1; 469#L829-3true assume 0 == ~E_7~0;~E_7~0 := 1; 356#L834-3true havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 440#L366-27true assume 1 == ~m_pc~0; 420#L367-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 153#L377-9true is_master_triggered_#res := is_master_triggered_~__retres1~0; 17#L378-9true activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 212#L945-27true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 312#L945-29true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 559#L385-27true assume !(1 == ~t1_pc~0); 548#L385-29true is_transmit1_triggered_~__retres1~1 := 0; 270#L396-9true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 109#L397-9true activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 712#L953-27true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 714#L953-29true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 754#L404-27true assume !(1 == ~t2_pc~0); 757#L404-29true is_transmit2_triggered_~__retres1~2 := 0; 365#L415-9true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 248#L416-9true activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 421#L961-27true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 405#L961-29true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60#L423-27true assume !(1 == ~t3_pc~0); 64#L423-29true is_transmit3_triggered_~__retres1~3 := 0; 505#L434-9true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 478#L435-9true activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 110#L969-27true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 112#L969-29true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 187#L442-27true assume 1 == ~t4_pc~0; 148#L443-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 599#L453-9true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 572#L454-9true activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 633#L977-27true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 623#L977-29true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 298#L461-27true assume 1 == ~t5_pc~0; 284#L462-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 611#L472-9true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 677#L473-9true activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 345#L985-27true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 346#L985-29true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 392#L480-27true assume 1 == ~t6_pc~0; 362#L481-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 720#L491-9true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 789#L492-9true activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 152#L993-27true assume !(0 != activate_threads_~tmp___5~0); 139#L993-29true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 395#L499-27true assume 1 == ~t7_pc~0; 514#L500-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 29#L510-9true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 84#L511-9true activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 659#L1001-27true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 661#L1001-29true assume 1 == ~M_E~0;~M_E~0 := 2; 701#L847-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 401#L852-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 239#L857-3true assume !(1 == ~T3_E~0); 42#L862-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 778#L867-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 593#L872-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 324#L877-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 108#L882-3true assume 1 == ~E_M~0;~E_M~0 := 2; 742#L887-3true assume 1 == ~E_1~0;~E_1~0 := 2; 645#L892-3true assume 1 == ~E_2~0;~E_2~0 := 2; 493#L897-3true assume !(1 == ~E_3~0); 306#L902-3true assume 1 == ~E_4~0;~E_4~0 := 2; 4#L907-3true assume 1 == ~E_5~0;~E_5~0 := 2; 620#L912-3true assume 1 == ~E_6~0;~E_6~0 := 2; 463#L917-3true assume 1 == ~E_7~0;~E_7~0 := 2; 354#L922-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 100#L574-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 299#L616-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 133#L617-1true start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 245#L1187true assume !(0 == start_simulation_~tmp~3); 249#L1187-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 101#L574-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 301#L616-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 135#L617-2true stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 366#L1142true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15#L1149true stop_simulation_#res := stop_simulation_~__retres2~0; 74#L1150true start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 678#L1200true assume !(0 != start_simulation_~tmp___0~1); 122#L1168-1true [2018-12-08 18:43:42,672 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:42,672 INFO L82 PathProgramCache]: Analyzing trace with hash -1537628007, now seen corresponding path program 1 times [2018-12-08 18:43:42,673 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:42,674 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:42,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:42,702 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:42,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:42,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:42,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:42,787 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:42,787 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:42,791 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:42,791 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:42,791 INFO L82 PathProgramCache]: Analyzing trace with hash 186909354, now seen corresponding path program 1 times [2018-12-08 18:43:42,792 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:42,792 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:42,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:42,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:42,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:42,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:42,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:42,809 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:42,809 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:42,810 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:42,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:42,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:42,821 INFO L87 Difference]: Start difference. First operand 812 states. Second operand 3 states. [2018-12-08 18:43:42,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:42,852 INFO L93 Difference]: Finished difference Result 812 states and 1222 transitions. [2018-12-08 18:43:42,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:42,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1222 transitions. [2018-12-08 18:43:42,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:42,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 807 states and 1217 transitions. [2018-12-08 18:43:42,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:42,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:42,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1217 transitions. [2018-12-08 18:43:42,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:42,869 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1217 transitions. [2018-12-08 18:43:42,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1217 transitions. [2018-12-08 18:43:42,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:42,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:42,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1217 transitions. [2018-12-08 18:43:42,905 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1217 transitions. [2018-12-08 18:43:42,905 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1217 transitions. [2018-12-08 18:43:42,905 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-12-08 18:43:42,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1217 transitions. [2018-12-08 18:43:42,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:42,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:42,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:42,910 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:42,910 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:42,910 INFO L794 eck$LassoCheckResult]: Stem: 2046#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1960#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1961#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2280#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 2132#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1925#L531-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1926#L536-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2281#L541-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2119#L546-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1864#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1763#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1764#L561-1 assume !(0 == ~M_E~0); 2391#L759-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2182#L764-1 assume !(0 == ~T2_E~0); 1997#L769-1 assume !(0 == ~T3_E~0); 1719#L774-1 assume !(0 == ~T4_E~0); 1720#L779-1 assume !(0 == ~T5_E~0); 2336#L784-1 assume !(0 == ~T6_E~0); 2168#L789-1 assume !(0 == ~T7_E~0); 1803#L794-1 assume !(0 == ~E_M~0); 1804#L799-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2375#L804-1 assume !(0 == ~E_2~0); 2265#L809-1 assume !(0 == ~E_3~0); 2074#L814-1 assume !(0 == ~E_4~0); 1637#L819-1 assume !(0 == ~E_5~0); 1638#L824-1 assume !(0 == ~E_6~0); 2238#L829-1 assume !(0 == ~E_7~0); 2140#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2141#L366 assume !(1 == ~m_pc~0); 2230#L366-2 is_master_triggered_~__retres1~0 := 0; 1896#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1700#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1701#L945 assume !(0 != activate_threads_~tmp~1); 1998#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1999#L385 assume 1 == ~t1_pc~0; 2299#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2063#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1843#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1844#L953 assume !(0 != activate_threads_~tmp___0~0); 2430#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2431#L404 assume !(1 == ~t2_pc~0); 2435#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 2167#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2133#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2134#L961 assume !(0 != activate_threads_~tmp___1~0); 2311#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1787#L423 assume 1 == ~t3_pc~0; 1742#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1743#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2249#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2031#L969 assume !(0 != activate_threads_~tmp___2~0); 2032#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1801#L442 assume 1 == ~t4_pc~0; 1802#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1793#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2283#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2330#L977 assume !(0 != activate_threads_~tmp___3~0); 2439#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1979#L461 assume !(1 == ~t5_pc~0); 1980#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 1983#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2345#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2268#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2269#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2120#L480 assume 1 == ~t6_pc~0; 2121#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2108#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2423#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1943#L993 assume !(0 != activate_threads_~tmp___5~0); 1944#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1946#L499 assume !(1 == ~t7_pc~0); 2223#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 1693#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1633#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1634#L1001 assume !(0 != activate_threads_~tmp___6~0); 2395#L1001-2 assume !(1 == ~M_E~0); 2393#L847-1 assume !(1 == ~T1_E~0); 2180#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1994#L857-1 assume !(1 == ~T3_E~0); 1715#L862-1 assume !(1 == ~T4_E~0); 1716#L867-1 assume !(1 == ~T5_E~0); 2334#L872-1 assume !(1 == ~T6_E~0); 2087#L877-1 assume !(1 == ~T7_E~0); 1811#L882-1 assume !(1 == ~E_M~0); 1812#L887-1 assume !(1 == ~E_1~0); 2379#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2273#L897-1 assume !(1 == ~E_3~0); 2083#L902-1 assume !(1 == ~E_4~0); 1652#L907-1 assume !(1 == ~E_5~0); 1653#L912-1 assume !(1 == ~E_6~0); 2235#L917-1 assume !(1 == ~E_7~0); 1838#L1168-1 [2018-12-08 18:43:42,911 INFO L796 eck$LassoCheckResult]: Loop: 1838#L1168-1 assume !false; 1839#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1948#L734 assume !false; 2388#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1798#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1710#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1854#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1855#L631 assume !(0 != eval_~tmp~0); 2026#L749 start_simulation_~kernel_st~0 := 2; 2027#L519-1 start_simulation_~kernel_st~0 := 3; 2282#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2389#L759-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2172#L764-3 assume !(0 == ~T2_E~0); 1990#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1704#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1705#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2332#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2171#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1807#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1808#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2376#L804-3 assume !(0 == ~E_2~0); 2266#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2075#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1639#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1640#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2239#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2142#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2143#L366-27 assume 1 == ~m_pc~0; 2202#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1892#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1664#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1665#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1958#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2077#L385-27 assume 1 == ~t1_pc~0; 2284#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2039#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1815#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1816#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2399#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2400#L404-27 assume 1 == ~t2_pc~0; 2356#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2158#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2007#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2008#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2185#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1760#L423-27 assume 1 == ~t3_pc~0; 1736#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1737#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2248#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1817#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1818#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1821#L442-27 assume 1 == ~t4_pc~0; 1883#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1884#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2316#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2317#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2349#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2068#L461-27 assume 1 == ~t5_pc~0; 2060#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2061#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2344#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2127#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2128#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2129#L480-27 assume 1 == ~t6_pc~0; 2151#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2152#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2405#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1891#L993-27 assume !(0 != activate_threads_~tmp___5~0); 1867#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1868#L499-27 assume 1 == ~t7_pc~0; 2174#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1688#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1689#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1781#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2380#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 2381#L847-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2181#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1996#L857-3 assume !(1 == ~T3_E~0); 1717#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1718#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2335#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2092#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1813#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1814#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2374#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2262#L897-3 assume !(1 == ~E_3~0); 2072#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1635#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1636#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2237#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2139#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1799#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1713#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1858#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1859#L1187 assume !(0 == start_simulation_~tmp~3); 1894#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1800#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1691#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1862#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 1863#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1660#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 1661#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1772#L1200 assume !(0 != start_simulation_~tmp___0~1); 1838#L1168-1 [2018-12-08 18:43:42,911 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:42,911 INFO L82 PathProgramCache]: Analyzing trace with hash -542934309, now seen corresponding path program 1 times [2018-12-08 18:43:42,911 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:42,912 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:42,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:42,912 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:42,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:42,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:42,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:42,939 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:42,939 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:42,940 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:42,940 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:42,940 INFO L82 PathProgramCache]: Analyzing trace with hash -291308708, now seen corresponding path program 1 times [2018-12-08 18:43:42,940 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:42,940 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:42,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:42,941 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:42,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:42,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:42,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:42,997 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:42,997 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:42,998 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:42,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:42,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:42,998 INFO L87 Difference]: Start difference. First operand 807 states and 1217 transitions. cyclomatic complexity: 411 Second operand 3 states. [2018-12-08 18:43:43,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,014 INFO L93 Difference]: Finished difference Result 807 states and 1216 transitions. [2018-12-08 18:43:43,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1216 transitions. [2018-12-08 18:43:43,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1216 transitions. [2018-12-08 18:43:43,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:43,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:43,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1216 transitions. [2018-12-08 18:43:43,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,027 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1216 transitions. [2018-12-08 18:43:43,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1216 transitions. [2018-12-08 18:43:43,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:43,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:43,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1216 transitions. [2018-12-08 18:43:43,041 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1216 transitions. [2018-12-08 18:43:43,041 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1216 transitions. [2018-12-08 18:43:43,042 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-12-08 18:43:43,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1216 transitions. [2018-12-08 18:43:43,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,046 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,046 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,046 INFO L794 eck$LassoCheckResult]: Stem: 3667#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3581#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3582#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3901#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 3753#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3546#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3547#L536-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3902#L541-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3740#L546-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3485#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3384#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3385#L561-1 assume !(0 == ~M_E~0); 4012#L759-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3803#L764-1 assume !(0 == ~T2_E~0); 3618#L769-1 assume !(0 == ~T3_E~0); 3340#L774-1 assume !(0 == ~T4_E~0); 3341#L779-1 assume !(0 == ~T5_E~0); 3957#L784-1 assume !(0 == ~T6_E~0); 3789#L789-1 assume !(0 == ~T7_E~0); 3424#L794-1 assume !(0 == ~E_M~0); 3425#L799-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3996#L804-1 assume !(0 == ~E_2~0); 3886#L809-1 assume !(0 == ~E_3~0); 3695#L814-1 assume !(0 == ~E_4~0); 3258#L819-1 assume !(0 == ~E_5~0); 3259#L824-1 assume !(0 == ~E_6~0); 3859#L829-1 assume !(0 == ~E_7~0); 3761#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3762#L366 assume !(1 == ~m_pc~0); 3851#L366-2 is_master_triggered_~__retres1~0 := 0; 3517#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3321#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3322#L945 assume !(0 != activate_threads_~tmp~1); 3619#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3620#L385 assume 1 == ~t1_pc~0; 3920#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3684#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3464#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3465#L953 assume !(0 != activate_threads_~tmp___0~0); 4051#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4052#L404 assume !(1 == ~t2_pc~0); 4056#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 3788#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3754#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3755#L961 assume !(0 != activate_threads_~tmp___1~0); 3932#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3408#L423 assume 1 == ~t3_pc~0; 3363#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3364#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3870#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3652#L969 assume !(0 != activate_threads_~tmp___2~0); 3653#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3422#L442 assume 1 == ~t4_pc~0; 3423#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3414#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3904#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3951#L977 assume !(0 != activate_threads_~tmp___3~0); 4060#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3600#L461 assume !(1 == ~t5_pc~0); 3601#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 3604#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3966#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3889#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3890#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3741#L480 assume 1 == ~t6_pc~0; 3742#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3729#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4044#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3564#L993 assume !(0 != activate_threads_~tmp___5~0); 3565#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3567#L499 assume !(1 == ~t7_pc~0); 3844#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 3314#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3254#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3255#L1001 assume !(0 != activate_threads_~tmp___6~0); 4016#L1001-2 assume !(1 == ~M_E~0); 4014#L847-1 assume !(1 == ~T1_E~0); 3801#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3615#L857-1 assume !(1 == ~T3_E~0); 3336#L862-1 assume !(1 == ~T4_E~0); 3337#L867-1 assume !(1 == ~T5_E~0); 3955#L872-1 assume !(1 == ~T6_E~0); 3708#L877-1 assume !(1 == ~T7_E~0); 3432#L882-1 assume !(1 == ~E_M~0); 3433#L887-1 assume !(1 == ~E_1~0); 4000#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3894#L897-1 assume !(1 == ~E_3~0); 3704#L902-1 assume !(1 == ~E_4~0); 3273#L907-1 assume !(1 == ~E_5~0); 3274#L912-1 assume !(1 == ~E_6~0); 3856#L917-1 assume !(1 == ~E_7~0); 3459#L1168-1 [2018-12-08 18:43:43,047 INFO L796 eck$LassoCheckResult]: Loop: 3459#L1168-1 assume !false; 3460#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3569#L734 assume !false; 4009#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3419#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3331#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3475#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3476#L631 assume !(0 != eval_~tmp~0); 3647#L749 start_simulation_~kernel_st~0 := 2; 3648#L519-1 start_simulation_~kernel_st~0 := 3; 3903#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4010#L759-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3793#L764-3 assume !(0 == ~T2_E~0); 3611#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3325#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3326#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3953#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3792#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3428#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3429#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3997#L804-3 assume !(0 == ~E_2~0); 3887#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3696#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3260#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3261#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3860#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3763#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3764#L366-27 assume !(1 == ~m_pc~0); 3824#L366-29 is_master_triggered_~__retres1~0 := 0; 3513#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3285#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3286#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3579#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3698#L385-27 assume 1 == ~t1_pc~0; 3905#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3660#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3436#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3437#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4020#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4021#L404-27 assume 1 == ~t2_pc~0; 3977#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3779#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3628#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3629#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3806#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3381#L423-27 assume 1 == ~t3_pc~0; 3357#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3358#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3869#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3438#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3439#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3442#L442-27 assume 1 == ~t4_pc~0; 3504#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3505#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3937#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3938#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3970#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3689#L461-27 assume 1 == ~t5_pc~0; 3681#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3682#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3965#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3748#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3749#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3750#L480-27 assume 1 == ~t6_pc~0; 3772#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3773#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4026#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3512#L993-27 assume !(0 != activate_threads_~tmp___5~0); 3488#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3489#L499-27 assume 1 == ~t7_pc~0; 3795#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3309#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3310#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3402#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4001#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 4002#L847-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3802#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3617#L857-3 assume !(1 == ~T3_E~0); 3338#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3339#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3956#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3713#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3434#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3435#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3995#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3883#L897-3 assume !(1 == ~E_3~0); 3693#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3256#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3257#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3858#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3760#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3420#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3334#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3479#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3480#L1187 assume !(0 == start_simulation_~tmp~3); 3515#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3421#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3312#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3483#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3484#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3281#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 3282#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3393#L1200 assume !(0 != start_simulation_~tmp___0~1); 3459#L1168-1 [2018-12-08 18:43:43,047 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,047 INFO L82 PathProgramCache]: Analyzing trace with hash 1415640477, now seen corresponding path program 1 times [2018-12-08 18:43:43,047 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,047 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,048 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,081 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,081 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,082 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,082 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,082 INFO L82 PathProgramCache]: Analyzing trace with hash -212190853, now seen corresponding path program 1 times [2018-12-08 18:43:43,082 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,082 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,083 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,147 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,147 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,147 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,147 INFO L87 Difference]: Start difference. First operand 807 states and 1216 transitions. cyclomatic complexity: 410 Second operand 3 states. [2018-12-08 18:43:43,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,156 INFO L93 Difference]: Finished difference Result 807 states and 1215 transitions. [2018-12-08 18:43:43,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1215 transitions. [2018-12-08 18:43:43,159 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1215 transitions. [2018-12-08 18:43:43,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:43,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:43,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1215 transitions. [2018-12-08 18:43:43,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,162 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1215 transitions. [2018-12-08 18:43:43,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1215 transitions. [2018-12-08 18:43:43,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:43,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:43,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1215 transitions. [2018-12-08 18:43:43,169 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1215 transitions. [2018-12-08 18:43:43,169 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1215 transitions. [2018-12-08 18:43:43,169 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-12-08 18:43:43,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1215 transitions. [2018-12-08 18:43:43,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,172 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,172 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,173 INFO L794 eck$LassoCheckResult]: Stem: 5288#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5202#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5203#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5522#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 5374#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5169#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5170#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5523#L541-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5361#L546-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5106#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5005#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5006#L561-1 assume !(0 == ~M_E~0); 5633#L759-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5425#L764-1 assume !(0 == ~T2_E~0); 5239#L769-1 assume !(0 == ~T3_E~0); 4961#L774-1 assume !(0 == ~T4_E~0); 4962#L779-1 assume !(0 == ~T5_E~0); 5578#L784-1 assume !(0 == ~T6_E~0); 5410#L789-1 assume !(0 == ~T7_E~0); 5045#L794-1 assume !(0 == ~E_M~0); 5046#L799-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5617#L804-1 assume !(0 == ~E_2~0); 5507#L809-1 assume !(0 == ~E_3~0); 5316#L814-1 assume !(0 == ~E_4~0); 4879#L819-1 assume !(0 == ~E_5~0); 4880#L824-1 assume !(0 == ~E_6~0); 5480#L829-1 assume !(0 == ~E_7~0); 5382#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5383#L366 assume !(1 == ~m_pc~0); 5472#L366-2 is_master_triggered_~__retres1~0 := 0; 5138#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4942#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4943#L945 assume !(0 != activate_threads_~tmp~1); 5240#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5241#L385 assume 1 == ~t1_pc~0; 5541#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5305#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5085#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5086#L953 assume !(0 != activate_threads_~tmp___0~0); 5672#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5673#L404 assume !(1 == ~t2_pc~0); 5677#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 5409#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5375#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5376#L961 assume !(0 != activate_threads_~tmp___1~0); 5553#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5029#L423 assume 1 == ~t3_pc~0; 4984#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4985#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5491#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5273#L969 assume !(0 != activate_threads_~tmp___2~0); 5274#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5043#L442 assume 1 == ~t4_pc~0; 5044#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5035#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5525#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5572#L977 assume !(0 != activate_threads_~tmp___3~0); 5681#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5221#L461 assume !(1 == ~t5_pc~0); 5222#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 5225#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5587#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5510#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5511#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5362#L480 assume 1 == ~t6_pc~0; 5363#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5350#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5665#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5185#L993 assume !(0 != activate_threads_~tmp___5~0); 5186#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5188#L499 assume !(1 == ~t7_pc~0); 5465#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 4935#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4875#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4876#L1001 assume !(0 != activate_threads_~tmp___6~0); 5637#L1001-2 assume !(1 == ~M_E~0); 5635#L847-1 assume !(1 == ~T1_E~0); 5422#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5236#L857-1 assume !(1 == ~T3_E~0); 4957#L862-1 assume !(1 == ~T4_E~0); 4958#L867-1 assume !(1 == ~T5_E~0); 5576#L872-1 assume !(1 == ~T6_E~0); 5329#L877-1 assume !(1 == ~T7_E~0); 5053#L882-1 assume !(1 == ~E_M~0); 5054#L887-1 assume !(1 == ~E_1~0); 5621#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5515#L897-1 assume !(1 == ~E_3~0); 5325#L902-1 assume !(1 == ~E_4~0); 4894#L907-1 assume !(1 == ~E_5~0); 4895#L912-1 assume !(1 == ~E_6~0); 5477#L917-1 assume !(1 == ~E_7~0); 5080#L1168-1 [2018-12-08 18:43:43,173 INFO L796 eck$LassoCheckResult]: Loop: 5080#L1168-1 assume !false; 5081#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 5190#L734 assume !false; 5630#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5040#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4952#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5096#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5097#L631 assume !(0 != eval_~tmp~0); 5268#L749 start_simulation_~kernel_st~0 := 2; 5269#L519-1 start_simulation_~kernel_st~0 := 3; 5524#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5631#L759-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5414#L764-3 assume !(0 == ~T2_E~0); 5232#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4946#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4947#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5574#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5413#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5049#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5050#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5618#L804-3 assume !(0 == ~E_2~0); 5508#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5317#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4881#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4882#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5481#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5384#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5385#L366-27 assume 1 == ~m_pc~0; 5444#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5134#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4906#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4907#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5200#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5319#L385-27 assume 1 == ~t1_pc~0; 5526#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5281#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5057#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5058#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5641#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5642#L404-27 assume 1 == ~t2_pc~0; 5598#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5400#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5249#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5250#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5427#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5002#L423-27 assume 1 == ~t3_pc~0; 4978#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4979#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5490#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5059#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5060#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5063#L442-27 assume 1 == ~t4_pc~0; 5125#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5126#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5558#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5559#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5591#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5310#L461-27 assume 1 == ~t5_pc~0; 5302#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5303#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5586#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5369#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5370#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5371#L480-27 assume 1 == ~t6_pc~0; 5393#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5394#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5647#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5133#L993-27 assume !(0 != activate_threads_~tmp___5~0); 5109#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5110#L499-27 assume 1 == ~t7_pc~0; 5416#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4930#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4931#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5023#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5622#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 5623#L847-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5423#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5238#L857-3 assume !(1 == ~T3_E~0); 4959#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4960#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5577#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5334#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5055#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5056#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5616#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5504#L897-3 assume !(1 == ~E_3~0); 5314#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4877#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4878#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5479#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5381#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5041#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4955#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5100#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 5101#L1187 assume !(0 == start_simulation_~tmp~3); 5136#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5042#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4933#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5104#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 5105#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4902#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 4903#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5014#L1200 assume !(0 != start_simulation_~tmp___0~1); 5080#L1168-1 [2018-12-08 18:43:43,173 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,173 INFO L82 PathProgramCache]: Analyzing trace with hash -460842341, now seen corresponding path program 1 times [2018-12-08 18:43:43,173 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,174 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,174 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,193 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,193 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,194 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,194 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,194 INFO L82 PathProgramCache]: Analyzing trace with hash -291308708, now seen corresponding path program 2 times [2018-12-08 18:43:43,194 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,194 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,194 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,195 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,218 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,218 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,219 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,219 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,219 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,219 INFO L87 Difference]: Start difference. First operand 807 states and 1215 transitions. cyclomatic complexity: 409 Second operand 3 states. [2018-12-08 18:43:43,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,231 INFO L93 Difference]: Finished difference Result 807 states and 1214 transitions. [2018-12-08 18:43:43,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1214 transitions. [2018-12-08 18:43:43,235 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1214 transitions. [2018-12-08 18:43:43,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:43,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:43,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1214 transitions. [2018-12-08 18:43:43,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,240 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1214 transitions. [2018-12-08 18:43:43,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1214 transitions. [2018-12-08 18:43:43,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:43,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:43,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1214 transitions. [2018-12-08 18:43:43,247 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1214 transitions. [2018-12-08 18:43:43,247 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1214 transitions. [2018-12-08 18:43:43,247 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-12-08 18:43:43,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1214 transitions. [2018-12-08 18:43:43,249 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,250 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,250 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,250 INFO L794 eck$LassoCheckResult]: Stem: 6909#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 6823#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6824#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7143#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 6995#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6790#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6791#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7144#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6982#L546-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6727#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6626#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6627#L561-1 assume !(0 == ~M_E~0); 7254#L759-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7046#L764-1 assume !(0 == ~T2_E~0); 6860#L769-1 assume !(0 == ~T3_E~0); 6582#L774-1 assume !(0 == ~T4_E~0); 6583#L779-1 assume !(0 == ~T5_E~0); 7199#L784-1 assume !(0 == ~T6_E~0); 7031#L789-1 assume !(0 == ~T7_E~0); 6666#L794-1 assume !(0 == ~E_M~0); 6667#L799-1 assume 0 == ~E_1~0;~E_1~0 := 1; 7238#L804-1 assume !(0 == ~E_2~0); 7128#L809-1 assume !(0 == ~E_3~0); 6937#L814-1 assume !(0 == ~E_4~0); 6500#L819-1 assume !(0 == ~E_5~0); 6501#L824-1 assume !(0 == ~E_6~0); 7101#L829-1 assume !(0 == ~E_7~0); 7003#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7004#L366 assume !(1 == ~m_pc~0); 7093#L366-2 is_master_triggered_~__retres1~0 := 0; 6759#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6565#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6566#L945 assume !(0 != activate_threads_~tmp~1); 6861#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6862#L385 assume 1 == ~t1_pc~0; 7162#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6926#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6706#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6707#L953 assume !(0 != activate_threads_~tmp___0~0); 7293#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7294#L404 assume !(1 == ~t2_pc~0); 7298#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 7030#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6996#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6997#L961 assume !(0 != activate_threads_~tmp___1~0); 7174#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6650#L423 assume 1 == ~t3_pc~0; 6605#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6606#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7112#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6894#L969 assume !(0 != activate_threads_~tmp___2~0); 6895#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6664#L442 assume 1 == ~t4_pc~0; 6665#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6656#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7146#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7193#L977 assume !(0 != activate_threads_~tmp___3~0); 7302#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6842#L461 assume !(1 == ~t5_pc~0); 6843#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 6846#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7208#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7131#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7132#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6983#L480 assume 1 == ~t6_pc~0; 6984#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6971#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7286#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6806#L993 assume !(0 != activate_threads_~tmp___5~0); 6807#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6809#L499 assume !(1 == ~t7_pc~0); 7086#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 6556#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6496#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6497#L1001 assume !(0 != activate_threads_~tmp___6~0); 7258#L1001-2 assume !(1 == ~M_E~0); 7256#L847-1 assume !(1 == ~T1_E~0); 7043#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6857#L857-1 assume !(1 == ~T3_E~0); 6578#L862-1 assume !(1 == ~T4_E~0); 6579#L867-1 assume !(1 == ~T5_E~0); 7197#L872-1 assume !(1 == ~T6_E~0); 6951#L877-1 assume !(1 == ~T7_E~0); 6674#L882-1 assume !(1 == ~E_M~0); 6675#L887-1 assume !(1 == ~E_1~0); 7242#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 7136#L897-1 assume !(1 == ~E_3~0); 6946#L902-1 assume !(1 == ~E_4~0); 6515#L907-1 assume !(1 == ~E_5~0); 6516#L912-1 assume !(1 == ~E_6~0); 7098#L917-1 assume !(1 == ~E_7~0); 6701#L1168-1 [2018-12-08 18:43:43,251 INFO L796 eck$LassoCheckResult]: Loop: 6701#L1168-1 assume !false; 6702#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 6811#L734 assume !false; 7251#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6661#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6573#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 6717#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 6718#L631 assume !(0 != eval_~tmp~0); 6889#L749 start_simulation_~kernel_st~0 := 2; 6890#L519-1 start_simulation_~kernel_st~0 := 3; 7145#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7252#L759-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7036#L764-3 assume !(0 == ~T2_E~0); 6853#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6567#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6568#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7195#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7034#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6670#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6671#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7239#L804-3 assume !(0 == ~E_2~0); 7129#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6938#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6502#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6503#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7102#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7005#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7006#L366-27 assume 1 == ~m_pc~0; 7065#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6755#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6527#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6528#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6821#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6941#L385-27 assume 1 == ~t1_pc~0; 7147#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6902#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6678#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6679#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7262#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7263#L404-27 assume 1 == ~t2_pc~0; 7219#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7021#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6870#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6871#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7048#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6623#L423-27 assume 1 == ~t3_pc~0; 6599#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6600#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7111#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6680#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6681#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6684#L442-27 assume 1 == ~t4_pc~0; 6745#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6746#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7179#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7180#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7212#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6930#L461-27 assume 1 == ~t5_pc~0; 6922#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6923#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7207#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6990#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6991#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6992#L480-27 assume 1 == ~t6_pc~0; 7013#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7014#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7267#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6754#L993-27 assume !(0 != activate_threads_~tmp___5~0); 6730#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6731#L499-27 assume 1 == ~t7_pc~0; 7037#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6549#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6550#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6644#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7243#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 7244#L847-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7044#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6859#L857-3 assume !(1 == ~T3_E~0); 6580#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6581#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7198#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6955#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6676#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6677#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7237#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7125#L897-3 assume !(1 == ~E_3~0); 6935#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6498#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6499#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7100#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7002#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6662#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6576#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 6721#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 6722#L1187 assume !(0 == start_simulation_~tmp~3); 6757#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6663#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6554#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 6725#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 6726#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6523#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 6524#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 6635#L1200 assume !(0 != start_simulation_~tmp___0~1); 6701#L1168-1 [2018-12-08 18:43:43,251 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,251 INFO L82 PathProgramCache]: Analyzing trace with hash 1418288605, now seen corresponding path program 1 times [2018-12-08 18:43:43,251 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,251 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,252 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:43,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,265 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,265 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,266 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,266 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,266 INFO L82 PathProgramCache]: Analyzing trace with hash -291308708, now seen corresponding path program 3 times [2018-12-08 18:43:43,266 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,266 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,267 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,286 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,286 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,286 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,287 INFO L87 Difference]: Start difference. First operand 807 states and 1214 transitions. cyclomatic complexity: 408 Second operand 3 states. [2018-12-08 18:43:43,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,294 INFO L93 Difference]: Finished difference Result 807 states and 1213 transitions. [2018-12-08 18:43:43,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1213 transitions. [2018-12-08 18:43:43,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1213 transitions. [2018-12-08 18:43:43,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:43,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:43,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1213 transitions. [2018-12-08 18:43:43,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,299 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1213 transitions. [2018-12-08 18:43:43,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1213 transitions. [2018-12-08 18:43:43,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:43,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:43,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1213 transitions. [2018-12-08 18:43:43,305 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1213 transitions. [2018-12-08 18:43:43,305 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1213 transitions. [2018-12-08 18:43:43,306 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-12-08 18:43:43,306 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1213 transitions. [2018-12-08 18:43:43,307 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,308 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,308 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,308 INFO L794 eck$LassoCheckResult]: Stem: 8530#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8444#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8445#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8764#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 8616#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8409#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8410#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8765#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8603#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8348#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8247#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8248#L561-1 assume !(0 == ~M_E~0); 8875#L759-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8666#L764-1 assume !(0 == ~T2_E~0); 8481#L769-1 assume !(0 == ~T3_E~0); 8203#L774-1 assume !(0 == ~T4_E~0); 8204#L779-1 assume !(0 == ~T5_E~0); 8820#L784-1 assume !(0 == ~T6_E~0); 8652#L789-1 assume !(0 == ~T7_E~0); 8287#L794-1 assume !(0 == ~E_M~0); 8288#L799-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8859#L804-1 assume !(0 == ~E_2~0); 8749#L809-1 assume !(0 == ~E_3~0); 8558#L814-1 assume !(0 == ~E_4~0); 8121#L819-1 assume !(0 == ~E_5~0); 8122#L824-1 assume !(0 == ~E_6~0); 8722#L829-1 assume !(0 == ~E_7~0); 8624#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8625#L366 assume !(1 == ~m_pc~0); 8714#L366-2 is_master_triggered_~__retres1~0 := 0; 8380#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8184#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8185#L945 assume !(0 != activate_threads_~tmp~1); 8482#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8483#L385 assume 1 == ~t1_pc~0; 8783#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8547#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8327#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8328#L953 assume !(0 != activate_threads_~tmp___0~0); 8914#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8915#L404 assume !(1 == ~t2_pc~0); 8919#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 8651#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8617#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8618#L961 assume !(0 != activate_threads_~tmp___1~0); 8795#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8271#L423 assume 1 == ~t3_pc~0; 8226#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8227#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8733#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8515#L969 assume !(0 != activate_threads_~tmp___2~0); 8516#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8285#L442 assume 1 == ~t4_pc~0; 8286#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8277#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8767#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8814#L977 assume !(0 != activate_threads_~tmp___3~0); 8923#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8463#L461 assume !(1 == ~t5_pc~0); 8464#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 8467#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8829#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8752#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8753#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8604#L480 assume 1 == ~t6_pc~0; 8605#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8592#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8907#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8427#L993 assume !(0 != activate_threads_~tmp___5~0); 8428#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8430#L499 assume !(1 == ~t7_pc~0); 8707#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 8177#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8117#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8118#L1001 assume !(0 != activate_threads_~tmp___6~0); 8879#L1001-2 assume !(1 == ~M_E~0); 8877#L847-1 assume !(1 == ~T1_E~0); 8664#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8478#L857-1 assume !(1 == ~T3_E~0); 8199#L862-1 assume !(1 == ~T4_E~0); 8200#L867-1 assume !(1 == ~T5_E~0); 8818#L872-1 assume !(1 == ~T6_E~0); 8571#L877-1 assume !(1 == ~T7_E~0); 8295#L882-1 assume !(1 == ~E_M~0); 8296#L887-1 assume !(1 == ~E_1~0); 8863#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 8757#L897-1 assume !(1 == ~E_3~0); 8567#L902-1 assume !(1 == ~E_4~0); 8136#L907-1 assume !(1 == ~E_5~0); 8137#L912-1 assume !(1 == ~E_6~0); 8719#L917-1 assume !(1 == ~E_7~0); 8322#L1168-1 [2018-12-08 18:43:43,308 INFO L796 eck$LassoCheckResult]: Loop: 8322#L1168-1 assume !false; 8323#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 8432#L734 assume !false; 8872#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8282#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8194#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8338#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 8339#L631 assume !(0 != eval_~tmp~0); 8510#L749 start_simulation_~kernel_st~0 := 2; 8511#L519-1 start_simulation_~kernel_st~0 := 3; 8766#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8873#L759-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8656#L764-3 assume !(0 == ~T2_E~0); 8474#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8188#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8189#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8816#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8655#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8291#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8292#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8860#L804-3 assume !(0 == ~E_2~0); 8750#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8559#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8123#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8124#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8723#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8626#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8627#L366-27 assume 1 == ~m_pc~0; 8686#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8376#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8148#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8149#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8442#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8561#L385-27 assume 1 == ~t1_pc~0; 8768#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8523#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8299#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8300#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8883#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8884#L404-27 assume 1 == ~t2_pc~0; 8840#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8642#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8491#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8492#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8669#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8244#L423-27 assume 1 == ~t3_pc~0; 8220#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8221#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8732#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8301#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8302#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8305#L442-27 assume !(1 == ~t4_pc~0); 8369#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 8368#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8800#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8801#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8833#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8552#L461-27 assume 1 == ~t5_pc~0; 8544#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8545#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8828#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8611#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8612#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8613#L480-27 assume 1 == ~t6_pc~0; 8635#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8636#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8889#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8375#L993-27 assume !(0 != activate_threads_~tmp___5~0); 8351#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8352#L499-27 assume 1 == ~t7_pc~0; 8658#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8172#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8173#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8265#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8864#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 8865#L847-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8665#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8480#L857-3 assume !(1 == ~T3_E~0); 8201#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8202#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8819#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8576#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8297#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8298#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8858#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8746#L897-3 assume !(1 == ~E_3~0); 8556#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8119#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8120#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8721#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8623#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8283#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8197#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8342#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 8343#L1187 assume !(0 == start_simulation_~tmp~3); 8378#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8284#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8175#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8346#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 8347#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8144#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 8145#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 8256#L1200 assume !(0 != start_simulation_~tmp___0~1); 8322#L1168-1 [2018-12-08 18:43:43,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,309 INFO L82 PathProgramCache]: Analyzing trace with hash 93432411, now seen corresponding path program 1 times [2018-12-08 18:43:43,309 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,309 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,309 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:43,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,321 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,321 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,321 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,321 INFO L82 PathProgramCache]: Analyzing trace with hash -992876933, now seen corresponding path program 1 times [2018-12-08 18:43:43,321 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,322 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,347 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,347 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,347 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,348 INFO L87 Difference]: Start difference. First operand 807 states and 1213 transitions. cyclomatic complexity: 407 Second operand 3 states. [2018-12-08 18:43:43,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,357 INFO L93 Difference]: Finished difference Result 807 states and 1212 transitions. [2018-12-08 18:43:43,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1212 transitions. [2018-12-08 18:43:43,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1212 transitions. [2018-12-08 18:43:43,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:43,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:43,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1212 transitions. [2018-12-08 18:43:43,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,365 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1212 transitions. [2018-12-08 18:43:43,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1212 transitions. [2018-12-08 18:43:43,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:43,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:43,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1212 transitions. [2018-12-08 18:43:43,376 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1212 transitions. [2018-12-08 18:43:43,376 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1212 transitions. [2018-12-08 18:43:43,376 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-12-08 18:43:43,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1212 transitions. [2018-12-08 18:43:43,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,380 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,380 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,380 INFO L794 eck$LassoCheckResult]: Stem: 10151#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10065#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10066#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10385#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 10237#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10030#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10031#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10386#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10224#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9969#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9868#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9869#L561-1 assume !(0 == ~M_E~0); 10496#L759-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10287#L764-1 assume !(0 == ~T2_E~0); 10102#L769-1 assume !(0 == ~T3_E~0); 9824#L774-1 assume !(0 == ~T4_E~0); 9825#L779-1 assume !(0 == ~T5_E~0); 10441#L784-1 assume !(0 == ~T6_E~0); 10273#L789-1 assume !(0 == ~T7_E~0); 9908#L794-1 assume !(0 == ~E_M~0); 9909#L799-1 assume 0 == ~E_1~0;~E_1~0 := 1; 10480#L804-1 assume !(0 == ~E_2~0); 10370#L809-1 assume !(0 == ~E_3~0); 10179#L814-1 assume !(0 == ~E_4~0); 9742#L819-1 assume !(0 == ~E_5~0); 9743#L824-1 assume !(0 == ~E_6~0); 10343#L829-1 assume !(0 == ~E_7~0); 10245#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10246#L366 assume !(1 == ~m_pc~0); 10335#L366-2 is_master_triggered_~__retres1~0 := 0; 10001#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9805#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9806#L945 assume !(0 != activate_threads_~tmp~1); 10103#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10104#L385 assume 1 == ~t1_pc~0; 10404#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10168#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9948#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9949#L953 assume !(0 != activate_threads_~tmp___0~0); 10535#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10536#L404 assume !(1 == ~t2_pc~0); 10540#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 10272#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10238#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10239#L961 assume !(0 != activate_threads_~tmp___1~0); 10416#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9892#L423 assume 1 == ~t3_pc~0; 9847#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9848#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10354#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10136#L969 assume !(0 != activate_threads_~tmp___2~0); 10137#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9906#L442 assume 1 == ~t4_pc~0; 9907#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9898#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10388#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10435#L977 assume !(0 != activate_threads_~tmp___3~0); 10544#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10084#L461 assume !(1 == ~t5_pc~0); 10085#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 10088#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10450#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10373#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10374#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10225#L480 assume 1 == ~t6_pc~0; 10226#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10213#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10528#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10048#L993 assume !(0 != activate_threads_~tmp___5~0); 10049#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10051#L499 assume !(1 == ~t7_pc~0); 10328#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 9798#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9738#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9739#L1001 assume !(0 != activate_threads_~tmp___6~0); 10500#L1001-2 assume !(1 == ~M_E~0); 10498#L847-1 assume !(1 == ~T1_E~0); 10285#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10099#L857-1 assume !(1 == ~T3_E~0); 9820#L862-1 assume !(1 == ~T4_E~0); 9821#L867-1 assume !(1 == ~T5_E~0); 10439#L872-1 assume !(1 == ~T6_E~0); 10192#L877-1 assume !(1 == ~T7_E~0); 9916#L882-1 assume !(1 == ~E_M~0); 9917#L887-1 assume !(1 == ~E_1~0); 10484#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10378#L897-1 assume !(1 == ~E_3~0); 10188#L902-1 assume !(1 == ~E_4~0); 9757#L907-1 assume !(1 == ~E_5~0); 9758#L912-1 assume !(1 == ~E_6~0); 10340#L917-1 assume !(1 == ~E_7~0); 9943#L1168-1 [2018-12-08 18:43:43,381 INFO L796 eck$LassoCheckResult]: Loop: 9943#L1168-1 assume !false; 9944#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 10053#L734 assume !false; 10493#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9903#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9815#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9959#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9960#L631 assume !(0 != eval_~tmp~0); 10131#L749 start_simulation_~kernel_st~0 := 2; 10132#L519-1 start_simulation_~kernel_st~0 := 3; 10387#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10494#L759-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10277#L764-3 assume !(0 == ~T2_E~0); 10095#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9809#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9810#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10437#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10276#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9912#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9913#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10481#L804-3 assume !(0 == ~E_2~0); 10371#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10180#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9744#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9745#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10344#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10247#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10248#L366-27 assume 1 == ~m_pc~0; 10307#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9997#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9769#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9770#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10063#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10182#L385-27 assume 1 == ~t1_pc~0; 10389#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10144#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9920#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9921#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10504#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10505#L404-27 assume 1 == ~t2_pc~0; 10461#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10263#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10112#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10113#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10290#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9865#L423-27 assume 1 == ~t3_pc~0; 9841#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9842#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10353#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9922#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9923#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9926#L442-27 assume 1 == ~t4_pc~0; 9988#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9989#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10421#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10422#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10454#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10173#L461-27 assume 1 == ~t5_pc~0; 10165#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10166#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10449#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10232#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10233#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10234#L480-27 assume 1 == ~t6_pc~0; 10256#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10257#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10510#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9996#L993-27 assume !(0 != activate_threads_~tmp___5~0); 9972#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9973#L499-27 assume 1 == ~t7_pc~0; 10279#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9793#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9794#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9886#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10485#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 10486#L847-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10286#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10101#L857-3 assume !(1 == ~T3_E~0); 9822#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9823#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10440#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10197#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9918#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9919#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10479#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10367#L897-3 assume !(1 == ~E_3~0); 10177#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9740#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9741#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10342#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10244#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9904#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9818#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9963#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 9964#L1187 assume !(0 == start_simulation_~tmp~3); 9999#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9905#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9796#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9967#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 9968#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9765#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 9766#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 9877#L1200 assume !(0 != start_simulation_~tmp___0~1); 9943#L1168-1 [2018-12-08 18:43:43,381 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,381 INFO L82 PathProgramCache]: Analyzing trace with hash -1473325539, now seen corresponding path program 1 times [2018-12-08 18:43:43,381 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,381 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,382 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,397 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,397 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,397 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,397 INFO L82 PathProgramCache]: Analyzing trace with hash -291308708, now seen corresponding path program 4 times [2018-12-08 18:43:43,397 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,397 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,398 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,420 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,420 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,420 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,420 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,421 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,421 INFO L87 Difference]: Start difference. First operand 807 states and 1212 transitions. cyclomatic complexity: 406 Second operand 3 states. [2018-12-08 18:43:43,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,428 INFO L93 Difference]: Finished difference Result 807 states and 1211 transitions. [2018-12-08 18:43:43,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1211 transitions. [2018-12-08 18:43:43,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1211 transitions. [2018-12-08 18:43:43,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:43,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:43,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1211 transitions. [2018-12-08 18:43:43,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,433 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1211 transitions. [2018-12-08 18:43:43,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1211 transitions. [2018-12-08 18:43:43,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:43,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:43,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1211 transitions. [2018-12-08 18:43:43,440 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1211 transitions. [2018-12-08 18:43:43,440 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1211 transitions. [2018-12-08 18:43:43,440 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-12-08 18:43:43,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1211 transitions. [2018-12-08 18:43:43,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,442 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,443 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,443 INFO L794 eck$LassoCheckResult]: Stem: 11772#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 11686#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11687#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12006#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 11858#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11651#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11652#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12007#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11845#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11590#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11489#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11490#L561-1 assume !(0 == ~M_E~0); 12117#L759-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11908#L764-1 assume !(0 == ~T2_E~0); 11723#L769-1 assume !(0 == ~T3_E~0); 11445#L774-1 assume !(0 == ~T4_E~0); 11446#L779-1 assume !(0 == ~T5_E~0); 12062#L784-1 assume !(0 == ~T6_E~0); 11894#L789-1 assume !(0 == ~T7_E~0); 11529#L794-1 assume !(0 == ~E_M~0); 11530#L799-1 assume 0 == ~E_1~0;~E_1~0 := 1; 12101#L804-1 assume !(0 == ~E_2~0); 11991#L809-1 assume !(0 == ~E_3~0); 11800#L814-1 assume !(0 == ~E_4~0); 11363#L819-1 assume !(0 == ~E_5~0); 11364#L824-1 assume !(0 == ~E_6~0); 11964#L829-1 assume !(0 == ~E_7~0); 11866#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11867#L366 assume !(1 == ~m_pc~0); 11956#L366-2 is_master_triggered_~__retres1~0 := 0; 11622#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11426#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11427#L945 assume !(0 != activate_threads_~tmp~1); 11724#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11725#L385 assume 1 == ~t1_pc~0; 12025#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11789#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11569#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11570#L953 assume !(0 != activate_threads_~tmp___0~0); 12156#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12157#L404 assume !(1 == ~t2_pc~0); 12161#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 11893#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11859#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11860#L961 assume !(0 != activate_threads_~tmp___1~0); 12037#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11513#L423 assume 1 == ~t3_pc~0; 11468#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11469#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11975#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11757#L969 assume !(0 != activate_threads_~tmp___2~0); 11758#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11527#L442 assume 1 == ~t4_pc~0; 11528#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11519#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12009#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12056#L977 assume !(0 != activate_threads_~tmp___3~0); 12165#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11705#L461 assume !(1 == ~t5_pc~0); 11706#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 11709#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12071#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11994#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11995#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11846#L480 assume 1 == ~t6_pc~0; 11847#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11834#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12149#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11669#L993 assume !(0 != activate_threads_~tmp___5~0); 11670#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11672#L499 assume !(1 == ~t7_pc~0); 11949#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 11419#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11359#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11360#L1001 assume !(0 != activate_threads_~tmp___6~0); 12121#L1001-2 assume !(1 == ~M_E~0); 12119#L847-1 assume !(1 == ~T1_E~0); 11906#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11720#L857-1 assume !(1 == ~T3_E~0); 11441#L862-1 assume !(1 == ~T4_E~0); 11442#L867-1 assume !(1 == ~T5_E~0); 12060#L872-1 assume !(1 == ~T6_E~0); 11813#L877-1 assume !(1 == ~T7_E~0); 11537#L882-1 assume !(1 == ~E_M~0); 11538#L887-1 assume !(1 == ~E_1~0); 12105#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11999#L897-1 assume !(1 == ~E_3~0); 11809#L902-1 assume !(1 == ~E_4~0); 11378#L907-1 assume !(1 == ~E_5~0); 11379#L912-1 assume !(1 == ~E_6~0); 11961#L917-1 assume !(1 == ~E_7~0); 11564#L1168-1 [2018-12-08 18:43:43,443 INFO L796 eck$LassoCheckResult]: Loop: 11564#L1168-1 assume !false; 11565#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 11674#L734 assume !false; 12114#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11524#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11436#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11580#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 11581#L631 assume !(0 != eval_~tmp~0); 11752#L749 start_simulation_~kernel_st~0 := 2; 11753#L519-1 start_simulation_~kernel_st~0 := 3; 12008#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12115#L759-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11898#L764-3 assume !(0 == ~T2_E~0); 11716#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11430#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11431#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12058#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11897#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11533#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11534#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12102#L804-3 assume !(0 == ~E_2~0); 11992#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11801#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11365#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11366#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11965#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11868#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11869#L366-27 assume 1 == ~m_pc~0; 11928#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 11618#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11390#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11391#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11684#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11803#L385-27 assume 1 == ~t1_pc~0; 12010#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11765#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11541#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11542#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12125#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12126#L404-27 assume 1 == ~t2_pc~0; 12082#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11884#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11733#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11734#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11911#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11486#L423-27 assume 1 == ~t3_pc~0; 11462#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11463#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11974#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11543#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11544#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11547#L442-27 assume 1 == ~t4_pc~0; 11609#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11610#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12042#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12043#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12075#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11794#L461-27 assume 1 == ~t5_pc~0; 11786#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11787#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12070#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11853#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11854#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11855#L480-27 assume 1 == ~t6_pc~0; 11877#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11878#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12131#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11617#L993-27 assume !(0 != activate_threads_~tmp___5~0); 11593#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11594#L499-27 assume 1 == ~t7_pc~0; 11900#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11414#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11415#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11507#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12106#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 12107#L847-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11907#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11722#L857-3 assume !(1 == ~T3_E~0); 11443#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11444#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12061#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11818#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11539#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11540#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12100#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11988#L897-3 assume !(1 == ~E_3~0); 11798#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11361#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11362#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11963#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11865#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11525#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11439#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11584#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 11585#L1187 assume !(0 == start_simulation_~tmp~3); 11620#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11526#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11417#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11588#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 11589#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11386#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 11387#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 11498#L1200 assume !(0 != start_simulation_~tmp___0~1); 11564#L1168-1 [2018-12-08 18:43:43,443 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,443 INFO L82 PathProgramCache]: Analyzing trace with hash -415487461, now seen corresponding path program 1 times [2018-12-08 18:43:43,443 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,443 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,444 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:43,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,461 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,461 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:43,461 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,461 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,461 INFO L82 PathProgramCache]: Analyzing trace with hash -291308708, now seen corresponding path program 5 times [2018-12-08 18:43:43,461 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,461 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,462 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,479 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,479 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,479 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,479 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,479 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,479 INFO L87 Difference]: Start difference. First operand 807 states and 1211 transitions. cyclomatic complexity: 405 Second operand 3 states. [2018-12-08 18:43:43,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,500 INFO L93 Difference]: Finished difference Result 807 states and 1206 transitions. [2018-12-08 18:43:43,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1206 transitions. [2018-12-08 18:43:43,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1206 transitions. [2018-12-08 18:43:43,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:43,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:43,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1206 transitions. [2018-12-08 18:43:43,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,505 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1206 transitions. [2018-12-08 18:43:43,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1206 transitions. [2018-12-08 18:43:43,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:43,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:43,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1206 transitions. [2018-12-08 18:43:43,511 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1206 transitions. [2018-12-08 18:43:43,511 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1206 transitions. [2018-12-08 18:43:43,511 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-12-08 18:43:43,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1206 transitions. [2018-12-08 18:43:43,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,514 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,514 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,514 INFO L794 eck$LassoCheckResult]: Stem: 13393#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 13307#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13308#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13627#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 13479#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13274#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13275#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13628#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13466#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13211#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13110#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13111#L561-1 assume !(0 == ~M_E~0); 13738#L759-1 assume !(0 == ~T1_E~0); 13530#L764-1 assume !(0 == ~T2_E~0); 13344#L769-1 assume !(0 == ~T3_E~0); 13066#L774-1 assume !(0 == ~T4_E~0); 13067#L779-1 assume !(0 == ~T5_E~0); 13683#L784-1 assume !(0 == ~T6_E~0); 13515#L789-1 assume !(0 == ~T7_E~0); 13150#L794-1 assume !(0 == ~E_M~0); 13151#L799-1 assume 0 == ~E_1~0;~E_1~0 := 1; 13722#L804-1 assume !(0 == ~E_2~0); 13612#L809-1 assume !(0 == ~E_3~0); 13421#L814-1 assume !(0 == ~E_4~0); 12984#L819-1 assume !(0 == ~E_5~0); 12985#L824-1 assume !(0 == ~E_6~0); 13585#L829-1 assume !(0 == ~E_7~0); 13487#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13488#L366 assume !(1 == ~m_pc~0); 13577#L366-2 is_master_triggered_~__retres1~0 := 0; 13246#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13049#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13050#L945 assume !(0 != activate_threads_~tmp~1); 13345#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13346#L385 assume 1 == ~t1_pc~0; 13646#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13410#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13190#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13191#L953 assume !(0 != activate_threads_~tmp___0~0); 13777#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13778#L404 assume !(1 == ~t2_pc~0); 13782#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 13514#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13480#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13481#L961 assume !(0 != activate_threads_~tmp___1~0); 13658#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13135#L423 assume 1 == ~t3_pc~0; 13089#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13090#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13596#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13378#L969 assume !(0 != activate_threads_~tmp___2~0); 13379#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13148#L442 assume 1 == ~t4_pc~0; 13149#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13140#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13630#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13677#L977 assume !(0 != activate_threads_~tmp___3~0); 13786#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13326#L461 assume !(1 == ~t5_pc~0); 13327#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 13330#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13692#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13615#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13616#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13467#L480 assume 1 == ~t6_pc~0; 13468#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13455#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13771#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13290#L993 assume !(0 != activate_threads_~tmp___5~0); 13291#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13293#L499 assume !(1 == ~t7_pc~0); 13571#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 13040#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12980#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12981#L1001 assume !(0 != activate_threads_~tmp___6~0); 13742#L1001-2 assume !(1 == ~M_E~0); 13740#L847-1 assume !(1 == ~T1_E~0); 13527#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13341#L857-1 assume !(1 == ~T3_E~0); 13062#L862-1 assume !(1 == ~T4_E~0); 13063#L867-1 assume !(1 == ~T5_E~0); 13681#L872-1 assume !(1 == ~T6_E~0); 13435#L877-1 assume !(1 == ~T7_E~0); 13158#L882-1 assume !(1 == ~E_M~0); 13159#L887-1 assume !(1 == ~E_1~0); 13726#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13620#L897-1 assume !(1 == ~E_3~0); 13430#L902-1 assume !(1 == ~E_4~0); 12999#L907-1 assume !(1 == ~E_5~0); 13000#L912-1 assume !(1 == ~E_6~0); 13582#L917-1 assume !(1 == ~E_7~0); 13185#L1168-1 [2018-12-08 18:43:43,514 INFO L796 eck$LassoCheckResult]: Loop: 13185#L1168-1 assume !false; 13186#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 13295#L734 assume !false; 13736#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13145#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13057#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13201#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 13202#L631 assume !(0 != eval_~tmp~0); 13373#L749 start_simulation_~kernel_st~0 := 2; 13374#L519-1 start_simulation_~kernel_st~0 := 3; 13629#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13735#L759-4 assume !(0 == ~T1_E~0); 13519#L764-3 assume !(0 == ~T2_E~0); 13337#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13051#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13052#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13679#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13518#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13154#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13155#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13723#L804-3 assume !(0 == ~E_2~0); 13613#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13422#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12986#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12987#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13586#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13489#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13490#L366-27 assume 1 == ~m_pc~0; 13549#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 13239#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13011#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13012#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13305#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13424#L385-27 assume !(1 == ~t1_pc~0); 13632#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 13386#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13162#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13163#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13746#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13747#L404-27 assume 1 == ~t2_pc~0; 13703#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13505#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13354#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13355#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13532#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13107#L423-27 assume 1 == ~t3_pc~0; 13083#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13084#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13595#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13164#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13165#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13168#L442-27 assume !(1 == ~t4_pc~0); 13232#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 13231#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13663#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13664#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13696#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13415#L461-27 assume !(1 == ~t5_pc~0); 13409#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 13408#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13691#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13474#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13475#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13476#L480-27 assume 1 == ~t6_pc~0; 13498#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13499#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13752#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13238#L993-27 assume !(0 != activate_threads_~tmp___5~0); 13214#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13215#L499-27 assume 1 == ~t7_pc~0; 13521#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13035#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13036#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13128#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13727#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 13728#L847-3 assume !(1 == ~T1_E~0); 13528#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13343#L857-3 assume !(1 == ~T3_E~0); 13064#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13065#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13682#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13439#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13160#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13161#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13721#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13609#L897-3 assume !(1 == ~E_3~0); 13419#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12982#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12983#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13584#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13486#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13146#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13060#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13205#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 13206#L1187 assume !(0 == start_simulation_~tmp~3); 13241#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13147#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13038#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13209#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 13210#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13007#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 13008#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 13119#L1200 assume !(0 != start_simulation_~tmp___0~1); 13185#L1168-1 [2018-12-08 18:43:43,514 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,514 INFO L82 PathProgramCache]: Analyzing trace with hash -175247715, now seen corresponding path program 1 times [2018-12-08 18:43:43,514 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,514 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,515 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:43,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,532 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,532 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:43,532 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,532 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1932098635, now seen corresponding path program 1 times [2018-12-08 18:43:43,533 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,533 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,560 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,560 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,560 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,561 INFO L87 Difference]: Start difference. First operand 807 states and 1206 transitions. cyclomatic complexity: 400 Second operand 3 states. [2018-12-08 18:43:43,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,595 INFO L93 Difference]: Finished difference Result 807 states and 1191 transitions. [2018-12-08 18:43:43,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1191 transitions. [2018-12-08 18:43:43,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1191 transitions. [2018-12-08 18:43:43,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2018-12-08 18:43:43,602 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2018-12-08 18:43:43,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1191 transitions. [2018-12-08 18:43:43,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,603 INFO L705 BuchiCegarLoop]: Abstraction has 807 states and 1191 transitions. [2018-12-08 18:43:43,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1191 transitions. [2018-12-08 18:43:43,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2018-12-08 18:43:43,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-08 18:43:43,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1191 transitions. [2018-12-08 18:43:43,615 INFO L728 BuchiCegarLoop]: Abstraction has 807 states and 1191 transitions. [2018-12-08 18:43:43,615 INFO L608 BuchiCegarLoop]: Abstraction has 807 states and 1191 transitions. [2018-12-08 18:43:43,615 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-12-08 18:43:43,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1191 transitions. [2018-12-08 18:43:43,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2018-12-08 18:43:43,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,619 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,619 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,619 INFO L794 eck$LassoCheckResult]: Stem: 15014#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14928#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14929#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15248#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 15100#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14895#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14896#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15249#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15087#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14832#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14731#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14732#L561-1 assume !(0 == ~M_E~0); 15359#L759-1 assume !(0 == ~T1_E~0); 15151#L764-1 assume !(0 == ~T2_E~0); 14965#L769-1 assume !(0 == ~T3_E~0); 14687#L774-1 assume !(0 == ~T4_E~0); 14688#L779-1 assume !(0 == ~T5_E~0); 15304#L784-1 assume !(0 == ~T6_E~0); 15136#L789-1 assume !(0 == ~T7_E~0); 14771#L794-1 assume !(0 == ~E_M~0); 14772#L799-1 assume !(0 == ~E_1~0); 15343#L804-1 assume !(0 == ~E_2~0); 15233#L809-1 assume !(0 == ~E_3~0); 15042#L814-1 assume !(0 == ~E_4~0); 14605#L819-1 assume !(0 == ~E_5~0); 14606#L824-1 assume !(0 == ~E_6~0); 15206#L829-1 assume !(0 == ~E_7~0); 15108#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15109#L366 assume !(1 == ~m_pc~0); 15198#L366-2 is_master_triggered_~__retres1~0 := 0; 14864#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14670#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14671#L945 assume !(0 != activate_threads_~tmp~1); 14966#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14967#L385 assume !(1 == ~t1_pc~0); 15268#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 15031#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14811#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14812#L953 assume !(0 != activate_threads_~tmp___0~0); 15398#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15399#L404 assume !(1 == ~t2_pc~0); 15403#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 15135#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15101#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15102#L961 assume !(0 != activate_threads_~tmp___1~0); 15279#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14755#L423 assume 1 == ~t3_pc~0; 14710#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14711#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15217#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14999#L969 assume !(0 != activate_threads_~tmp___2~0); 15000#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14769#L442 assume 1 == ~t4_pc~0; 14770#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14761#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15251#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15298#L977 assume !(0 != activate_threads_~tmp___3~0); 15407#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14947#L461 assume !(1 == ~t5_pc~0); 14948#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 14951#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15313#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15236#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15237#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15088#L480 assume 1 == ~t6_pc~0; 15089#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15076#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15391#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14911#L993 assume !(0 != activate_threads_~tmp___5~0); 14912#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14914#L499 assume !(1 == ~t7_pc~0); 15191#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 14661#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14601#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14602#L1001 assume !(0 != activate_threads_~tmp___6~0); 15363#L1001-2 assume !(1 == ~M_E~0); 15361#L847-1 assume !(1 == ~T1_E~0); 15148#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14962#L857-1 assume !(1 == ~T3_E~0); 14683#L862-1 assume !(1 == ~T4_E~0); 14684#L867-1 assume !(1 == ~T5_E~0); 15302#L872-1 assume !(1 == ~T6_E~0); 15056#L877-1 assume !(1 == ~T7_E~0); 14779#L882-1 assume !(1 == ~E_M~0); 14780#L887-1 assume !(1 == ~E_1~0); 15347#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15241#L897-1 assume !(1 == ~E_3~0); 15051#L902-1 assume !(1 == ~E_4~0); 14620#L907-1 assume !(1 == ~E_5~0); 14621#L912-1 assume !(1 == ~E_6~0); 15203#L917-1 assume !(1 == ~E_7~0); 14806#L1168-1 [2018-12-08 18:43:43,619 INFO L796 eck$LassoCheckResult]: Loop: 14806#L1168-1 assume !false; 14807#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 14916#L734 assume !false; 15356#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14766#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14678#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14822#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 14823#L631 assume !(0 != eval_~tmp~0); 14994#L749 start_simulation_~kernel_st~0 := 2; 14995#L519-1 start_simulation_~kernel_st~0 := 3; 15250#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15357#L759-4 assume !(0 == ~T1_E~0); 15141#L764-3 assume !(0 == ~T2_E~0); 14958#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14672#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14673#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15300#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15139#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14775#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14776#L799-3 assume !(0 == ~E_1~0); 15344#L804-3 assume !(0 == ~E_2~0); 15234#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15043#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14607#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14608#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15207#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15110#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15111#L366-27 assume 1 == ~m_pc~0; 15170#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 14860#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14632#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14633#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14926#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15046#L385-27 assume !(1 == ~t1_pc~0); 15253#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 15007#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14783#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14784#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15367#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15368#L404-27 assume 1 == ~t2_pc~0; 15324#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15126#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14975#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14976#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15155#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14728#L423-27 assume 1 == ~t3_pc~0; 14704#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14705#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15216#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14785#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14786#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14789#L442-27 assume 1 == ~t4_pc~0; 14850#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14851#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15284#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15285#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15317#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15035#L461-27 assume 1 == ~t5_pc~0; 15027#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15028#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15312#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15095#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15096#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15097#L480-27 assume !(1 == ~t6_pc~0); 15120#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 15119#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15372#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14859#L993-27 assume !(0 != activate_threads_~tmp___5~0); 14835#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14836#L499-27 assume 1 == ~t7_pc~0; 15142#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 14654#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14655#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14749#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15348#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 15349#L847-3 assume !(1 == ~T1_E~0); 15149#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14964#L857-3 assume !(1 == ~T3_E~0); 14685#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14686#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15303#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15060#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14781#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14782#L887-3 assume !(1 == ~E_1~0); 15342#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15230#L897-3 assume !(1 == ~E_3~0); 15040#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14603#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14604#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15205#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15107#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14767#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14681#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14826#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 14827#L1187 assume !(0 == start_simulation_~tmp~3); 14862#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14768#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14659#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14830#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 14831#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14628#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 14629#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 14740#L1200 assume !(0 != start_simulation_~tmp___0~1); 14806#L1168-1 [2018-12-08 18:43:43,620 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,620 INFO L82 PathProgramCache]: Analyzing trace with hash -902331040, now seen corresponding path program 1 times [2018-12-08 18:43:43,620 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,620 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,641 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,641 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:43,642 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,642 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,642 INFO L82 PathProgramCache]: Analyzing trace with hash 2075653458, now seen corresponding path program 1 times [2018-12-08 18:43:43,642 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,642 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,662 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,662 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,663 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,663 INFO L87 Difference]: Start difference. First operand 807 states and 1191 transitions. cyclomatic complexity: 385 Second operand 3 states. [2018-12-08 18:43:43,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,722 INFO L93 Difference]: Finished difference Result 1448 states and 2120 transitions. [2018-12-08 18:43:43,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1448 states and 2120 transitions. [2018-12-08 18:43:43,726 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1348 [2018-12-08 18:43:43,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1448 states to 1448 states and 2120 transitions. [2018-12-08 18:43:43,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1448 [2018-12-08 18:43:43,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1448 [2018-12-08 18:43:43,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1448 states and 2120 transitions. [2018-12-08 18:43:43,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,731 INFO L705 BuchiCegarLoop]: Abstraction has 1448 states and 2120 transitions. [2018-12-08 18:43:43,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states and 2120 transitions. [2018-12-08 18:43:43,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 1446. [2018-12-08 18:43:43,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1446 states. [2018-12-08 18:43:43,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2118 transitions. [2018-12-08 18:43:43,748 INFO L728 BuchiCegarLoop]: Abstraction has 1446 states and 2118 transitions. [2018-12-08 18:43:43,748 INFO L608 BuchiCegarLoop]: Abstraction has 1446 states and 2118 transitions. [2018-12-08 18:43:43,748 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-12-08 18:43:43,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2118 transitions. [2018-12-08 18:43:43,752 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1346 [2018-12-08 18:43:43,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,753 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,753 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,754 INFO L794 eck$LassoCheckResult]: Stem: 17292#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 17205#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 17206#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17529#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 17379#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17171#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17172#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17530#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17365#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17108#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16992#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16993#L561-1 assume !(0 == ~M_E~0); 17644#L759-1 assume !(0 == ~T1_E~0); 17430#L764-1 assume !(0 == ~T2_E~0); 17242#L769-1 assume !(0 == ~T3_E~0); 16949#L774-1 assume !(0 == ~T4_E~0); 16950#L779-1 assume !(0 == ~T5_E~0); 17586#L784-1 assume !(0 == ~T6_E~0); 17415#L789-1 assume !(0 == ~T7_E~0); 17047#L794-1 assume !(0 == ~E_M~0); 17048#L799-1 assume !(0 == ~E_1~0); 17628#L804-1 assume !(0 == ~E_2~0); 17514#L809-1 assume !(0 == ~E_3~0); 17320#L814-1 assume !(0 == ~E_4~0); 16867#L819-1 assume !(0 == ~E_5~0); 16868#L824-1 assume !(0 == ~E_6~0); 17487#L829-1 assume !(0 == ~E_7~0); 17387#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17388#L366 assume !(1 == ~m_pc~0); 17478#L366-2 is_master_triggered_~__retres1~0 := 0; 17140#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16932#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16933#L945 assume !(0 != activate_threads_~tmp~1); 17243#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17244#L385 assume !(1 == ~t1_pc~0); 17549#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 17309#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17087#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17088#L953 assume !(0 != activate_threads_~tmp___0~0); 17686#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17687#L404 assume !(1 == ~t2_pc~0); 17694#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 17414#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17380#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17381#L961 assume !(0 != activate_threads_~tmp___1~0); 17561#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17029#L423 assume !(1 == ~t3_pc~0); 17030#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 17034#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17498#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17276#L969 assume !(0 != activate_threads_~tmp___2~0); 17277#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17045#L442 assume 1 == ~t4_pc~0; 17046#L443 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17037#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17532#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17580#L977 assume !(0 != activate_threads_~tmp___3~0); 17700#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17224#L461 assume !(1 == ~t5_pc~0); 17225#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 17228#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17598#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17517#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17518#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17366#L480 assume 1 == ~t6_pc~0; 17367#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17354#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17678#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17188#L993 assume !(0 != activate_threads_~tmp___5~0); 17189#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17191#L499 assume !(1 == ~t7_pc~0); 17471#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 16923#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16863#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16864#L1001 assume !(0 != activate_threads_~tmp___6~0); 17648#L1001-2 assume !(1 == ~M_E~0); 17646#L847-1 assume !(1 == ~T1_E~0); 17427#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17239#L857-1 assume !(1 == ~T3_E~0); 16945#L862-1 assume !(1 == ~T4_E~0); 16946#L867-1 assume !(1 == ~T5_E~0); 17584#L872-1 assume !(1 == ~T6_E~0); 17334#L877-1 assume !(1 == ~T7_E~0); 17055#L882-1 assume !(1 == ~E_M~0); 17056#L887-1 assume !(1 == ~E_1~0); 17632#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17522#L897-1 assume !(1 == ~E_3~0); 17329#L902-1 assume !(1 == ~E_4~0); 16882#L907-1 assume !(1 == ~E_5~0); 16883#L912-1 assume !(1 == ~E_6~0); 17484#L917-1 assume !(1 == ~E_7~0); 17082#L1168-1 [2018-12-08 18:43:43,754 INFO L796 eck$LassoCheckResult]: Loop: 17082#L1168-1 assume !false; 17083#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 17193#L734 assume !false; 17641#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 17042#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16940#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17098#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 17099#L631 assume !(0 != eval_~tmp~0); 17483#L749 start_simulation_~kernel_st~0 := 2; 18273#L519-1 start_simulation_~kernel_st~0 := 3; 18272#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 18271#L759-4 assume !(0 == ~T1_E~0); 18270#L764-3 assume !(0 == ~T2_E~0); 18269#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18268#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18267#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18266#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18265#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18263#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18260#L799-3 assume !(0 == ~E_1~0); 17629#L804-3 assume !(0 == ~E_2~0); 17515#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17321#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16869#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16870#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17488#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17389#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17390#L366-27 assume 1 == ~m_pc~0; 17450#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 17136#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16894#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16895#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17203#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17324#L385-27 assume !(1 == ~t1_pc~0); 17534#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 17284#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17059#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17060#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17652#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17653#L404-27 assume 1 == ~t2_pc~0; 17609#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17405#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17252#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17253#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17434#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16988#L423-27 assume !(1 == ~t3_pc~0); 16989#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 16996#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17497#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17061#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17062#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17065#L442-27 assume 1 == ~t4_pc~0; 17126#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17127#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17566#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17567#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17602#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17313#L461-27 assume 1 == ~t5_pc~0; 17305#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 17306#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18275#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 18274#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17375#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17376#L480-27 assume 1 == ~t6_pc~0; 17397#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17398#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17657#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17135#L993-27 assume !(0 != activate_threads_~tmp___5~0); 17111#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17112#L499-27 assume 1 == ~t7_pc~0; 17421#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16916#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16917#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17022#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17633#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 17634#L847-3 assume !(1 == ~T1_E~0); 17428#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17241#L857-3 assume !(1 == ~T3_E~0); 16947#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16948#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17585#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17338#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17057#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17058#L887-3 assume !(1 == ~E_1~0); 17627#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17511#L897-3 assume !(1 == ~E_3~0); 17318#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16865#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16866#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17486#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17386#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 17043#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16943#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17102#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 17103#L1187 assume !(0 == start_simulation_~tmp~3); 17138#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 17044#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16921#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17106#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 17107#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16890#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 16891#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 17009#L1200 assume !(0 != start_simulation_~tmp___0~1); 17082#L1168-1 [2018-12-08 18:43:43,754 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,754 INFO L82 PathProgramCache]: Analyzing trace with hash -1775808735, now seen corresponding path program 1 times [2018-12-08 18:43:43,754 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,754 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,755 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,755 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,755 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,780 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,780 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:43,781 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,781 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,781 INFO L82 PathProgramCache]: Analyzing trace with hash 534014866, now seen corresponding path program 1 times [2018-12-08 18:43:43,781 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,781 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,781 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,782 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,809 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,810 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,810 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,810 INFO L87 Difference]: Start difference. First operand 1446 states and 2118 transitions. cyclomatic complexity: 674 Second operand 3 states. [2018-12-08 18:43:43,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:43,869 INFO L93 Difference]: Finished difference Result 2663 states and 3875 transitions. [2018-12-08 18:43:43,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:43,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2663 states and 3875 transitions. [2018-12-08 18:43:43,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2558 [2018-12-08 18:43:43,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2663 states to 2663 states and 3875 transitions. [2018-12-08 18:43:43,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2663 [2018-12-08 18:43:43,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2663 [2018-12-08 18:43:43,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2663 states and 3875 transitions. [2018-12-08 18:43:43,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:43,885 INFO L705 BuchiCegarLoop]: Abstraction has 2663 states and 3875 transitions. [2018-12-08 18:43:43,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2663 states and 3875 transitions. [2018-12-08 18:43:43,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2663 to 2659. [2018-12-08 18:43:43,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2659 states. [2018-12-08 18:43:43,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2659 states to 2659 states and 3871 transitions. [2018-12-08 18:43:43,917 INFO L728 BuchiCegarLoop]: Abstraction has 2659 states and 3871 transitions. [2018-12-08 18:43:43,917 INFO L608 BuchiCegarLoop]: Abstraction has 2659 states and 3871 transitions. [2018-12-08 18:43:43,917 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-12-08 18:43:43,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2659 states and 3871 transitions. [2018-12-08 18:43:43,921 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2554 [2018-12-08 18:43:43,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:43,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:43,921 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,922 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:43,922 INFO L794 eck$LassoCheckResult]: Stem: 21414#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 21324#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 21325#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21657#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 21501#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21286#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21287#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21658#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21488#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21225#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21108#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21109#L561-1 assume !(0 == ~M_E~0); 21774#L759-1 assume !(0 == ~T1_E~0); 21552#L764-1 assume !(0 == ~T2_E~0); 21363#L769-1 assume !(0 == ~T3_E~0); 21065#L774-1 assume !(0 == ~T4_E~0); 21066#L779-1 assume !(0 == ~T5_E~0); 21715#L784-1 assume !(0 == ~T6_E~0); 21538#L789-1 assume !(0 == ~T7_E~0); 21164#L794-1 assume !(0 == ~E_M~0); 21165#L799-1 assume !(0 == ~E_1~0); 21756#L804-1 assume !(0 == ~E_2~0); 21640#L809-1 assume !(0 == ~E_3~0); 21442#L814-1 assume !(0 == ~E_4~0); 20983#L819-1 assume !(0 == ~E_5~0); 20984#L824-1 assume !(0 == ~E_6~0); 21611#L829-1 assume !(0 == ~E_7~0); 21509#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21510#L366 assume !(1 == ~m_pc~0); 21600#L366-2 is_master_triggered_~__retres1~0 := 0; 21257#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21046#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21047#L945 assume !(0 != activate_threads_~tmp~1); 21364#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21365#L385 assume !(1 == ~t1_pc~0); 21678#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 21431#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21204#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21205#L953 assume !(0 != activate_threads_~tmp___0~0); 21814#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21815#L404 assume !(1 == ~t2_pc~0); 21825#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 21537#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21502#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21503#L961 assume !(0 != activate_threads_~tmp___1~0); 21689#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21145#L423 assume !(1 == ~t3_pc~0); 21146#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 21151#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21622#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21397#L969 assume !(0 != activate_threads_~tmp___2~0); 21398#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21163#L442 assume !(1 == ~t4_pc~0); 21153#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 21154#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21660#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21709#L977 assume !(0 != activate_threads_~tmp___3~0); 21829#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21343#L461 assume !(1 == ~t5_pc~0); 21344#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 21347#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21726#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21643#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21644#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21489#L480 assume 1 == ~t6_pc~0; 21490#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 21477#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21807#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21307#L993 assume !(0 != activate_threads_~tmp___5~0); 21308#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21310#L499 assume !(1 == ~t7_pc~0); 21593#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 21039#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 20979#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20980#L1001 assume !(0 != activate_threads_~tmp___6~0); 21779#L1001-2 assume !(1 == ~M_E~0); 21777#L847-1 assume !(1 == ~T1_E~0); 21550#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21360#L857-1 assume !(1 == ~T3_E~0); 21061#L862-1 assume !(1 == ~T4_E~0); 21062#L867-1 assume !(1 == ~T5_E~0); 21713#L872-1 assume !(1 == ~T6_E~0); 21455#L877-1 assume !(1 == ~T7_E~0); 21172#L882-1 assume !(1 == ~E_M~0); 21173#L887-1 assume !(1 == ~E_1~0); 21760#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21648#L897-1 assume !(1 == ~E_3~0); 21451#L902-1 assume !(1 == ~E_4~0); 20998#L907-1 assume !(1 == ~E_5~0); 20999#L912-1 assume !(1 == ~E_6~0); 21606#L917-1 assume !(1 == ~E_7~0); 21607#L1168-1 [2018-12-08 18:43:43,922 INFO L796 eck$LassoCheckResult]: Loop: 21607#L1168-1 assume !false; 23074#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 23063#L734 assume !false; 23060#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 22965#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 22953#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 22948#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 22941#L631 assume !(0 != eval_~tmp~0); 21392#L749 start_simulation_~kernel_st~0 := 2; 21393#L519-1 start_simulation_~kernel_st~0 := 3; 21659#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 21772#L759-4 assume !(0 == ~T1_E~0); 21542#L764-3 assume !(0 == ~T2_E~0); 21355#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21356#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23583#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23582#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23581#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23580#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23579#L799-3 assume !(0 == ~E_1~0); 23578#L804-3 assume !(0 == ~E_2~0); 23577#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23576#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23575#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23574#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23573#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23572#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23571#L366-27 assume 1 == ~m_pc~0; 23569#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 23567#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23565#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 23563#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23561#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23559#L385-27 assume !(1 == ~t1_pc~0); 23556#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 23554#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23552#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 23550#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 23548#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23546#L404-27 assume 1 == ~t2_pc~0; 23543#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 23541#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23539#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23537#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23535#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23533#L423-27 assume !(1 == ~t3_pc~0); 23531#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 23529#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23526#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23524#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23522#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23520#L442-27 assume !(1 == ~t4_pc~0); 23518#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 23515#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23513#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23511#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 23509#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23507#L461-27 assume !(1 == ~t5_pc~0); 23504#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 23502#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23499#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 23497#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 23495#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23493#L480-27 assume 1 == ~t6_pc~0; 23490#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 23489#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23488#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23487#L993-27 assume !(0 != activate_threads_~tmp___5~0); 23486#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23485#L499-27 assume 1 == ~t7_pc~0; 23483#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 23482#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 23481#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23480#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 23479#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 23478#L847-3 assume !(1 == ~T1_E~0); 23476#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23474#L857-3 assume !(1 == ~T3_E~0); 23472#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23470#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23467#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23465#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23463#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23461#L887-3 assume !(1 == ~E_1~0); 23459#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23457#L897-3 assume !(1 == ~E_3~0); 23454#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23452#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23451#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23450#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23387#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 23146#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 23137#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 23135#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 23132#L1187 assume !(0 == start_simulation_~tmp~3); 23128#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 23126#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 23117#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 23115#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 23105#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23104#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 23103#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 23100#L1200 assume !(0 != start_simulation_~tmp___0~1); 21607#L1168-1 [2018-12-08 18:43:43,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,922 INFO L82 PathProgramCache]: Analyzing trace with hash 1562230178, now seen corresponding path program 1 times [2018-12-08 18:43:43,922 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,922 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,923 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,941 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:43,941 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:43,942 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:43,942 INFO L82 PathProgramCache]: Analyzing trace with hash -1475558128, now seen corresponding path program 1 times [2018-12-08 18:43:43,942 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:43,942 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:43,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,942 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:43,943 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:43,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:43,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:43,961 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:43,961 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:43,962 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:43,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:43,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:43,962 INFO L87 Difference]: Start difference. First operand 2659 states and 3871 transitions. cyclomatic complexity: 1216 Second operand 3 states. [2018-12-08 18:43:44,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:44,023 INFO L93 Difference]: Finished difference Result 4964 states and 7186 transitions. [2018-12-08 18:43:44,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:44,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4964 states and 7186 transitions. [2018-12-08 18:43:44,034 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4844 [2018-12-08 18:43:44,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4964 states to 4964 states and 7186 transitions. [2018-12-08 18:43:44,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4964 [2018-12-08 18:43:44,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4964 [2018-12-08 18:43:44,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4964 states and 7186 transitions. [2018-12-08 18:43:44,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:44,049 INFO L705 BuchiCegarLoop]: Abstraction has 4964 states and 7186 transitions. [2018-12-08 18:43:44,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4964 states and 7186 transitions. [2018-12-08 18:43:44,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4964 to 4956. [2018-12-08 18:43:44,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4956 states. [2018-12-08 18:43:44,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4956 states to 4956 states and 7178 transitions. [2018-12-08 18:43:44,086 INFO L728 BuchiCegarLoop]: Abstraction has 4956 states and 7178 transitions. [2018-12-08 18:43:44,086 INFO L608 BuchiCegarLoop]: Abstraction has 4956 states and 7178 transitions. [2018-12-08 18:43:44,086 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-12-08 18:43:44,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4956 states and 7178 transitions. [2018-12-08 18:43:44,093 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4836 [2018-12-08 18:43:44,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:44,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:44,094 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,094 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,094 INFO L794 eck$LassoCheckResult]: Stem: 29055#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 28967#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 28968#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29324#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 29139#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28915#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28916#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29325#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29126#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28851#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28738#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28739#L561-1 assume !(0 == ~M_E~0); 29445#L759-1 assume !(0 == ~T1_E~0); 29218#L764-1 assume !(0 == ~T2_E~0); 29004#L769-1 assume !(0 == ~T3_E~0); 28695#L774-1 assume !(0 == ~T4_E~0); 28696#L779-1 assume !(0 == ~T5_E~0); 29384#L784-1 assume !(0 == ~T6_E~0); 29199#L789-1 assume !(0 == ~T7_E~0); 28790#L794-1 assume !(0 == ~E_M~0); 28791#L799-1 assume !(0 == ~E_1~0); 29425#L804-1 assume !(0 == ~E_2~0); 29307#L809-1 assume !(0 == ~E_3~0); 29084#L814-1 assume !(0 == ~E_4~0); 28613#L819-1 assume !(0 == ~E_5~0); 28614#L824-1 assume !(0 == ~E_6~0); 29280#L829-1 assume !(0 == ~E_7~0); 29148#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29149#L366 assume !(1 == ~m_pc~0); 29269#L366-2 is_master_triggered_~__retres1~0 := 0; 28886#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28678#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28679#L945 assume !(0 != activate_threads_~tmp~1); 29005#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29006#L385 assume !(1 == ~t1_pc~0); 29345#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 29072#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28830#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 28831#L953 assume !(0 != activate_threads_~tmp___0~0); 29485#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29486#L404 assume !(1 == ~t2_pc~0); 29494#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 29198#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29140#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 29141#L961 assume !(0 != activate_threads_~tmp___1~0); 29358#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28775#L423 assume !(1 == ~t3_pc~0); 28776#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 28779#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29291#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 29039#L969 assume !(0 != activate_threads_~tmp___2~0); 29040#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28789#L442 assume !(1 == ~t4_pc~0); 28781#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 28782#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29327#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 29378#L977 assume !(0 != activate_threads_~tmp___3~0); 29499#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28986#L461 assume !(1 == ~t5_pc~0); 28987#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 28990#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29393#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 29310#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 29311#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 29127#L480 assume !(1 == ~t6_pc~0); 29116#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 29117#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 29478#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 28945#L993 assume !(0 != activate_threads_~tmp___5~0); 28946#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 28949#L499 assume !(1 == ~t7_pc~0); 29262#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 28669#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28609#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 28610#L1001 assume !(0 != activate_threads_~tmp___6~0); 29449#L1001-2 assume !(1 == ~M_E~0); 29447#L847-1 assume !(1 == ~T1_E~0); 29215#L852-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29001#L857-1 assume !(1 == ~T3_E~0); 28691#L862-1 assume !(1 == ~T4_E~0); 28692#L867-1 assume !(1 == ~T5_E~0); 29382#L872-1 assume !(1 == ~T6_E~0); 29099#L877-1 assume !(1 == ~T7_E~0); 28798#L882-1 assume !(1 == ~E_M~0); 28799#L887-1 assume !(1 == ~E_1~0); 29429#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29315#L897-1 assume !(1 == ~E_3~0); 29095#L902-1 assume !(1 == ~E_4~0); 28628#L907-1 assume !(1 == ~E_5~0); 28629#L912-1 assume !(1 == ~E_6~0); 29276#L917-1 assume !(1 == ~E_7~0); 28825#L1168-1 [2018-12-08 18:43:44,095 INFO L796 eck$LassoCheckResult]: Loop: 28825#L1168-1 assume !false; 28826#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 28953#L734 assume !false; 29443#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 28786#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 28686#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 28841#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 28842#L631 assume !(0 != eval_~tmp~0); 29034#L749 start_simulation_~kernel_st~0 := 2; 29035#L519-1 start_simulation_~kernel_st~0 := 3; 29326#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 29442#L759-4 assume !(0 == ~T1_E~0); 29207#L764-3 assume !(0 == ~T2_E~0); 28997#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28680#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28681#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29380#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29203#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28794#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28795#L799-3 assume !(0 == ~E_1~0); 29426#L804-3 assume !(0 == ~E_2~0); 29308#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29085#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28615#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28616#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29281#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29150#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29151#L366-27 assume 1 == ~m_pc~0; 29240#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 28879#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28640#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28641#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 28965#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29087#L385-27 assume !(1 == ~t1_pc~0); 29330#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 29047#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28802#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 28803#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 29453#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29454#L404-27 assume 1 == ~t2_pc~0; 29404#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 29166#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29014#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 29015#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 29220#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28734#L423-27 assume !(1 == ~t3_pc~0); 28735#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 28742#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33510#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 33509#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 33508#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33507#L442-27 assume !(1 == ~t4_pc~0); 33506#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 33505#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33504#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 33503#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 33502#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33501#L461-27 assume !(1 == ~t5_pc~0); 33499#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 33498#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29436#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 29133#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 29134#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 29135#L480-27 assume !(1 == ~t6_pc~0); 29206#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 33523#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 33392#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 33148#L993-27 assume !(0 != activate_threads_~tmp___5~0); 33147#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 33146#L499-27 assume 1 == ~t7_pc~0; 33144#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 33143#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 33142#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 33141#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 33140#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 33139#L847-3 assume !(1 == ~T1_E~0); 33138#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33137#L857-3 assume !(1 == ~T3_E~0); 33136#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33135#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33134#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33132#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33130#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33123#L887-3 assume !(1 == ~E_1~0); 33122#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33121#L897-3 assume !(1 == ~E_3~0); 33120#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33119#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33118#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33117#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33116#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 28787#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 28689#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 28845#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 28846#L1187 assume !(0 == start_simulation_~tmp~3); 28881#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 28788#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 28667#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 28849#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 28850#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28636#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 28637#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 28756#L1200 assume !(0 != start_simulation_~tmp___0~1); 28825#L1168-1 [2018-12-08 18:43:44,095 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,095 INFO L82 PathProgramCache]: Analyzing trace with hash -110287453, now seen corresponding path program 1 times [2018-12-08 18:43:44,095 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,095 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:44,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:44,121 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:44,121 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:44,121 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:44,122 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,122 INFO L82 PathProgramCache]: Analyzing trace with hash -1075566929, now seen corresponding path program 1 times [2018-12-08 18:43:44,122 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,122 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:44,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:44,139 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:44,139 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:44,139 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:44,139 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:44,139 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:44,139 INFO L87 Difference]: Start difference. First operand 4956 states and 7178 transitions. cyclomatic complexity: 2230 Second operand 3 states. [2018-12-08 18:43:44,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:44,167 INFO L93 Difference]: Finished difference Result 4956 states and 7152 transitions. [2018-12-08 18:43:44,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:44,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4956 states and 7152 transitions. [2018-12-08 18:43:44,182 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4836 [2018-12-08 18:43:44,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4956 states to 4956 states and 7152 transitions. [2018-12-08 18:43:44,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4956 [2018-12-08 18:43:44,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4956 [2018-12-08 18:43:44,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4956 states and 7152 transitions. [2018-12-08 18:43:44,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:44,200 INFO L705 BuchiCegarLoop]: Abstraction has 4956 states and 7152 transitions. [2018-12-08 18:43:44,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4956 states and 7152 transitions. [2018-12-08 18:43:44,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4956 to 4956. [2018-12-08 18:43:44,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4956 states. [2018-12-08 18:43:44,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4956 states to 4956 states and 7152 transitions. [2018-12-08 18:43:44,245 INFO L728 BuchiCegarLoop]: Abstraction has 4956 states and 7152 transitions. [2018-12-08 18:43:44,245 INFO L608 BuchiCegarLoop]: Abstraction has 4956 states and 7152 transitions. [2018-12-08 18:43:44,245 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-12-08 18:43:44,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4956 states and 7152 transitions. [2018-12-08 18:43:44,256 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4836 [2018-12-08 18:43:44,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:44,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:44,257 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,257 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,257 INFO L794 eck$LassoCheckResult]: Stem: 38969#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 38876#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 38877#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 39240#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 39057#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38832#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38833#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39241#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39044#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38768#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38658#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38659#L561-1 assume !(0 == ~M_E~0); 39368#L759-1 assume !(0 == ~T1_E~0); 39126#L764-1 assume !(0 == ~T2_E~0); 38913#L769-1 assume !(0 == ~T3_E~0); 38614#L774-1 assume !(0 == ~T4_E~0); 38615#L779-1 assume !(0 == ~T5_E~0); 39299#L784-1 assume !(0 == ~T6_E~0); 39110#L789-1 assume !(0 == ~T7_E~0); 38707#L794-1 assume !(0 == ~E_M~0); 38708#L799-1 assume !(0 == ~E_1~0); 39343#L804-1 assume !(0 == ~E_2~0); 39221#L809-1 assume !(0 == ~E_3~0); 39002#L814-1 assume !(0 == ~E_4~0); 38532#L819-1 assume !(0 == ~E_5~0); 38533#L824-1 assume !(0 == ~E_6~0); 39191#L829-1 assume !(0 == ~E_7~0); 39065#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39066#L366 assume !(1 == ~m_pc~0); 39179#L366-2 is_master_triggered_~__retres1~0 := 0; 38800#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38595#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 38596#L945 assume !(0 != activate_threads_~tmp~1); 38914#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38915#L385 assume !(1 == ~t1_pc~0); 39262#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 38986#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38747#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 38748#L953 assume !(0 != activate_threads_~tmp___0~0); 39409#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39410#L404 assume !(1 == ~t2_pc~0); 39415#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 39106#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39058#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 39059#L961 assume !(0 != activate_threads_~tmp___1~0); 39274#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38690#L423 assume !(1 == ~t3_pc~0); 38691#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 38695#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39203#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 38952#L969 assume !(0 != activate_threads_~tmp___2~0); 38953#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 38706#L442 assume !(1 == ~t4_pc~0); 38697#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 38698#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39243#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 39293#L977 assume !(0 != activate_threads_~tmp___3~0); 39421#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 38895#L461 assume !(1 == ~t5_pc~0); 38896#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 38899#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39312#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 39224#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 39225#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 39045#L480 assume !(1 == ~t6_pc~0); 39033#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 39034#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 39401#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 38855#L993 assume !(0 != activate_threads_~tmp___5~0); 38856#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 38858#L499 assume !(1 == ~t7_pc~0); 39171#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 38588#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 38528#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 38529#L1001 assume !(0 != activate_threads_~tmp___6~0); 39373#L1001-2 assume !(1 == ~M_E~0); 39370#L847-1 assume !(1 == ~T1_E~0); 39124#L852-1 assume !(1 == ~T2_E~0); 38910#L857-1 assume !(1 == ~T3_E~0); 38610#L862-1 assume !(1 == ~T4_E~0); 38611#L867-1 assume !(1 == ~T5_E~0); 39297#L872-1 assume !(1 == ~T6_E~0); 39014#L877-1 assume !(1 == ~T7_E~0); 38715#L882-1 assume !(1 == ~E_M~0); 38716#L887-1 assume !(1 == ~E_1~0); 39348#L892-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39229#L897-1 assume !(1 == ~E_3~0); 39011#L902-1 assume !(1 == ~E_4~0); 38547#L907-1 assume !(1 == ~E_5~0); 38548#L912-1 assume !(1 == ~E_6~0); 39187#L917-1 assume !(1 == ~E_7~0); 39188#L1168-1 [2018-12-08 18:43:44,258 INFO L796 eck$LassoCheckResult]: Loop: 39188#L1168-1 assume !false; 41977#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 41972#L734 assume !false; 41970#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 41964#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 41956#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 41953#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 41951#L631 assume !(0 != eval_~tmp~0); 38944#L749 start_simulation_~kernel_st~0 := 2; 38945#L519-1 start_simulation_~kernel_st~0 := 3; 39242#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 39366#L759-4 assume !(0 == ~T1_E~0); 39116#L764-3 assume !(0 == ~T2_E~0); 38906#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38599#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38600#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39295#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39114#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38711#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38712#L799-3 assume !(0 == ~E_1~0); 39344#L804-3 assume !(0 == ~E_2~0); 39222#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39003#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38534#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38535#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39193#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39067#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39068#L366-27 assume 1 == ~m_pc~0; 39148#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 38796#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38559#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 38560#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 38874#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 39005#L385-27 assume !(1 == ~t1_pc~0); 39246#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 38961#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38719#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 38720#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 39377#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39378#L404-27 assume 1 == ~t2_pc~0; 39324#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 39084#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 38923#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 38924#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 39129#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38654#L423-27 assume !(1 == ~t3_pc~0); 38655#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 43483#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43482#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 43481#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43480#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43479#L442-27 assume !(1 == ~t4_pc~0); 43478#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 43477#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43476#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43475#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 43474#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43473#L461-27 assume 1 == ~t5_pc~0; 43472#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 43470#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43469#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 43468#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 43467#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 43466#L480-27 assume !(1 == ~t6_pc~0); 43465#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 43464#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 43463#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 43462#L993-27 assume !(0 != activate_threads_~tmp___5~0); 43461#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 43460#L499-27 assume 1 == ~t7_pc~0; 43458#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 43457#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 43456#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 43455#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 43454#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 43453#L847-3 assume !(1 == ~T1_E~0); 43452#L852-3 assume !(1 == ~T2_E~0); 43451#L857-3 assume !(1 == ~T3_E~0); 43450#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43449#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43448#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 43447#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43446#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 43445#L887-3 assume !(1 == ~E_1~0); 43444#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43443#L897-3 assume !(1 == ~E_3~0); 43442#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43441#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43440#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43439#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43438#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 42019#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 42010#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 42008#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 42005#L1187 assume !(0 == start_simulation_~tmp~3); 42002#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 42000#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 41991#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 41989#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 41987#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41984#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 41982#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 41980#L1200 assume !(0 != start_simulation_~tmp___0~1); 39188#L1168-1 [2018-12-08 18:43:44,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,258 INFO L82 PathProgramCache]: Analyzing trace with hash -1121404703, now seen corresponding path program 1 times [2018-12-08 18:43:44,258 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,258 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:44,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:44,293 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:44,293 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:44,293 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:44,293 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,293 INFO L82 PathProgramCache]: Analyzing trace with hash -2139301422, now seen corresponding path program 1 times [2018-12-08 18:43:44,294 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,294 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,294 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:44,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:44,317 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:44,317 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:44,317 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:44,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:44,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:44,317 INFO L87 Difference]: Start difference. First operand 4956 states and 7152 transitions. cyclomatic complexity: 2204 Second operand 3 states. [2018-12-08 18:43:44,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:44,358 INFO L93 Difference]: Finished difference Result 4956 states and 7065 transitions. [2018-12-08 18:43:44,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:44,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4956 states and 7065 transitions. [2018-12-08 18:43:44,369 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4836 [2018-12-08 18:43:44,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4956 states to 4956 states and 7065 transitions. [2018-12-08 18:43:44,380 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4956 [2018-12-08 18:43:44,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4956 [2018-12-08 18:43:44,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4956 states and 7065 transitions. [2018-12-08 18:43:44,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:44,385 INFO L705 BuchiCegarLoop]: Abstraction has 4956 states and 7065 transitions. [2018-12-08 18:43:44,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4956 states and 7065 transitions. [2018-12-08 18:43:44,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4956 to 4956. [2018-12-08 18:43:44,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4956 states. [2018-12-08 18:43:44,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4956 states to 4956 states and 7065 transitions. [2018-12-08 18:43:44,424 INFO L728 BuchiCegarLoop]: Abstraction has 4956 states and 7065 transitions. [2018-12-08 18:43:44,424 INFO L608 BuchiCegarLoop]: Abstraction has 4956 states and 7065 transitions. [2018-12-08 18:43:44,424 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-12-08 18:43:44,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4956 states and 7065 transitions. [2018-12-08 18:43:44,433 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4836 [2018-12-08 18:43:44,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:44,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:44,433 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,434 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,434 INFO L794 eck$LassoCheckResult]: Stem: 48883#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 48793#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 48794#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49148#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 48964#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48745#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48746#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49149#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48952#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48683#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48574#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48575#L561-1 assume !(0 == ~M_E~0); 49267#L759-1 assume !(0 == ~T1_E~0); 49040#L764-1 assume !(0 == ~T2_E~0); 48832#L769-1 assume !(0 == ~T3_E~0); 48533#L774-1 assume !(0 == ~T4_E~0); 48534#L779-1 assume !(0 == ~T5_E~0); 49208#L784-1 assume !(0 == ~T6_E~0); 49023#L789-1 assume !(0 == ~T7_E~0); 48622#L794-1 assume !(0 == ~E_M~0); 48623#L799-1 assume !(0 == ~E_1~0); 49249#L804-1 assume !(0 == ~E_2~0); 49128#L809-1 assume !(0 == ~E_3~0); 48913#L814-1 assume !(0 == ~E_4~0); 48451#L819-1 assume !(0 == ~E_5~0); 48452#L824-1 assume !(0 == ~E_6~0); 49100#L829-1 assume !(0 == ~E_7~0); 48972#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48973#L366 assume !(1 == ~m_pc~0); 49090#L366-2 is_master_triggered_~__retres1~0 := 0; 48715#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48514#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 48515#L945 assume !(0 != activate_threads_~tmp~1); 48833#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48834#L385 assume !(1 == ~t1_pc~0); 49169#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 48900#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48662#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 48663#L953 assume !(0 != activate_threads_~tmp___0~0); 49310#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49311#L404 assume !(1 == ~t2_pc~0); 49321#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 49019#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48965#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 48966#L961 assume !(0 != activate_threads_~tmp___1~0); 49181#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48606#L423 assume !(1 == ~t3_pc~0); 48607#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 48611#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49111#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 48868#L969 assume !(0 != activate_threads_~tmp___2~0); 48869#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48621#L442 assume !(1 == ~t4_pc~0); 48613#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 48614#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49151#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 49202#L977 assume !(0 != activate_threads_~tmp___3~0); 49329#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48812#L461 assume !(1 == ~t5_pc~0); 48813#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 48816#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49218#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 49132#L985 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 49133#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 48953#L480 assume !(1 == ~t6_pc~0); 48942#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 48943#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49302#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 48772#L993 assume !(0 != activate_threads_~tmp___5~0); 48773#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 48775#L499 assume !(1 == ~t7_pc~0); 49083#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 48507#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 48447#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 48448#L1001 assume !(0 != activate_threads_~tmp___6~0); 49271#L1001-2 assume !(1 == ~M_E~0); 49269#L847-1 assume !(1 == ~T1_E~0); 49038#L852-1 assume !(1 == ~T2_E~0); 48828#L857-1 assume !(1 == ~T3_E~0); 48529#L862-1 assume !(1 == ~T4_E~0); 48530#L867-1 assume !(1 == ~T5_E~0); 49206#L872-1 assume !(1 == ~T6_E~0); 48925#L877-1 assume !(1 == ~T7_E~0); 48630#L882-1 assume !(1 == ~E_M~0); 48631#L887-1 assume !(1 == ~E_1~0); 49254#L892-1 assume !(1 == ~E_2~0); 49137#L897-1 assume !(1 == ~E_3~0); 48922#L902-1 assume !(1 == ~E_4~0); 48466#L907-1 assume !(1 == ~E_5~0); 48467#L912-1 assume !(1 == ~E_6~0); 49095#L917-1 assume !(1 == ~E_7~0); 49096#L1168-1 [2018-12-08 18:43:44,434 INFO L796 eck$LassoCheckResult]: Loop: 49096#L1168-1 assume !false; 51976#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 51971#L734 assume !false; 51969#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 51963#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 51955#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 51952#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 51949#L631 assume !(0 != eval_~tmp~0); 51950#L749 start_simulation_~kernel_st~0 := 2; 53375#L519-1 start_simulation_~kernel_st~0 := 3; 53373#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 53371#L759-4 assume !(0 == ~T1_E~0); 53369#L764-3 assume !(0 == ~T2_E~0); 53367#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53365#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53363#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53361#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53359#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53357#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53355#L799-3 assume !(0 == ~E_1~0); 53354#L804-3 assume !(0 == ~E_2~0); 53334#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53333#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53332#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53301#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53300#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53299#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53298#L366-27 assume 1 == ~m_pc~0; 53296#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 53295#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53294#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53293#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 53292#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53291#L385-27 assume !(1 == ~t1_pc~0); 53289#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 53288#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53287#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53284#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 53282#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53280#L404-27 assume !(1 == ~t2_pc~0); 53277#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 53274#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53272#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53270#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 53268#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53266#L423-27 assume !(1 == ~t3_pc~0); 53264#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 53261#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53259#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 53257#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 53255#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53253#L442-27 assume !(1 == ~t4_pc~0); 53250#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 53248#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53246#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 53244#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 53242#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53240#L461-27 assume !(1 == ~t5_pc~0); 53237#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 53236#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 53235#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 53234#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 53233#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 53232#L480-27 assume !(1 == ~t6_pc~0); 53231#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 53230#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53229#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 53228#L993-27 assume !(0 != activate_threads_~tmp___5~0); 53100#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 53099#L499-27 assume 1 == ~t7_pc~0; 53097#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 53096#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 53095#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 53094#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 53093#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 53091#L847-3 assume !(1 == ~T1_E~0); 53090#L852-3 assume !(1 == ~T2_E~0); 52949#L857-3 assume !(1 == ~T3_E~0); 52948#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52947#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52946#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52945#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52944#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52943#L887-3 assume !(1 == ~E_1~0); 52942#L892-3 assume !(1 == ~E_2~0); 52940#L897-3 assume !(1 == ~E_3~0); 52939#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48449#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48450#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49098#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49099#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 52018#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 52009#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 52007#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 52004#L1187 assume !(0 == start_simulation_~tmp~3); 52001#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 51999#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 51990#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 51988#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 51986#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 51983#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 51981#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 51979#L1200 assume !(0 != start_simulation_~tmp___0~1); 49096#L1168-1 [2018-12-08 18:43:44,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,434 INFO L82 PathProgramCache]: Analyzing trace with hash -1064146401, now seen corresponding path program 1 times [2018-12-08 18:43:44,434 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,434 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:44,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:44,484 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:44,484 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:44,484 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:44,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,484 INFO L82 PathProgramCache]: Analyzing trace with hash -136363950, now seen corresponding path program 1 times [2018-12-08 18:43:44,484 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,485 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:44,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:44,509 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:44,509 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:44,510 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:44,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 18:43:44,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 18:43:44,510 INFO L87 Difference]: Start difference. First operand 4956 states and 7065 transitions. cyclomatic complexity: 2117 Second operand 5 states. [2018-12-08 18:43:44,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:44,686 INFO L93 Difference]: Finished difference Result 11809 states and 16906 transitions. [2018-12-08 18:43:44,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 18:43:44,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11809 states and 16906 transitions. [2018-12-08 18:43:44,714 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11580 [2018-12-08 18:43:44,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11809 states to 11809 states and 16906 transitions. [2018-12-08 18:43:44,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11809 [2018-12-08 18:43:44,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11809 [2018-12-08 18:43:44,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11809 states and 16906 transitions. [2018-12-08 18:43:44,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:44,749 INFO L705 BuchiCegarLoop]: Abstraction has 11809 states and 16906 transitions. [2018-12-08 18:43:44,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11809 states and 16906 transitions. [2018-12-08 18:43:44,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11809 to 5163. [2018-12-08 18:43:44,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5163 states. [2018-12-08 18:43:44,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5163 states to 5163 states and 7272 transitions. [2018-12-08 18:43:44,812 INFO L728 BuchiCegarLoop]: Abstraction has 5163 states and 7272 transitions. [2018-12-08 18:43:44,812 INFO L608 BuchiCegarLoop]: Abstraction has 5163 states and 7272 transitions. [2018-12-08 18:43:44,812 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-12-08 18:43:44,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5163 states and 7272 transitions. [2018-12-08 18:43:44,822 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5040 [2018-12-08 18:43:44,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:44,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:44,823 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,823 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,823 INFO L794 eck$LassoCheckResult]: Stem: 65667#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 65578#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 65579#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65935#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 65771#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65531#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65532#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65936#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65759#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65470#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65355#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65356#L561-1 assume !(0 == ~M_E~0); 66074#L759-1 assume !(0 == ~T1_E~0); 65835#L764-1 assume !(0 == ~T2_E~0); 65615#L769-1 assume !(0 == ~T3_E~0); 65311#L774-1 assume !(0 == ~T4_E~0); 65312#L779-1 assume !(0 == ~T5_E~0); 65994#L784-1 assume !(0 == ~T6_E~0); 65820#L789-1 assume !(0 == ~T7_E~0); 65409#L794-1 assume !(0 == ~E_M~0); 65410#L799-1 assume !(0 == ~E_1~0); 66040#L804-1 assume !(0 == ~E_2~0); 65919#L809-1 assume !(0 == ~E_3~0); 65709#L814-1 assume !(0 == ~E_4~0); 65229#L819-1 assume !(0 == ~E_5~0); 65230#L824-1 assume !(0 == ~E_6~0); 65892#L829-1 assume !(0 == ~E_7~0); 65780#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65781#L366 assume !(1 == ~m_pc~0); 65883#L366-2 is_master_triggered_~__retres1~0 := 0; 65502#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65292#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 65293#L945 assume !(0 != activate_threads_~tmp~1); 65616#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65617#L385 assume !(1 == ~t1_pc~0); 65956#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 65687#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65449#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 65450#L953 assume !(0 != activate_threads_~tmp___0~0); 66116#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 66117#L404 assume !(1 == ~t2_pc~0); 66123#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 65816#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65772#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 65773#L961 assume !(0 != activate_threads_~tmp___1~0); 65968#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65391#L423 assume !(1 == ~t3_pc~0); 65392#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 65397#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65903#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 65651#L969 assume !(0 != activate_threads_~tmp___2~0); 65652#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65408#L442 assume !(1 == ~t4_pc~0); 65399#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 65400#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65938#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 65988#L977 assume !(0 != activate_threads_~tmp___3~0); 66128#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65597#L461 assume !(1 == ~t5_pc~0); 65598#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 65601#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 66007#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 65922#L985 assume !(0 != activate_threads_~tmp___4~0); 65923#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 65760#L480 assume !(1 == ~t6_pc~0); 65748#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 65749#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 66109#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 65556#L993 assume !(0 != activate_threads_~tmp___5~0); 65557#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 65559#L499 assume !(1 == ~t7_pc~0); 65876#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 65285#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 65225#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 65226#L1001 assume !(0 != activate_threads_~tmp___6~0); 66080#L1001-2 assume !(1 == ~M_E~0); 66077#L847-1 assume !(1 == ~T1_E~0); 65833#L852-1 assume !(1 == ~T2_E~0); 65612#L857-1 assume !(1 == ~T3_E~0); 65307#L862-1 assume !(1 == ~T4_E~0); 65308#L867-1 assume !(1 == ~T5_E~0); 65992#L872-1 assume !(1 == ~T6_E~0); 65729#L877-1 assume !(1 == ~T7_E~0); 65417#L882-1 assume !(1 == ~E_M~0); 65418#L887-1 assume !(1 == ~E_1~0); 66044#L892-1 assume !(1 == ~E_2~0); 65927#L897-1 assume !(1 == ~E_3~0); 65726#L902-1 assume !(1 == ~E_4~0); 65244#L907-1 assume !(1 == ~E_5~0); 65245#L912-1 assume !(1 == ~E_6~0); 65888#L917-1 assume !(1 == ~E_7~0); 65889#L1168-1 [2018-12-08 18:43:44,824 INFO L796 eck$LassoCheckResult]: Loop: 65889#L1168-1 assume !false; 68882#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 68876#L734 assume !false; 68874#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 68866#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 68858#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 68856#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 68853#L631 assume !(0 != eval_~tmp~0); 68854#L749 start_simulation_~kernel_st~0 := 2; 69784#L519-1 start_simulation_~kernel_st~0 := 3; 69782#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 69779#L759-4 assume !(0 == ~T1_E~0); 69777#L764-3 assume !(0 == ~T2_E~0); 69775#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69773#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69771#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69769#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69767#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69766#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69765#L799-3 assume !(0 == ~E_1~0); 69764#L804-3 assume !(0 == ~E_2~0); 69763#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69762#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69683#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69678#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69654#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69647#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69646#L366-27 assume !(1 == ~m_pc~0); 69645#L366-29 is_master_triggered_~__retres1~0 := 0; 69643#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69642#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 69641#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 69640#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69639#L385-27 assume !(1 == ~t1_pc~0); 69637#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 69636#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69635#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 69634#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 69633#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69632#L404-27 assume !(1 == ~t2_pc~0); 69630#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 69629#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69628#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 69627#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 69626#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69625#L423-27 assume !(1 == ~t3_pc~0); 69624#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 69623#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69622#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 69621#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 69620#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69619#L442-27 assume !(1 == ~t4_pc~0); 69618#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 69617#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69616#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69615#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 69614#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69613#L461-27 assume 1 == ~t5_pc~0; 69611#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 69612#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 70107#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 69606#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 69604#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 69602#L480-27 assume !(1 == ~t6_pc~0); 69599#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 69597#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 69595#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 69593#L993-27 assume !(0 != activate_threads_~tmp___5~0); 69591#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 69589#L499-27 assume !(1 == ~t7_pc~0); 69587#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 69584#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 69582#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 69580#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 69578#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 69560#L847-3 assume !(1 == ~T1_E~0); 69554#L852-3 assume !(1 == ~T2_E~0); 69550#L857-3 assume !(1 == ~T3_E~0); 69546#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69465#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69457#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69455#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69453#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69451#L887-3 assume !(1 == ~E_1~0); 69449#L892-3 assume !(1 == ~E_2~0); 69447#L897-3 assume !(1 == ~E_3~0); 69445#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69443#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69441#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69438#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69436#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 69434#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 69425#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 69423#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 69420#L1187 assume !(0 == start_simulation_~tmp~3); 69159#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 68905#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 68896#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 68894#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 68892#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 68890#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 68888#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 68886#L1200 assume !(0 != start_simulation_~tmp___0~1); 65889#L1168-1 [2018-12-08 18:43:44,824 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,824 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 1 times [2018-12-08 18:43:44,824 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,824 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,825 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:44,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:44,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,859 INFO L82 PathProgramCache]: Analyzing trace with hash -377891599, now seen corresponding path program 1 times [2018-12-08 18:43:44,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:44,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:44,890 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:44,891 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:44,891 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:44,891 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:44,891 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:44,891 INFO L87 Difference]: Start difference. First operand 5163 states and 7272 transitions. cyclomatic complexity: 2117 Second operand 3 states. [2018-12-08 18:43:44,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:44,917 INFO L93 Difference]: Finished difference Result 5823 states and 8199 transitions. [2018-12-08 18:43:44,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:44,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5823 states and 8199 transitions. [2018-12-08 18:43:44,930 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5628 [2018-12-08 18:43:44,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5823 states to 5823 states and 8199 transitions. [2018-12-08 18:43:44,940 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5823 [2018-12-08 18:43:44,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5823 [2018-12-08 18:43:44,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5823 states and 8199 transitions. [2018-12-08 18:43:44,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:44,945 INFO L705 BuchiCegarLoop]: Abstraction has 5823 states and 8199 transitions. [2018-12-08 18:43:44,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5823 states and 8199 transitions. [2018-12-08 18:43:44,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5823 to 5823. [2018-12-08 18:43:44,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5823 states. [2018-12-08 18:43:44,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5823 states to 5823 states and 8199 transitions. [2018-12-08 18:43:44,984 INFO L728 BuchiCegarLoop]: Abstraction has 5823 states and 8199 transitions. [2018-12-08 18:43:44,984 INFO L608 BuchiCegarLoop]: Abstraction has 5823 states and 8199 transitions. [2018-12-08 18:43:44,984 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-12-08 18:43:44,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5823 states and 8199 transitions. [2018-12-08 18:43:44,995 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5628 [2018-12-08 18:43:44,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:44,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:44,996 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,996 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:44,996 INFO L794 eck$LassoCheckResult]: Stem: 76662#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 76568#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 76569#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 76930#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 76759#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76525#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76526#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76931#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76745#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76458#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76345#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76346#L561-1 assume !(0 == ~M_E~0); 77068#L759-1 assume !(0 == ~T1_E~0); 76824#L764-1 assume !(0 == ~T2_E~0); 76607#L769-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76304#L774-1 assume !(0 == ~T4_E~0); 76305#L779-1 assume !(0 == ~T5_E~0); 77128#L784-1 assume !(0 == ~T6_E~0); 77196#L789-1 assume !(0 == ~T7_E~0); 77195#L794-1 assume !(0 == ~E_M~0); 77109#L799-1 assume !(0 == ~E_1~0); 77110#L804-1 assume !(0 == ~E_2~0); 77194#L809-1 assume !(0 == ~E_3~0); 76700#L814-1 assume !(0 == ~E_4~0); 76221#L819-1 assume !(0 == ~E_5~0); 76222#L824-1 assume !(0 == ~E_6~0); 77192#L829-1 assume !(0 == ~E_7~0); 76767#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76768#L366 assume !(1 == ~m_pc~0); 76872#L366-2 is_master_triggered_~__retres1~0 := 0; 76873#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76287#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 76288#L945 assume !(0 != activate_threads_~tmp~1); 76609#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76610#L385 assume !(1 == ~t1_pc~0); 77061#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 77062#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 77188#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 77113#L953 assume !(0 != activate_threads_~tmp___0~0); 77114#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 77186#L404 assume !(1 == ~t2_pc~0); 77178#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 77177#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76760#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 76761#L961 assume !(0 != activate_threads_~tmp___1~0); 76966#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76967#L423 assume !(1 == ~t3_pc~0); 76383#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 76384#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 77176#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 76644#L969 assume !(0 != activate_threads_~tmp___2~0); 76645#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 77175#L442 assume !(1 == ~t4_pc~0); 76386#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 76387#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 76989#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 76990#L977 assume !(0 != activate_threads_~tmp___3~0); 77129#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 76587#L461 assume !(1 == ~t5_pc~0); 76588#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 76591#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 77007#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 76916#L985 assume !(0 != activate_threads_~tmp___4~0); 76917#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 76918#L480 assume !(1 == ~t6_pc~0); 76733#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 76734#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 77151#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 77150#L993 assume !(0 != activate_threads_~tmp___5~0); 77149#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 77148#L499 assume !(1 == ~t7_pc~0); 77146#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 77145#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 76217#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 76218#L1001 assume !(0 != activate_threads_~tmp___6~0); 77142#L1001-2 assume !(1 == ~M_E~0); 77070#L847-1 assume !(1 == ~T1_E~0); 76821#L852-1 assume !(1 == ~T2_E~0); 76604#L857-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76300#L862-1 assume !(1 == ~T4_E~0); 76301#L867-1 assume !(1 == ~T5_E~0); 76994#L872-1 assume !(1 == ~T6_E~0); 76716#L877-1 assume !(1 == ~T7_E~0); 76405#L882-1 assume !(1 == ~E_M~0); 76406#L887-1 assume !(1 == ~E_1~0); 77046#L892-1 assume !(1 == ~E_2~0); 76922#L897-1 assume !(1 == ~E_3~0); 76712#L902-1 assume !(1 == ~E_4~0); 76236#L907-1 assume !(1 == ~E_5~0); 76237#L912-1 assume !(1 == ~E_6~0); 76879#L917-1 assume !(1 == ~E_7~0); 76880#L1168-1 [2018-12-08 18:43:44,996 INFO L796 eck$LassoCheckResult]: Loop: 76880#L1168-1 assume !false; 80178#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 80172#L734 assume !false; 80171#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 80096#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 80065#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 80057#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 80052#L631 assume !(0 != eval_~tmp~0); 76638#L749 start_simulation_~kernel_st~0 := 2; 76639#L519-1 start_simulation_~kernel_st~0 := 3; 76932#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 77066#L759-4 assume !(0 == ~T1_E~0); 76814#L764-3 assume !(0 == ~T2_E~0); 76598#L769-3 assume !(0 == ~T3_E~0); 76289#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76290#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77126#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81832#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81830#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 81828#L799-3 assume !(0 == ~E_1~0); 81826#L804-3 assume !(0 == ~E_2~0); 81824#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81823#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81822#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81821#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 81820#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 81819#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81818#L366-27 assume !(1 == ~m_pc~0); 81817#L366-29 is_master_triggered_~__retres1~0 := 0; 81815#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81814#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 81813#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 76705#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76706#L385-27 assume !(1 == ~t1_pc~0); 76936#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 76654#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76409#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 76410#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 77079#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 77080#L404-27 assume !(1 == ~t2_pc~0); 77024#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 76786#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76618#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 76619#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 76827#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76341#L423-27 assume !(1 == ~t3_pc~0); 76342#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 82023#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 82022#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 82021#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 82020#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 82019#L442-27 assume !(1 == ~t4_pc~0); 82018#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 82017#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 82016#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 82015#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 82014#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 82013#L461-27 assume !(1 == ~t5_pc~0); 82011#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 82009#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 82007#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 82006#L985-27 assume !(0 != activate_threads_~tmp___4~0); 82004#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 82003#L480-27 assume !(1 == ~t6_pc~0); 82000#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 81998#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 81996#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 81994#L993-27 assume !(0 != activate_threads_~tmp___5~0); 81991#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 81990#L499-27 assume !(1 == ~t7_pc~0); 81989#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 81987#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 81986#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 81985#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 81984#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 81755#L847-3 assume !(1 == ~T1_E~0); 81754#L852-3 assume !(1 == ~T2_E~0); 81053#L857-3 assume !(1 == ~T3_E~0); 81051#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81047#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81041#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81033#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81025#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81016#L887-3 assume !(1 == ~E_1~0); 81008#L892-3 assume !(1 == ~E_2~0); 81000#L897-3 assume !(1 == ~E_3~0); 80993#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80992#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 80991#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 80990#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 80989#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 80984#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 80975#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 80973#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 80966#L1187 assume !(0 == start_simulation_~tmp~3); 80958#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 80954#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 80275#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 80262#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 80229#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 80189#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 80185#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 80183#L1200 assume !(0 != start_simulation_~tmp___0~1); 76880#L1168-1 [2018-12-08 18:43:44,996 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:44,996 INFO L82 PathProgramCache]: Analyzing trace with hash 881797405, now seen corresponding path program 1 times [2018-12-08 18:43:44,996 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:44,997 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:44,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:44,997 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:44,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:45,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:45,010 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:45,010 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:45,011 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:45,011 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,011 INFO L82 PathProgramCache]: Analyzing trace with hash 439313356, now seen corresponding path program 1 times [2018-12-08 18:43:45,011 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,011 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,012 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:45,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:45,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:45,030 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:45,030 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:45,031 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:45,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:45,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:45,031 INFO L87 Difference]: Start difference. First operand 5823 states and 8199 transitions. cyclomatic complexity: 2384 Second operand 3 states. [2018-12-08 18:43:45,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:45,050 INFO L93 Difference]: Finished difference Result 5163 states and 7246 transitions. [2018-12-08 18:43:45,050 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:45,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5163 states and 7246 transitions. [2018-12-08 18:43:45,063 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5040 [2018-12-08 18:43:45,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5163 states to 5163 states and 7246 transitions. [2018-12-08 18:43:45,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5163 [2018-12-08 18:43:45,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5163 [2018-12-08 18:43:45,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5163 states and 7246 transitions. [2018-12-08 18:43:45,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:45,079 INFO L705 BuchiCegarLoop]: Abstraction has 5163 states and 7246 transitions. [2018-12-08 18:43:45,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5163 states and 7246 transitions. [2018-12-08 18:43:45,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5163 to 5163. [2018-12-08 18:43:45,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5163 states. [2018-12-08 18:43:45,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5163 states to 5163 states and 7246 transitions. [2018-12-08 18:43:45,109 INFO L728 BuchiCegarLoop]: Abstraction has 5163 states and 7246 transitions. [2018-12-08 18:43:45,109 INFO L608 BuchiCegarLoop]: Abstraction has 5163 states and 7246 transitions. [2018-12-08 18:43:45,109 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-12-08 18:43:45,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5163 states and 7246 transitions. [2018-12-08 18:43:45,118 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5040 [2018-12-08 18:43:45,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:45,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:45,119 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,119 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,119 INFO L794 eck$LassoCheckResult]: Stem: 87663#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 87569#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 87570#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 87947#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 87764#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87518#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87519#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87948#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87751#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87454#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87339#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 87340#L561-1 assume !(0 == ~M_E~0); 88090#L759-1 assume !(0 == ~T1_E~0); 87832#L764-1 assume !(0 == ~T2_E~0); 87606#L769-1 assume !(0 == ~T3_E~0); 87296#L774-1 assume !(0 == ~T4_E~0); 87297#L779-1 assume !(0 == ~T5_E~0); 88011#L784-1 assume !(0 == ~T6_E~0); 87815#L789-1 assume !(0 == ~T7_E~0); 87392#L794-1 assume !(0 == ~E_M~0); 87393#L799-1 assume !(0 == ~E_1~0); 88060#L804-1 assume !(0 == ~E_2~0); 87928#L809-1 assume !(0 == ~E_3~0); 87705#L814-1 assume !(0 == ~E_4~0); 87214#L819-1 assume !(0 == ~E_5~0); 87215#L824-1 assume !(0 == ~E_6~0); 87897#L829-1 assume !(0 == ~E_7~0); 87772#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87773#L366 assume !(1 == ~m_pc~0); 87888#L366-2 is_master_triggered_~__retres1~0 := 0; 87488#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87277#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 87278#L945 assume !(0 != activate_threads_~tmp~1); 87607#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87608#L385 assume !(1 == ~t1_pc~0); 87969#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 87684#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87433#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 87434#L953 assume !(0 != activate_threads_~tmp___0~0); 88138#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 88139#L404 assume !(1 == ~t2_pc~0); 88146#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 87814#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87765#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 87766#L961 assume !(0 != activate_threads_~tmp___1~0); 87983#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87375#L423 assume !(1 == ~t3_pc~0); 87376#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 87380#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87910#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 87646#L969 assume !(0 != activate_threads_~tmp___2~0); 87647#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87391#L442 assume !(1 == ~t4_pc~0); 87382#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 87383#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87950#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 88005#L977 assume !(0 != activate_threads_~tmp___3~0); 88156#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 87588#L461 assume !(1 == ~t5_pc~0); 87589#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 87592#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 88026#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 87931#L985 assume !(0 != activate_threads_~tmp___4~0); 87932#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 87752#L480 assume !(1 == ~t6_pc~0); 87740#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 87741#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 88129#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 87545#L993 assume !(0 != activate_threads_~tmp___5~0); 87546#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 87549#L499 assume !(1 == ~t7_pc~0); 87880#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 87270#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 87210#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 87211#L1001 assume !(0 != activate_threads_~tmp___6~0); 88096#L1001-2 assume !(1 == ~M_E~0); 88092#L847-1 assume !(1 == ~T1_E~0); 87830#L852-1 assume !(1 == ~T2_E~0); 87603#L857-1 assume !(1 == ~T3_E~0); 87292#L862-1 assume !(1 == ~T4_E~0); 87293#L867-1 assume !(1 == ~T5_E~0); 88009#L872-1 assume !(1 == ~T6_E~0); 87722#L877-1 assume !(1 == ~T7_E~0); 87401#L882-1 assume !(1 == ~E_M~0); 87402#L887-1 assume !(1 == ~E_1~0); 88067#L892-1 assume !(1 == ~E_2~0); 87936#L897-1 assume !(1 == ~E_3~0); 87718#L902-1 assume !(1 == ~E_4~0); 87229#L907-1 assume !(1 == ~E_5~0); 87230#L912-1 assume !(1 == ~E_6~0); 87893#L917-1 assume !(1 == ~E_7~0); 87894#L1168-1 [2018-12-08 18:43:45,120 INFO L796 eck$LassoCheckResult]: Loop: 87894#L1168-1 assume !false; 91135#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 88164#L734 assume !false; 88165#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 87388#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 87287#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 87693#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 91179#L631 assume !(0 != eval_~tmp~0); 91180#L749 start_simulation_~kernel_st~0 := 2; 92116#L519-1 start_simulation_~kernel_st~0 := 3; 92115#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 92114#L759-4 assume !(0 == ~T1_E~0); 92113#L764-3 assume !(0 == ~T2_E~0); 92112#L769-3 assume !(0 == ~T3_E~0); 92111#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 92110#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 92109#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 92107#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 92105#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 92104#L799-3 assume !(0 == ~E_1~0); 92103#L804-3 assume !(0 == ~E_2~0); 92102#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 92100#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 92097#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 92095#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 92093#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 92091#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 92087#L366-27 assume 1 == ~m_pc~0; 92085#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 92083#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 92082#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 92081#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 92080#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 92079#L385-27 assume !(1 == ~t1_pc~0); 92077#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 92076#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 92075#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 92073#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 92071#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 92069#L404-27 assume !(1 == ~t2_pc~0); 92066#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 92064#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 92062#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 92060#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 92058#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 92056#L423-27 assume !(1 == ~t3_pc~0); 92054#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 92052#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 92050#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 92048#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 92045#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 92042#L442-27 assume !(1 == ~t4_pc~0); 92039#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 92036#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 92033#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 92029#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 92024#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 92020#L461-27 assume !(1 == ~t5_pc~0); 92016#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 92012#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 92008#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 92004#L985-27 assume !(0 != activate_threads_~tmp___4~0); 92001#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 91999#L480-27 assume !(1 == ~t6_pc~0); 91997#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 91995#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 91993#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 91992#L993-27 assume !(0 != activate_threads_~tmp___5~0); 91991#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 91453#L499-27 assume 1 == ~t7_pc~0; 91449#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 91447#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 91445#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 91443#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 91441#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 91439#L847-3 assume !(1 == ~T1_E~0); 91437#L852-3 assume !(1 == ~T2_E~0); 91434#L857-3 assume !(1 == ~T3_E~0); 91432#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 91430#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 91428#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 91426#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 91424#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 91422#L887-3 assume !(1 == ~E_1~0); 91420#L892-3 assume !(1 == ~E_2~0); 91418#L897-3 assume !(1 == ~E_3~0); 91416#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 91414#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 91412#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 91410#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 91408#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 91406#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 91396#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 91394#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 91386#L1187 assume !(0 == start_simulation_~tmp~3); 91382#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 91380#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 91370#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 91367#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 91363#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 91356#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 91138#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 91139#L1200 assume !(0 != start_simulation_~tmp___0~1); 87894#L1168-1 [2018-12-08 18:43:45,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,120 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 2 times [2018-12-08 18:43:45,120 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,120 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:45,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:45,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:45,144 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,145 INFO L82 PathProgramCache]: Analyzing trace with hash 1988845774, now seen corresponding path program 1 times [2018-12-08 18:43:45,145 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,145 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,145 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:45,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:45,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:45,161 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:45,162 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:45,162 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:45,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:45,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:45,162 INFO L87 Difference]: Start difference. First operand 5163 states and 7246 transitions. cyclomatic complexity: 2091 Second operand 3 states. [2018-12-08 18:43:45,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:45,226 INFO L93 Difference]: Finished difference Result 7717 states and 10770 transitions. [2018-12-08 18:43:45,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:45,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7717 states and 10770 transitions. [2018-12-08 18:43:45,241 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7514 [2018-12-08 18:43:45,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7717 states to 7717 states and 10770 transitions. [2018-12-08 18:43:45,251 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7717 [2018-12-08 18:43:45,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7717 [2018-12-08 18:43:45,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7717 states and 10770 transitions. [2018-12-08 18:43:45,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:45,257 INFO L705 BuchiCegarLoop]: Abstraction has 7717 states and 10770 transitions. [2018-12-08 18:43:45,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7717 states and 10770 transitions. [2018-12-08 18:43:45,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7717 to 7713. [2018-12-08 18:43:45,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7713 states. [2018-12-08 18:43:45,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7713 states to 7713 states and 10766 transitions. [2018-12-08 18:43:45,299 INFO L728 BuchiCegarLoop]: Abstraction has 7713 states and 10766 transitions. [2018-12-08 18:43:45,299 INFO L608 BuchiCegarLoop]: Abstraction has 7713 states and 10766 transitions. [2018-12-08 18:43:45,299 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-12-08 18:43:45,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7713 states and 10766 transitions. [2018-12-08 18:43:45,311 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7510 [2018-12-08 18:43:45,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:45,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:45,312 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,312 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,312 INFO L794 eck$LassoCheckResult]: Stem: 100542#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 100450#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 100451#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 100815#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 100635#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100398#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100399#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100816#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100622#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100332#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 100217#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 100218#L561-1 assume !(0 == ~M_E~0); 100951#L759-1 assume !(0 == ~T1_E~0); 100702#L764-1 assume !(0 == ~T2_E~0); 100489#L769-1 assume !(0 == ~T3_E~0); 100183#L774-1 assume !(0 == ~T4_E~0); 100184#L779-1 assume !(0 == ~T5_E~0); 100883#L784-1 assume !(0 == ~T6_E~0); 100686#L789-1 assume !(0 == ~T7_E~0); 100271#L794-1 assume !(0 == ~E_M~0); 100272#L799-1 assume !(0 == ~E_1~0); 100924#L804-1 assume !(0 == ~E_2~0); 100796#L809-1 assume 0 == ~E_3~0;~E_3~0 := 1; 100797#L814-1 assume !(0 == ~E_4~0); 101060#L819-1 assume !(0 == ~E_5~0); 100897#L824-1 assume !(0 == ~E_6~0); 100767#L829-1 assume !(0 == ~E_7~0); 100768#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 100862#L366 assume !(1 == ~m_pc~0); 100863#L366-2 is_master_triggered_~__retres1~0 := 0; 100365#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 100366#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 101058#L945 assume !(0 != activate_threads_~tmp~1); 101057#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 100942#L385 assume !(1 == ~t1_pc~0); 100837#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 100562#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 100311#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 100312#L953 assume !(0 != activate_threads_~tmp___0~0); 100999#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 101000#L404 assume !(1 == ~t2_pc~0); 101010#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 101023#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 100636#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 100637#L961 assume !(0 != activate_threads_~tmp___1~0); 100852#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 100853#L423 assume !(1 == ~t3_pc~0); 100258#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 100259#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 101051#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 100525#L969 assume !(0 != activate_threads_~tmp___2~0); 100526#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 101050#L442 assume !(1 == ~t4_pc~0); 100261#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 100262#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 100875#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 100876#L977 assume !(0 != activate_threads_~tmp___3~0); 101018#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 100469#L461 assume !(1 == ~t5_pc~0); 100470#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 100474#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 100893#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 100800#L985 assume !(0 != activate_threads_~tmp___4~0); 100801#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 100802#L480 assume !(1 == ~t6_pc~0); 100612#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 100613#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 101037#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 101036#L993 assume !(0 != activate_threads_~tmp___5~0); 101035#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 101034#L499 assume !(1 == ~t7_pc~0); 101032#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 101031#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 100096#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 100097#L1001 assume !(0 != activate_threads_~tmp___6~0); 100957#L1001-2 assume !(1 == ~M_E~0); 100958#L847-1 assume !(1 == ~T1_E~0); 101030#L852-1 assume !(1 == ~T2_E~0); 101029#L857-1 assume !(1 == ~T3_E~0); 100179#L862-1 assume !(1 == ~T4_E~0); 100180#L867-1 assume !(1 == ~T5_E~0); 101017#L872-1 assume !(1 == ~T6_E~0); 100593#L877-1 assume !(1 == ~T7_E~0); 100279#L882-1 assume !(1 == ~E_M~0); 100280#L887-1 assume !(1 == ~E_1~0); 100928#L892-1 assume !(1 == ~E_2~0); 100806#L897-1 assume 1 == ~E_3~0;~E_3~0 := 2; 100590#L902-1 assume !(1 == ~E_4~0); 100115#L907-1 assume !(1 == ~E_5~0); 100116#L912-1 assume !(1 == ~E_6~0); 100763#L917-1 assume !(1 == ~E_7~0); 100764#L1168-1 [2018-12-08 18:43:45,313 INFO L796 eck$LassoCheckResult]: Loop: 100764#L1168-1 assume !false; 106080#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 106074#L734 assume !false; 106072#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 105823#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 105810#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 105804#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 105795#L631 assume !(0 != eval_~tmp~0); 105796#L749 start_simulation_~kernel_st~0 := 2; 106416#L519-1 start_simulation_~kernel_st~0 := 3; 106415#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 106414#L759-4 assume !(0 == ~T1_E~0); 106413#L764-3 assume !(0 == ~T2_E~0); 106412#L769-3 assume !(0 == ~T3_E~0); 106410#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 106409#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106408#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 106406#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 106405#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 106404#L799-3 assume !(0 == ~E_1~0); 106403#L804-3 assume !(0 == ~E_2~0); 106401#L809-3 assume !(0 == ~E_3~0); 106400#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106399#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106398#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 106397#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 106395#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 106392#L366-27 assume 1 == ~m_pc~0; 106389#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 106387#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 106385#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 106383#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 106382#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 106381#L385-27 assume !(1 == ~t1_pc~0); 106377#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 106375#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 106373#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 106371#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 106369#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 106367#L404-27 assume !(1 == ~t2_pc~0); 106364#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 106361#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 106359#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 106357#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 106355#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 106353#L423-27 assume !(1 == ~t3_pc~0); 106351#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 106349#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 106347#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 106345#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 106343#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 106341#L442-27 assume !(1 == ~t4_pc~0); 106339#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 106337#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 106335#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 106333#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 106331#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 106329#L461-27 assume !(1 == ~t5_pc~0); 106323#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 106321#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 106319#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 106317#L985-27 assume !(0 != activate_threads_~tmp___4~0); 106313#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 106311#L480-27 assume !(1 == ~t6_pc~0); 106309#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 106306#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 106304#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 106302#L993-27 assume !(0 != activate_threads_~tmp___5~0); 106300#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 106298#L499-27 assume 1 == ~t7_pc~0; 106295#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 106292#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 106290#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 106288#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 106286#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 106285#L847-3 assume !(1 == ~T1_E~0); 106281#L852-3 assume !(1 == ~T2_E~0); 106279#L857-3 assume !(1 == ~T3_E~0); 106278#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106277#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 106276#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 106275#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 106274#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 106273#L887-3 assume !(1 == ~E_1~0); 106272#L892-3 assume !(1 == ~E_2~0); 106153#L897-3 assume !(1 == ~E_3~0); 106151#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106149#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 106147#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 106145#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 106143#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 106141#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 106132#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 106130#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 106128#L1187 assume !(0 == start_simulation_~tmp~3); 106122#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 106120#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 106110#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 106108#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 106106#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 106104#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 106102#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 106099#L1200 assume !(0 != start_simulation_~tmp___0~1); 100764#L1168-1 [2018-12-08 18:43:45,313 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,313 INFO L82 PathProgramCache]: Analyzing trace with hash 812836125, now seen corresponding path program 1 times [2018-12-08 18:43:45,313 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,313 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,314 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:45,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:45,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:45,324 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:45,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:43:45,325 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:45,325 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,325 INFO L82 PathProgramCache]: Analyzing trace with hash -739363572, now seen corresponding path program 1 times [2018-12-08 18:43:45,325 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,325 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,325 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:45,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:45,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:45,346 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:45,346 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:45,347 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:45,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:45,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:45,347 INFO L87 Difference]: Start difference. First operand 7713 states and 10766 transitions. cyclomatic complexity: 3061 Second operand 3 states. [2018-12-08 18:43:45,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:45,378 INFO L93 Difference]: Finished difference Result 5163 states and 7184 transitions. [2018-12-08 18:43:45,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:45,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5163 states and 7184 transitions. [2018-12-08 18:43:45,387 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5040 [2018-12-08 18:43:45,394 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5163 states to 5163 states and 7184 transitions. [2018-12-08 18:43:45,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5163 [2018-12-08 18:43:45,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5163 [2018-12-08 18:43:45,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5163 states and 7184 transitions. [2018-12-08 18:43:45,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:45,399 INFO L705 BuchiCegarLoop]: Abstraction has 5163 states and 7184 transitions. [2018-12-08 18:43:45,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5163 states and 7184 transitions. [2018-12-08 18:43:45,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5163 to 5163. [2018-12-08 18:43:45,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5163 states. [2018-12-08 18:43:45,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5163 states to 5163 states and 7184 transitions. [2018-12-08 18:43:45,428 INFO L728 BuchiCegarLoop]: Abstraction has 5163 states and 7184 transitions. [2018-12-08 18:43:45,428 INFO L608 BuchiCegarLoop]: Abstraction has 5163 states and 7184 transitions. [2018-12-08 18:43:45,428 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-12-08 18:43:45,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5163 states and 7184 transitions. [2018-12-08 18:43:45,436 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5040 [2018-12-08 18:43:45,436 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:45,436 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:45,436 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,436 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,436 INFO L794 eck$LassoCheckResult]: Stem: 113421#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 113327#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 113328#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 113696#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 113518#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 113285#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113286#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 113697#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 113506#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 113221#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 113103#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 113104#L561-1 assume !(0 == ~M_E~0); 113834#L759-1 assume !(0 == ~T1_E~0); 113584#L764-1 assume !(0 == ~T2_E~0); 113366#L769-1 assume !(0 == ~T3_E~0); 113067#L774-1 assume !(0 == ~T4_E~0); 113068#L779-1 assume !(0 == ~T5_E~0); 113759#L784-1 assume !(0 == ~T6_E~0); 113568#L789-1 assume !(0 == ~T7_E~0); 113160#L794-1 assume !(0 == ~E_M~0); 113161#L799-1 assume !(0 == ~E_1~0); 113805#L804-1 assume !(0 == ~E_2~0); 113675#L809-1 assume !(0 == ~E_3~0); 113458#L814-1 assume !(0 == ~E_4~0); 112985#L819-1 assume !(0 == ~E_5~0); 112986#L824-1 assume !(0 == ~E_6~0); 113648#L829-1 assume !(0 == ~E_7~0); 113527#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 113528#L366 assume !(1 == ~m_pc~0); 113636#L366-2 is_master_triggered_~__retres1~0 := 0; 113253#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 113048#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 113049#L945 assume !(0 != activate_threads_~tmp~1); 113367#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 113368#L385 assume !(1 == ~t1_pc~0); 113717#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 113441#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 113200#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 113201#L953 assume !(0 != activate_threads_~tmp___0~0); 113879#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 113880#L404 assume !(1 == ~t2_pc~0); 113888#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 113564#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 113519#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 113520#L961 assume !(0 != activate_threads_~tmp___1~0); 113731#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 113143#L423 assume !(1 == ~t3_pc~0); 113144#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 113148#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 113659#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 113403#L969 assume !(0 != activate_threads_~tmp___2~0); 113404#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 113159#L442 assume !(1 == ~t4_pc~0); 113150#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 113151#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 113699#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 113753#L977 assume !(0 != activate_threads_~tmp___3~0); 113899#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 113347#L461 assume !(1 == ~t5_pc~0); 113348#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 113351#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 113771#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 113679#L985 assume !(0 != activate_threads_~tmp___4~0); 113680#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 113507#L480 assume !(1 == ~t6_pc~0); 113496#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 113497#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 113871#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 113308#L993 assume !(0 != activate_threads_~tmp___5~0); 113309#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 113311#L499 assume !(1 == ~t7_pc~0); 113628#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 113041#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 112981#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 112982#L1001 assume !(0 != activate_threads_~tmp___6~0); 113840#L1001-2 assume !(1 == ~M_E~0); 113838#L847-1 assume !(1 == ~T1_E~0); 113582#L852-1 assume !(1 == ~T2_E~0); 113363#L857-1 assume !(1 == ~T3_E~0); 113063#L862-1 assume !(1 == ~T4_E~0); 113064#L867-1 assume !(1 == ~T5_E~0); 113757#L872-1 assume !(1 == ~T6_E~0); 113475#L877-1 assume !(1 == ~T7_E~0); 113168#L882-1 assume !(1 == ~E_M~0); 113169#L887-1 assume !(1 == ~E_1~0); 113810#L892-1 assume !(1 == ~E_2~0); 113684#L897-1 assume !(1 == ~E_3~0); 113471#L902-1 assume !(1 == ~E_4~0); 113000#L907-1 assume !(1 == ~E_5~0); 113001#L912-1 assume !(1 == ~E_6~0); 113644#L917-1 assume !(1 == ~E_7~0); 113645#L1168-1 [2018-12-08 18:43:45,437 INFO L796 eck$LassoCheckResult]: Loop: 113645#L1168-1 assume !false; 115550#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 115545#L734 assume !false; 115543#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 115537#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 115529#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 115526#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 115523#L631 assume !(0 != eval_~tmp~0); 115524#L749 start_simulation_~kernel_st~0 := 2; 117311#L519-1 start_simulation_~kernel_st~0 := 3; 117309#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 117308#L759-4 assume !(0 == ~T1_E~0); 117307#L764-3 assume !(0 == ~T2_E~0); 117306#L769-3 assume !(0 == ~T3_E~0); 117305#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117303#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117302#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117301#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117300#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117299#L799-3 assume !(0 == ~E_1~0); 117297#L804-3 assume !(0 == ~E_2~0); 117295#L809-3 assume !(0 == ~E_3~0); 117293#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117289#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117287#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117285#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117283#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117280#L366-27 assume 1 == ~m_pc~0; 117277#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 117274#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 117271#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 117269#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 117267#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117185#L385-27 assume !(1 == ~t1_pc~0); 117182#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 117180#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 117177#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 117174#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 117175#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117567#L404-27 assume !(1 == ~t2_pc~0); 117564#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 117562#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 117560#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 117556#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 117554#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 117552#L423-27 assume !(1 == ~t3_pc~0); 117550#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 117547#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 117545#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 117543#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 117540#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 117538#L442-27 assume !(1 == ~t4_pc~0); 117536#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 117534#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 117532#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 117530#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 117527#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 117525#L461-27 assume !(1 == ~t5_pc~0); 117521#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 117519#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 117517#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 117515#L985-27 assume !(0 != activate_threads_~tmp___4~0); 117512#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 117510#L480-27 assume !(1 == ~t6_pc~0); 117508#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 117506#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 117504#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 117502#L993-27 assume !(0 != activate_threads_~tmp___5~0); 117500#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 117498#L499-27 assume 1 == ~t7_pc~0; 117495#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 117493#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 117491#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 117489#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 117487#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 117485#L847-3 assume !(1 == ~T1_E~0); 117483#L852-3 assume !(1 == ~T2_E~0); 117474#L857-3 assume !(1 == ~T3_E~0); 117472#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117470#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 117466#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 117464#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 117463#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 117462#L887-3 assume !(1 == ~E_1~0); 117460#L892-3 assume !(1 == ~E_2~0); 117458#L897-3 assume !(1 == ~E_3~0); 117457#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 117456#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 117455#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 117454#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 117453#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 115593#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 115584#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 115582#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 115579#L1187 assume !(0 == start_simulation_~tmp~3); 115576#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 115574#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 115565#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 115564#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 115560#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 115558#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 115556#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 115554#L1200 assume !(0 != start_simulation_~tmp___0~1); 113645#L1168-1 [2018-12-08 18:43:45,437 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,437 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 3 times [2018-12-08 18:43:45,437 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,437 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,437 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,437 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:45,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:45,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:45,453 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,453 INFO L82 PathProgramCache]: Analyzing trace with hash -739363572, now seen corresponding path program 2 times [2018-12-08 18:43:45,453 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,453 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,454 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:45,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:45,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:45,472 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:45,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:45,472 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:45,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 18:43:45,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 18:43:45,473 INFO L87 Difference]: Start difference. First operand 5163 states and 7184 transitions. cyclomatic complexity: 2029 Second operand 5 states. [2018-12-08 18:43:45,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:45,557 INFO L93 Difference]: Finished difference Result 9407 states and 12968 transitions. [2018-12-08 18:43:45,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-08 18:43:45,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9407 states and 12968 transitions. [2018-12-08 18:43:45,576 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9260 [2018-12-08 18:43:45,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9407 states to 9407 states and 12968 transitions. [2018-12-08 18:43:45,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9407 [2018-12-08 18:43:45,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9407 [2018-12-08 18:43:45,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9407 states and 12968 transitions. [2018-12-08 18:43:45,599 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:45,599 INFO L705 BuchiCegarLoop]: Abstraction has 9407 states and 12968 transitions. [2018-12-08 18:43:45,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9407 states and 12968 transitions. [2018-12-08 18:43:45,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9407 to 5187. [2018-12-08 18:43:45,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5187 states. [2018-12-08 18:43:45,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5187 states to 5187 states and 7208 transitions. [2018-12-08 18:43:45,637 INFO L728 BuchiCegarLoop]: Abstraction has 5187 states and 7208 transitions. [2018-12-08 18:43:45,637 INFO L608 BuchiCegarLoop]: Abstraction has 5187 states and 7208 transitions. [2018-12-08 18:43:45,638 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-12-08 18:43:45,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5187 states and 7208 transitions. [2018-12-08 18:43:45,646 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5064 [2018-12-08 18:43:45,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:45,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:45,647 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,647 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,647 INFO L794 eck$LassoCheckResult]: Stem: 128012#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 127918#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 127919#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 128289#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 128106#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127868#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 127869#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128290#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 128094#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127804#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 127688#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 127689#L561-1 assume !(0 == ~M_E~0); 128412#L759-1 assume !(0 == ~T1_E~0); 128181#L764-1 assume !(0 == ~T2_E~0); 127956#L769-1 assume !(0 == ~T3_E~0); 127653#L774-1 assume !(0 == ~T4_E~0); 127654#L779-1 assume !(0 == ~T5_E~0); 128348#L784-1 assume !(0 == ~T6_E~0); 128160#L789-1 assume !(0 == ~T7_E~0); 127743#L794-1 assume !(0 == ~E_M~0); 127744#L799-1 assume !(0 == ~E_1~0); 128390#L804-1 assume !(0 == ~E_2~0); 128271#L809-1 assume !(0 == ~E_3~0); 128051#L814-1 assume !(0 == ~E_4~0); 127571#L819-1 assume !(0 == ~E_5~0); 127572#L824-1 assume !(0 == ~E_6~0); 128243#L829-1 assume !(0 == ~E_7~0); 128115#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128116#L366 assume !(1 == ~m_pc~0); 128232#L366-2 is_master_triggered_~__retres1~0 := 0; 127836#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 127634#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 127635#L945 assume !(0 != activate_threads_~tmp~1); 127957#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 127958#L385 assume !(1 == ~t1_pc~0); 128309#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 128032#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 127783#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 127784#L953 assume !(0 != activate_threads_~tmp___0~0); 128460#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 128461#L404 assume !(1 == ~t2_pc~0); 128469#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 128156#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 128107#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 128108#L961 assume !(0 != activate_threads_~tmp___1~0); 128321#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 127726#L423 assume !(1 == ~t3_pc~0); 127727#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 127731#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128254#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 127994#L969 assume !(0 != activate_threads_~tmp___2~0); 127995#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 127742#L442 assume !(1 == ~t4_pc~0); 127733#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 127734#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 128292#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 128341#L977 assume !(0 != activate_threads_~tmp___3~0); 128477#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 127937#L461 assume !(1 == ~t5_pc~0); 127938#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 127941#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 128405#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 128275#L985 assume !(0 != activate_threads_~tmp___4~0); 128276#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 128095#L480 assume !(1 == ~t6_pc~0); 128084#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 128085#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 128451#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 127898#L993 assume !(0 != activate_threads_~tmp___5~0); 127899#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 127901#L499 assume !(1 == ~t7_pc~0); 128225#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 127627#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 127567#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 127568#L1001 assume !(0 != activate_threads_~tmp___6~0); 128418#L1001-2 assume !(1 == ~M_E~0); 128414#L847-1 assume !(1 == ~T1_E~0); 128177#L852-1 assume !(1 == ~T2_E~0); 127952#L857-1 assume !(1 == ~T3_E~0); 127649#L862-1 assume !(1 == ~T4_E~0); 127650#L867-1 assume !(1 == ~T5_E~0); 128345#L872-1 assume !(1 == ~T6_E~0); 128065#L877-1 assume !(1 == ~T7_E~0); 127751#L882-1 assume !(1 == ~E_M~0); 127752#L887-1 assume !(1 == ~E_1~0); 128394#L892-1 assume !(1 == ~E_2~0); 128280#L897-1 assume !(1 == ~E_3~0); 128062#L902-1 assume !(1 == ~E_4~0); 127586#L907-1 assume !(1 == ~E_5~0); 127587#L912-1 assume !(1 == ~E_6~0); 128239#L917-1 assume !(1 == ~E_7~0); 127778#L1168-1 [2018-12-08 18:43:45,647 INFO L796 eck$LassoCheckResult]: Loop: 127778#L1168-1 assume !false; 127779#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 127905#L734 assume !false; 128409#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 127739#L574 assume !(0 == ~m_st~0); 127682#L578 assume !(0 == ~t1_st~0); 127683#L582 assume !(0 == ~t2_st~0); 128344#L586 assume !(0 == ~t3_st~0); 128091#L590 assume !(0 == ~t4_st~0); 128041#L594 assume !(0 == ~t5_st~0); 127643#L598 assume !(0 == ~t6_st~0); 127645#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 128480#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 130744#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 130745#L631 assume !(0 != eval_~tmp~0); 127987#L749 start_simulation_~kernel_st~0 := 2; 127988#L519-1 start_simulation_~kernel_st~0 := 3; 128291#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 128410#L759-4 assume !(0 == ~T1_E~0); 128168#L764-3 assume !(0 == ~T2_E~0); 127948#L769-3 assume !(0 == ~T3_E~0); 127638#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 127639#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 128343#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 128164#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 127747#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 127748#L799-3 assume !(0 == ~E_1~0); 129229#L804-3 assume !(0 == ~E_2~0); 129227#L809-3 assume !(0 == ~E_3~0); 129224#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 129222#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 129220#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 129218#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 129216#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 129214#L366-27 assume 1 == ~m_pc~0; 129211#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 129209#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 129207#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 129205#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 129203#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 129201#L385-27 assume !(1 == ~t1_pc~0); 129198#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 129196#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 129194#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 129192#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 128424#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 128425#L404-27 assume !(1 == ~t2_pc~0); 128372#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 128134#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 127966#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 127967#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 128185#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 127684#L423-27 assume !(1 == ~t3_pc~0); 127685#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 127692#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128253#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 127757#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 127758#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 127761#L442-27 assume !(1 == ~t4_pc~0); 131408#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 131407#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 131406#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 131405#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 131404#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 131403#L461-27 assume !(1 == ~t5_pc~0); 131402#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 131400#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 131398#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 131396#L985-27 assume !(0 != activate_threads_~tmp___4~0); 131394#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 131393#L480-27 assume !(1 == ~t6_pc~0); 131392#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 131391#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 131390#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 131389#L993-27 assume !(0 != activate_threads_~tmp___5~0); 131388#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 131387#L499-27 assume !(1 == ~t7_pc~0); 131386#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 131384#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 131383#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 131382#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 131381#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 131380#L847-3 assume !(1 == ~T1_E~0); 131379#L852-3 assume !(1 == ~T2_E~0); 131378#L857-3 assume !(1 == ~T3_E~0); 131377#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 131376#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131375#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131374#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 131373#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 131372#L887-3 assume !(1 == ~E_1~0); 131371#L892-3 assume !(1 == ~E_2~0); 131370#L897-3 assume !(1 == ~E_3~0); 131369#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131368#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 131367#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 131366#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 131365#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 131364#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 131353#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 131349#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 131344#L1187 assume !(0 == start_simulation_~tmp~3); 131337#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 127741#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 127625#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 127802#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 127803#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 127594#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 127595#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 127705#L1200 assume !(0 != start_simulation_~tmp___0~1); 127778#L1168-1 [2018-12-08 18:43:45,647 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,647 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 4 times [2018-12-08 18:43:45,647 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,648 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,648 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:45,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:45,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:45,685 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,685 INFO L82 PathProgramCache]: Analyzing trace with hash 1936868703, now seen corresponding path program 1 times [2018-12-08 18:43:45,685 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,685 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,685 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,685 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:45,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:45,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:45,714 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:45,714 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:45,714 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:45,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 18:43:45,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 18:43:45,714 INFO L87 Difference]: Start difference. First operand 5187 states and 7208 transitions. cyclomatic complexity: 2029 Second operand 5 states. [2018-12-08 18:43:45,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:45,807 INFO L93 Difference]: Finished difference Result 7727 states and 10875 transitions. [2018-12-08 18:43:45,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 18:43:45,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7727 states and 10875 transitions. [2018-12-08 18:43:45,828 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7556 [2018-12-08 18:43:45,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7727 states to 7727 states and 10875 transitions. [2018-12-08 18:43:45,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7727 [2018-12-08 18:43:45,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7727 [2018-12-08 18:43:45,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7727 states and 10875 transitions. [2018-12-08 18:43:45,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:45,851 INFO L705 BuchiCegarLoop]: Abstraction has 7727 states and 10875 transitions. [2018-12-08 18:43:45,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7727 states and 10875 transitions. [2018-12-08 18:43:45,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7727 to 5211. [2018-12-08 18:43:45,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5211 states. [2018-12-08 18:43:45,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5211 states to 5211 states and 7171 transitions. [2018-12-08 18:43:45,889 INFO L728 BuchiCegarLoop]: Abstraction has 5211 states and 7171 transitions. [2018-12-08 18:43:45,889 INFO L608 BuchiCegarLoop]: Abstraction has 5211 states and 7171 transitions. [2018-12-08 18:43:45,889 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-12-08 18:43:45,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5211 states and 7171 transitions. [2018-12-08 18:43:45,897 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5088 [2018-12-08 18:43:45,897 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:45,897 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:45,898 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,898 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:45,898 INFO L794 eck$LassoCheckResult]: Stem: 140959#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 140864#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 140865#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 141284#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 141063#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 140804#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 140805#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 141285#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 141050#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 140740#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 140617#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 140618#L561-1 assume !(0 == ~M_E~0); 141448#L759-1 assume !(0 == ~T1_E~0); 141143#L764-1 assume !(0 == ~T2_E~0); 140904#L769-1 assume !(0 == ~T3_E~0); 140581#L774-1 assume !(0 == ~T4_E~0); 140582#L779-1 assume !(0 == ~T5_E~0); 141352#L784-1 assume !(0 == ~T6_E~0); 141123#L789-1 assume !(0 == ~T7_E~0); 140677#L794-1 assume !(0 == ~E_M~0); 140678#L799-1 assume !(0 == ~E_1~0); 141400#L804-1 assume !(0 == ~E_2~0); 141253#L809-1 assume !(0 == ~E_3~0); 141000#L814-1 assume !(0 == ~E_4~0); 140499#L819-1 assume !(0 == ~E_5~0); 140500#L824-1 assume !(0 == ~E_6~0); 141219#L829-1 assume !(0 == ~E_7~0); 141072#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 141073#L366 assume !(1 == ~m_pc~0); 141208#L366-2 is_master_triggered_~__retres1~0 := 0; 140772#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 140562#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 140563#L945 assume !(0 != activate_threads_~tmp~1); 140905#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 140906#L385 assume !(1 == ~t1_pc~0); 141307#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 140980#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 140718#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 140719#L953 assume !(0 != activate_threads_~tmp___0~0); 141499#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 141500#L404 assume !(1 == ~t2_pc~0); 141509#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 141119#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 141064#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 141065#L961 assume !(0 != activate_threads_~tmp___1~0); 141322#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 140659#L423 assume !(1 == ~t3_pc~0); 140660#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 140666#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141233#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 140941#L969 assume !(0 != activate_threads_~tmp___2~0); 140942#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 140676#L442 assume !(1 == ~t4_pc~0); 140668#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 140669#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 141287#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 141346#L977 assume !(0 != activate_threads_~tmp___3~0); 141524#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 140883#L461 assume !(1 == ~t5_pc~0); 140884#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 140887#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 141365#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 141258#L985 assume !(0 != activate_threads_~tmp___4~0); 141259#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 141051#L480 assume !(1 == ~t6_pc~0); 141039#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 141040#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 141490#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 140839#L993 assume !(0 != activate_threads_~tmp___5~0); 140840#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 140844#L499 assume !(1 == ~t7_pc~0); 141200#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 140555#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 140495#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 140496#L1001 assume !(0 != activate_threads_~tmp___6~0); 141457#L1001-2 assume !(1 == ~M_E~0); 141451#L847-1 assume !(1 == ~T1_E~0); 141139#L852-1 assume !(1 == ~T2_E~0); 140901#L857-1 assume !(1 == ~T3_E~0); 140577#L862-1 assume !(1 == ~T4_E~0); 140578#L867-1 assume !(1 == ~T5_E~0); 141350#L872-1 assume !(1 == ~T6_E~0); 141019#L877-1 assume !(1 == ~T7_E~0); 140685#L882-1 assume !(1 == ~E_M~0); 140686#L887-1 assume !(1 == ~E_1~0); 141406#L892-1 assume !(1 == ~E_2~0); 141263#L897-1 assume !(1 == ~E_3~0); 141015#L902-1 assume !(1 == ~E_4~0); 140514#L907-1 assume !(1 == ~E_5~0); 140515#L912-1 assume !(1 == ~E_6~0); 141216#L917-1 assume !(1 == ~E_7~0); 140713#L1168-1 [2018-12-08 18:43:45,898 INFO L796 eck$LassoCheckResult]: Loop: 140713#L1168-1 assume !false; 140714#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 145149#L734 assume !false; 145624#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 145622#L574 assume !(0 == ~m_st~0); 145621#L578 assume !(0 == ~t1_st~0); 141369#L582 assume !(0 == ~t2_st~0); 141349#L586 assume !(0 == ~t3_st~0); 141047#L590 assume !(0 == ~t4_st~0); 140991#L594 assume !(0 == ~t5_st~0); 140571#L598 assume !(0 == ~t6_st~0); 140573#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 141532#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 145625#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 145623#L631 assume !(0 != eval_~tmp~0); 140934#L749 start_simulation_~kernel_st~0 := 2; 140935#L519-1 start_simulation_~kernel_st~0 := 3; 141286#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 141444#L759-4 assume !(0 == ~T1_E~0); 141129#L764-3 assume !(0 == ~T2_E~0); 140896#L769-3 assume !(0 == ~T3_E~0); 140897#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 145606#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 141348#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 141127#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 140681#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 140682#L799-3 assume !(0 == ~E_1~0); 145603#L804-3 assume !(0 == ~E_2~0); 145602#L809-3 assume !(0 == ~E_3~0); 141002#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 140501#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 140502#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 141220#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 141074#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 141075#L366-27 assume 1 == ~m_pc~0; 141171#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 140768#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 140526#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 140527#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 140862#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 141004#L385-27 assume !(1 == ~t1_pc~0); 141304#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 141305#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 140689#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 140690#L953-27 assume !(0 != activate_threads_~tmp___0~0); 145454#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 145452#L404-27 assume !(1 == ~t2_pc~0); 141506#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 141091#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 141092#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 141173#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 141174#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 140613#L423-27 assume !(1 == ~t3_pc~0); 140614#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 145579#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 145578#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 145577#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 145576#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 145575#L442-27 assume !(1 == ~t4_pc~0); 145574#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 145573#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 145572#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 145571#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 145570#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 140992#L461-27 assume !(1 == ~t5_pc~0); 140975#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 140994#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 141364#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 141058#L985-27 assume !(0 != activate_threads_~tmp___4~0); 141059#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 141060#L480-27 assume !(1 == ~t6_pc~0); 141112#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 141113#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 141470#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 140767#L993-27 assume !(0 != activate_threads_~tmp___5~0); 140743#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 140744#L499-27 assume 1 == ~t7_pc~0; 141132#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 140550#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 140551#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 140651#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 141410#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 141412#L847-3 assume !(1 == ~T1_E~0); 141142#L852-3 assume !(1 == ~T2_E~0); 140903#L857-3 assume !(1 == ~T3_E~0); 140579#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 140580#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 141351#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 141024#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 140687#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 140688#L887-3 assume !(1 == ~E_1~0); 141399#L892-3 assume !(1 == ~E_2~0); 141250#L897-3 assume !(1 == ~E_3~0); 140998#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 140497#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 140498#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 141218#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 141070#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 141071#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 145400#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 145393#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 145394#L1187 assume !(0 == start_simulation_~tmp~3); 145387#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 145388#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 145376#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 145377#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 141093#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 141094#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 145368#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 145369#L1200 assume !(0 != start_simulation_~tmp___0~1); 140713#L1168-1 [2018-12-08 18:43:45,898 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,898 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 5 times [2018-12-08 18:43:45,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,899 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:45,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:45,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:45,920 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:45,920 INFO L82 PathProgramCache]: Analyzing trace with hash -1461415746, now seen corresponding path program 1 times [2018-12-08 18:43:45,920 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:45,921 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:45,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,921 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:45,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:45,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:45,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:45,972 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:45,972 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:45,972 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:45,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 18:43:45,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 18:43:45,973 INFO L87 Difference]: Start difference. First operand 5211 states and 7171 transitions. cyclomatic complexity: 1968 Second operand 5 states. [2018-12-08 18:43:46,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:46,072 INFO L93 Difference]: Finished difference Result 8083 states and 11214 transitions. [2018-12-08 18:43:46,072 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 18:43:46,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8083 states and 11214 transitions. [2018-12-08 18:43:46,088 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7912 [2018-12-08 18:43:46,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8083 states to 8083 states and 11214 transitions. [2018-12-08 18:43:46,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8083 [2018-12-08 18:43:46,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8083 [2018-12-08 18:43:46,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8083 states and 11214 transitions. [2018-12-08 18:43:46,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:46,108 INFO L705 BuchiCegarLoop]: Abstraction has 8083 states and 11214 transitions. [2018-12-08 18:43:46,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8083 states and 11214 transitions. [2018-12-08 18:43:46,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8083 to 5235. [2018-12-08 18:43:46,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5235 states. [2018-12-08 18:43:46,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5235 states to 5235 states and 7134 transitions. [2018-12-08 18:43:46,144 INFO L728 BuchiCegarLoop]: Abstraction has 5235 states and 7134 transitions. [2018-12-08 18:43:46,144 INFO L608 BuchiCegarLoop]: Abstraction has 5235 states and 7134 transitions. [2018-12-08 18:43:46,144 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-12-08 18:43:46,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5235 states and 7134 transitions. [2018-12-08 18:43:46,153 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5112 [2018-12-08 18:43:46,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:46,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:46,154 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:46,154 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:46,155 INFO L794 eck$LassoCheckResult]: Stem: 154258#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 154170#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 154171#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 154586#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 154360#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154111#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154112#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154587#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 154348#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154045#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 153925#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 153926#L561-1 assume !(0 == ~M_E~0); 154736#L759-1 assume !(0 == ~T1_E~0); 154445#L764-1 assume !(0 == ~T2_E~0); 154207#L769-1 assume !(0 == ~T3_E~0); 153889#L774-1 assume !(0 == ~T4_E~0); 153890#L779-1 assume !(0 == ~T5_E~0); 154647#L784-1 assume !(0 == ~T6_E~0); 154425#L789-1 assume !(0 == ~T7_E~0); 153981#L794-1 assume !(0 == ~E_M~0); 153982#L799-1 assume !(0 == ~E_1~0); 154700#L804-1 assume !(0 == ~E_2~0); 154557#L809-1 assume !(0 == ~E_3~0); 154301#L814-1 assume !(0 == ~E_4~0); 153807#L819-1 assume !(0 == ~E_5~0); 153808#L824-1 assume !(0 == ~E_6~0); 154517#L829-1 assume !(0 == ~E_7~0); 154370#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 154371#L366 assume !(1 == ~m_pc~0); 154508#L366-2 is_master_triggered_~__retres1~0 := 0; 154082#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 153872#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 153873#L945 assume !(0 != activate_threads_~tmp~1); 154208#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 154209#L385 assume !(1 == ~t1_pc~0); 154606#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 154279#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 154024#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 154025#L953 assume !(0 != activate_threads_~tmp___0~0); 154787#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 154788#L404 assume !(1 == ~t2_pc~0); 154798#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 154424#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 154361#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 154362#L961 assume !(0 != activate_threads_~tmp___1~0); 154619#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 153966#L423 assume !(1 == ~t3_pc~0); 153967#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 153970#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 154534#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 154243#L969 assume !(0 != activate_threads_~tmp___2~0); 154244#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 153980#L442 assume !(1 == ~t4_pc~0); 153972#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 153973#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 154589#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 154640#L977 assume !(0 != activate_threads_~tmp___3~0); 154807#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 154189#L461 assume !(1 == ~t5_pc~0); 154190#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 154193#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 154722#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 154560#L985 assume !(0 != activate_threads_~tmp___4~0); 154561#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 154349#L480 assume !(1 == ~t6_pc~0); 154337#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 154338#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 154780#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 154145#L993 assume !(0 != activate_threads_~tmp___5~0); 154146#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 154151#L499 assume !(1 == ~t7_pc~0); 154499#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 153863#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 153803#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 153804#L1001 assume !(0 != activate_threads_~tmp___6~0); 154743#L1001-2 assume !(1 == ~M_E~0); 154740#L847-1 assume !(1 == ~T1_E~0); 154439#L852-1 assume !(1 == ~T2_E~0); 154204#L857-1 assume !(1 == ~T3_E~0); 153885#L862-1 assume !(1 == ~T4_E~0); 153886#L867-1 assume !(1 == ~T5_E~0); 154645#L872-1 assume !(1 == ~T6_E~0); 154319#L877-1 assume !(1 == ~T7_E~0); 153989#L882-1 assume !(1 == ~E_M~0); 153990#L887-1 assume !(1 == ~E_1~0); 154705#L892-1 assume !(1 == ~E_2~0); 154565#L897-1 assume !(1 == ~E_3~0); 154314#L902-1 assume !(1 == ~E_4~0); 153822#L907-1 assume !(1 == ~E_5~0); 153823#L912-1 assume !(1 == ~E_6~0); 154514#L917-1 assume !(1 == ~E_7~0); 154018#L1168-1 [2018-12-08 18:43:46,155 INFO L796 eck$LassoCheckResult]: Loop: 154018#L1168-1 assume !false; 154019#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 154447#L734 assume !false; 158989#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 158987#L574 assume !(0 == ~m_st~0); 158988#L578 assume !(0 == ~t1_st~0); 158984#L582 assume !(0 == ~t2_st~0); 158985#L586 assume !(0 == ~t3_st~0); 158986#L590 assume !(0 == ~t4_st~0); 158983#L594 assume !(0 == ~t5_st~0); 158982#L598 assume !(0 == ~t6_st~0); 158979#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 158978#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 158977#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 158976#L631 assume !(0 != eval_~tmp~0); 158975#L749 start_simulation_~kernel_st~0 := 2; 158974#L519-1 start_simulation_~kernel_st~0 := 3; 158973#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 158972#L759-4 assume !(0 == ~T1_E~0); 158971#L764-3 assume !(0 == ~T2_E~0); 158970#L769-3 assume !(0 == ~T3_E~0); 158969#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 158968#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 158967#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 158966#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 158965#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 158964#L799-3 assume !(0 == ~E_1~0); 158963#L804-3 assume !(0 == ~E_2~0); 158962#L809-3 assume !(0 == ~E_3~0); 158961#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 158959#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 158958#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 158957#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 154372#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 154373#L366-27 assume !(1 == ~m_pc~0); 154478#L366-29 is_master_triggered_~__retres1~0 := 0; 154075#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 153834#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 153835#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 154167#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 154305#L385-27 assume !(1 == ~t1_pc~0); 154591#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 154251#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 153993#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 153994#L953-27 assume !(0 != activate_threads_~tmp___0~0); 154747#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 154748#L404-27 assume !(1 == ~t2_pc~0); 154796#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 154389#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 154218#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 154219#L961-27 assume !(0 != activate_threads_~tmp___1~0); 154449#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 153921#L423-27 assume !(1 == ~t3_pc~0); 153922#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 158850#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 154531#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 153995#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 153996#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 153999#L442-27 assume !(1 == ~t4_pc~0); 154131#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 157466#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 157465#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 157464#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 157463#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157462#L461-27 assume 1 == ~t5_pc~0; 157460#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 157458#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157456#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 157454#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 157453#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 157452#L480-27 assume !(1 == ~t6_pc~0); 157416#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 157417#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 157334#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 157335#L993-27 assume !(0 != activate_threads_~tmp___5~0); 157324#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 157325#L499-27 assume !(1 == ~t7_pc~0); 157307#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 157306#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 157286#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 157287#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 157273#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 157274#L847-3 assume !(1 == ~T1_E~0); 157260#L852-3 assume !(1 == ~T2_E~0); 157261#L857-3 assume !(1 == ~T3_E~0); 157247#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 157248#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 157235#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 157236#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 157222#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 157223#L887-3 assume !(1 == ~E_1~0); 157210#L892-3 assume !(1 == ~E_2~0); 157211#L897-3 assume !(1 == ~E_3~0); 157198#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 157199#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 157185#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 157186#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 157164#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 157165#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 157149#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 157150#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 157139#L1187 assume !(0 == start_simulation_~tmp~3); 157140#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 158998#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 154291#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 154292#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 154390#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 154391#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 153944#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 153945#L1200 assume !(0 != start_simulation_~tmp___0~1); 154018#L1168-1 [2018-12-08 18:43:46,155 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:46,155 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 6 times [2018-12-08 18:43:46,155 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:46,155 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:46,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:46,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:46,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:46,178 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:46,179 INFO L82 PathProgramCache]: Analyzing trace with hash -1749265955, now seen corresponding path program 1 times [2018-12-08 18:43:46,179 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:46,179 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:46,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,179 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:46,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:46,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:46,220 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:46,220 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:46,220 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:46,221 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 18:43:46,221 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 18:43:46,221 INFO L87 Difference]: Start difference. First operand 5235 states and 7134 transitions. cyclomatic complexity: 1907 Second operand 5 states. [2018-12-08 18:43:46,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:46,367 INFO L93 Difference]: Finished difference Result 15028 states and 20289 transitions. [2018-12-08 18:43:46,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 18:43:46,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15028 states and 20289 transitions. [2018-12-08 18:43:46,412 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14724 [2018-12-08 18:43:46,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15028 states to 15028 states and 20289 transitions. [2018-12-08 18:43:46,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15028 [2018-12-08 18:43:46,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15028 [2018-12-08 18:43:46,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15028 states and 20289 transitions. [2018-12-08 18:43:46,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:46,452 INFO L705 BuchiCegarLoop]: Abstraction has 15028 states and 20289 transitions. [2018-12-08 18:43:46,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15028 states and 20289 transitions. [2018-12-08 18:43:46,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15028 to 5442. [2018-12-08 18:43:46,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5442 states. [2018-12-08 18:43:46,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5442 states to 5442 states and 7341 transitions. [2018-12-08 18:43:46,502 INFO L728 BuchiCegarLoop]: Abstraction has 5442 states and 7341 transitions. [2018-12-08 18:43:46,502 INFO L608 BuchiCegarLoop]: Abstraction has 5442 states and 7341 transitions. [2018-12-08 18:43:46,502 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-12-08 18:43:46,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5442 states and 7341 transitions. [2018-12-08 18:43:46,511 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5316 [2018-12-08 18:43:46,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:46,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:46,512 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:46,512 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:46,512 INFO L794 eck$LassoCheckResult]: Stem: 174535#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 174437#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 174438#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 174832#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 174629#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 174387#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174388#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174833#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174617#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174314#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 174199#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 174200#L561-1 assume !(0 == ~M_E~0); 174964#L759-1 assume !(0 == ~T1_E~0); 174704#L764-1 assume !(0 == ~T2_E~0); 174480#L769-1 assume !(0 == ~T3_E~0); 174165#L774-1 assume !(0 == ~T4_E~0); 174166#L779-1 assume !(0 == ~T5_E~0); 174901#L784-1 assume !(0 == ~T6_E~0); 174686#L789-1 assume !(0 == ~T7_E~0); 174253#L794-1 assume !(0 == ~E_M~0); 174254#L799-1 assume !(0 == ~E_1~0); 174941#L804-1 assume !(0 == ~E_2~0); 174815#L809-1 assume !(0 == ~E_3~0); 174574#L814-1 assume !(0 == ~E_4~0); 174083#L819-1 assume !(0 == ~E_5~0); 174084#L824-1 assume !(0 == ~E_6~0); 174783#L829-1 assume !(0 == ~E_7~0); 174637#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 174638#L366 assume !(1 == ~m_pc~0); 174768#L366-2 is_master_triggered_~__retres1~0 := 0; 174354#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 174355#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 174481#L945 assume !(0 != activate_threads_~tmp~1); 174482#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 174483#L385 assume !(1 == ~t1_pc~0); 174852#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 174556#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 174293#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 174294#L953 assume !(0 != activate_threads_~tmp___0~0); 175005#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 175006#L404 assume !(1 == ~t2_pc~0); 175013#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 174685#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 174630#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 174631#L961 assume !(0 != activate_threads_~tmp___1~0); 174869#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 174237#L423 assume !(1 == ~t3_pc~0); 174238#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 174242#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 174798#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 174517#L969 assume !(0 != activate_threads_~tmp___2~0); 174518#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 174252#L442 assume !(1 == ~t4_pc~0); 174244#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 174245#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 174835#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 174895#L977 assume !(0 != activate_threads_~tmp___3~0); 175019#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 174457#L461 assume !(1 == ~t5_pc~0); 174458#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 174462#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 174910#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 174818#L985 assume !(0 != activate_threads_~tmp___4~0); 174819#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 174618#L480 assume !(1 == ~t6_pc~0); 174607#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 174608#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 174999#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 174416#L993 assume !(0 != activate_threads_~tmp___5~0); 174417#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 174419#L499 assume !(1 == ~t7_pc~0); 174760#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 174139#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 174079#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 174080#L1001 assume !(0 != activate_threads_~tmp___6~0); 174970#L1001-2 assume !(1 == ~M_E~0); 174966#L847-1 assume !(1 == ~T1_E~0); 174700#L852-1 assume !(1 == ~T2_E~0); 174476#L857-1 assume !(1 == ~T3_E~0); 174161#L862-1 assume !(1 == ~T4_E~0); 174162#L867-1 assume !(1 == ~T5_E~0); 174899#L872-1 assume !(1 == ~T6_E~0); 174590#L877-1 assume !(1 == ~T7_E~0); 174261#L882-1 assume !(1 == ~E_M~0); 174262#L887-1 assume !(1 == ~E_1~0); 174946#L892-1 assume !(1 == ~E_2~0); 174823#L897-1 assume !(1 == ~E_3~0); 174586#L902-1 assume !(1 == ~E_4~0); 174098#L907-1 assume !(1 == ~E_5~0); 174099#L912-1 assume !(1 == ~E_6~0); 174780#L917-1 assume !(1 == ~E_7~0); 174288#L1168-1 [2018-12-08 18:43:46,512 INFO L796 eck$LassoCheckResult]: Loop: 174288#L1168-1 assume !false; 174289#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 174421#L734 assume !false; 174961#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 174249#L574 assume !(0 == ~m_st~0); 174193#L578 assume !(0 == ~t1_st~0); 174194#L582 assume !(0 == ~t2_st~0); 174898#L586 assume !(0 == ~t3_st~0); 174614#L590 assume !(0 == ~t4_st~0); 174566#L594 assume !(0 == ~t5_st~0); 174155#L598 assume !(0 == ~t6_st~0); 174157#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 175023#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 179436#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 179435#L631 assume !(0 != eval_~tmp~0); 179434#L749 start_simulation_~kernel_st~0 := 2; 179433#L519-1 start_simulation_~kernel_st~0 := 3; 179432#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 179431#L759-4 assume !(0 == ~T1_E~0); 179430#L764-3 assume !(0 == ~T2_E~0); 179429#L769-3 assume !(0 == ~T3_E~0); 179428#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 179427#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 179426#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 179425#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 179424#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 179423#L799-3 assume !(0 == ~E_1~0); 179422#L804-3 assume !(0 == ~E_2~0); 179421#L809-3 assume !(0 == ~E_3~0); 179420#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 179419#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 179418#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 179417#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 179416#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 174757#L366-27 assume 1 == ~m_pc~0; 174758#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 179414#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 179412#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 179410#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 179409#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 179408#L385-27 assume !(1 == ~t1_pc~0); 179406#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 179405#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 179404#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 179403#L953-27 assume !(0 != activate_threads_~tmp___0~0); 179402#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 175009#L404-27 assume !(1 == ~t2_pc~0); 174923#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 174656#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 174491#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 174492#L961-27 assume !(0 != activate_threads_~tmp___1~0); 174706#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 174195#L423-27 assume !(1 == ~t3_pc~0); 174196#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 174203#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 174797#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 174267#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 174268#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 174271#L442-27 assume !(1 == ~t4_pc~0); 174383#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 174384#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 174878#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 174879#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 174915#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 174565#L461-27 assume !(1 == ~t5_pc~0); 174551#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 174568#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 174909#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 174624#L985-27 assume !(0 != activate_threads_~tmp___4~0); 174625#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 174626#L480-27 assume !(1 == ~t6_pc~0); 174675#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 174676#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 174980#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 174344#L993-27 assume !(0 != activate_threads_~tmp___5~0); 174317#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 174318#L499-27 assume 1 == ~t7_pc~0; 174694#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 174132#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 174133#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 174230#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 174947#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 174948#L847-3 assume !(1 == ~T1_E~0); 174702#L852-3 assume !(1 == ~T2_E~0); 174478#L857-3 assume !(1 == ~T3_E~0); 174163#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 174164#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 174900#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 174594#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 174263#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 174264#L887-3 assume !(1 == ~E_1~0); 174940#L892-3 assume !(1 == ~E_2~0); 174812#L897-3 assume !(1 == ~E_3~0); 174572#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 174081#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 174082#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 174782#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 174636#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 174250#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 174159#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 174308#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 174309#L1187 assume !(0 == start_simulation_~tmp~3); 174348#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 174251#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 174137#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 174312#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 174313#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 174106#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 174107#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 174217#L1200 assume !(0 != start_simulation_~tmp___0~1); 174288#L1168-1 [2018-12-08 18:43:46,513 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:46,513 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 7 times [2018-12-08 18:43:46,513 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:46,513 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:46,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:46,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:46,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:46,530 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:46,530 INFO L82 PathProgramCache]: Analyzing trace with hash -1259591812, now seen corresponding path program 1 times [2018-12-08 18:43:46,530 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:46,530 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:46,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,531 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:46,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:46,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:46,579 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:46,579 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:46,579 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:46,579 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 18:43:46,579 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 18:43:46,579 INFO L87 Difference]: Start difference. First operand 5442 states and 7341 transitions. cyclomatic complexity: 1907 Second operand 5 states. [2018-12-08 18:43:46,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:46,681 INFO L93 Difference]: Finished difference Result 7198 states and 9688 transitions. [2018-12-08 18:43:46,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 18:43:46,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7198 states and 9688 transitions. [2018-12-08 18:43:46,696 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7056 [2018-12-08 18:43:46,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7198 states to 7198 states and 9688 transitions. [2018-12-08 18:43:46,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7198 [2018-12-08 18:43:46,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7198 [2018-12-08 18:43:46,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7198 states and 9688 transitions. [2018-12-08 18:43:46,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:46,711 INFO L705 BuchiCegarLoop]: Abstraction has 7198 states and 9688 transitions. [2018-12-08 18:43:46,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7198 states and 9688 transitions. [2018-12-08 18:43:46,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7198 to 5454. [2018-12-08 18:43:46,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5454 states. [2018-12-08 18:43:46,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5454 states to 5454 states and 7288 transitions. [2018-12-08 18:43:46,745 INFO L728 BuchiCegarLoop]: Abstraction has 5454 states and 7288 transitions. [2018-12-08 18:43:46,745 INFO L608 BuchiCegarLoop]: Abstraction has 5454 states and 7288 transitions. [2018-12-08 18:43:46,745 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-12-08 18:43:46,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5454 states and 7288 transitions. [2018-12-08 18:43:46,754 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5328 [2018-12-08 18:43:46,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:46,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:46,754 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:46,755 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:46,755 INFO L794 eck$LassoCheckResult]: Stem: 187199#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 187102#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 187103#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 187532#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 187301#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 187047#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 187048#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 187533#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 187287#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 186977#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 186853#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 186854#L561-1 assume !(0 == ~M_E~0); 187686#L759-1 assume !(0 == ~T1_E~0); 187380#L764-1 assume !(0 == ~T2_E~0); 187144#L769-1 assume !(0 == ~T3_E~0); 186819#L774-1 assume !(0 == ~T4_E~0); 186820#L779-1 assume !(0 == ~T5_E~0); 187594#L784-1 assume !(0 == ~T6_E~0); 187359#L789-1 assume !(0 == ~T7_E~0); 186915#L794-1 assume !(0 == ~E_M~0); 186916#L799-1 assume !(0 == ~E_1~0); 187649#L804-1 assume !(0 == ~E_2~0); 187504#L809-1 assume !(0 == ~E_3~0); 187243#L814-1 assume !(0 == ~E_4~0); 186737#L819-1 assume !(0 == ~E_5~0); 186738#L824-1 assume !(0 == ~E_6~0); 187468#L829-1 assume !(0 == ~E_7~0); 187310#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 187311#L366 assume !(1 == ~m_pc~0); 187455#L366-2 is_master_triggered_~__retres1~0 := 0; 187014#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 186802#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 186803#L945 assume !(0 != activate_threads_~tmp~1); 187145#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 187146#L385 assume !(1 == ~t1_pc~0); 187552#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 187222#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 186956#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 186957#L953 assume !(0 != activate_threads_~tmp___0~0); 187737#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 187738#L404 assume !(1 == ~t2_pc~0); 187745#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 187358#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 187302#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 187303#L961 assume !(0 != activate_threads_~tmp___1~0); 187564#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 186898#L423 assume !(1 == ~t3_pc~0); 186899#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 186903#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 187483#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 187181#L969 assume !(0 != activate_threads_~tmp___2~0); 187182#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 186914#L442 assume !(1 == ~t4_pc~0); 186905#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 186906#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 187535#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 187586#L977 assume !(0 != activate_threads_~tmp___3~0); 187754#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 187122#L461 assume !(1 == ~t5_pc~0); 187123#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 187126#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 187676#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 187509#L985 assume !(0 != activate_threads_~tmp___4~0); 187510#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 187288#L480 assume !(1 == ~t6_pc~0); 187276#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 187277#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 187730#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 187077#L993 assume !(0 != activate_threads_~tmp___5~0); 187078#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 187080#L499 assume !(1 == ~t7_pc~0); 187444#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 186793#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 186733#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 186734#L1001 assume !(0 != activate_threads_~tmp___6~0); 187694#L1001-2 assume !(1 == ~M_E~0); 187690#L847-1 assume !(1 == ~T1_E~0); 187374#L852-1 assume !(1 == ~T2_E~0); 187139#L857-1 assume !(1 == ~T3_E~0); 186815#L862-1 assume !(1 == ~T4_E~0); 186816#L867-1 assume !(1 == ~T5_E~0); 187591#L872-1 assume !(1 == ~T6_E~0); 187258#L877-1 assume !(1 == ~T7_E~0); 186923#L882-1 assume !(1 == ~E_M~0); 186924#L887-1 assume !(1 == ~E_1~0); 187653#L892-1 assume !(1 == ~E_2~0); 187514#L897-1 assume !(1 == ~E_3~0); 187254#L902-1 assume !(1 == ~E_4~0); 186752#L907-1 assume !(1 == ~E_5~0); 186753#L912-1 assume !(1 == ~E_6~0); 187463#L917-1 assume !(1 == ~E_7~0); 187464#L1168-1 [2018-12-08 18:43:46,755 INFO L796 eck$LassoCheckResult]: Loop: 187464#L1168-1 assume !false; 190739#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 190735#L734 assume !false; 190734#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 190731#L574 assume !(0 == ~m_st~0); 190732#L578 assume !(0 == ~t1_st~0); 190727#L582 assume !(0 == ~t2_st~0); 190728#L586 assume !(0 == ~t3_st~0); 190730#L590 assume !(0 == ~t4_st~0); 190725#L594 assume !(0 == ~t5_st~0); 190726#L598 assume !(0 == ~t6_st~0); 190729#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 190733#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 190717#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 190718#L631 assume !(0 != eval_~tmp~0); 190981#L749 start_simulation_~kernel_st~0 := 2; 190980#L519-1 start_simulation_~kernel_st~0 := 3; 190979#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 190978#L759-4 assume !(0 == ~T1_E~0); 190977#L764-3 assume !(0 == ~T2_E~0); 190976#L769-3 assume !(0 == ~T3_E~0); 190975#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 190974#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 190973#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 190972#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 190971#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 190970#L799-3 assume !(0 == ~E_1~0); 190969#L804-3 assume !(0 == ~E_2~0); 190968#L809-3 assume !(0 == ~E_3~0); 190967#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 190966#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 190965#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 190964#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 190963#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 190962#L366-27 assume 1 == ~m_pc~0; 190960#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 190958#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 190956#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 190953#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 190950#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 190947#L385-27 assume !(1 == ~t1_pc~0); 190943#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 190940#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 190938#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 190935#L953-27 assume !(0 != activate_threads_~tmp___0~0); 190933#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 190931#L404-27 assume !(1 == ~t2_pc~0); 190928#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 190927#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 190926#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 190923#L961-27 assume !(0 != activate_threads_~tmp___1~0); 190921#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 190919#L423-27 assume !(1 == ~t3_pc~0); 190917#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 190915#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 190913#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 190911#L969-27 assume !(0 != activate_threads_~tmp___2~0); 190909#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 190907#L442-27 assume !(1 == ~t4_pc~0); 190906#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 190904#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 190902#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 190901#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 190898#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 190894#L461-27 assume !(1 == ~t5_pc~0); 190890#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 190885#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 187671#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 187294#L985-27 assume !(0 != activate_threads_~tmp___4~0); 187295#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 190871#L480-27 assume !(1 == ~t6_pc~0); 190867#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 190863#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 190860#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 190857#L993-27 assume !(0 != activate_threads_~tmp___5~0); 190853#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 190850#L499-27 assume 1 == ~t7_pc~0; 190846#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 190843#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 186887#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 186888#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 187657#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 187658#L847-3 assume !(1 == ~T1_E~0); 187376#L852-3 assume !(1 == ~T2_E~0); 187141#L857-3 assume !(1 == ~T3_E~0); 187142#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 187753#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 187592#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 187593#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 190815#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 190812#L887-3 assume !(1 == ~E_1~0); 190809#L892-3 assume !(1 == ~E_2~0); 190806#L897-3 assume !(1 == ~E_3~0); 190803#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 190799#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 190795#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 190791#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 190788#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 190786#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 190776#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 190773#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 190769#L1187 assume !(0 == start_simulation_~tmp~3); 190766#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 190764#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 190755#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 190753#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 190750#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 190748#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 190746#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 190744#L1200 assume !(0 != start_simulation_~tmp___0~1); 187464#L1168-1 [2018-12-08 18:43:46,755 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:46,755 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 8 times [2018-12-08 18:43:46,755 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:46,755 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:46,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,756 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:46,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:46,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:46,774 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:46,774 INFO L82 PathProgramCache]: Analyzing trace with hash -383572806, now seen corresponding path program 1 times [2018-12-08 18:43:46,774 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:46,774 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:46,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,775 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:46,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:46,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:46,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:46,816 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:46,816 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:46,816 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:46,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 18:43:46,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 18:43:46,817 INFO L87 Difference]: Start difference. First operand 5454 states and 7288 transitions. cyclomatic complexity: 1842 Second operand 5 states. [2018-12-08 18:43:46,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:46,982 INFO L93 Difference]: Finished difference Result 9641 states and 12943 transitions. [2018-12-08 18:43:46,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 18:43:46,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9641 states and 12943 transitions. [2018-12-08 18:43:47,017 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9499 [2018-12-08 18:43:47,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9641 states to 9641 states and 12943 transitions. [2018-12-08 18:43:47,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9641 [2018-12-08 18:43:47,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9641 [2018-12-08 18:43:47,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9641 states and 12943 transitions. [2018-12-08 18:43:47,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:47,052 INFO L705 BuchiCegarLoop]: Abstraction has 9641 states and 12943 transitions. [2018-12-08 18:43:47,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9641 states and 12943 transitions. [2018-12-08 18:43:47,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9641 to 5562. [2018-12-08 18:43:47,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5562 states. [2018-12-08 18:43:47,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5562 states to 5562 states and 7363 transitions. [2018-12-08 18:43:47,125 INFO L728 BuchiCegarLoop]: Abstraction has 5562 states and 7363 transitions. [2018-12-08 18:43:47,125 INFO L608 BuchiCegarLoop]: Abstraction has 5562 states and 7363 transitions. [2018-12-08 18:43:47,125 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-12-08 18:43:47,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5562 states and 7363 transitions. [2018-12-08 18:43:47,134 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5436 [2018-12-08 18:43:47,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:47,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:47,135 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:47,135 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:47,135 INFO L794 eck$LassoCheckResult]: Stem: 202312#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 202213#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 202214#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 202628#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 202409#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 202152#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 202153#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 202629#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 202396#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 202085#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 201961#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 201962#L561-1 assume !(0 == ~M_E~0); 202780#L759-1 assume !(0 == ~T1_E~0); 202482#L764-1 assume !(0 == ~T2_E~0); 202252#L769-1 assume !(0 == ~T3_E~0); 201928#L774-1 assume !(0 == ~T4_E~0); 201929#L779-1 assume !(0 == ~T5_E~0); 202704#L784-1 assume !(0 == ~T6_E~0); 202464#L789-1 assume !(0 == ~T7_E~0); 202021#L794-1 assume !(0 == ~E_M~0); 202022#L799-1 assume !(0 == ~E_1~0); 202755#L804-1 assume !(0 == ~E_2~0); 202605#L809-1 assume !(0 == ~E_3~0); 202350#L814-1 assume !(0 == ~E_4~0); 201846#L819-1 assume !(0 == ~E_5~0); 201847#L824-1 assume !(0 == ~E_6~0); 202572#L829-1 assume !(0 == ~E_7~0); 202417#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 202418#L366 assume !(1 == ~m_pc~0); 202555#L366-2 is_master_triggered_~__retres1~0 := 0; 202119#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 201911#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 201912#L945 assume !(0 != activate_threads_~tmp~1); 202253#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 202254#L385 assume !(1 == ~t1_pc~0); 202653#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 202332#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 202063#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 202064#L953 assume !(0 != activate_threads_~tmp___0~0); 202830#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 202831#L404 assume !(1 == ~t2_pc~0); 202839#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 202463#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 202410#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 202411#L961 assume !(0 != activate_threads_~tmp___1~0); 202672#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 202005#L423 assume !(1 == ~t3_pc~0); 202006#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 202009#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 202588#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 202291#L969 assume !(0 != activate_threads_~tmp___2~0); 202292#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 202020#L442 assume !(1 == ~t4_pc~0); 202011#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 202012#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 202632#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 202696#L977 assume !(0 != activate_threads_~tmp___3~0); 202854#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 202232#L461 assume !(1 == ~t5_pc~0); 202233#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 202236#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 202771#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 202608#L985 assume !(0 != activate_threads_~tmp___4~0); 202609#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 202397#L480 assume !(1 == ~t6_pc~0); 202386#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 202387#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 202824#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 202188#L993 assume !(0 != activate_threads_~tmp___5~0); 202189#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 202194#L499 assume !(1 == ~t7_pc~0); 202545#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 201902#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 201842#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 201843#L1001 assume !(0 != activate_threads_~tmp___6~0); 202784#L1001-2 assume !(1 == ~M_E~0); 202782#L847-1 assume !(1 == ~T1_E~0); 202479#L852-1 assume !(1 == ~T2_E~0); 202248#L857-1 assume !(1 == ~T3_E~0); 201924#L862-1 assume !(1 == ~T4_E~0); 201925#L867-1 assume !(1 == ~T5_E~0); 202701#L872-1 assume !(1 == ~T6_E~0); 202368#L877-1 assume !(1 == ~T7_E~0); 202029#L882-1 assume !(1 == ~E_M~0); 202030#L887-1 assume !(1 == ~E_1~0); 202761#L892-1 assume !(1 == ~E_2~0); 202613#L897-1 assume !(1 == ~E_3~0); 202364#L902-1 assume !(1 == ~E_4~0); 201861#L907-1 assume !(1 == ~E_5~0); 201862#L912-1 assume !(1 == ~E_6~0); 202566#L917-1 assume !(1 == ~E_7~0); 202567#L1168-1 [2018-12-08 18:43:47,135 INFO L796 eck$LassoCheckResult]: Loop: 202567#L1168-1 assume !false; 203914#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 203909#L734 assume !false; 203908#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 203905#L574 assume !(0 == ~m_st~0); 203906#L578 assume !(0 == ~t1_st~0); 203901#L582 assume !(0 == ~t2_st~0); 203902#L586 assume !(0 == ~t3_st~0); 203904#L590 assume !(0 == ~t4_st~0); 203899#L594 assume !(0 == ~t5_st~0); 203900#L598 assume !(0 == ~t6_st~0); 203903#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 203907#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 203843#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 203844#L631 assume !(0 != eval_~tmp~0); 204374#L749 start_simulation_~kernel_st~0 := 2; 204373#L519-1 start_simulation_~kernel_st~0 := 3; 204372#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 204371#L759-4 assume !(0 == ~T1_E~0); 204370#L764-3 assume !(0 == ~T2_E~0); 204369#L769-3 assume !(0 == ~T3_E~0); 204368#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 204367#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 204366#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 204365#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 204364#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 204363#L799-3 assume !(0 == ~E_1~0); 204362#L804-3 assume !(0 == ~E_2~0); 204361#L809-3 assume !(0 == ~E_3~0); 204360#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 204359#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 204358#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 204357#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 204356#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 204355#L366-27 assume !(1 == ~m_pc~0); 204354#L366-29 is_master_triggered_~__retres1~0 := 0; 204352#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 204350#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 204348#L945-27 assume !(0 != activate_threads_~tmp~1); 204345#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 204342#L385-27 assume !(1 == ~t1_pc~0); 204338#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 204335#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 204332#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 204330#L953-27 assume !(0 != activate_threads_~tmp___0~0); 204327#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 204325#L404-27 assume !(1 == ~t2_pc~0); 204322#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 204320#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 204318#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 204316#L961-27 assume !(0 != activate_threads_~tmp___1~0); 204314#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 204311#L423-27 assume !(1 == ~t3_pc~0); 204308#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 204305#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 204302#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 204300#L969-27 assume !(0 != activate_threads_~tmp___2~0); 204298#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 204296#L442-27 assume !(1 == ~t4_pc~0); 204294#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 204291#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 204287#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 204283#L977-27 assume !(0 != activate_threads_~tmp___3~0); 204279#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 204274#L461-27 assume !(1 == ~t5_pc~0); 204270#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 204264#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 204259#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 204254#L985-27 assume !(0 != activate_threads_~tmp___4~0); 204248#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 204242#L480-27 assume !(1 == ~t6_pc~0); 204236#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 204229#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 204224#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 204220#L993-27 assume !(0 != activate_threads_~tmp___5~0); 204216#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 204212#L499-27 assume !(1 == ~t7_pc~0); 204208#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 204203#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 204198#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 204192#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 204185#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 204178#L847-3 assume !(1 == ~T1_E~0); 204173#L852-3 assume !(1 == ~T2_E~0); 204169#L857-3 assume !(1 == ~T3_E~0); 204164#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 204160#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 204156#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 204151#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 204146#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 204141#L887-3 assume !(1 == ~E_1~0); 204134#L892-3 assume !(1 == ~E_2~0); 204129#L897-3 assume !(1 == ~E_3~0); 204085#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 204082#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 204080#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 204078#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 204076#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 204074#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 204063#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 204060#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 203983#L1187 assume !(0 == start_simulation_~tmp~3); 203980#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 203978#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 203962#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 203954#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 203946#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 203939#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 203931#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 203926#L1200 assume !(0 != start_simulation_~tmp___0~1); 202567#L1168-1 [2018-12-08 18:43:47,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:47,136 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 9 times [2018-12-08 18:43:47,136 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:47,136 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:47,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,137 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:47,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:47,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:47,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:47,160 INFO L82 PathProgramCache]: Analyzing trace with hash 82957620, now seen corresponding path program 1 times [2018-12-08 18:43:47,160 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:47,160 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:47,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,161 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:47,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:47,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:47,184 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:47,184 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:47,184 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:47,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:47,184 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:47,184 INFO L87 Difference]: Start difference. First operand 5562 states and 7363 transitions. cyclomatic complexity: 1809 Second operand 3 states. [2018-12-08 18:43:47,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:47,229 INFO L93 Difference]: Finished difference Result 10486 states and 13695 transitions. [2018-12-08 18:43:47,229 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:47,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10486 states and 13695 transitions. [2018-12-08 18:43:47,250 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10336 [2018-12-08 18:43:47,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10486 states to 10486 states and 13695 transitions. [2018-12-08 18:43:47,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10486 [2018-12-08 18:43:47,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10486 [2018-12-08 18:43:47,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10486 states and 13695 transitions. [2018-12-08 18:43:47,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:47,270 INFO L705 BuchiCegarLoop]: Abstraction has 10486 states and 13695 transitions. [2018-12-08 18:43:47,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10486 states and 13695 transitions. [2018-12-08 18:43:47,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10486 to 10038. [2018-12-08 18:43:47,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10038 states. [2018-12-08 18:43:47,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10038 states to 10038 states and 13135 transitions. [2018-12-08 18:43:47,325 INFO L728 BuchiCegarLoop]: Abstraction has 10038 states and 13135 transitions. [2018-12-08 18:43:47,325 INFO L608 BuchiCegarLoop]: Abstraction has 10038 states and 13135 transitions. [2018-12-08 18:43:47,325 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-12-08 18:43:47,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10038 states and 13135 transitions. [2018-12-08 18:43:47,341 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9888 [2018-12-08 18:43:47,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:47,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:47,342 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:47,342 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:47,342 INFO L794 eck$LassoCheckResult]: Stem: 218350#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 218256#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 218257#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 218642#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 218448#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 218201#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 218202#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 218643#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 218435#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 218131#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 218017#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 218018#L561-1 assume !(0 == ~M_E~0); 218784#L759-1 assume !(0 == ~T1_E~0); 218516#L764-1 assume !(0 == ~T2_E~0); 218299#L769-1 assume !(0 == ~T3_E~0); 217982#L774-1 assume !(0 == ~T4_E~0); 217983#L779-1 assume !(0 == ~T5_E~0); 218709#L784-1 assume !(0 == ~T6_E~0); 218498#L789-1 assume !(0 == ~T7_E~0); 218070#L794-1 assume !(0 == ~E_M~0); 218071#L799-1 assume !(0 == ~E_1~0); 218757#L804-1 assume !(0 == ~E_2~0); 218623#L809-1 assume !(0 == ~E_3~0); 218391#L814-1 assume !(0 == ~E_4~0); 217900#L819-1 assume !(0 == ~E_5~0); 217901#L824-1 assume !(0 == ~E_6~0); 218594#L829-1 assume !(0 == ~E_7~0); 218456#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 218457#L366 assume !(1 == ~m_pc~0); 218579#L366-2 is_master_triggered_~__retres1~0 := 0; 218169#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 217965#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 217966#L945 assume !(0 != activate_threads_~tmp~1); 218300#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 218301#L385 assume !(1 == ~t1_pc~0); 218664#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 218371#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 218110#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 218111#L953 assume !(0 != activate_threads_~tmp___0~0); 218826#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 218827#L404 assume !(1 == ~t2_pc~0); 218832#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 218497#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 218449#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 218450#L961 assume !(0 != activate_threads_~tmp___1~0); 218679#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 218054#L423 assume !(1 == ~t3_pc~0); 218055#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 218059#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 218607#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 218333#L969 assume !(0 != activate_threads_~tmp___2~0); 218334#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 218069#L442 assume !(1 == ~t4_pc~0); 218061#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 218062#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 218645#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 218703#L977 assume !(0 != activate_threads_~tmp___3~0); 218838#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 218275#L461 assume !(1 == ~t5_pc~0); 218276#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 218280#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 218772#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 218626#L985 assume !(0 != activate_threads_~tmp___4~0); 218627#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 218436#L480 assume !(1 == ~t6_pc~0); 218423#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 218424#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 218819#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 218233#L993 assume !(0 != activate_threads_~tmp___5~0); 218234#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 218237#L499 assume !(1 == ~t7_pc~0); 218570#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 217956#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 217896#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 217897#L1001 assume !(0 != activate_threads_~tmp___6~0); 218790#L1001-2 assume !(1 == ~M_E~0); 218786#L847-1 assume !(1 == ~T1_E~0); 218513#L852-1 assume !(1 == ~T2_E~0); 218295#L857-1 assume !(1 == ~T3_E~0); 217978#L862-1 assume !(1 == ~T4_E~0); 217979#L867-1 assume !(1 == ~T5_E~0); 218707#L872-1 assume !(1 == ~T6_E~0); 218407#L877-1 assume !(1 == ~T7_E~0); 218078#L882-1 assume !(1 == ~E_M~0); 218079#L887-1 assume !(1 == ~E_1~0); 218762#L892-1 assume !(1 == ~E_2~0); 218631#L897-1 assume !(1 == ~E_3~0); 218402#L902-1 assume !(1 == ~E_4~0); 217915#L907-1 assume !(1 == ~E_5~0); 217916#L912-1 assume !(1 == ~E_6~0); 218589#L917-1 assume !(1 == ~E_7~0); 218590#L1168-1 [2018-12-08 18:43:47,342 INFO L796 eck$LassoCheckResult]: Loop: 218590#L1168-1 assume !false; 222682#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 222677#L734 assume !false; 222675#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 222672#L574 assume !(0 == ~m_st~0); 222673#L578 assume !(0 == ~t1_st~0); 222913#L582 assume !(0 == ~t2_st~0); 222911#L586 assume !(0 == ~t3_st~0); 222909#L590 assume !(0 == ~t4_st~0); 222907#L594 assume !(0 == ~t5_st~0); 222906#L598 assume !(0 == ~t6_st~0); 222904#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 222903#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 222902#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 222895#L631 assume !(0 != eval_~tmp~0); 222893#L749 start_simulation_~kernel_st~0 := 2; 222891#L519-1 start_simulation_~kernel_st~0 := 3; 222888#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 222886#L759-4 assume !(0 == ~T1_E~0); 222884#L764-3 assume !(0 == ~T2_E~0); 222881#L769-3 assume !(0 == ~T3_E~0); 222879#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 222877#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 222876#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 222875#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 222873#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 222871#L799-3 assume !(0 == ~E_1~0); 222870#L804-3 assume !(0 == ~E_2~0); 222869#L809-3 assume !(0 == ~E_3~0); 222867#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 222864#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 222862#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 222860#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 222855#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 222853#L366-27 assume 1 == ~m_pc~0; 222849#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 222847#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 222845#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 222842#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 222840#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 222838#L385-27 assume !(1 == ~t1_pc~0); 222834#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 222832#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 222830#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 222828#L953-27 assume !(0 != activate_threads_~tmp___0~0); 222826#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 222824#L404-27 assume !(1 == ~t2_pc~0); 222821#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 222819#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 222817#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 222815#L961-27 assume !(0 != activate_threads_~tmp___1~0); 222813#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 222811#L423-27 assume !(1 == ~t3_pc~0); 222809#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 222807#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 222805#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 222803#L969-27 assume !(0 != activate_threads_~tmp___2~0); 222801#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 222799#L442-27 assume !(1 == ~t4_pc~0); 222795#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 222793#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 222791#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 222789#L977-27 assume !(0 != activate_threads_~tmp___3~0); 222786#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 222784#L461-27 assume 1 == ~t5_pc~0; 222782#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 222783#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 223616#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 222773#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 222771#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 222769#L480-27 assume !(1 == ~t6_pc~0); 222767#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 222764#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 222762#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 222760#L993-27 assume !(0 != activate_threads_~tmp___5~0); 222758#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 222756#L499-27 assume !(1 == ~t7_pc~0); 222754#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 222751#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 222749#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 222747#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 222745#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 222743#L847-3 assume !(1 == ~T1_E~0); 222741#L852-3 assume !(1 == ~T2_E~0); 222739#L857-3 assume !(1 == ~T3_E~0); 222737#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 222735#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 222733#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 222731#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 222729#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 222727#L887-3 assume !(1 == ~E_1~0); 222726#L892-3 assume !(1 == ~E_2~0); 222725#L897-3 assume !(1 == ~E_3~0); 222723#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 222721#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 222719#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 222718#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 222717#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 222713#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 222711#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 222709#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 222706#L1187 assume !(0 == start_simulation_~tmp~3); 222703#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 222700#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 222696#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 222694#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 222692#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 222690#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 222687#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 222685#L1200 assume !(0 != start_simulation_~tmp___0~1); 218590#L1168-1 [2018-12-08 18:43:47,342 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:47,343 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 10 times [2018-12-08 18:43:47,343 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:47,343 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:47,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,343 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:47,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:47,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:47,361 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:47,361 INFO L82 PathProgramCache]: Analyzing trace with hash 986797242, now seen corresponding path program 1 times [2018-12-08 18:43:47,361 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:47,361 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:47,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,362 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:47,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:47,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:47,420 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:47,421 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 18:43:47,421 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:47,421 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 18:43:47,421 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 18:43:47,421 INFO L87 Difference]: Start difference. First operand 10038 states and 13135 transitions. cyclomatic complexity: 3105 Second operand 5 states. [2018-12-08 18:43:47,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:47,576 INFO L93 Difference]: Finished difference Result 21705 states and 28590 transitions. [2018-12-08 18:43:47,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 18:43:47,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21705 states and 28590 transitions. [2018-12-08 18:43:47,620 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21424 [2018-12-08 18:43:47,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21705 states to 21705 states and 28590 transitions. [2018-12-08 18:43:47,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21705 [2018-12-08 18:43:47,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21705 [2018-12-08 18:43:47,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21705 states and 28590 transitions. [2018-12-08 18:43:47,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-12-08 18:43:47,667 INFO L705 BuchiCegarLoop]: Abstraction has 21705 states and 28590 transitions. [2018-12-08 18:43:47,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21705 states and 28590 transitions. [2018-12-08 18:43:47,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21705 to 10425. [2018-12-08 18:43:47,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10425 states. [2018-12-08 18:43:47,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10425 states to 10425 states and 13522 transitions. [2018-12-08 18:43:47,744 INFO L728 BuchiCegarLoop]: Abstraction has 10425 states and 13522 transitions. [2018-12-08 18:43:47,744 INFO L608 BuchiCegarLoop]: Abstraction has 10425 states and 13522 transitions. [2018-12-08 18:43:47,744 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-12-08 18:43:47,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10425 states and 13522 transitions. [2018-12-08 18:43:47,759 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10272 [2018-12-08 18:43:47,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:47,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:47,760 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:47,761 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:47,761 INFO L794 eck$LassoCheckResult]: Stem: 250109#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 250015#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 250016#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 250427#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 250205#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 249963#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 249964#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 250428#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 250193#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 249896#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 249774#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 249775#L561-1 assume !(0 == ~M_E~0); 250559#L759-1 assume !(0 == ~T1_E~0); 250286#L764-1 assume !(0 == ~T2_E~0); 250055#L769-1 assume !(0 == ~T3_E~0); 249740#L774-1 assume !(0 == ~T4_E~0); 249741#L779-1 assume !(0 == ~T5_E~0); 250491#L784-1 assume !(0 == ~T6_E~0); 250263#L789-1 assume !(0 == ~T7_E~0); 249835#L794-1 assume !(0 == ~E_M~0); 249836#L799-1 assume !(0 == ~E_1~0); 250533#L804-1 assume !(0 == ~E_2~0); 250395#L809-1 assume !(0 == ~E_3~0); 250151#L814-1 assume !(0 == ~E_4~0); 249657#L819-1 assume !(0 == ~E_5~0); 249658#L824-1 assume !(0 == ~E_6~0); 250366#L829-1 assume !(0 == ~E_7~0); 250214#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 250215#L366 assume !(1 == ~m_pc~0); 250352#L366-2 is_master_triggered_~__retres1~0 := 0; 250476#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 249723#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 249724#L945 assume !(0 != activate_threads_~tmp~1); 250056#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 250057#L385 assume !(1 == ~t1_pc~0); 250448#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 250130#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 249875#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 249876#L953 assume !(0 != activate_threads_~tmp___0~0); 250609#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 250610#L404 assume !(1 == ~t2_pc~0); 250617#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 250262#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 250206#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 250207#L961 assume !(0 != activate_threads_~tmp___1~0); 250462#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 249817#L423 assume !(1 == ~t3_pc~0); 249818#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 249823#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 250379#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 250091#L969 assume !(0 != activate_threads_~tmp___2~0); 250092#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 249834#L442 assume !(1 == ~t4_pc~0); 249826#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 249827#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 250430#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 250485#L977 assume !(0 != activate_threads_~tmp___3~0); 250621#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 250035#L461 assume !(1 == ~t5_pc~0); 250036#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 250040#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 250550#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 250398#L985 assume !(0 != activate_threads_~tmp___4~0); 250399#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 250194#L480 assume !(1 == ~t6_pc~0); 250182#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 250183#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 250601#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 249993#L993 assume !(0 != activate_threads_~tmp___5~0); 249994#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 249996#L499 assume !(1 == ~t7_pc~0); 250345#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 249713#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 249714#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 250565#L1001 assume !(0 != activate_threads_~tmp___6~0); 250566#L1001-2 assume !(1 == ~M_E~0); 250562#L847-1 assume !(1 == ~T1_E~0); 250281#L852-1 assume !(1 == ~T2_E~0); 250052#L857-1 assume !(1 == ~T3_E~0); 249736#L862-1 assume !(1 == ~T4_E~0); 249737#L867-1 assume !(1 == ~T5_E~0); 250489#L872-1 assume !(1 == ~T6_E~0); 250166#L877-1 assume !(1 == ~T7_E~0); 249843#L882-1 assume !(1 == ~E_M~0); 249844#L887-1 assume !(1 == ~E_1~0); 250538#L892-1 assume !(1 == ~E_2~0); 250403#L897-1 assume !(1 == ~E_3~0); 250162#L902-1 assume !(1 == ~E_4~0); 249672#L907-1 assume !(1 == ~E_5~0); 249673#L912-1 assume !(1 == ~E_6~0); 250361#L917-1 assume !(1 == ~E_7~0); 250362#L1168-1 [2018-12-08 18:43:47,761 INFO L796 eck$LassoCheckResult]: Loop: 250362#L1168-1 assume !false; 259377#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 259371#L734 assume !false; 259369#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 259272#L574 assume !(0 == ~m_st~0); 249768#L578 assume !(0 == ~t1_st~0); 249769#L582 assume !(0 == ~t2_st~0); 250488#L586 assume !(0 == ~t3_st~0); 250190#L590 assume !(0 == ~t4_st~0); 250138#L594 assume !(0 == ~t5_st~0); 249730#L598 assume !(0 == ~t6_st~0); 249732#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 250629#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 259260#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 259255#L631 assume !(0 != eval_~tmp~0); 250085#L749 start_simulation_~kernel_st~0 := 2; 250086#L519-1 start_simulation_~kernel_st~0 := 3; 250429#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 250556#L759-4 assume !(0 == ~T1_E~0); 250269#L764-3 assume !(0 == ~T2_E~0); 250047#L769-3 assume !(0 == ~T3_E~0); 249725#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 249726#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 250487#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 250267#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 249839#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 249840#L799-3 assume !(0 == ~E_1~0); 250534#L804-3 assume !(0 == ~E_2~0); 250396#L809-3 assume !(0 == ~E_3~0); 250153#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 249659#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 249660#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 250368#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 250216#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 250217#L366-27 assume 1 == ~m_pc~0; 250312#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 250313#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 259898#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 259896#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 259894#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 259892#L385-27 assume !(1 == ~t1_pc~0); 259889#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 259887#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 259885#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 259883#L953-27 assume !(0 != activate_threads_~tmp___0~0); 259881#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 259879#L404-27 assume !(1 == ~t2_pc~0); 259876#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 259875#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 259874#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 259873#L961-27 assume !(0 != activate_threads_~tmp___1~0); 259872#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 259871#L423-27 assume !(1 == ~t3_pc~0); 259870#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 259868#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 259866#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 249849#L969-27 assume !(0 != activate_threads_~tmp___2~0); 249850#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 249853#L442-27 assume !(1 == ~t4_pc~0); 249959#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 249960#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 250493#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 250515#L977-27 assume !(0 != activate_threads_~tmp___3~0); 250505#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 250139#L461-27 assume !(1 == ~t5_pc~0); 250141#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 259846#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 259843#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 259841#L985-27 assume !(0 != activate_threads_~tmp___4~0); 259839#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 259837#L480-27 assume !(1 == ~t6_pc~0); 259836#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 250580#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 250581#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 250622#L993-27 assume !(0 != activate_threads_~tmp___5~0); 249899#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 249900#L499-27 assume !(1 == ~t7_pc~0); 250273#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 259832#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 259830#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 259828#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 259825#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 259823#L847-3 assume !(1 == ~T1_E~0); 259821#L852-3 assume !(1 == ~T2_E~0); 259819#L857-3 assume !(1 == ~T3_E~0); 259817#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 259812#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 259810#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 259806#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 259795#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 259793#L887-3 assume !(1 == ~E_1~0); 259791#L892-3 assume !(1 == ~E_2~0); 259789#L897-3 assume !(1 == ~E_3~0); 259787#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 259785#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 259783#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 259781#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 259779#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 259777#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 259775#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 259773#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 259770#L1187 assume !(0 == start_simulation_~tmp~3); 259767#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 259765#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 250143#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 249894#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 249895#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 259501#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 259497#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 259407#L1200 assume !(0 != start_simulation_~tmp___0~1); 250362#L1168-1 [2018-12-08 18:43:47,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:47,761 INFO L82 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 11 times [2018-12-08 18:43:47,761 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:47,761 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:47,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,762 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:47,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:47,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:47,787 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:47,787 INFO L82 PathProgramCache]: Analyzing trace with hash -50428779, now seen corresponding path program 1 times [2018-12-08 18:43:47,787 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:47,787 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:47,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,788 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:47,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:47,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:47,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:47,812 INFO L82 PathProgramCache]: Analyzing trace with hash -1171570763, now seen corresponding path program 1 times [2018-12-08 18:43:47,812 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:47,812 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:47,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:47,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:47,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:47,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:47,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:47,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:48,419 WARN L180 SmtUtils]: Spent 565.00 ms on a formula simplification. DAG size of input: 237 DAG size of output: 222 [2018-12-08 18:43:48,593 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification that was a NOOP. DAG size: 190 [2018-12-08 18:43:48,601 INFO L216 LassoAnalysis]: Preferences: [2018-12-08 18:43:48,602 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-12-08 18:43:48,602 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-12-08 18:43:48,602 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-12-08 18:43:48,602 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-12-08 18:43:48,602 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:48,602 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-12-08 18:43:48,602 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-12-08 18:43:48,603 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.07_true-unreach-call_false-termination.cil.c_Iteration28_Loop [2018-12-08 18:43:48,603 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-12-08 18:43:48,603 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-12-08 18:43:48,620 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,623 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,625 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,626 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,628 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,631 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,642 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,647 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,648 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,650 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,652 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,653 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,654 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,656 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,657 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,658 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,661 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,662 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,663 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,666 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,668 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,670 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,671 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,675 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,679 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,681 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,684 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,686 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,689 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,691 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,694 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,698 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,699 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,700 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,701 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,704 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,705 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,706 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,707 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,708 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,709 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,713 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,714 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,715 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,716 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,717 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,718 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,719 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,722 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,723 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,724 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,728 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,729 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,730 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,731 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,732 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,735 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,736 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,739 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,741 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,742 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,743 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,744 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,745 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,746 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,755 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,757 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,759 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,762 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,764 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,767 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,768 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,769 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,772 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,773 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,782 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:48,784 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,166 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-12-08 18:43:49,166 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,172 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,172 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,177 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,177 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret1=0} Honda state: {ULTIMATE.start_eval_#t~ret1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,193 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,193 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,196 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,196 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,212 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,212 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,215 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,215 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,243 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,243 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,245 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,245 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,261 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,261 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,263 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,263 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,288 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,288 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,291 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,291 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res=0, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res=0, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,307 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,307 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,310 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,310 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-5} Honda state: {~E_3~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,327 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,327 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,329 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,329 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret14=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret14=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,344 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,344 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,347 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,347 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret10=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret10=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,363 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,363 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,365 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,365 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,380 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,381 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,383 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,383 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=4} Honda state: {~t7_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,398 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,398 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,400 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,400 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_8~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_8~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,415 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,415 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,417 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,417 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=0} Honda state: {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,434 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,434 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,436 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,436 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet9=0} Honda state: {ULTIMATE.start_eval_#t~nondet9=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,451 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,451 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,453 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-12-08 18:43:49,453 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,468 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-12-08 18:43:49,468 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,485 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-12-08 18:43:49,485 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-12-08 18:43:49,488 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-12-08 18:43:49,501 INFO L216 LassoAnalysis]: Preferences: [2018-12-08 18:43:49,502 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-12-08 18:43:49,502 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-12-08 18:43:49,502 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-12-08 18:43:49,502 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-12-08 18:43:49,502 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-12-08 18:43:49,502 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-12-08 18:43:49,502 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-12-08 18:43:49,502 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.07_true-unreach-call_false-termination.cil.c_Iteration28_Loop [2018-12-08 18:43:49,502 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-12-08 18:43:49,502 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-12-08 18:43:49,506 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,507 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,510 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,511 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,512 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,514 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,516 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,518 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,520 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,521 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,523 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,524 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,524 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,526 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,527 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,527 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,530 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,532 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,533 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,534 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,535 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,538 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,539 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,540 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,544 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,547 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,550 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,554 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,556 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,559 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,561 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,564 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,565 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,566 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,568 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,570 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,570 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,573 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,574 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,575 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,576 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,577 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,580 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,581 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,582 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,586 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,587 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,588 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,590 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,591 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,594 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,602 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,603 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,604 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,606 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,610 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,614 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,615 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,618 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,619 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,621 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,622 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,623 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,625 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,626 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,627 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,628 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,630 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,632 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,634 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,637 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,639 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,640 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,642 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,645 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,646 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:49,648 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-12-08 18:43:50,071 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-12-08 18:43:50,074 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-12-08 18:43:50,075 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,076 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,076 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,077 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,077 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,077 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,078 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,078 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,079 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,080 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,080 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,080 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,080 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,080 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,080 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,081 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,081 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,082 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,083 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,083 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,083 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,083 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,083 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,083 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,084 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,084 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,084 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,084 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,085 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,085 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,085 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,085 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,085 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,085 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,085 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,086 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,086 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,086 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,086 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,087 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,087 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-12-08 18:43:50,087 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,087 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-12-08 18:43:50,087 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,087 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,088 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,088 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,088 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,088 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,088 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,088 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,089 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,089 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,089 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,089 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,090 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,090 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,090 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,090 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,090 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,090 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,090 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,091 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,091 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,092 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,092 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,092 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,092 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-12-08 18:43:50,092 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,092 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-12-08 18:43:50,092 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,093 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,093 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,093 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,094 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,094 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,094 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,094 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,094 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,094 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,094 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,095 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,095 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,095 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,095 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,095 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,095 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,095 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,095 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,096 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,096 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,096 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,096 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,097 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,097 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,097 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,097 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,097 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,097 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,098 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,098 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,098 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,098 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,098 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,098 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,098 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,098 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,099 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,099 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,099 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,099 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,100 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,100 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-12-08 18:43:50,100 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,100 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-12-08 18:43:50,100 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,101 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,101 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,101 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,101 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,101 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,101 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-12-08 18:43:50,101 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,102 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-12-08 18:43:50,102 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,102 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,102 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,102 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,102 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,103 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,103 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,103 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,103 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,103 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,103 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-12-08 18:43:50,103 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-12-08 18:43:50,104 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-12-08 18:43:50,104 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-12-08 18:43:50,104 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-12-08 18:43:50,104 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-12-08 18:43:50,104 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-12-08 18:43:50,104 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-12-08 18:43:50,104 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-12-08 18:43:50,105 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-12-08 18:43:50,111 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-12-08 18:43:50,111 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-12-08 18:43:50,112 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-12-08 18:43:50,112 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-12-08 18:43:50,112 INFO L518 LassoAnalysis]: Proved termination. [2018-12-08 18:43:50,113 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_5~0) = -1*~E_5~0 + 1 Supporting invariants [] [2018-12-08 18:43:50,113 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-12-08 18:43:50,133 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:50,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:50,163 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 18:43:50,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:50,207 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 18:43:50,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:50,300 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-12-08 18:43:50,300 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 10425 states and 13522 transitions. cyclomatic complexity: 3105 Second operand 5 states. [2018-12-08 18:43:50,548 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 10425 states and 13522 transitions. cyclomatic complexity: 3105. Second operand 5 states. Result 35635 states and 46401 transitions. Complement of second has 5 states. [2018-12-08 18:43:50,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-12-08 18:43:50,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-12-08 18:43:50,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 2025 transitions. [2018-12-08 18:43:50,552 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2025 transitions. Stem has 91 letters. Loop has 110 letters. [2018-12-08 18:43:50,556 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-12-08 18:43:50,556 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2025 transitions. Stem has 201 letters. Loop has 110 letters. [2018-12-08 18:43:50,557 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-12-08 18:43:50,557 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2025 transitions. Stem has 91 letters. Loop has 220 letters. [2018-12-08 18:43:50,559 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-12-08 18:43:50,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35635 states and 46401 transitions. [2018-12-08 18:43:50,664 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 25544 [2018-12-08 18:43:50,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35635 states to 35627 states and 46393 transitions. [2018-12-08 18:43:50,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25770 [2018-12-08 18:43:50,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25811 [2018-12-08 18:43:50,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35627 states and 46393 transitions. [2018-12-08 18:43:50,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:50,754 INFO L705 BuchiCegarLoop]: Abstraction has 35627 states and 46393 transitions. [2018-12-08 18:43:50,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35627 states and 46393 transitions. [2018-12-08 18:43:50,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35627 to 30002. [2018-12-08 18:43:50,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30002 states. [2018-12-08 18:43:51,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30002 states to 30002 states and 39028 transitions. [2018-12-08 18:43:51,022 INFO L728 BuchiCegarLoop]: Abstraction has 30002 states and 39028 transitions. [2018-12-08 18:43:51,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:51,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:51,022 INFO L87 Difference]: Start difference. First operand 30002 states and 39028 transitions. Second operand 3 states. [2018-12-08 18:43:51,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:51,138 INFO L93 Difference]: Finished difference Result 31418 states and 40684 transitions. [2018-12-08 18:43:51,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:51,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31418 states and 40684 transitions. [2018-12-08 18:43:51,231 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20944 [2018-12-08 18:43:51,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31418 states to 31418 states and 40684 transitions. [2018-12-08 18:43:51,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21146 [2018-12-08 18:43:51,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21146 [2018-12-08 18:43:51,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31418 states and 40684 transitions. [2018-12-08 18:43:51,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:51,303 INFO L705 BuchiCegarLoop]: Abstraction has 31418 states and 40684 transitions. [2018-12-08 18:43:51,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31418 states and 40684 transitions. [2018-12-08 18:43:51,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31418 to 30002. [2018-12-08 18:43:51,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30002 states. [2018-12-08 18:43:51,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30002 states to 30002 states and 38932 transitions. [2018-12-08 18:43:51,494 INFO L728 BuchiCegarLoop]: Abstraction has 30002 states and 38932 transitions. [2018-12-08 18:43:51,494 INFO L608 BuchiCegarLoop]: Abstraction has 30002 states and 38932 transitions. [2018-12-08 18:43:51,494 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-12-08 18:43:51,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30002 states and 38932 transitions. [2018-12-08 18:43:51,545 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20000 [2018-12-08 18:43:51,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:51,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:51,546 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:51,546 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:51,547 INFO L794 eck$LassoCheckResult]: Stem: 358596#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 358427#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 358428#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 359160#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 358780#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 358322#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 358323#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 359161#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 358758#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 358191#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 357978#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 357979#L561-1 assume !(0 == ~M_E~0); 359438#L759-1 assume !(0 == ~T1_E~0); 358904#L764-1 assume !(0 == ~T2_E~0); 358500#L769-1 assume !(0 == ~T3_E~0); 357918#L774-1 assume !(0 == ~T4_E~0); 357919#L779-1 assume !(0 == ~T5_E~0); 359286#L784-1 assume !(0 == ~T6_E~0); 358869#L789-1 assume !(0 == ~T7_E~0); 358079#L794-1 assume !(0 == ~E_M~0); 358080#L799-1 assume !(0 == ~E_1~0); 359373#L804-1 assume !(0 == ~E_2~0); 359111#L809-1 assume !(0 == ~E_3~0); 358676#L814-1 assume !(0 == ~E_4~0); 357766#L819-1 assume !(0 == ~E_5~0); 357767#L824-1 assume !(0 == ~E_6~0); 359054#L829-1 assume !(0 == ~E_7~0); 358794#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 358795#L366 assume !(1 == ~m_pc~0); 359030#L366-2 is_master_triggered_~__retres1~0 := 0; 358264#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 357888#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 357889#L945 assume !(0 != activate_threads_~tmp~1); 358501#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 358502#L385 assume !(1 == ~t1_pc~0); 359196#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 358638#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 358151#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 358152#L953 assume !(0 != activate_threads_~tmp___0~0); 359523#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 359524#L404 assume !(1 == ~t2_pc~0); 359533#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 358868#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 358781#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 358782#L961 assume !(0 != activate_threads_~tmp___1~0); 359227#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 358052#L423 assume !(1 == ~t3_pc~0); 358053#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 358058#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 359077#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 358566#L969 assume !(0 != activate_threads_~tmp___2~0); 358567#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 358078#L442 assume !(1 == ~t4_pc~0); 358061#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 358062#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 359164#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 359274#L977 assume !(0 != activate_threads_~tmp___3~0); 359548#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 358463#L461 assume !(1 == ~t5_pc~0); 358464#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 358468#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 359311#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 359117#L985 assume !(0 != activate_threads_~tmp___4~0); 359118#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 358759#L480 assume !(1 == ~t6_pc~0); 358738#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 358739#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 359505#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 358383#L993 assume !(0 != activate_threads_~tmp___5~0); 358384#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 358388#L499 assume !(1 == ~t7_pc~0); 359017#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 357871#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 357759#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 357760#L1001 assume !(0 != activate_threads_~tmp___6~0); 359449#L1001-2 assume !(1 == ~M_E~0); 359444#L847-1 assume !(1 == ~T1_E~0); 358895#L852-1 assume !(1 == ~T2_E~0); 358493#L857-1 assume !(1 == ~T3_E~0); 357912#L862-1 assume !(1 == ~T4_E~0); 357913#L867-1 assume !(1 == ~T5_E~0); 359282#L872-1 assume !(1 == ~T6_E~0); 358707#L877-1 assume !(1 == ~T7_E~0); 358093#L882-1 assume !(1 == ~E_M~0); 358094#L887-1 assume !(1 == ~E_1~0); 359384#L892-1 assume !(1 == ~E_2~0); 359125#L897-1 assume !(1 == ~E_3~0); 358699#L902-1 assume !(1 == ~E_4~0); 357795#L907-1 assume !(1 == ~E_5~0); 357796#L912-1 assume !(1 == ~E_6~0); 359044#L917-1 assume 1 == ~E_7~0;~E_7~0 := 2; 359045#L1168-1 [2018-12-08 18:43:51,547 INFO L796 eck$LassoCheckResult]: Loop: 359045#L1168-1 assume !false; 376818#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 373160#L734 assume !false; 373159#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 373158#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 373156#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 373154#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 373153#L631 assume 0 != eval_~tmp~0; 373139#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 373137#L639 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0; 373138#L70 assume 0 == ~m_pc~0; 377755#L95 assume !false; 377753#L82 ~token~0 := master_#t~nondet0;havoc master_#t~nondet0;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 377751#L366-3 assume 1 == ~m_pc~0; 377749#L367-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 377748#L377-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 377747#L378-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 377731#L945-3 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 377729#L945-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 377727#L385-3 assume !(1 == ~t1_pc~0); 377724#L385-5 is_transmit1_triggered_~__retres1~1 := 0; 377759#L396-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 377758#L397-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 377715#L953-3 assume !(0 != activate_threads_~tmp___0~0); 377713#L953-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 377710#L404-3 assume !(1 == ~t2_pc~0); 377707#L404-5 is_transmit2_triggered_~__retres1~2 := 0; 377705#L415-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 377703#L416-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 377701#L961-3 assume !(0 != activate_threads_~tmp___1~0); 377699#L961-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 377696#L423-3 assume !(1 == ~t3_pc~0); 377694#L423-5 is_transmit3_triggered_~__retres1~3 := 0; 377692#L434-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 377690#L435-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 377688#L969-3 assume !(0 != activate_threads_~tmp___2~0); 377686#L969-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 377684#L442-3 assume !(1 == ~t4_pc~0); 377682#L442-5 is_transmit4_triggered_~__retres1~4 := 0; 377680#L453-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 377678#L454-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 377676#L977-3 assume !(0 != activate_threads_~tmp___3~0); 377674#L977-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 377671#L461-3 assume !(1 == ~t5_pc~0); 377667#L461-5 is_transmit5_triggered_~__retres1~5 := 0; 377665#L472-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 377663#L473-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 377661#L985-3 assume !(0 != activate_threads_~tmp___4~0); 377657#L985-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 377655#L480-3 assume !(1 == ~t6_pc~0); 377653#L480-5 is_transmit6_triggered_~__retres1~6 := 0; 377651#L491-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 377649#L492-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 377647#L993-3 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 377645#L993-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 377643#L499-3 assume !(1 == ~t7_pc~0); 377637#L499-5 is_transmit7_triggered_~__retres1~7 := 0; 377635#L510-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 377633#L511-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 377623#L1001-3 assume !(0 != activate_threads_~tmp___6~0); 371797#L1001-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 371791#L636 assume !(0 == ~t1_st~0); 371789#L650 assume !(0 == ~t2_st~0); 371786#L664 assume !(0 == ~t3_st~0); 371785#L678 assume !(0 == ~t4_st~0); 376177#L692 assume !(0 == ~t5_st~0); 377068#L706 assume !(0 == ~t6_st~0); 377063#L720 assume !(0 == ~t7_st~0); 377059#L734 assume !false; 377058#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 377055#L574 assume !(0 == ~m_st~0); 377053#L578 assume !(0 == ~t1_st~0); 377051#L582 assume !(0 == ~t2_st~0); 377049#L586 assume !(0 == ~t3_st~0); 377047#L590 assume !(0 == ~t4_st~0); 377045#L594 assume !(0 == ~t5_st~0); 377042#L598 assume !(0 == ~t6_st~0); 377039#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 377037#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 377035#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 377033#L631 assume !(0 != eval_~tmp~0); 377031#L749 start_simulation_~kernel_st~0 := 2; 377029#L519-1 start_simulation_~kernel_st~0 := 3; 377027#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 377025#L759-4 assume !(0 == ~T1_E~0); 377023#L764-3 assume !(0 == ~T2_E~0); 377021#L769-3 assume !(0 == ~T3_E~0); 377019#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 377017#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 377015#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 377013#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 377011#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 377009#L799-3 assume !(0 == ~E_1~0); 377007#L804-3 assume !(0 == ~E_2~0); 377003#L809-3 assume !(0 == ~E_3~0); 377001#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 376999#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 376997#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 376994#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 376992#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 376990#L366-27 assume 1 == ~m_pc~0; 376987#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 376985#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 376983#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 376980#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 376978#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 376974#L385-27 assume !(1 == ~t1_pc~0); 376971#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 376969#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 376967#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 376964#L953-27 assume !(0 != activate_threads_~tmp___0~0); 376962#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 376960#L404-27 assume !(1 == ~t2_pc~0); 376957#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 376955#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 376953#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 376951#L961-27 assume !(0 != activate_threads_~tmp___1~0); 376949#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 376947#L423-27 assume !(1 == ~t3_pc~0); 376945#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 376943#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 376941#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 376939#L969-27 assume !(0 != activate_threads_~tmp___2~0); 376937#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 376935#L442-27 assume !(1 == ~t4_pc~0); 376933#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 376932#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 376931#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 376930#L977-27 assume !(0 != activate_threads_~tmp___3~0); 376928#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 376927#L461-27 assume 1 == ~t5_pc~0; 376925#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 376923#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 376922#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 376915#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 376913#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 376911#L480-27 assume !(1 == ~t6_pc~0); 376909#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 376907#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 376905#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 376903#L993-27 assume !(0 != activate_threads_~tmp___5~0); 376901#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 376899#L499-27 assume 1 == ~t7_pc~0; 376897#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 376898#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 376924#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 376888#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 376886#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 376884#L847-3 assume !(1 == ~T1_E~0); 376882#L852-3 assume !(1 == ~T2_E~0); 376880#L857-3 assume !(1 == ~T3_E~0); 376878#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 376877#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 376873#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 376871#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 376869#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 376867#L887-3 assume !(1 == ~E_1~0); 376864#L892-3 assume !(1 == ~E_2~0); 376862#L897-3 assume !(1 == ~E_3~0); 376860#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 376858#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 376856#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 376854#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 376852#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 376850#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 376846#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 376844#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 376841#L1187 assume !(0 == start_simulation_~tmp~3); 376838#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 376835#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 376834#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 376830#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 376828#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 376827#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 376826#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 376822#L1200 assume !(0 != start_simulation_~tmp___0~1); 359045#L1168-1 [2018-12-08 18:43:51,547 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:51,548 INFO L82 PathProgramCache]: Analyzing trace with hash 322056991, now seen corresponding path program 1 times [2018-12-08 18:43:51,548 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:51,548 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:51,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:51,548 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:51,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:51,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:51,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:51,587 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:51,587 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2018-12-08 18:43:51,587 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:51,588 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:51,588 INFO L82 PathProgramCache]: Analyzing trace with hash -2070138028, now seen corresponding path program 1 times [2018-12-08 18:43:51,588 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:51,588 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:51,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:51,588 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:51,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:51,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:51,622 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:51,622 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:51,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:51,623 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:51,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:51,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:51,623 INFO L87 Difference]: Start difference. First operand 30002 states and 38932 transitions. cyclomatic complexity: 8954 Second operand 3 states. [2018-12-08 18:43:51,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:51,703 INFO L93 Difference]: Finished difference Result 24375 states and 31269 transitions. [2018-12-08 18:43:51,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:51,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24375 states and 31269 transitions. [2018-12-08 18:43:51,752 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14744 [2018-12-08 18:43:51,788 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24375 states to 24375 states and 31269 transitions. [2018-12-08 18:43:51,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14911 [2018-12-08 18:43:51,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14911 [2018-12-08 18:43:51,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24375 states and 31269 transitions. [2018-12-08 18:43:51,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:51,799 INFO L705 BuchiCegarLoop]: Abstraction has 24375 states and 31269 transitions. [2018-12-08 18:43:51,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24375 states and 31269 transitions. [2018-12-08 18:43:52,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24375 to 24375. [2018-12-08 18:43:52,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24375 states. [2018-12-08 18:43:52,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24375 states to 24375 states and 31269 transitions. [2018-12-08 18:43:52,036 INFO L728 BuchiCegarLoop]: Abstraction has 24375 states and 31269 transitions. [2018-12-08 18:43:52,036 INFO L608 BuchiCegarLoop]: Abstraction has 24375 states and 31269 transitions. [2018-12-08 18:43:52,036 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-12-08 18:43:52,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24375 states and 31269 transitions. [2018-12-08 18:43:52,071 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14744 [2018-12-08 18:43:52,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:52,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:52,072 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:52,073 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:52,073 INFO L794 eck$LassoCheckResult]: Stem: 412966#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 412802#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 412803#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 413492#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 413147#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 412707#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 412708#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 413493#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 413125#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 412582#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 412362#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 412363#L561-1 assume !(0 == ~M_E~0); 413746#L759-1 assume !(0 == ~T1_E~0); 413269#L764-1 assume !(0 == ~T2_E~0); 412870#L769-1 assume !(0 == ~T3_E~0); 412302#L774-1 assume !(0 == ~T4_E~0); 412303#L779-1 assume !(0 == ~T5_E~0); 413604#L784-1 assume !(0 == ~T6_E~0); 413229#L789-1 assume !(0 == ~T7_E~0); 412470#L794-1 assume !(0 == ~E_M~0); 412471#L799-1 assume !(0 == ~E_1~0); 413693#L804-1 assume !(0 == ~E_2~0); 413463#L809-1 assume !(0 == ~E_3~0); 413041#L814-1 assume !(0 == ~E_4~0); 412150#L819-1 assume !(0 == ~E_5~0); 412151#L824-1 assume !(0 == ~E_6~0); 413413#L829-1 assume !(0 == ~E_7~0); 413162#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 413163#L366 assume !(1 == ~m_pc~0); 413385#L366-2 is_master_triggered_~__retres1~0 := 0; 412652#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 412272#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 412273#L945 assume !(0 != activate_threads_~tmp~1); 412871#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 412872#L385 assume !(1 == ~t1_pc~0); 413527#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 413006#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 412542#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 412543#L953 assume !(0 != activate_threads_~tmp___0~0); 413831#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 413832#L404 assume !(1 == ~t2_pc~0); 413842#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 413228#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 413148#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 413149#L961 assume !(0 != activate_threads_~tmp___1~0); 413553#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 412439#L423 assume !(1 == ~t3_pc~0); 412440#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 412445#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 413434#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 412937#L969 assume !(0 != activate_threads_~tmp___2~0); 412938#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 412469#L442 assume !(1 == ~t4_pc~0); 412447#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 412448#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 413496#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 413592#L977 assume !(0 != activate_threads_~tmp___3~0); 413860#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 412839#L461 assume !(1 == ~t5_pc~0); 412840#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 412844#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 413628#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 413468#L985 assume !(0 != activate_threads_~tmp___4~0); 413469#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 413126#L480 assume !(1 == ~t6_pc~0); 413104#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 413105#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 413820#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 412761#L993 assume !(0 != activate_threads_~tmp___5~0); 412762#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 412765#L499 assume !(1 == ~t7_pc~0); 413375#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 412255#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 412143#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 412144#L1001 assume !(0 != activate_threads_~tmp___6~0); 413755#L1001-2 assume !(1 == ~M_E~0); 413749#L847-1 assume !(1 == ~T1_E~0); 413260#L852-1 assume !(1 == ~T2_E~0); 412865#L857-1 assume !(1 == ~T3_E~0); 412296#L862-1 assume !(1 == ~T4_E~0); 412297#L867-1 assume !(1 == ~T5_E~0); 413601#L872-1 assume !(1 == ~T6_E~0); 413071#L877-1 assume !(1 == ~T7_E~0); 412484#L882-1 assume !(1 == ~E_M~0); 412485#L887-1 assume !(1 == ~E_1~0); 413701#L892-1 assume !(1 == ~E_2~0); 413476#L897-1 assume !(1 == ~E_3~0); 413063#L902-1 assume !(1 == ~E_4~0); 412179#L907-1 assume !(1 == ~E_5~0); 412180#L912-1 assume !(1 == ~E_6~0); 413401#L917-1 assume !(1 == ~E_7~0); 413402#L1168-1 assume !false; 421632#L1169 [2018-12-08 18:43:52,073 INFO L796 eck$LassoCheckResult]: Loop: 421632#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 424524#L734 assume !false; 424523#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 424522#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 424521#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 424520#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 424519#L631 assume 0 != eval_~tmp~0; 424518#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 424516#L639 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0; 424512#L70 assume 0 == ~m_pc~0; 424510#L95 assume !false; 424508#L82 ~token~0 := master_#t~nondet0;havoc master_#t~nondet0;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 424507#L366-3 assume 1 == ~m_pc~0; 424503#L367-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 424500#L377-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 424496#L378-1 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 424492#L945-3 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 424488#L945-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 424485#L385-3 assume !(1 == ~t1_pc~0); 424480#L385-5 is_transmit1_triggered_~__retres1~1 := 0; 424476#L396-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 424471#L397-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 424466#L953-3 assume !(0 != activate_threads_~tmp___0~0); 424461#L953-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 424456#L404-3 assume !(1 == ~t2_pc~0); 424449#L404-5 is_transmit2_triggered_~__retres1~2 := 0; 424442#L415-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 424434#L416-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 424427#L961-3 assume !(0 != activate_threads_~tmp___1~0); 424420#L961-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 424414#L423-3 assume !(1 == ~t3_pc~0); 424408#L423-5 is_transmit3_triggered_~__retres1~3 := 0; 424401#L434-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 424393#L435-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 424385#L969-3 assume !(0 != activate_threads_~tmp___2~0); 424378#L969-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 424372#L442-3 assume !(1 == ~t4_pc~0); 424366#L442-5 is_transmit4_triggered_~__retres1~4 := 0; 424359#L453-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 424352#L454-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 424345#L977-3 assume !(0 != activate_threads_~tmp___3~0); 424338#L977-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 424331#L461-3 assume !(1 == ~t5_pc~0); 424324#L461-5 is_transmit5_triggered_~__retres1~5 := 0; 424316#L472-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 424308#L473-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 424300#L985-3 assume !(0 != activate_threads_~tmp___4~0); 424291#L985-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 424282#L480-3 assume !(1 == ~t6_pc~0); 424272#L480-5 is_transmit6_triggered_~__retres1~6 := 0; 424264#L491-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 424257#L492-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 424250#L993-3 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 424241#L993-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 424233#L499-3 assume !(1 == ~t7_pc~0); 424224#L499-5 is_transmit7_triggered_~__retres1~7 := 0; 424216#L510-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 424209#L511-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 424200#L1001-3 assume !(0 != activate_threads_~tmp___6~0); 424192#L1001-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 424164#L636 assume !(0 == ~t1_st~0); 424161#L650 assume !(0 == ~t2_st~0); 424145#L664 assume !(0 == ~t3_st~0); 424138#L678 assume !(0 == ~t4_st~0); 424132#L692 assume !(0 == ~t5_st~0); 424993#L706 assume !(0 == ~t6_st~0); 425124#L720 assume !(0 == ~t7_st~0); 425119#L734 assume !false; 425117#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 425115#L574 assume !(0 == ~m_st~0); 425113#L578 assume !(0 == ~t1_st~0); 425111#L582 assume !(0 == ~t2_st~0); 425109#L586 assume !(0 == ~t3_st~0); 425107#L590 assume !(0 == ~t4_st~0); 425105#L594 assume !(0 == ~t5_st~0); 425103#L598 assume !(0 == ~t6_st~0); 425100#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 425098#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 425096#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 425094#L631 assume !(0 != eval_~tmp~0); 425091#L749 start_simulation_~kernel_st~0 := 2; 425088#L519-1 start_simulation_~kernel_st~0 := 3; 425085#L759-2 assume 0 == ~M_E~0;~M_E~0 := 1; 425082#L759-4 assume !(0 == ~T1_E~0); 425080#L764-3 assume !(0 == ~T2_E~0); 425078#L769-3 assume !(0 == ~T3_E~0); 425076#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 425074#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 425072#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 425070#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 425068#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 425065#L799-3 assume !(0 == ~E_1~0); 425063#L804-3 assume !(0 == ~E_2~0); 425061#L809-3 assume !(0 == ~E_3~0); 425059#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 425057#L819-3 assume !(0 == ~E_5~0); 425055#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 425053#L829-3 assume !(0 == ~E_7~0); 425051#L834-3 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 425049#L366-27 assume 1 == ~m_pc~0; 425046#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 425044#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 425042#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 425039#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 425037#L945-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 425035#L385-27 assume !(1 == ~t1_pc~0); 425032#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 425030#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 425028#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 425026#L953-27 assume !(0 != activate_threads_~tmp___0~0); 425023#L953-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 425019#L404-27 assume !(1 == ~t2_pc~0); 425016#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 425013#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 425005#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 425003#L961-27 assume !(0 != activate_threads_~tmp___1~0); 425001#L961-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 424998#L423-27 assume !(1 == ~t3_pc~0); 424996#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 424995#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 424994#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 424991#L969-27 assume !(0 != activate_threads_~tmp___2~0); 424989#L969-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 424986#L442-27 assume !(1 == ~t4_pc~0); 424981#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 424974#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 424968#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 424963#L977-27 assume !(0 != activate_threads_~tmp___3~0); 424956#L977-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 424952#L461-27 assume 1 == ~t5_pc~0; 424944#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 424935#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 424926#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 424909#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 424905#L985-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 424903#L480-27 assume !(1 == ~t6_pc~0); 424902#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 424901#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 424899#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 424896#L993-27 assume !(0 != activate_threads_~tmp___5~0); 424894#L993-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 424891#L499-27 assume !(1 == ~t7_pc~0); 424888#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 424886#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 424884#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 424871#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 424863#L1001-29 assume 1 == ~M_E~0;~M_E~0 := 2; 424855#L847-3 assume !(1 == ~T1_E~0); 424847#L852-3 assume !(1 == ~T2_E~0); 424840#L857-3 assume !(1 == ~T3_E~0); 424833#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 424825#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 424819#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 424812#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 424805#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 424799#L887-3 assume !(1 == ~E_1~0); 424793#L892-3 assume !(1 == ~E_2~0); 424787#L897-3 assume !(1 == ~E_3~0); 424781#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 424699#L907-3 assume !(1 == ~E_5~0); 424643#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 424635#L917-3 assume !(1 == ~E_7~0); 424627#L922-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 424620#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 424612#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 424604#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 424596#L1187 assume !(0 == start_simulation_~tmp~3); 424590#L1187-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 424584#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 424577#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 424569#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 424562#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 424555#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 424547#L1150 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 424541#L1200 assume !(0 != start_simulation_~tmp___0~1); 424533#L1168-1 assume !false; 421632#L1169 [2018-12-08 18:43:52,074 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:52,074 INFO L82 PathProgramCache]: Analyzing trace with hash 1393832633, now seen corresponding path program 1 times [2018-12-08 18:43:52,074 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:52,074 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:52,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:52,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:52,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:52,098 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:52,098 INFO L82 PathProgramCache]: Analyzing trace with hash -1124585575, now seen corresponding path program 1 times [2018-12-08 18:43:52,099 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:52,099 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:52,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,099 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:52,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:52,128 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:52,128 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:52,128 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:52,129 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-12-08 18:43:52,129 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:52,129 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:52,129 INFO L87 Difference]: Start difference. First operand 24375 states and 31269 transitions. cyclomatic complexity: 6914 Second operand 3 states. [2018-12-08 18:43:52,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:52,230 INFO L93 Difference]: Finished difference Result 32911 states and 41753 transitions. [2018-12-08 18:43:52,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:52,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32911 states and 41753 transitions. [2018-12-08 18:43:52,294 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19946 [2018-12-08 18:43:52,341 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32911 states to 32911 states and 41753 transitions. [2018-12-08 18:43:52,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20154 [2018-12-08 18:43:52,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20154 [2018-12-08 18:43:52,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32911 states and 41753 transitions. [2018-12-08 18:43:52,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:52,353 INFO L705 BuchiCegarLoop]: Abstraction has 32911 states and 41753 transitions. [2018-12-08 18:43:52,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32911 states and 41753 transitions. [2018-12-08 18:43:52,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32911 to 31703. [2018-12-08 18:43:52,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31703 states. [2018-12-08 18:43:52,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31703 states to 31703 states and 40299 transitions. [2018-12-08 18:43:52,536 INFO L728 BuchiCegarLoop]: Abstraction has 31703 states and 40299 transitions. [2018-12-08 18:43:52,536 INFO L608 BuchiCegarLoop]: Abstraction has 31703 states and 40299 transitions. [2018-12-08 18:43:52,536 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-12-08 18:43:52,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31703 states and 40299 transitions. [2018-12-08 18:43:52,584 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19218 [2018-12-08 18:43:52,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:52,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:52,585 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:52,585 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:52,585 INFO L794 eck$LassoCheckResult]: Stem: 470256#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 470092#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 470093#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 470794#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 470440#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 469993#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 469994#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 470795#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 470416#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 469869#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 469656#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 469657#L561-1 assume !(0 == ~M_E~0); 471055#L759-1 assume !(0 == ~T1_E~0); 470565#L764-1 assume !(0 == ~T2_E~0); 470161#L769-1 assume !(0 == ~T3_E~0); 469592#L774-1 assume !(0 == ~T4_E~0); 469593#L779-1 assume !(0 == ~T5_E~0); 470914#L784-1 assume !(0 == ~T6_E~0); 470531#L789-1 assume !(0 == ~T7_E~0); 469757#L794-1 assume !(0 == ~E_M~0); 469758#L799-1 assume !(0 == ~E_1~0); 471006#L804-1 assume !(0 == ~E_2~0); 470763#L809-1 assume !(0 == ~E_3~0); 470333#L814-1 assume !(0 == ~E_4~0); 469442#L819-1 assume !(0 == ~E_5~0); 469443#L824-1 assume !(0 == ~E_6~0); 470708#L829-1 assume !(0 == ~E_7~0); 470454#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 470455#L366 assume !(1 == ~m_pc~0); 470883#L366-2 is_master_triggered_~__retres1~0 := 0; 469939#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 469562#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 469563#L945 assume !(0 != activate_threads_~tmp~1); 470162#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 470163#L385 assume !(1 == ~t1_pc~0); 470828#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 470296#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 469829#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 469830#L953 assume !(0 != activate_threads_~tmp___0~0); 471136#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 471137#L404 assume !(1 == ~t2_pc~0); 471150#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 470530#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 470441#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 470442#L961 assume !(0 != activate_threads_~tmp___1~0); 470859#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 469729#L423 assume !(1 == ~t3_pc~0); 469730#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 469735#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 470730#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 470229#L969 assume !(0 != activate_threads_~tmp___2~0); 470230#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 469756#L442 assume !(1 == ~t4_pc~0); 469737#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 469738#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 470798#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 470902#L977 assume !(0 != activate_threads_~tmp___3~0); 471160#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 470129#L461 assume !(1 == ~t5_pc~0); 470130#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 470133#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 471037#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 470768#L985 assume !(0 != activate_threads_~tmp___4~0); 470769#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 470417#L480 assume !(1 == ~t6_pc~0); 470395#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 470396#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 471123#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 470046#L993 assume !(0 != activate_threads_~tmp___5~0); 470047#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 470052#L499 assume !(1 == ~t7_pc~0); 470677#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 469545#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 469435#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 469436#L1001 assume !(0 != activate_threads_~tmp___6~0); 471062#L1001-2 assume !(1 == ~M_E~0); 471059#L847-1 assume !(1 == ~T1_E~0); 470558#L852-1 assume !(1 == ~T2_E~0); 470156#L857-1 assume !(1 == ~T3_E~0); 469586#L862-1 assume !(1 == ~T4_E~0); 469587#L867-1 assume !(1 == ~T5_E~0); 470909#L872-1 assume !(1 == ~T6_E~0); 470364#L877-1 assume !(1 == ~T7_E~0); 469771#L882-1 assume !(1 == ~E_M~0); 469772#L887-1 assume !(1 == ~E_1~0); 471014#L892-1 assume !(1 == ~E_2~0); 470776#L897-1 assume !(1 == ~E_3~0); 470356#L902-1 assume !(1 == ~E_4~0); 469469#L907-1 assume !(1 == ~E_5~0); 469470#L912-1 assume !(1 == ~E_6~0); 470698#L917-1 assume !(1 == ~E_7~0); 470699#L1168-1 assume !false; 477318#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 487788#L734 [2018-12-08 18:43:52,585 INFO L796 eck$LassoCheckResult]: Loop: 487788#L734 assume !false; 487759#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 487750#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 487744#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 487738#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 487731#L631 assume 0 != eval_~tmp~0; 487724#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 487716#L639 assume !(0 != eval_~tmp_ndt_1~0); 487337#L636 assume !(0 == ~t1_st~0); 487333#L650 assume !(0 == ~t2_st~0); 487324#L664 assume !(0 == ~t3_st~0); 487318#L678 assume !(0 == ~t4_st~0); 487675#L692 assume !(0 == ~t5_st~0); 487667#L706 assume !(0 == ~t6_st~0); 487659#L720 assume !(0 == ~t7_st~0); 487788#L734 [2018-12-08 18:43:52,585 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:52,585 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 1 times [2018-12-08 18:43:52,586 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:52,586 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:52,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,586 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:52,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:52,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:52,609 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:52,609 INFO L82 PathProgramCache]: Analyzing trace with hash 1325025558, now seen corresponding path program 1 times [2018-12-08 18:43:52,609 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:52,609 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:52,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:52,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:52,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:52,614 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:52,615 INFO L82 PathProgramCache]: Analyzing trace with hash -912860492, now seen corresponding path program 1 times [2018-12-08 18:43:52,615 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:52,615 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:52,615 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,616 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:52,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:52,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:52,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:52,644 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:52,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:52,721 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:52,721 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:52,721 INFO L87 Difference]: Start difference. First operand 31703 states and 40299 transitions. cyclomatic complexity: 8636 Second operand 3 states. [2018-12-08 18:43:52,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:52,847 INFO L93 Difference]: Finished difference Result 55097 states and 69610 transitions. [2018-12-08 18:43:52,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:52,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55097 states and 69610 transitions. [2018-12-08 18:43:52,959 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 33452 [2018-12-08 18:43:53,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55097 states to 55097 states and 69610 transitions. [2018-12-08 18:43:53,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33863 [2018-12-08 18:43:53,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33863 [2018-12-08 18:43:53,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55097 states and 69610 transitions. [2018-12-08 18:43:53,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:53,053 INFO L705 BuchiCegarLoop]: Abstraction has 55097 states and 69610 transitions. [2018-12-08 18:43:53,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55097 states and 69610 transitions. [2018-12-08 18:43:53,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55097 to 55097. [2018-12-08 18:43:53,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55097 states. [2018-12-08 18:43:53,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55097 states to 55097 states and 69610 transitions. [2018-12-08 18:43:53,346 INFO L728 BuchiCegarLoop]: Abstraction has 55097 states and 69610 transitions. [2018-12-08 18:43:53,346 INFO L608 BuchiCegarLoop]: Abstraction has 55097 states and 69610 transitions. [2018-12-08 18:43:53,346 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-12-08 18:43:53,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55097 states and 69610 transitions. [2018-12-08 18:43:53,433 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 33452 [2018-12-08 18:43:53,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:53,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:53,433 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:53,433 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:53,434 INFO L794 eck$LassoCheckResult]: Stem: 557067#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 556899#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 556900#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 557610#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 557251#L526-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 556803#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 556804#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 557611#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 557224#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 556679#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 556464#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 556465#L561-1 assume !(0 == ~M_E~0); 557890#L759-1 assume !(0 == ~T1_E~0); 557381#L764-1 assume !(0 == ~T2_E~0); 556970#L769-1 assume !(0 == ~T3_E~0); 556400#L774-1 assume !(0 == ~T4_E~0); 556401#L779-1 assume !(0 == ~T5_E~0); 557732#L784-1 assume !(0 == ~T6_E~0); 557346#L789-1 assume !(0 == ~T7_E~0); 556566#L794-1 assume !(0 == ~E_M~0); 556567#L799-1 assume !(0 == ~E_1~0); 557830#L804-1 assume !(0 == ~E_2~0); 557580#L809-1 assume !(0 == ~E_3~0); 557142#L814-1 assume !(0 == ~E_4~0); 556250#L819-1 assume !(0 == ~E_5~0); 556251#L824-1 assume !(0 == ~E_6~0); 557526#L829-1 assume !(0 == ~E_7~0); 557264#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 557265#L366 assume !(1 == ~m_pc~0); 557704#L366-2 is_master_triggered_~__retres1~0 := 0; 556748#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 556370#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 556371#L945 assume !(0 != activate_threads_~tmp~1); 556971#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 556972#L385 assume !(1 == ~t1_pc~0); 557647#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 557106#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 556639#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 556640#L953 assume !(0 != activate_threads_~tmp___0~0); 557977#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 557978#L404 assume !(1 == ~t2_pc~0); 557987#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 557345#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 557253#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 557254#L961 assume !(0 != activate_threads_~tmp___1~0); 557681#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 556538#L423 assume !(1 == ~t3_pc~0); 556539#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 556544#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 557550#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 557037#L969 assume !(0 != activate_threads_~tmp___2~0); 557038#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 556565#L442 assume !(1 == ~t4_pc~0); 556546#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 556547#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 557614#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 557722#L977 assume !(0 != activate_threads_~tmp___3~0); 557997#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 556936#L461 assume !(1 == ~t5_pc~0); 556937#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 556940#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 557868#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 557585#L985 assume !(0 != activate_threads_~tmp___4~0); 557586#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 557225#L480 assume !(1 == ~t6_pc~0); 557204#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 557205#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 557963#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 556858#L993 assume !(0 != activate_threads_~tmp___5~0); 556859#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 556862#L499 assume !(1 == ~t7_pc~0); 557487#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 556353#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 556243#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 556244#L1001 assume !(0 != activate_threads_~tmp___6~0); 557899#L1001-2 assume !(1 == ~M_E~0); 557895#L847-1 assume !(1 == ~T1_E~0); 557374#L852-1 assume !(1 == ~T2_E~0); 556965#L857-1 assume !(1 == ~T3_E~0); 556394#L862-1 assume !(1 == ~T4_E~0); 556395#L867-1 assume !(1 == ~T5_E~0); 557729#L872-1 assume !(1 == ~T6_E~0); 557174#L877-1 assume !(1 == ~T7_E~0); 556580#L882-1 assume !(1 == ~E_M~0); 556581#L887-1 assume !(1 == ~E_1~0); 557843#L892-1 assume !(1 == ~E_2~0); 557593#L897-1 assume !(1 == ~E_3~0); 557165#L902-1 assume !(1 == ~E_4~0); 556277#L907-1 assume !(1 == ~E_5~0); 556278#L912-1 assume !(1 == ~E_6~0); 557518#L917-1 assume !(1 == ~E_7~0); 557519#L1168-1 assume !false; 567504#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 609627#L734 [2018-12-08 18:43:53,434 INFO L796 eck$LassoCheckResult]: Loop: 609627#L734 assume !false; 609625#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 609623#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 609622#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 606002#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 591745#L631 assume 0 != eval_~tmp~0; 591742#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 591739#L639 assume !(0 != eval_~tmp_ndt_1~0); 591740#L636 assume !(0 == ~t1_st~0); 593471#L650 assume !(0 == ~t2_st~0); 593468#L664 assume !(0 == ~t3_st~0); 593464#L678 assume !(0 == ~t4_st~0); 600935#L692 assume !(0 == ~t5_st~0); 600928#L706 assume !(0 == ~t6_st~0); 600912#L720 assume !(0 == ~t7_st~0); 609627#L734 [2018-12-08 18:43:53,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:53,434 INFO L82 PathProgramCache]: Analyzing trace with hash -511594459, now seen corresponding path program 1 times [2018-12-08 18:43:53,434 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:53,434 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:53,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:53,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:53,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:53,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:53,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:53,463 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:53,463 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:53,463 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-12-08 18:43:53,463 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:53,463 INFO L82 PathProgramCache]: Analyzing trace with hash 1325025558, now seen corresponding path program 2 times [2018-12-08 18:43:53,463 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:53,463 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:53,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:53,464 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:53,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:53,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:53,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:53,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:53,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:53,514 INFO L87 Difference]: Start difference. First operand 55097 states and 69610 transitions. cyclomatic complexity: 14553 Second operand 3 states. [2018-12-08 18:43:53,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:53,625 INFO L93 Difference]: Finished difference Result 55001 states and 69487 transitions. [2018-12-08 18:43:53,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:53,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55001 states and 69487 transitions. [2018-12-08 18:43:53,856 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 33452 [2018-12-08 18:43:53,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55001 states to 55001 states and 69487 transitions. [2018-12-08 18:43:53,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33768 [2018-12-08 18:43:53,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33768 [2018-12-08 18:43:53,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55001 states and 69487 transitions. [2018-12-08 18:43:53,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:53,930 INFO L705 BuchiCegarLoop]: Abstraction has 55001 states and 69487 transitions. [2018-12-08 18:43:53,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55001 states and 69487 transitions. [2018-12-08 18:43:54,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55001 to 55001. [2018-12-08 18:43:54,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55001 states. [2018-12-08 18:43:54,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55001 states to 55001 states and 69487 transitions. [2018-12-08 18:43:54,233 INFO L728 BuchiCegarLoop]: Abstraction has 55001 states and 69487 transitions. [2018-12-08 18:43:54,233 INFO L608 BuchiCegarLoop]: Abstraction has 55001 states and 69487 transitions. [2018-12-08 18:43:54,233 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2018-12-08 18:43:54,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55001 states and 69487 transitions. [2018-12-08 18:43:54,320 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 33452 [2018-12-08 18:43:54,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:54,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:54,320 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:54,320 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:54,321 INFO L794 eck$LassoCheckResult]: Stem: 667167#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 666999#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 667000#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 667710#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 667351#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 666906#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 666907#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 667711#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 667328#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 666784#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 666569#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 666570#L561-1 assume !(0 == ~M_E~0); 667988#L759-1 assume !(0 == ~T1_E~0); 667474#L764-1 assume !(0 == ~T2_E~0); 667071#L769-1 assume !(0 == ~T3_E~0); 666504#L774-1 assume !(0 == ~T4_E~0); 666505#L779-1 assume !(0 == ~T5_E~0); 667836#L784-1 assume !(0 == ~T6_E~0); 667435#L789-1 assume !(0 == ~T7_E~0); 666670#L794-1 assume !(0 == ~E_M~0); 666671#L799-1 assume !(0 == ~E_1~0); 667932#L804-1 assume !(0 == ~E_2~0); 667674#L809-1 assume !(0 == ~E_3~0); 667242#L814-1 assume !(0 == ~E_4~0); 666354#L819-1 assume !(0 == ~E_5~0); 666355#L824-1 assume !(0 == ~E_6~0); 667615#L829-1 assume !(0 == ~E_7~0); 667363#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 667364#L366 assume !(1 == ~m_pc~0); 667800#L366-2 is_master_triggered_~__retres1~0 := 0; 666854#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 666474#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 666475#L945 assume !(0 != activate_threads_~tmp~1); 667072#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 667073#L385 assume !(1 == ~t1_pc~0); 667744#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 667207#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 666743#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 666744#L953 assume !(0 != activate_threads_~tmp___0~0); 668078#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 668079#L404 assume !(1 == ~t2_pc~0); 668091#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 667434#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 667352#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 667353#L961 assume !(0 != activate_threads_~tmp___1~0); 667776#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 666639#L423 assume !(1 == ~t3_pc~0); 666640#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 666647#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 667641#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 667140#L969 assume !(0 != activate_threads_~tmp___2~0); 667141#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 666669#L442 assume !(1 == ~t4_pc~0); 666649#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 666650#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 667714#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 667823#L977 assume !(0 != activate_threads_~tmp___3~0); 668107#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 667036#L461 assume !(1 == ~t5_pc~0); 667037#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 667041#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 667968#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 667681#L985 assume !(0 != activate_threads_~tmp___4~0); 667682#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 667329#L480 assume !(1 == ~t6_pc~0); 667305#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 667306#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 668061#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 666962#L993 assume !(0 != activate_threads_~tmp___5~0); 666963#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 666966#L499 assume !(1 == ~t7_pc~0); 667580#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 666457#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 666347#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 666348#L1001 assume !(0 != activate_threads_~tmp___6~0); 668001#L1001-2 assume !(1 == ~M_E~0); 667992#L847-1 assume !(1 == ~T1_E~0); 667467#L852-1 assume !(1 == ~T2_E~0); 667064#L857-1 assume !(1 == ~T3_E~0); 666498#L862-1 assume !(1 == ~T4_E~0); 666499#L867-1 assume !(1 == ~T5_E~0); 667833#L872-1 assume !(1 == ~T6_E~0); 667272#L877-1 assume !(1 == ~T7_E~0); 666685#L882-1 assume !(1 == ~E_M~0); 666686#L887-1 assume !(1 == ~E_1~0); 667942#L892-1 assume !(1 == ~E_2~0); 667690#L897-1 assume !(1 == ~E_3~0); 667264#L902-1 assume !(1 == ~E_4~0); 666381#L907-1 assume !(1 == ~E_5~0); 666382#L912-1 assume !(1 == ~E_6~0); 667608#L917-1 assume !(1 == ~E_7~0); 667609#L1168-1 assume !false; 671996#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 688993#L734 [2018-12-08 18:43:54,321 INFO L796 eck$LassoCheckResult]: Loop: 688993#L734 assume !false; 695874#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 695873#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 695872#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 695870#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 695869#L631 assume 0 != eval_~tmp~0; 695868#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 695866#L639 assume !(0 != eval_~tmp_ndt_1~0); 695867#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 695897#L653 assume !(0 != eval_~tmp_ndt_2~0); 695894#L650 assume !(0 == ~t2_st~0); 695891#L664 assume !(0 == ~t3_st~0); 695888#L678 assume !(0 == ~t4_st~0); 695885#L692 assume !(0 == ~t5_st~0); 695881#L706 assume !(0 == ~t6_st~0); 695878#L720 assume !(0 == ~t7_st~0); 688993#L734 [2018-12-08 18:43:54,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:54,321 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 2 times [2018-12-08 18:43:54,321 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:54,321 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:54,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:54,322 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:54,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:54,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:54,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:54,337 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:54,337 INFO L82 PathProgramCache]: Analyzing trace with hash 958375116, now seen corresponding path program 1 times [2018-12-08 18:43:54,337 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:54,337 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:54,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:54,337 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:54,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:54,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:54,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:54,340 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:54,341 INFO L82 PathProgramCache]: Analyzing trace with hash 303384302, now seen corresponding path program 1 times [2018-12-08 18:43:54,341 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:54,341 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:54,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:54,341 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:54,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:54,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:54,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:54,368 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:54,368 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:54,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:54,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:54,423 INFO L87 Difference]: Start difference. First operand 55001 states and 69487 transitions. cyclomatic complexity: 14526 Second operand 3 states. [2018-12-08 18:43:54,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:54,571 INFO L93 Difference]: Finished difference Result 94341 states and 118827 transitions. [2018-12-08 18:43:54,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:54,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94341 states and 118827 transitions. [2018-12-08 18:43:54,767 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 57560 [2018-12-08 18:43:54,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94341 states to 94341 states and 118827 transitions. [2018-12-08 18:43:54,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58092 [2018-12-08 18:43:54,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58092 [2018-12-08 18:43:54,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94341 states and 118827 transitions. [2018-12-08 18:43:54,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:54,943 INFO L705 BuchiCegarLoop]: Abstraction has 94341 states and 118827 transitions. [2018-12-08 18:43:54,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94341 states and 118827 transitions. [2018-12-08 18:43:55,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94341 to 94341. [2018-12-08 18:43:55,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94341 states. [2018-12-08 18:43:55,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94341 states to 94341 states and 118827 transitions. [2018-12-08 18:43:55,642 INFO L728 BuchiCegarLoop]: Abstraction has 94341 states and 118827 transitions. [2018-12-08 18:43:55,642 INFO L608 BuchiCegarLoop]: Abstraction has 94341 states and 118827 transitions. [2018-12-08 18:43:55,642 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2018-12-08 18:43:55,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94341 states and 118827 transitions. [2018-12-08 18:43:55,781 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 57560 [2018-12-08 18:43:55,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:55,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:55,782 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:55,782 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:55,782 INFO L794 eck$LassoCheckResult]: Stem: 816511#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 816346#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 816347#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 817049#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 816696#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 816254#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 816255#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 817050#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 816671#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 816130#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 815916#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 815917#L561-1 assume !(0 == ~M_E~0); 817317#L759-1 assume !(0 == ~T1_E~0); 816814#L764-1 assume !(0 == ~T2_E~0); 816416#L769-1 assume !(0 == ~T3_E~0); 815854#L774-1 assume !(0 == ~T4_E~0); 815855#L779-1 assume !(0 == ~T5_E~0); 817169#L784-1 assume !(0 == ~T6_E~0); 816778#L789-1 assume !(0 == ~T7_E~0); 816014#L794-1 assume !(0 == ~E_M~0); 816015#L799-1 assume !(0 == ~E_1~0); 817268#L804-1 assume !(0 == ~E_2~0); 817018#L809-1 assume !(0 == ~E_3~0); 816587#L814-1 assume !(0 == ~E_4~0); 815704#L819-1 assume !(0 == ~E_5~0); 815705#L824-1 assume !(0 == ~E_6~0); 816960#L829-1 assume !(0 == ~E_7~0); 816708#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 816709#L366 assume !(1 == ~m_pc~0); 817139#L366-2 is_master_triggered_~__retres1~0 := 0; 816198#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 815824#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 815825#L945 assume !(0 != activate_threads_~tmp~1); 816417#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 816418#L385 assume !(1 == ~t1_pc~0); 817085#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 816551#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 816090#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 816091#L953 assume !(0 != activate_threads_~tmp___0~0); 817405#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 817406#L404 assume !(1 == ~t2_pc~0); 817416#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 816777#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 816697#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 816698#L961 assume !(0 != activate_threads_~tmp___1~0); 817116#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 815986#L423 assume !(1 == ~t3_pc~0); 815987#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 815992#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 816988#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 816484#L969 assume !(0 != activate_threads_~tmp___2~0); 816485#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 816013#L442 assume !(1 == ~t4_pc~0); 815994#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 815995#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 817053#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 817159#L977 assume !(0 != activate_threads_~tmp___3~0); 817429#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 816384#L461 assume !(1 == ~t5_pc~0); 816385#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 816389#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 817300#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 817023#L985 assume !(0 != activate_threads_~tmp___4~0); 817024#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 816672#L480 assume !(1 == ~t6_pc~0); 816649#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 816650#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 817390#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 816305#L993 assume !(0 != activate_threads_~tmp___5~0); 816306#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 816309#L499 assume !(1 == ~t7_pc~0); 816925#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 815807#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 815697#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 815698#L1001 assume !(0 != activate_threads_~tmp___6~0); 817325#L1001-2 assume !(1 == ~M_E~0); 817321#L847-1 assume !(1 == ~T1_E~0); 816805#L852-1 assume !(1 == ~T2_E~0); 816411#L857-1 assume !(1 == ~T3_E~0); 815848#L862-1 assume !(1 == ~T4_E~0); 815849#L867-1 assume !(1 == ~T5_E~0); 817166#L872-1 assume !(1 == ~T6_E~0); 816616#L877-1 assume !(1 == ~T7_E~0); 816028#L882-1 assume !(1 == ~E_M~0); 816029#L887-1 assume !(1 == ~E_1~0); 817279#L892-1 assume !(1 == ~E_2~0); 817031#L897-1 assume !(1 == ~E_3~0); 816608#L902-1 assume !(1 == ~E_4~0); 815731#L907-1 assume !(1 == ~E_5~0); 815732#L912-1 assume !(1 == ~E_6~0); 816951#L917-1 assume !(1 == ~E_7~0); 816952#L1168-1 assume !false; 827440#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 857861#L734 [2018-12-08 18:43:55,782 INFO L796 eck$LassoCheckResult]: Loop: 857861#L734 assume !false; 858260#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 858259#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 858258#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 857847#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 857845#L631 assume 0 != eval_~tmp~0; 857843#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 857840#L639 assume !(0 != eval_~tmp_ndt_1~0); 857838#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 857835#L653 assume !(0 != eval_~tmp_ndt_2~0); 857833#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 857819#L667 assume !(0 != eval_~tmp_ndt_3~0); 857831#L664 assume !(0 == ~t3_st~0); 857876#L678 assume !(0 == ~t4_st~0); 857871#L692 assume !(0 == ~t5_st~0); 857866#L706 assume !(0 == ~t6_st~0); 857865#L720 assume !(0 == ~t7_st~0); 857861#L734 [2018-12-08 18:43:55,783 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:55,783 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 3 times [2018-12-08 18:43:55,783 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:55,783 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:55,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:55,783 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:55,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:55,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:55,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:55,802 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:55,802 INFO L82 PathProgramCache]: Analyzing trace with hash -1372155581, now seen corresponding path program 1 times [2018-12-08 18:43:55,802 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:55,802 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:55,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:55,802 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:55,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:55,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:55,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:55,806 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:55,807 INFO L82 PathProgramCache]: Analyzing trace with hash -202034335, now seen corresponding path program 1 times [2018-12-08 18:43:55,807 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:55,807 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:55,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:55,808 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:55,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:55,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:55,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:55,836 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:55,837 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:55,893 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:55,893 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:55,894 INFO L87 Difference]: Start difference. First operand 94341 states and 118827 transitions. cyclomatic complexity: 24526 Second operand 3 states. [2018-12-08 18:43:56,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:56,129 INFO L93 Difference]: Finished difference Result 124969 states and 156849 transitions. [2018-12-08 18:43:56,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:56,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124969 states and 156849 transitions. [2018-12-08 18:43:56,400 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 76528 [2018-12-08 18:43:56,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124969 states to 124969 states and 156849 transitions. [2018-12-08 18:43:56,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77204 [2018-12-08 18:43:56,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77204 [2018-12-08 18:43:56,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124969 states and 156849 transitions. [2018-12-08 18:43:56,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:56,624 INFO L705 BuchiCegarLoop]: Abstraction has 124969 states and 156849 transitions. [2018-12-08 18:43:56,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124969 states and 156849 transitions. [2018-12-08 18:43:57,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124969 to 124969. [2018-12-08 18:43:57,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124969 states. [2018-12-08 18:43:57,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124969 states to 124969 states and 156849 transitions. [2018-12-08 18:43:57,370 INFO L728 BuchiCegarLoop]: Abstraction has 124969 states and 156849 transitions. [2018-12-08 18:43:57,370 INFO L608 BuchiCegarLoop]: Abstraction has 124969 states and 156849 transitions. [2018-12-08 18:43:57,370 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2018-12-08 18:43:57,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124969 states and 156849 transitions. [2018-12-08 18:43:58,201 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 76528 [2018-12-08 18:43:58,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:43:58,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:43:58,201 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:58,201 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:43:58,202 INFO L794 eck$LassoCheckResult]: Stem: 1035824#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1035656#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1035657#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1036355#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 1036001#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1035567#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1035568#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1036356#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1035977#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1035445#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1035232#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1035233#L561-1 assume !(0 == ~M_E~0); 1036623#L759-1 assume !(0 == ~T1_E~0); 1036131#L764-1 assume !(0 == ~T2_E~0); 1035729#L769-1 assume !(0 == ~T3_E~0); 1035170#L774-1 assume !(0 == ~T4_E~0); 1035171#L779-1 assume !(0 == ~T5_E~0); 1036484#L784-1 assume !(0 == ~T6_E~0); 1036098#L789-1 assume !(0 == ~T7_E~0); 1035333#L794-1 assume !(0 == ~E_M~0); 1035334#L799-1 assume !(0 == ~E_1~0); 1036579#L804-1 assume !(0 == ~E_2~0); 1036327#L809-1 assume !(0 == ~E_3~0); 1035899#L814-1 assume !(0 == ~E_4~0); 1035022#L819-1 assume !(0 == ~E_5~0); 1035023#L824-1 assume !(0 == ~E_6~0); 1036276#L829-1 assume !(0 == ~E_7~0); 1036014#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1036015#L366 assume !(1 == ~m_pc~0); 1036445#L366-2 is_master_triggered_~__retres1~0 := 0; 1035507#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1035138#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1035139#L945 assume !(0 != activate_threads_~tmp~1); 1035730#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1035731#L385 assume !(1 == ~t1_pc~0); 1036390#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 1035861#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1035405#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1035406#L953 assume !(0 != activate_threads_~tmp___0~0); 1036708#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1036709#L404 assume !(1 == ~t2_pc~0); 1036716#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 1036091#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1036002#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1036003#L961 assume !(0 != activate_threads_~tmp___1~0); 1036420#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1035302#L423 assume !(1 == ~t3_pc~0); 1035303#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 1035311#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1036298#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1035796#L969 assume !(0 != activate_threads_~tmp___2~0); 1035797#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1035332#L442 assume !(1 == ~t4_pc~0); 1035314#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 1035315#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1036359#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1036472#L977 assume !(0 != activate_threads_~tmp___3~0); 1036727#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1035693#L461 assume !(1 == ~t5_pc~0); 1035694#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 1035697#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1036608#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1036332#L985 assume !(0 != activate_threads_~tmp___4~0); 1036333#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1035978#L480 assume !(1 == ~t6_pc~0); 1035959#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 1035960#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1036691#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1035616#L993 assume !(0 != activate_threads_~tmp___5~0); 1035617#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1035620#L499 assume !(1 == ~t7_pc~0); 1036240#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 1035125#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1035015#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1035016#L1001 assume !(0 != activate_threads_~tmp___6~0); 1036633#L1001-2 assume !(1 == ~M_E~0); 1036629#L847-1 assume !(1 == ~T1_E~0); 1036126#L852-1 assume !(1 == ~T2_E~0); 1035724#L857-1 assume !(1 == ~T3_E~0); 1035164#L862-1 assume !(1 == ~T4_E~0); 1035165#L867-1 assume !(1 == ~T5_E~0); 1036481#L872-1 assume !(1 == ~T6_E~0); 1035927#L877-1 assume !(1 == ~T7_E~0); 1035347#L882-1 assume !(1 == ~E_M~0); 1035348#L887-1 assume !(1 == ~E_1~0); 1036589#L892-1 assume !(1 == ~E_2~0); 1036340#L897-1 assume !(1 == ~E_3~0); 1035920#L902-1 assume !(1 == ~E_4~0); 1035049#L907-1 assume !(1 == ~E_5~0); 1035050#L912-1 assume !(1 == ~E_6~0); 1036269#L917-1 assume !(1 == ~E_7~0); 1036270#L1168-1 assume !false; 1056523#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1056518#L734 [2018-12-08 18:43:58,202 INFO L796 eck$LassoCheckResult]: Loop: 1056518#L734 assume !false; 1056516#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1056514#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1056512#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1056511#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1056507#L631 assume 0 != eval_~tmp~0; 1056505#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1056503#L639 assume !(0 != eval_~tmp_ndt_1~0); 1056502#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1056472#L653 assume !(0 != eval_~tmp_ndt_2~0); 1049101#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1049096#L667 assume !(0 != eval_~tmp_ndt_3~0); 1049094#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1049092#L681 assume !(0 != eval_~tmp_ndt_4~0); 1049091#L678 assume !(0 == ~t4_st~0); 1049088#L692 assume !(0 == ~t5_st~0); 1049084#L706 assume !(0 == ~t6_st~0); 1049083#L720 assume !(0 == ~t7_st~0); 1056518#L734 [2018-12-08 18:43:58,202 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:58,202 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 4 times [2018-12-08 18:43:58,202 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:58,202 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:58,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:58,203 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:58,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:58,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:58,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:58,217 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:58,217 INFO L82 PathProgramCache]: Analyzing trace with hash -1836711777, now seen corresponding path program 1 times [2018-12-08 18:43:58,217 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:58,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:58,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:58,217 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:43:58,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:58,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:58,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:43:58,220 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:43:58,221 INFO L82 PathProgramCache]: Analyzing trace with hash 77308481, now seen corresponding path program 1 times [2018-12-08 18:43:58,221 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:43:58,221 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:43:58,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:58,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:43:58,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:43:58,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:43:58,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:43:58,238 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:43:58,238 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:43:58,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:43:58,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:43:58,315 INFO L87 Difference]: Start difference. First operand 124969 states and 156849 transitions. cyclomatic complexity: 31920 Second operand 3 states. [2018-12-08 18:43:58,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:43:58,650 INFO L93 Difference]: Finished difference Result 195547 states and 245439 transitions. [2018-12-08 18:43:58,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:43:58,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195547 states and 245439 transitions. [2018-12-08 18:43:59,083 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 124524 [2018-12-08 18:43:59,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195547 states to 195547 states and 245439 transitions. [2018-12-08 18:43:59,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125488 [2018-12-08 18:43:59,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125488 [2018-12-08 18:43:59,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195547 states and 245439 transitions. [2018-12-08 18:43:59,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:43:59,458 INFO L705 BuchiCegarLoop]: Abstraction has 195547 states and 245439 transitions. [2018-12-08 18:43:59,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195547 states and 245439 transitions. [2018-12-08 18:44:00,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195547 to 193639. [2018-12-08 18:44:00,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193639 states. [2018-12-08 18:44:00,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193639 states to 193639 states and 243099 transitions. [2018-12-08 18:44:00,775 INFO L728 BuchiCegarLoop]: Abstraction has 193639 states and 243099 transitions. [2018-12-08 18:44:00,775 INFO L608 BuchiCegarLoop]: Abstraction has 193639 states and 243099 transitions. [2018-12-08 18:44:00,775 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2018-12-08 18:44:00,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193639 states and 243099 transitions. [2018-12-08 18:44:01,089 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 122616 [2018-12-08 18:44:01,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:44:01,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:44:01,090 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:44:01,090 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:44:01,090 INFO L794 eck$LassoCheckResult]: Stem: 1356383#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1356202#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1356203#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1356931#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 1356573#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1356100#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1356101#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1356932#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1356552#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1355975#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1355759#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1355760#L561-1 assume !(0 == ~M_E~0); 1357214#L759-1 assume !(0 == ~T1_E~0); 1356691#L764-1 assume !(0 == ~T2_E~0); 1356282#L769-1 assume !(0 == ~T3_E~0); 1355694#L774-1 assume !(0 == ~T4_E~0); 1355695#L779-1 assume !(0 == ~T5_E~0); 1357059#L784-1 assume !(0 == ~T6_E~0); 1356662#L789-1 assume !(0 == ~T7_E~0); 1355859#L794-1 assume !(0 == ~E_M~0); 1355860#L799-1 assume !(0 == ~E_1~0); 1357157#L804-1 assume !(0 == ~E_2~0); 1356892#L809-1 assume !(0 == ~E_3~0); 1356463#L814-1 assume !(0 == ~E_4~0); 1355546#L819-1 assume !(0 == ~E_5~0); 1355547#L824-1 assume !(0 == ~E_6~0); 1356838#L829-1 assume !(0 == ~E_7~0); 1356586#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1356587#L366 assume !(1 == ~m_pc~0); 1357021#L366-2 is_master_triggered_~__retres1~0 := 0; 1356047#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1355666#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1355667#L945 assume !(0 != activate_threads_~tmp~1); 1356283#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1356284#L385 assume !(1 == ~t1_pc~0); 1356969#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 1356424#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1355933#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1355934#L953 assume !(0 != activate_threads_~tmp___0~0); 1357300#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1357301#L404 assume !(1 == ~t2_pc~0); 1357309#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 1356661#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1356574#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1356575#L961 assume !(0 != activate_threads_~tmp___1~0); 1356996#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1355832#L423 assume !(1 == ~t3_pc~0); 1355833#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 1355838#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1356861#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1356351#L969 assume !(0 != activate_threads_~tmp___2~0); 1356352#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1355858#L442 assume !(1 == ~t4_pc~0); 1355840#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 1355841#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1356935#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1357047#L977 assume !(0 != activate_threads_~tmp___3~0); 1357327#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1356241#L461 assume !(1 == ~t5_pc~0); 1356242#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 1356245#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1357083#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1356898#L985 assume !(0 != activate_threads_~tmp___4~0); 1356899#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1356553#L480 assume !(1 == ~t6_pc~0); 1356525#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 1356526#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1357285#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1356158#L993 assume !(0 != activate_threads_~tmp___5~0); 1356159#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1356163#L499 assume !(1 == ~t7_pc~0); 1356798#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 1355649#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1355539#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1355540#L1001 assume !(0 != activate_threads_~tmp___6~0); 1357224#L1001-2 assume !(1 == ~M_E~0); 1357219#L847-1 assume !(1 == ~T1_E~0); 1356686#L852-1 assume !(1 == ~T2_E~0); 1356275#L857-1 assume !(1 == ~T3_E~0); 1355688#L862-1 assume !(1 == ~T4_E~0); 1355689#L867-1 assume !(1 == ~T5_E~0); 1357056#L872-1 assume !(1 == ~T6_E~0); 1356493#L877-1 assume !(1 == ~T7_E~0); 1355874#L882-1 assume !(1 == ~E_M~0); 1355875#L887-1 assume !(1 == ~E_1~0); 1357169#L892-1 assume !(1 == ~E_2~0); 1356906#L897-1 assume !(1 == ~E_3~0); 1356484#L902-1 assume !(1 == ~E_4~0); 1355573#L907-1 assume !(1 == ~E_5~0); 1355574#L912-1 assume !(1 == ~E_6~0); 1356829#L917-1 assume !(1 == ~E_7~0); 1356830#L1168-1 assume !false; 1372654#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1457216#L734 [2018-12-08 18:44:01,090 INFO L796 eck$LassoCheckResult]: Loop: 1457216#L734 assume !false; 1457214#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1457212#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1457210#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1457208#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1457206#L631 assume 0 != eval_~tmp~0; 1457204#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1457200#L639 assume !(0 != eval_~tmp_ndt_1~0); 1457198#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1457195#L653 assume !(0 != eval_~tmp_ndt_2~0); 1457193#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1457180#L667 assume !(0 != eval_~tmp_ndt_3~0); 1457190#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1457392#L681 assume !(0 != eval_~tmp_ndt_4~0); 1457390#L678 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1457388#L695 assume !(0 != eval_~tmp_ndt_5~0); 1457387#L692 assume !(0 == ~t5_st~0); 1457383#L706 assume !(0 == ~t6_st~0); 1457221#L720 assume !(0 == ~t7_st~0); 1457216#L734 [2018-12-08 18:44:01,090 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:01,091 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 5 times [2018-12-08 18:44:01,091 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:01,091 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:01,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:01,092 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:01,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:01,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:01,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:01,115 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:01,115 INFO L82 PathProgramCache]: Analyzing trace with hash -1314601616, now seen corresponding path program 1 times [2018-12-08 18:44:01,116 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:01,116 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:01,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:01,116 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:44:01,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:01,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:01,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:01,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:01,120 INFO L82 PathProgramCache]: Analyzing trace with hash -2109515762, now seen corresponding path program 1 times [2018-12-08 18:44:01,120 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:01,120 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:01,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:01,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:01,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:01,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:44:01,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:44:01,144 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:44:01,144 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:44:01,216 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:44:01,216 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:44:01,216 INFO L87 Difference]: Start difference. First operand 193639 states and 243099 transitions. cyclomatic complexity: 49500 Second operand 3 states. [2018-12-08 18:44:01,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:44:01,817 INFO L93 Difference]: Finished difference Result 356773 states and 447371 transitions. [2018-12-08 18:44:01,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:44:01,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 356773 states and 447371 transitions. [2018-12-08 18:44:02,665 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 226124 [2018-12-08 18:44:03,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 356773 states to 356773 states and 447371 transitions. [2018-12-08 18:44:03,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 227952 [2018-12-08 18:44:03,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 227952 [2018-12-08 18:44:03,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 356773 states and 447371 transitions. [2018-12-08 18:44:03,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:44:03,408 INFO L705 BuchiCegarLoop]: Abstraction has 356773 states and 447371 transitions. [2018-12-08 18:44:03,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 356773 states and 447371 transitions. [2018-12-08 18:44:05,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 356773 to 347269. [2018-12-08 18:44:05,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 347269 states. [2018-12-08 18:44:06,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347269 states to 347269 states and 436139 transitions. [2018-12-08 18:44:06,167 INFO L728 BuchiCegarLoop]: Abstraction has 347269 states and 436139 transitions. [2018-12-08 18:44:06,167 INFO L608 BuchiCegarLoop]: Abstraction has 347269 states and 436139 transitions. [2018-12-08 18:44:06,167 INFO L442 BuchiCegarLoop]: ======== Iteration 37============ [2018-12-08 18:44:06,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 347269 states and 436139 transitions. [2018-12-08 18:44:08,333 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 220184 [2018-12-08 18:44:08,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:44:08,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:44:08,334 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:44:08,334 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:44:08,334 INFO L794 eck$LassoCheckResult]: Stem: 1906828#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1906647#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1906648#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1907442#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 1907035#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1906532#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1906533#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1907443#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1907011#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1906405#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1906178#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1906179#L561-1 assume !(0 == ~M_E~0); 1907770#L759-1 assume !(0 == ~T1_E~0); 1907186#L764-1 assume !(0 == ~T2_E~0); 1906728#L769-1 assume !(0 == ~T3_E~0); 1906114#L774-1 assume !(0 == ~T4_E~0); 1906115#L779-1 assume !(0 == ~T5_E~0); 1907584#L784-1 assume !(0 == ~T6_E~0); 1907148#L789-1 assume !(0 == ~T7_E~0); 1906289#L794-1 assume !(0 == ~E_M~0); 1906290#L799-1 assume !(0 == ~E_1~0); 1907698#L804-1 assume !(0 == ~E_2~0); 1907399#L809-1 assume !(0 == ~E_3~0); 1906920#L814-1 assume !(0 == ~E_4~0); 1905966#L819-1 assume !(0 == ~E_5~0); 1905967#L824-1 assume !(0 == ~E_6~0); 1907340#L829-1 assume !(0 == ~E_7~0); 1907048#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1907049#L366 assume !(1 == ~m_pc~0); 1907542#L366-2 is_master_triggered_~__retres1~0 := 0; 1906475#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1906086#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1906087#L945 assume !(0 != activate_threads_~tmp~1); 1906729#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1906730#L385 assume !(1 == ~t1_pc~0); 1907485#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 1906871#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1906365#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1906366#L953 assume !(0 != activate_threads_~tmp___0~0); 1907871#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1907872#L404 assume !(1 == ~t2_pc~0); 1907879#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 1907147#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1907036#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1907037#L961 assume !(0 != activate_threads_~tmp___1~0); 1907513#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1906259#L423 assume !(1 == ~t3_pc~0); 1906260#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 1906265#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1907367#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1906799#L969 assume !(0 != activate_threads_~tmp___2~0); 1906800#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1906288#L442 assume !(1 == ~t4_pc~0); 1906268#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 1906269#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1907447#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1907571#L977 assume !(0 != activate_threads_~tmp___3~0); 1907902#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1906685#L461 assume !(1 == ~t5_pc~0); 1906686#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 1906690#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1907616#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1907406#L985 assume !(0 != activate_threads_~tmp___4~0); 1907407#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1907012#L480 assume !(1 == ~t6_pc~0); 1906984#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 1906985#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1907850#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1906597#L993 assume !(0 != activate_threads_~tmp___5~0); 1906598#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1906601#L499 assume !(1 == ~t7_pc~0); 1907302#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 1906069#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1905959#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1905960#L1001 assume !(0 != activate_threads_~tmp___6~0); 1907784#L1001-2 assume !(1 == ~M_E~0); 1907774#L847-1 assume !(1 == ~T1_E~0); 1907180#L852-1 assume !(1 == ~T2_E~0); 1906722#L857-1 assume !(1 == ~T3_E~0); 1906108#L862-1 assume !(1 == ~T4_E~0); 1906109#L867-1 assume !(1 == ~T5_E~0); 1907581#L872-1 assume !(1 == ~T6_E~0); 1906954#L877-1 assume !(1 == ~T7_E~0); 1906305#L882-1 assume !(1 == ~E_M~0); 1906306#L887-1 assume !(1 == ~E_1~0); 1907709#L892-1 assume !(1 == ~E_2~0); 1907415#L897-1 assume !(1 == ~E_3~0); 1906947#L902-1 assume !(1 == ~E_4~0); 1905993#L907-1 assume !(1 == ~E_5~0); 1905994#L912-1 assume !(1 == ~E_6~0); 1907330#L917-1 assume !(1 == ~E_7~0); 1907331#L1168-1 assume !false; 1977657#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 2063355#L734 [2018-12-08 18:44:08,334 INFO L796 eck$LassoCheckResult]: Loop: 2063355#L734 assume !false; 2063350#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2063347#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 2063344#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2063340#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2063336#L631 assume 0 != eval_~tmp~0; 2063333#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2063327#L639 assume !(0 != eval_~tmp_ndt_1~0); 2063328#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2076368#L653 assume !(0 != eval_~tmp_ndt_2~0); 2040810#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2040807#L667 assume !(0 != eval_~tmp_ndt_3~0); 2040804#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2037497#L681 assume !(0 != eval_~tmp_ndt_4~0); 2037498#L678 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2063620#L695 assume !(0 != eval_~tmp_ndt_5~0); 2063614#L692 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 2063590#L709 assume !(0 != eval_~tmp_ndt_6~0); 2063599#L706 assume !(0 == ~t6_st~0); 2063362#L720 assume !(0 == ~t7_st~0); 2063355#L734 [2018-12-08 18:44:08,334 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:08,334 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 6 times [2018-12-08 18:44:08,334 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:08,334 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:08,335 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:08,335 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:08,335 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:08,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:08,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:08,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:08,348 INFO L82 PathProgramCache]: Analyzing trace with hash -2104752014, now seen corresponding path program 1 times [2018-12-08 18:44:08,348 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:08,348 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:08,348 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:08,348 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:44:08,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:08,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:08,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:08,352 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:08,352 INFO L82 PathProgramCache]: Analyzing trace with hash -977286764, now seen corresponding path program 1 times [2018-12-08 18:44:08,352 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:08,352 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:08,353 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:08,353 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:08,353 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:08,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:44:08,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:44:08,372 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:44:08,372 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 18:44:08,443 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:44:08,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:44:08,443 INFO L87 Difference]: Start difference. First operand 347269 states and 436139 transitions. cyclomatic complexity: 88910 Second operand 3 states. [2018-12-08 18:44:09,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:44:09,342 INFO L93 Difference]: Finished difference Result 497237 states and 624001 transitions. [2018-12-08 18:44:09,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:44:09,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 497237 states and 624001 transitions. [2018-12-08 18:44:10,640 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 315438 [2018-12-08 18:44:11,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 497237 states to 497237 states and 624001 transitions. [2018-12-08 18:44:11,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 317770 [2018-12-08 18:44:11,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 317770 [2018-12-08 18:44:11,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 497237 states and 624001 transitions. [2018-12-08 18:44:11,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:44:11,634 INFO L705 BuchiCegarLoop]: Abstraction has 497237 states and 624001 transitions. [2018-12-08 18:44:11,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 497237 states and 624001 transitions. [2018-12-08 18:44:14,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 497237 to 489749. [2018-12-08 18:44:14,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 489749 states. [2018-12-08 18:44:15,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489749 states to 489749 states and 614785 transitions. [2018-12-08 18:44:15,216 INFO L728 BuchiCegarLoop]: Abstraction has 489749 states and 614785 transitions. [2018-12-08 18:44:15,216 INFO L608 BuchiCegarLoop]: Abstraction has 489749 states and 614785 transitions. [2018-12-08 18:44:15,216 INFO L442 BuchiCegarLoop]: ======== Iteration 38============ [2018-12-08 18:44:15,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489749 states and 614785 transitions. [2018-12-08 18:44:16,161 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 310758 [2018-12-08 18:44:16,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:44:16,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:44:16,162 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:44:16,162 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:44:16,162 INFO L794 eck$LassoCheckResult]: Stem: 2751339#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2751152#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2751153#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2751932#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 2751540#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2751037#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2751038#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2751933#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2751516#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2750907#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2750686#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2750687#L561-1 assume !(0 == ~M_E~0); 2752267#L759-1 assume !(0 == ~T1_E~0); 2751661#L764-1 assume !(0 == ~T2_E~0); 2751233#L769-1 assume !(0 == ~T3_E~0); 2750622#L774-1 assume !(0 == ~T4_E~0); 2750623#L779-1 assume !(0 == ~T5_E~0); 2752069#L784-1 assume !(0 == ~T6_E~0); 2751628#L789-1 assume !(0 == ~T7_E~0); 2750793#L794-1 assume !(0 == ~E_M~0); 2750794#L799-1 assume !(0 == ~E_1~0); 2752181#L804-1 assume !(0 == ~E_2~0); 2751891#L809-1 assume !(0 == ~E_3~0); 2751425#L814-1 assume !(0 == ~E_4~0); 2750480#L819-1 assume !(0 == ~E_5~0); 2750481#L824-1 assume !(0 == ~E_6~0); 2751829#L829-1 assume !(0 == ~E_7~0); 2751553#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2751554#L366 assume !(1 == ~m_pc~0); 2752029#L366-2 is_master_triggered_~__retres1~0 := 0; 2750977#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2750594#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2750595#L945 assume !(0 != activate_threads_~tmp~1); 2751234#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2751235#L385 assume !(1 == ~t1_pc~0); 2751971#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 2751381#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2750866#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2750867#L953 assume !(0 != activate_threads_~tmp___0~0); 2752369#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2752370#L404 assume !(1 == ~t2_pc~0); 2752382#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 2751624#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2751541#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2751542#L961 assume !(0 != activate_threads_~tmp___1~0); 2752002#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2750759#L423 assume !(1 == ~t3_pc~0); 2750760#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 2750770#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2751855#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2751308#L969 assume !(0 != activate_threads_~tmp___2~0); 2751309#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2750792#L442 assume !(1 == ~t4_pc~0); 2750772#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 2750773#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2751936#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2752054#L977 assume !(0 != activate_threads_~tmp___3~0); 2752409#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2751192#L461 assume !(1 == ~t5_pc~0); 2751193#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 2751197#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2752105#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2751898#L985 assume !(0 != activate_threads_~tmp___4~0); 2751899#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2751517#L480 assume !(1 == ~t6_pc~0); 2751490#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 2751491#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2752348#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2751107#L993 assume !(0 != activate_threads_~tmp___5~0); 2751108#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2751111#L499 assume !(1 == ~t7_pc~0); 2751784#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 2750581#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2750473#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2750474#L1001 assume !(0 != activate_threads_~tmp___6~0); 2752277#L1001-2 assume !(1 == ~M_E~0); 2752272#L847-1 assume !(1 == ~T1_E~0); 2751657#L852-1 assume !(1 == ~T2_E~0); 2751226#L857-1 assume !(1 == ~T3_E~0); 2750616#L862-1 assume !(1 == ~T4_E~0); 2750617#L867-1 assume !(1 == ~T5_E~0); 2752065#L872-1 assume !(1 == ~T6_E~0); 2751453#L877-1 assume !(1 == ~T7_E~0); 2750807#L882-1 assume !(1 == ~E_M~0); 2750808#L887-1 assume !(1 == ~E_1~0); 2752195#L892-1 assume !(1 == ~E_2~0); 2751906#L897-1 assume !(1 == ~E_3~0); 2751448#L902-1 assume !(1 == ~E_4~0); 2750507#L907-1 assume !(1 == ~E_5~0); 2750508#L912-1 assume !(1 == ~E_6~0); 2751822#L917-1 assume !(1 == ~E_7~0); 2751823#L1168-1 assume !false; 3015203#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3042715#L734 [2018-12-08 18:44:16,162 INFO L796 eck$LassoCheckResult]: Loop: 3042715#L734 assume !false; 3042713#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3042711#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3042709#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3042707#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3042705#L631 assume 0 != eval_~tmp~0; 3042703#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 3042701#L639 assume !(0 != eval_~tmp_ndt_1~0); 2896482#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2896478#L653 assume !(0 != eval_~tmp_ndt_2~0); 2896480#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2906006#L667 assume !(0 != eval_~tmp_ndt_3~0); 2906002#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2906000#L681 assume !(0 != eval_~tmp_ndt_4~0); 2905999#L678 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2905996#L695 assume !(0 != eval_~tmp_ndt_5~0); 2878375#L692 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 2878372#L709 assume !(0 != eval_~tmp_ndt_6~0); 2878370#L706 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 2878368#L723 assume !(0 != eval_~tmp_ndt_7~0); 2878369#L720 assume !(0 == ~t7_st~0); 3042715#L734 [2018-12-08 18:44:16,163 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:16,163 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 7 times [2018-12-08 18:44:16,163 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:16,163 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:16,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:16,164 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:16,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:16,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:16,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:16,179 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:16,179 INFO L82 PathProgramCache]: Analyzing trace with hash -823020131, now seen corresponding path program 1 times [2018-12-08 18:44:16,179 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:16,179 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:16,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:16,180 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:16,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:16,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:16,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:16,183 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:16,184 INFO L82 PathProgramCache]: Analyzing trace with hash -231335749, now seen corresponding path program 1 times [2018-12-08 18:44:16,184 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:16,184 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:16,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:16,184 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:16,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:16,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 18:44:16,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 18:44:16,207 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 18:44:16,208 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-12-08 18:44:16,615 WARN L180 SmtUtils]: Spent 406.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 54 [2018-12-08 18:44:16,643 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 18:44:16,643 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 18:44:16,643 INFO L87 Difference]: Start difference. First operand 489749 states and 614785 transitions. cyclomatic complexity: 125076 Second operand 3 states. [2018-12-08 18:44:18,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 18:44:18,375 INFO L93 Difference]: Finished difference Result 844776 states and 1059835 transitions. [2018-12-08 18:44:18,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 18:44:18,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 844776 states and 1059835 transitions. [2018-12-08 18:44:24,732 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 536492 [2018-12-08 18:44:26,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 844776 states to 844776 states and 1059835 transitions. [2018-12-08 18:44:26,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 541056 [2018-12-08 18:44:26,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 541056 [2018-12-08 18:44:26,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 844776 states and 1059835 transitions. [2018-12-08 18:44:26,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-12-08 18:44:26,227 INFO L705 BuchiCegarLoop]: Abstraction has 844776 states and 1059835 transitions. [2018-12-08 18:44:26,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 844776 states and 1059835 transitions. [2018-12-08 18:44:31,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 844776 to 844776. [2018-12-08 18:44:31,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 844776 states. [2018-12-08 18:44:32,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 844776 states to 844776 states and 1059835 transitions. [2018-12-08 18:44:32,455 INFO L728 BuchiCegarLoop]: Abstraction has 844776 states and 1059835 transitions. [2018-12-08 18:44:32,455 INFO L608 BuchiCegarLoop]: Abstraction has 844776 states and 1059835 transitions. [2018-12-08 18:44:32,455 INFO L442 BuchiCegarLoop]: ======== Iteration 39============ [2018-12-08 18:44:32,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 844776 states and 1059835 transitions. [2018-12-08 18:44:34,535 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 536492 [2018-12-08 18:44:34,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-12-08 18:44:34,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-12-08 18:44:34,536 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:44:34,536 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 18:44:34,536 INFO L794 eck$LassoCheckResult]: Stem: 4085854#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 4085678#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4085679#L1131 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4086417#L519 assume 1 == ~m_i~0;~m_st~0 := 0; 4086055#L526-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4085565#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4085566#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4086418#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4086031#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4085435#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4085220#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4085221#L561-1 assume !(0 == ~M_E~0); 4086712#L759-1 assume !(0 == ~T1_E~0); 4086174#L764-1 assume !(0 == ~T2_E~0); 4085755#L769-1 assume !(0 == ~T3_E~0); 4085155#L774-1 assume !(0 == ~T4_E~0); 4085156#L779-1 assume !(0 == ~T5_E~0); 4086551#L784-1 assume !(0 == ~T6_E~0); 4086142#L789-1 assume !(0 == ~T7_E~0); 4085323#L794-1 assume !(0 == ~E_M~0); 4085324#L799-1 assume !(0 == ~E_1~0); 4086658#L804-1 assume !(0 == ~E_2~0); 4086379#L809-1 assume !(0 == ~E_3~0); 4085939#L814-1 assume !(0 == ~E_4~0); 4085013#L819-1 assume !(0 == ~E_5~0); 4085014#L824-1 assume !(0 == ~E_6~0); 4086323#L829-1 assume !(0 == ~E_7~0); 4086069#L834-1 havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4086070#L366 assume !(1 == ~m_pc~0); 4086514#L366-2 is_master_triggered_~__retres1~0 := 0; 4085504#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4085127#L378 activate_threads_#t~ret10 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4085128#L945 assume !(0 != activate_threads_~tmp~1); 4085756#L945-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4085757#L385 assume !(1 == ~t1_pc~0); 4086456#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 4085892#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4085395#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4085396#L953 assume !(0 != activate_threads_~tmp___0~0); 4086812#L953-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4086813#L404 assume !(1 == ~t2_pc~0); 4086821#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 4086138#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4086056#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4086057#L961 assume !(0 != activate_threads_~tmp___1~0); 4086486#L961-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4085289#L423 assume !(1 == ~t3_pc~0); 4085290#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 4085299#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4086348#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4085825#L969 assume !(0 != activate_threads_~tmp___2~0); 4085826#L969-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4085322#L442 assume !(1 == ~t4_pc~0); 4085301#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 4085302#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4086421#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4086539#L977 assume !(0 != activate_threads_~tmp___3~0); 4086836#L977-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4085716#L461 assume !(1 == ~t5_pc~0); 4085717#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 4085720#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4086580#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4086385#L985 assume !(0 != activate_threads_~tmp___4~0); 4086386#L985-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4086032#L480 assume !(1 == ~t6_pc~0); 4086005#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 4086006#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4086791#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4085632#L993 assume !(0 != activate_threads_~tmp___5~0); 4085633#L993-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4085636#L499 assume !(1 == ~t7_pc~0); 4086281#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 4085114#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4085006#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4085007#L1001 assume !(0 != activate_threads_~tmp___6~0); 4086731#L1001-2 assume !(1 == ~M_E~0); 4086717#L847-1 assume !(1 == ~T1_E~0); 4086168#L852-1 assume !(1 == ~T2_E~0); 4085748#L857-1 assume !(1 == ~T3_E~0); 4085149#L862-1 assume !(1 == ~T4_E~0); 4085150#L867-1 assume !(1 == ~T5_E~0); 4086548#L872-1 assume !(1 == ~T6_E~0); 4085971#L877-1 assume !(1 == ~T7_E~0); 4085337#L882-1 assume !(1 == ~E_M~0); 4085338#L887-1 assume !(1 == ~E_1~0); 4086667#L892-1 assume !(1 == ~E_2~0); 4086393#L897-1 assume !(1 == ~E_3~0); 4085964#L902-1 assume !(1 == ~E_4~0); 4085040#L907-1 assume !(1 == ~E_5~0); 4085041#L912-1 assume !(1 == ~E_6~0); 4086316#L917-1 assume !(1 == ~E_7~0); 4086317#L1168-1 assume !false; 4256776#L1169 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 4425505#L734 [2018-12-08 18:44:34,536 INFO L796 eck$LassoCheckResult]: Loop: 4425505#L734 assume !false; 4425503#L627 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4425500#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4425498#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 4425496#L617 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4425494#L631 assume 0 != eval_~tmp~0; 4425492#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 4425489#L639 assume !(0 != eval_~tmp_ndt_1~0); 4425487#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 4425476#L653 assume !(0 != eval_~tmp_ndt_2~0); 4360638#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 4360622#L667 assume !(0 != eval_~tmp_ndt_3~0); 4360616#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 4360610#L681 assume !(0 != eval_~tmp_ndt_4~0); 4360611#L678 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 4439113#L695 assume !(0 != eval_~tmp_ndt_5~0); 4369041#L692 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 4369038#L709 assume !(0 != eval_~tmp_ndt_6~0); 4369035#L706 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 4369032#L723 assume !(0 != eval_~tmp_ndt_7~0); 4369033#L720 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 4425507#L737 assume !(0 != eval_~tmp_ndt_8~0); 4425505#L734 [2018-12-08 18:44:34,536 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:34,537 INFO L82 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 8 times [2018-12-08 18:44:34,537 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:34,537 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:34,537 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:34,537 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:34,537 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:34,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:34,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:34,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:34,550 INFO L82 PathProgramCache]: Analyzing trace with hash 256175173, now seen corresponding path program 1 times [2018-12-08 18:44:34,550 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:34,550 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:34,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:34,550 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-08 18:44:34,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:34,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:34,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:34,554 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 18:44:34,554 INFO L82 PathProgramCache]: Analyzing trace with hash 1418521831, now seen corresponding path program 1 times [2018-12-08 18:44:34,554 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 18:44:34,554 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 18:44:34,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:34,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 18:44:34,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 18:44:34,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:34,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 18:44:35,157 WARN L180 SmtUtils]: Spent 483.00 ms on a formula simplification. DAG size of input: 260 DAG size of output: 172 [2018-12-08 18:44:35,274 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification that was a NOOP. DAG size: 138 [2018-12-08 18:44:35,296 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 08.12 06:44:35 BoogieIcfgContainer [2018-12-08 18:44:35,296 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-12-08 18:44:35,297 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-08 18:44:35,297 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-08 18:44:35,297 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-08 18:44:35,297 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 06:43:42" (3/4) ... [2018-12-08 18:44:35,300 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-12-08 18:44:35,341 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_505afa25-d8c3-4df9-b0ad-002b49389af2/bin-2019/uautomizer/witness.graphml [2018-12-08 18:44:35,341 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-08 18:44:35,341 INFO L168 Benchmark]: Toolchain (without parser) took 53988.66 ms. Allocated memory was 1.0 GB in the beginning and 6.3 GB in the end (delta: 5.3 GB). Free memory was 956.0 MB in the beginning and 1.5 GB in the end (delta: -518.0 MB). Peak memory consumption was 4.8 GB. Max. memory is 11.5 GB. [2018-12-08 18:44:35,342 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-08 18:44:35,342 INFO L168 Benchmark]: CACSL2BoogieTranslator took 277.89 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 114.3 MB). Free memory was 956.0 MB in the beginning and 1.1 GB in the end (delta: -148.9 MB). Peak memory consumption was 36.5 MB. Max. memory is 11.5 GB. [2018-12-08 18:44:35,342 INFO L168 Benchmark]: Boogie Procedure Inliner took 48.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.3 MB). Peak memory consumption was 10.3 MB. Max. memory is 11.5 GB. [2018-12-08 18:44:35,343 INFO L168 Benchmark]: Boogie Preprocessor took 38.31 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. [2018-12-08 18:44:35,343 INFO L168 Benchmark]: RCFGBuilder took 825.31 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 923.3 MB in the end (delta: 157.6 MB). Peak memory consumption was 157.6 MB. Max. memory is 11.5 GB. [2018-12-08 18:44:35,343 INFO L168 Benchmark]: BuchiAutomizer took 52751.06 ms. Allocated memory was 1.1 GB in the beginning and 6.3 GB in the end (delta: 5.2 GB). Free memory was 923.3 MB in the beginning and 1.5 GB in the end (delta: -550.6 MB). Peak memory consumption was 4.6 GB. Max. memory is 11.5 GB. [2018-12-08 18:44:35,343 INFO L168 Benchmark]: Witness Printer took 44.21 ms. Allocated memory is still 6.3 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-08 18:44:35,345 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 277.89 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 114.3 MB). Free memory was 956.0 MB in the beginning and 1.1 GB in the end (delta: -148.9 MB). Peak memory consumption was 36.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 48.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.3 MB). Peak memory consumption was 10.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 38.31 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 825.31 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 923.3 MB in the end (delta: 157.6 MB). Peak memory consumption was 157.6 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 52751.06 ms. Allocated memory was 1.1 GB in the beginning and 6.3 GB in the end (delta: 5.2 GB). Free memory was 923.3 MB in the beginning and 1.5 GB in the end (delta: -550.6 MB). Peak memory consumption was 4.6 GB. Max. memory is 11.5 GB. * Witness Printer took 44.21 ms. Allocated memory is still 6.3 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 39 terminating modules (38 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_5 + 1 and consists of 3 locations. 38 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 844776 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 52.7s and 39 iterations. TraceHistogramMax:2. Analysis of lassos took 6.0s. Construction of modules took 1.0s. Büchi inclusion checks took 5.5s. Highest rank in rank-based complementation 3. Minimization of det autom 27. Minimization of nondet autom 12. Automata minimization 17.6s AutomataMinimizationTime, 39 MinimizatonAttempts, 70534 StatesRemovedByMinimization, 19 NontrivialMinimizations. Non-live state removal took 14.3s Buchi closure took 0.7s. Biggest automaton had 844776 states and ocurred in iteration 38. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 50464 SDtfs, 53672 SDslu, 42146 SDs, 0 SdLazy, 1333 SolverSat, 630 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time LassoAnalysisResults: nont1 unkn0 SFLI11 SFLT0 conc7 concLT1 SILN1 SILU0 SILI18 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital275 mio100 ax100 hnf100 lsp3 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 1ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 15 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 626]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, tmp_ndt_4=0, \result=0, m_st=0, t6_pc=0, tmp___2=0, __retres1=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t5_st=0, __retres1=1, E_2=2, t7_pc=0, tmp=0, M_E=2, tmp_ndt_3=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@40586aa=0, T4_E=2, t4_st=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7d4714e6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7d6b86a2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79539c67=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d926cfd=0, t5_pc=0, t7_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50a9a20=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@40af46f7=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@615082e9=0, tmp_ndt_7=0, tmp___3=0, t1_i=1, __retres1=0, token=0, T7_E=2, tmp=1, t2_st=0, t4_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6250f122=0, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, tmp___0=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@144867a9=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@605406d1=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5af3f473=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@83f074=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@77595513=0, tmp___0=0, t1_pc=0, E_4=2, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, m_i=1, t1_st=0, tmp_ndt_5=0, local=0, __retres1=0, t2_pc=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33e284e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@505589ed=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4023545a=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5a0b3ed9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34d8d284=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 626]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int t7_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int t3_i ; [L34] int t4_i ; [L35] int t5_i ; [L36] int t6_i ; [L37] int t7_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int T7_E = 2; [L46] int E_M = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L63] int token ; [L65] int local ; [L1213] int __retres1 ; [L1122] m_i = 1 [L1123] t1_i = 1 [L1124] t2_i = 1 [L1125] t3_i = 1 [L1126] t4_i = 1 [L1127] t5_i = 1 [L1128] t6_i = 1 [L1129] t7_i = 1 [L1154] int kernel_st ; [L1155] int tmp ; [L1156] int tmp___0 ; [L1160] kernel_st = 0 [L526] COND TRUE m_i == 1 [L527] m_st = 0 [L531] COND TRUE t1_i == 1 [L532] t1_st = 0 [L536] COND TRUE t2_i == 1 [L537] t2_st = 0 [L541] COND TRUE t3_i == 1 [L542] t3_st = 0 [L546] COND TRUE t4_i == 1 [L547] t4_st = 0 [L551] COND TRUE t5_i == 1 [L552] t5_st = 0 [L556] COND TRUE t6_i == 1 [L557] t6_st = 0 [L561] COND TRUE t7_i == 1 [L562] t7_st = 0 [L759] COND FALSE !(M_E == 0) [L764] COND FALSE !(T1_E == 0) [L769] COND FALSE !(T2_E == 0) [L774] COND FALSE !(T3_E == 0) [L779] COND FALSE !(T4_E == 0) [L784] COND FALSE !(T5_E == 0) [L789] COND FALSE !(T6_E == 0) [L794] COND FALSE !(T7_E == 0) [L799] COND FALSE !(E_M == 0) [L804] COND FALSE !(E_1 == 0) [L809] COND FALSE !(E_2 == 0) [L814] COND FALSE !(E_3 == 0) [L819] COND FALSE !(E_4 == 0) [L824] COND FALSE !(E_5 == 0) [L829] COND FALSE !(E_6 == 0) [L834] COND FALSE !(E_7 == 0) [L932] int tmp ; [L933] int tmp___0 ; [L934] int tmp___1 ; [L935] int tmp___2 ; [L936] int tmp___3 ; [L937] int tmp___4 ; [L938] int tmp___5 ; [L939] int tmp___6 ; [L363] int __retres1 ; [L366] COND FALSE !(m_pc == 1) [L376] __retres1 = 0 [L378] return (__retres1); [L943] tmp = is_master_triggered() [L945] COND FALSE !(\read(tmp)) [L382] int __retres1 ; [L385] COND FALSE !(t1_pc == 1) [L395] __retres1 = 0 [L397] return (__retres1); [L951] tmp___0 = is_transmit1_triggered() [L953] COND FALSE !(\read(tmp___0)) [L401] int __retres1 ; [L404] COND FALSE !(t2_pc == 1) [L414] __retres1 = 0 [L416] return (__retres1); [L959] tmp___1 = is_transmit2_triggered() [L961] COND FALSE !(\read(tmp___1)) [L420] int __retres1 ; [L423] COND FALSE !(t3_pc == 1) [L433] __retres1 = 0 [L435] return (__retres1); [L967] tmp___2 = is_transmit3_triggered() [L969] COND FALSE !(\read(tmp___2)) [L439] int __retres1 ; [L442] COND FALSE !(t4_pc == 1) [L452] __retres1 = 0 [L454] return (__retres1); [L975] tmp___3 = is_transmit4_triggered() [L977] COND FALSE !(\read(tmp___3)) [L458] int __retres1 ; [L461] COND FALSE !(t5_pc == 1) [L471] __retres1 = 0 [L473] return (__retres1); [L983] tmp___4 = is_transmit5_triggered() [L985] COND FALSE !(\read(tmp___4)) [L477] int __retres1 ; [L480] COND FALSE !(t6_pc == 1) [L490] __retres1 = 0 [L492] return (__retres1); [L991] tmp___5 = is_transmit6_triggered() [L993] COND FALSE !(\read(tmp___5)) [L496] int __retres1 ; [L499] COND FALSE !(t7_pc == 1) [L509] __retres1 = 0 [L511] return (__retres1); [L999] tmp___6 = is_transmit7_triggered() [L1001] COND FALSE !(\read(tmp___6)) [L847] COND FALSE !(M_E == 1) [L852] COND FALSE !(T1_E == 1) [L857] COND FALSE !(T2_E == 1) [L862] COND FALSE !(T3_E == 1) [L867] COND FALSE !(T4_E == 1) [L872] COND FALSE !(T5_E == 1) [L877] COND FALSE !(T6_E == 1) [L882] COND FALSE !(T7_E == 1) [L887] COND FALSE !(E_M == 1) [L892] COND FALSE !(E_1 == 1) [L897] COND FALSE !(E_2 == 1) [L902] COND FALSE !(E_3 == 1) [L907] COND FALSE !(E_4 == 1) [L912] COND FALSE !(E_5 == 1) [L917] COND FALSE !(E_6 == 1) [L922] COND FALSE !(E_7 == 1) [L1168] COND TRUE 1 [L1171] kernel_st = 1 [L622] int tmp ; Loop: [L626] COND TRUE 1 [L571] int __retres1 ; [L574] COND TRUE m_st == 0 [L575] __retres1 = 1 [L617] return (__retres1); [L629] tmp = exists_runnable_thread() [L631] COND TRUE \read(tmp) [L636] COND TRUE m_st == 0 [L637] int tmp_ndt_1; [L638] tmp_ndt_1 = __VERIFIER_nondet_int() [L639] COND FALSE !(\read(tmp_ndt_1)) [L650] COND TRUE t1_st == 0 [L651] int tmp_ndt_2; [L652] tmp_ndt_2 = __VERIFIER_nondet_int() [L653] COND FALSE !(\read(tmp_ndt_2)) [L664] COND TRUE t2_st == 0 [L665] int tmp_ndt_3; [L666] tmp_ndt_3 = __VERIFIER_nondet_int() [L667] COND FALSE !(\read(tmp_ndt_3)) [L678] COND TRUE t3_st == 0 [L679] int tmp_ndt_4; [L680] tmp_ndt_4 = __VERIFIER_nondet_int() [L681] COND FALSE !(\read(tmp_ndt_4)) [L692] COND TRUE t4_st == 0 [L693] int tmp_ndt_5; [L694] tmp_ndt_5 = __VERIFIER_nondet_int() [L695] COND FALSE !(\read(tmp_ndt_5)) [L706] COND TRUE t5_st == 0 [L707] int tmp_ndt_6; [L708] tmp_ndt_6 = __VERIFIER_nondet_int() [L709] COND FALSE !(\read(tmp_ndt_6)) [L720] COND TRUE t6_st == 0 [L721] int tmp_ndt_7; [L722] tmp_ndt_7 = __VERIFIER_nondet_int() [L723] COND FALSE !(\read(tmp_ndt_7)) [L734] COND TRUE t7_st == 0 [L735] int tmp_ndt_8; [L736] tmp_ndt_8 = __VERIFIER_nondet_int() [L737] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...