./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 532163d21d7e473fbfa4a073427e9fd2a45c7337 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-08 09:25:28,240 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-08 09:25:28,241 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-08 09:25:28,246 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-08 09:25:28,247 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-08 09:25:28,247 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-08 09:25:28,248 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-08 09:25:28,248 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-08 09:25:28,249 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-08 09:25:28,250 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-08 09:25:28,250 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-08 09:25:28,250 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-08 09:25:28,251 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-08 09:25:28,251 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-08 09:25:28,252 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-08 09:25:28,252 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-08 09:25:28,252 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-08 09:25:28,253 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-08 09:25:28,254 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-08 09:25:28,255 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-08 09:25:28,255 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-08 09:25:28,256 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-08 09:25:28,257 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-08 09:25:28,257 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-08 09:25:28,257 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-08 09:25:28,258 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-08 09:25:28,258 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-08 09:25:28,259 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-08 09:25:28,259 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-08 09:25:28,259 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-08 09:25:28,260 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-08 09:25:28,260 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-08 09:25:28,260 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-08 09:25:28,260 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-08 09:25:28,260 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-08 09:25:28,261 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-08 09:25:28,261 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-12-08 09:25:28,268 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-08 09:25:28,268 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-08 09:25:28,268 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-08 09:25:28,268 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-08 09:25:28,269 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-08 09:25:28,269 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-08 09:25:28,269 INFO L133 SettingsManager]: * Use SBE=true [2018-12-08 09:25:28,269 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-08 09:25:28,269 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-08 09:25:28,269 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-08 09:25:28,269 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-08 09:25:28,269 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-08 09:25:28,269 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-08 09:25:28,269 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-08 09:25:28,270 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-08 09:25:28,270 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-08 09:25:28,271 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-08 09:25:28,271 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-08 09:25:28,271 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-08 09:25:28,271 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-08 09:25:28,271 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-08 09:25:28,271 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-08 09:25:28,271 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 532163d21d7e473fbfa4a073427e9fd2a45c7337 [2018-12-08 09:25:28,289 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-08 09:25:28,298 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-08 09:25:28,300 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-08 09:25:28,301 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-08 09:25:28,301 INFO L276 PluginConnector]: CDTParser initialized [2018-12-08 09:25:28,302 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c [2018-12-08 09:25:28,337 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/data/e3b8b97dc/466ea79535b540b98c007f2a0541e62a/FLAGcc7d7e877 [2018-12-08 09:25:28,631 INFO L307 CDTParser]: Found 1 translation units. [2018-12-08 09:25:28,631 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/sv-benchmarks/c/systemc/kundu1_false-unreach-call_false-termination.cil.c [2018-12-08 09:25:28,636 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/data/e3b8b97dc/466ea79535b540b98c007f2a0541e62a/FLAGcc7d7e877 [2018-12-08 09:25:28,644 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/data/e3b8b97dc/466ea79535b540b98c007f2a0541e62a [2018-12-08 09:25:28,646 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-08 09:25:28,646 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-08 09:25:28,647 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-08 09:25:28,647 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-08 09:25:28,649 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-08 09:25:28,649 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,651 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6a86b9f0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28, skipping insertion in model container [2018-12-08 09:25:28,651 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,655 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-08 09:25:28,670 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-08 09:25:28,772 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-08 09:25:28,775 INFO L191 MainTranslator]: Completed pre-run [2018-12-08 09:25:28,795 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-08 09:25:28,805 INFO L195 MainTranslator]: Completed translation [2018-12-08 09:25:28,805 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28 WrapperNode [2018-12-08 09:25:28,805 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-08 09:25:28,805 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-08 09:25:28,806 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-08 09:25:28,806 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-08 09:25:28,810 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,815 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,849 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-08 09:25:28,849 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-08 09:25:28,849 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-08 09:25:28,849 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-08 09:25:28,854 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,855 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,856 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,856 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,863 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,869 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,871 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... [2018-12-08 09:25:28,873 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-08 09:25:28,873 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-08 09:25:28,874 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-08 09:25:28,874 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-08 09:25:28,874 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-08 09:25:28,909 INFO L130 BoogieDeclarations]: Found specification of procedure P_1 [2018-12-08 09:25:28,909 INFO L138 BoogieDeclarations]: Found implementation of procedure P_1 [2018-12-08 09:25:28,909 INFO L130 BoogieDeclarations]: Found specification of procedure write_data [2018-12-08 09:25:28,909 INFO L138 BoogieDeclarations]: Found implementation of procedure write_data [2018-12-08 09:25:28,909 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-08 09:25:28,909 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-08 09:25:28,910 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-08 09:25:28,910 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-08 09:25:28,910 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-08 09:25:28,910 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-08 09:25:28,910 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-08 09:25:28,910 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-08 09:25:28,910 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-08 09:25:28,910 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-08 09:25:28,910 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-08 09:25:28,910 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-08 09:25:28,910 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-08 09:25:28,910 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-08 09:25:28,910 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-08 09:25:28,910 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-08 09:25:28,911 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-08 09:25:28,911 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-08 09:25:28,911 INFO L130 BoogieDeclarations]: Found specification of procedure is_P_1_triggered [2018-12-08 09:25:28,911 INFO L138 BoogieDeclarations]: Found implementation of procedure is_P_1_triggered [2018-12-08 09:25:28,911 INFO L130 BoogieDeclarations]: Found specification of procedure read_data [2018-12-08 09:25:28,911 INFO L138 BoogieDeclarations]: Found implementation of procedure read_data [2018-12-08 09:25:28,911 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-08 09:25:28,911 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-08 09:25:28,911 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-08 09:25:28,911 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-08 09:25:28,911 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-08 09:25:28,911 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-08 09:25:28,911 INFO L130 BoogieDeclarations]: Found specification of procedure C_1 [2018-12-08 09:25:28,911 INFO L138 BoogieDeclarations]: Found implementation of procedure C_1 [2018-12-08 09:25:28,912 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-08 09:25:28,912 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-08 09:25:28,912 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-08 09:25:28,912 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-08 09:25:28,912 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-08 09:25:28,912 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-08 09:25:28,912 INFO L130 BoogieDeclarations]: Found specification of procedure is_C_1_triggered [2018-12-08 09:25:28,912 INFO L138 BoogieDeclarations]: Found implementation of procedure is_C_1_triggered [2018-12-08 09:25:28,912 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-08 09:25:28,912 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-08 09:25:29,150 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-08 09:25:29,150 INFO L280 CfgBuilder]: Removed 4 assue(true) statements. [2018-12-08 09:25:29,150 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 09:25:29 BoogieIcfgContainer [2018-12-08 09:25:29,150 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-08 09:25:29,151 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-08 09:25:29,151 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-08 09:25:29,152 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-08 09:25:29,153 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 08.12 09:25:28" (1/3) ... [2018-12-08 09:25:29,153 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@78475d8e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.12 09:25:29, skipping insertion in model container [2018-12-08 09:25:29,153 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:25:28" (2/3) ... [2018-12-08 09:25:29,153 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@78475d8e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.12 09:25:29, skipping insertion in model container [2018-12-08 09:25:29,153 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 09:25:29" (3/3) ... [2018-12-08 09:25:29,154 INFO L112 eAbstractionObserver]: Analyzing ICFG kundu1_false-unreach-call_false-termination.cil.c [2018-12-08 09:25:29,160 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-08 09:25:29,165 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-08 09:25:29,174 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-08 09:25:29,193 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-08 09:25:29,193 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-08 09:25:29,193 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-08 09:25:29,193 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-08 09:25:29,193 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-08 09:25:29,193 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-08 09:25:29,193 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-08 09:25:29,193 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-08 09:25:29,193 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-08 09:25:29,206 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states. [2018-12-08 09:25:29,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-08 09:25:29,211 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:29,211 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:29,213 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:29,216 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:29,216 INFO L82 PathProgramCache]: Analyzing trace with hash -1385664965, now seen corresponding path program 1 times [2018-12-08 09:25:29,217 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:29,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:29,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:29,245 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:29,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:29,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:29,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:29,348 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:29,348 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:25:29,351 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:25:29,358 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:25:29,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:29,360 INFO L87 Difference]: Start difference. First operand 150 states. Second operand 4 states. [2018-12-08 09:25:29,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:29,453 INFO L93 Difference]: Finished difference Result 282 states and 384 transitions. [2018-12-08 09:25:29,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:25:29,455 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2018-12-08 09:25:29,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:29,462 INFO L225 Difference]: With dead ends: 282 [2018-12-08 09:25:29,462 INFO L226 Difference]: Without dead ends: 140 [2018-12-08 09:25:29,464 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:29,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-12-08 09:25:29,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-12-08 09:25:29,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-12-08 09:25:29,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 179 transitions. [2018-12-08 09:25:29,495 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 179 transitions. Word has length 72 [2018-12-08 09:25:29,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:29,496 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 179 transitions. [2018-12-08 09:25:29,496 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:25:29,497 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 179 transitions. [2018-12-08 09:25:29,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-08 09:25:29,498 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:29,498 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:29,499 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:29,499 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:29,499 INFO L82 PathProgramCache]: Analyzing trace with hash -1426339715, now seen corresponding path program 1 times [2018-12-08 09:25:29,499 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:29,499 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:29,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:29,500 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:29,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:29,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:29,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:29,560 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:29,560 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:25:29,561 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:25:29,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:25:29,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:29,561 INFO L87 Difference]: Start difference. First operand 140 states and 179 transitions. Second operand 4 states. [2018-12-08 09:25:29,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:29,683 INFO L93 Difference]: Finished difference Result 373 states and 490 transitions. [2018-12-08 09:25:29,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:25:29,683 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2018-12-08 09:25:29,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:29,685 INFO L225 Difference]: With dead ends: 373 [2018-12-08 09:25:29,685 INFO L226 Difference]: Without dead ends: 253 [2018-12-08 09:25:29,686 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:29,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states. [2018-12-08 09:25:29,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 238. [2018-12-08 09:25:29,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-12-08 09:25:29,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 301 transitions. [2018-12-08 09:25:29,705 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 301 transitions. Word has length 72 [2018-12-08 09:25:29,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:29,706 INFO L480 AbstractCegarLoop]: Abstraction has 238 states and 301 transitions. [2018-12-08 09:25:29,706 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:25:29,706 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 301 transitions. [2018-12-08 09:25:29,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-08 09:25:29,707 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:29,707 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:29,707 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:29,707 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:29,707 INFO L82 PathProgramCache]: Analyzing trace with hash 1691683492, now seen corresponding path program 1 times [2018-12-08 09:25:29,708 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:29,708 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:29,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:29,708 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:29,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:29,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:29,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:29,759 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:29,759 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:25:29,760 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:25:29,760 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:25:29,760 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:29,760 INFO L87 Difference]: Start difference. First operand 238 states and 301 transitions. Second operand 4 states. [2018-12-08 09:25:29,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:29,891 INFO L93 Difference]: Finished difference Result 573 states and 746 transitions. [2018-12-08 09:25:29,892 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:25:29,892 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2018-12-08 09:25:29,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:29,895 INFO L225 Difference]: With dead ends: 573 [2018-12-08 09:25:29,895 INFO L226 Difference]: Without dead ends: 355 [2018-12-08 09:25:29,897 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:29,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355 states. [2018-12-08 09:25:29,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355 to 339. [2018-12-08 09:25:29,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 339 states. [2018-12-08 09:25:29,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 339 states to 339 states and 428 transitions. [2018-12-08 09:25:29,921 INFO L78 Accepts]: Start accepts. Automaton has 339 states and 428 transitions. Word has length 73 [2018-12-08 09:25:29,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:29,922 INFO L480 AbstractCegarLoop]: Abstraction has 339 states and 428 transitions. [2018-12-08 09:25:29,922 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:25:29,922 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 428 transitions. [2018-12-08 09:25:29,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-08 09:25:29,923 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:29,924 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:29,924 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:29,924 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:29,924 INFO L82 PathProgramCache]: Analyzing trace with hash -73133117, now seen corresponding path program 1 times [2018-12-08 09:25:29,924 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:29,924 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:29,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:29,925 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:29,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:29,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:29,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:29,993 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:29,993 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 09:25:29,993 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:25:29,993 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:25:29,993 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:25:29,993 INFO L87 Difference]: Start difference. First operand 339 states and 428 transitions. Second operand 6 states. [2018-12-08 09:25:30,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:30,056 INFO L93 Difference]: Finished difference Result 688 states and 882 transitions. [2018-12-08 09:25:30,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 09:25:30,056 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-08 09:25:30,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:30,059 INFO L225 Difference]: With dead ends: 688 [2018-12-08 09:25:30,059 INFO L226 Difference]: Without dead ends: 369 [2018-12-08 09:25:30,060 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-08 09:25:30,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 369 states. [2018-12-08 09:25:30,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 354. [2018-12-08 09:25:30,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2018-12-08 09:25:30,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 443 transitions. [2018-12-08 09:25:30,085 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 443 transitions. Word has length 73 [2018-12-08 09:25:30,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:30,086 INFO L480 AbstractCegarLoop]: Abstraction has 354 states and 443 transitions. [2018-12-08 09:25:30,086 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:25:30,086 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 443 transitions. [2018-12-08 09:25:30,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-08 09:25:30,087 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:30,087 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:30,088 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:30,088 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:30,088 INFO L82 PathProgramCache]: Analyzing trace with hash -1444940415, now seen corresponding path program 1 times [2018-12-08 09:25:30,088 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:30,088 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:30,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:30,089 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:30,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:30,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:30,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:30,158 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:30,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 09:25:30,158 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:25:30,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:25:30,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:25:30,158 INFO L87 Difference]: Start difference. First operand 354 states and 443 transitions. Second operand 6 states. [2018-12-08 09:25:30,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:30,198 INFO L93 Difference]: Finished difference Result 702 states and 887 transitions. [2018-12-08 09:25:30,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-08 09:25:30,198 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-08 09:25:30,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:30,200 INFO L225 Difference]: With dead ends: 702 [2018-12-08 09:25:30,200 INFO L226 Difference]: Without dead ends: 368 [2018-12-08 09:25:30,201 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-08 09:25:30,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states. [2018-12-08 09:25:30,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 364. [2018-12-08 09:25:30,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2018-12-08 09:25:30,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 452 transitions. [2018-12-08 09:25:30,216 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 452 transitions. Word has length 73 [2018-12-08 09:25:30,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:30,216 INFO L480 AbstractCegarLoop]: Abstraction has 364 states and 452 transitions. [2018-12-08 09:25:30,217 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:25:30,217 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 452 transitions. [2018-12-08 09:25:30,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-08 09:25:30,218 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:30,218 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:30,218 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:30,218 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:30,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1422308161, now seen corresponding path program 1 times [2018-12-08 09:25:30,219 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:30,219 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:30,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:30,220 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:30,220 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:30,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:30,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:30,278 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:30,278 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 09:25:30,278 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:25:30,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:25:30,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:25:30,278 INFO L87 Difference]: Start difference. First operand 364 states and 452 transitions. Second operand 6 states. [2018-12-08 09:25:30,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:30,359 INFO L93 Difference]: Finished difference Result 926 states and 1173 transitions. [2018-12-08 09:25:30,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-08 09:25:30,359 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-12-08 09:25:30,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:30,361 INFO L225 Difference]: With dead ends: 926 [2018-12-08 09:25:30,361 INFO L226 Difference]: Without dead ends: 583 [2018-12-08 09:25:30,362 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-08 09:25:30,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states. [2018-12-08 09:25:30,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 570. [2018-12-08 09:25:30,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 570 states. [2018-12-08 09:25:30,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 570 states to 570 states and 714 transitions. [2018-12-08 09:25:30,381 INFO L78 Accepts]: Start accepts. Automaton has 570 states and 714 transitions. Word has length 73 [2018-12-08 09:25:30,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:30,381 INFO L480 AbstractCegarLoop]: Abstraction has 570 states and 714 transitions. [2018-12-08 09:25:30,381 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:25:30,381 INFO L276 IsEmpty]: Start isEmpty. Operand 570 states and 714 transitions. [2018-12-08 09:25:30,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-08 09:25:30,382 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:30,382 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:30,382 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:30,382 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:30,382 INFO L82 PathProgramCache]: Analyzing trace with hash -1577822909, now seen corresponding path program 1 times [2018-12-08 09:25:30,382 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:30,382 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:30,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:30,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:30,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:30,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:30,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:30,430 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:30,431 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 09:25:30,431 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:25:30,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:25:30,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:25:30,431 INFO L87 Difference]: Start difference. First operand 570 states and 714 transitions. Second operand 6 states. [2018-12-08 09:25:30,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:30,873 INFO L93 Difference]: Finished difference Result 1162 states and 1558 transitions. [2018-12-08 09:25:30,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-08 09:25:30,873 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 86 [2018-12-08 09:25:30,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:30,876 INFO L225 Difference]: With dead ends: 1162 [2018-12-08 09:25:30,876 INFO L226 Difference]: Without dead ends: 824 [2018-12-08 09:25:30,877 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2018-12-08 09:25:30,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 824 states. [2018-12-08 09:25:30,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 824 to 771. [2018-12-08 09:25:30,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 771 states. [2018-12-08 09:25:30,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 771 states and 1019 transitions. [2018-12-08 09:25:30,905 INFO L78 Accepts]: Start accepts. Automaton has 771 states and 1019 transitions. Word has length 86 [2018-12-08 09:25:30,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:30,906 INFO L480 AbstractCegarLoop]: Abstraction has 771 states and 1019 transitions. [2018-12-08 09:25:30,906 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:25:30,906 INFO L276 IsEmpty]: Start isEmpty. Operand 771 states and 1019 transitions. [2018-12-08 09:25:30,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-08 09:25:30,906 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:30,907 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:30,907 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:30,907 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:30,907 INFO L82 PathProgramCache]: Analyzing trace with hash -627422246, now seen corresponding path program 1 times [2018-12-08 09:25:30,907 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:30,907 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:30,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:30,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:30,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:30,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:30,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:30,985 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:30,985 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-12-08 09:25:30,985 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-08 09:25:30,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-08 09:25:30,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:25:30,986 INFO L87 Difference]: Start difference. First operand 771 states and 1019 transitions. Second operand 8 states. [2018-12-08 09:25:31,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:31,764 INFO L93 Difference]: Finished difference Result 1991 states and 2867 transitions. [2018-12-08 09:25:31,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-12-08 09:25:31,764 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 90 [2018-12-08 09:25:31,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:31,771 INFO L225 Difference]: With dead ends: 1991 [2018-12-08 09:25:31,771 INFO L226 Difference]: Without dead ends: 1466 [2018-12-08 09:25:31,774 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=44, Invalid=138, Unknown=0, NotChecked=0, Total=182 [2018-12-08 09:25:31,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2018-12-08 09:25:31,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1355. [2018-12-08 09:25:31,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1355 states. [2018-12-08 09:25:31,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1882 transitions. [2018-12-08 09:25:31,830 INFO L78 Accepts]: Start accepts. Automaton has 1355 states and 1882 transitions. Word has length 90 [2018-12-08 09:25:31,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:31,831 INFO L480 AbstractCegarLoop]: Abstraction has 1355 states and 1882 transitions. [2018-12-08 09:25:31,831 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-08 09:25:31,831 INFO L276 IsEmpty]: Start isEmpty. Operand 1355 states and 1882 transitions. [2018-12-08 09:25:31,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-12-08 09:25:31,831 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:31,832 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:31,832 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:31,832 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:31,832 INFO L82 PathProgramCache]: Analyzing trace with hash 1334723078, now seen corresponding path program 1 times [2018-12-08 09:25:31,832 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:31,832 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:31,833 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:31,833 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:31,833 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:31,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:31,850 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-08 09:25:31,850 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:31,850 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:31,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:31,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:31,906 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:31,933 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-08 09:25:31,958 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:25:31,958 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 3 [2018-12-08 09:25:31,959 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 09:25:31,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 09:25:31,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:25:31,959 INFO L87 Difference]: Start difference. First operand 1355 states and 1882 transitions. Second operand 3 states. [2018-12-08 09:25:32,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:32,088 INFO L93 Difference]: Finished difference Result 3840 states and 5897 transitions. [2018-12-08 09:25:32,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 09:25:32,089 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 92 [2018-12-08 09:25:32,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:32,097 INFO L225 Difference]: With dead ends: 3840 [2018-12-08 09:25:32,097 INFO L226 Difference]: Without dead ends: 2506 [2018-12-08 09:25:32,102 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 92 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:25:32,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2506 states. [2018-12-08 09:25:32,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2506 to 2502. [2018-12-08 09:25:32,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2502 states. [2018-12-08 09:25:32,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2502 states to 2502 states and 3704 transitions. [2018-12-08 09:25:32,196 INFO L78 Accepts]: Start accepts. Automaton has 2502 states and 3704 transitions. Word has length 92 [2018-12-08 09:25:32,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:32,196 INFO L480 AbstractCegarLoop]: Abstraction has 2502 states and 3704 transitions. [2018-12-08 09:25:32,196 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 09:25:32,196 INFO L276 IsEmpty]: Start isEmpty. Operand 2502 states and 3704 transitions. [2018-12-08 09:25:32,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-12-08 09:25:32,197 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:32,197 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:32,197 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:32,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:32,197 INFO L82 PathProgramCache]: Analyzing trace with hash -1839079452, now seen corresponding path program 1 times [2018-12-08 09:25:32,198 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:32,198 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:32,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:32,198 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:32,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:32,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:32,250 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-12-08 09:25:32,251 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:32,251 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:32,258 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:32,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:32,300 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:32,319 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:32,344 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:25:32,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-12-08 09:25:32,344 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-08 09:25:32,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-08 09:25:32,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-12-08 09:25:32,345 INFO L87 Difference]: Start difference. First operand 2502 states and 3704 transitions. Second operand 9 states. [2018-12-08 09:25:33,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:33,377 INFO L93 Difference]: Finished difference Result 6390 states and 10750 transitions. [2018-12-08 09:25:33,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-12-08 09:25:33,377 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 96 [2018-12-08 09:25:33,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:33,390 INFO L225 Difference]: With dead ends: 6390 [2018-12-08 09:25:33,391 INFO L226 Difference]: Without dead ends: 3909 [2018-12-08 09:25:33,406 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 105 SyntacticMatches, 3 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=90, Invalid=252, Unknown=0, NotChecked=0, Total=342 [2018-12-08 09:25:33,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3909 states. [2018-12-08 09:25:33,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3909 to 3843. [2018-12-08 09:25:33,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3843 states. [2018-12-08 09:25:33,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3843 states to 3843 states and 5464 transitions. [2018-12-08 09:25:33,551 INFO L78 Accepts]: Start accepts. Automaton has 3843 states and 5464 transitions. Word has length 96 [2018-12-08 09:25:33,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:33,551 INFO L480 AbstractCegarLoop]: Abstraction has 3843 states and 5464 transitions. [2018-12-08 09:25:33,551 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-08 09:25:33,551 INFO L276 IsEmpty]: Start isEmpty. Operand 3843 states and 5464 transitions. [2018-12-08 09:25:33,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-12-08 09:25:33,552 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:33,552 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:33,552 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:33,552 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:33,552 INFO L82 PathProgramCache]: Analyzing trace with hash -758498226, now seen corresponding path program 1 times [2018-12-08 09:25:33,552 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:33,553 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:33,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:33,553 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:33,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:33,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:33,619 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-08 09:25:33,620 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:33,620 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:33,626 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:33,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:33,668 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:33,692 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:25:33,708 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:25:33,708 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-12-08 09:25:33,708 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-08 09:25:33,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-08 09:25:33,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:25:33,708 INFO L87 Difference]: Start difference. First operand 3843 states and 5464 transitions. Second operand 8 states. [2018-12-08 09:25:35,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:35,438 INFO L93 Difference]: Finished difference Result 17414 states and 28965 transitions. [2018-12-08 09:25:35,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-12-08 09:25:35,439 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 94 [2018-12-08 09:25:35,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:35,498 INFO L225 Difference]: With dead ends: 17414 [2018-12-08 09:25:35,498 INFO L226 Difference]: Without dead ends: 12986 [2018-12-08 09:25:35,533 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=146, Invalid=360, Unknown=0, NotChecked=0, Total=506 [2018-12-08 09:25:35,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12986 states. [2018-12-08 09:25:36,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12986 to 10564. [2018-12-08 09:25:36,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10564 states. [2018-12-08 09:25:36,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10564 states to 10564 states and 14050 transitions. [2018-12-08 09:25:36,074 INFO L78 Accepts]: Start accepts. Automaton has 10564 states and 14050 transitions. Word has length 94 [2018-12-08 09:25:36,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:36,074 INFO L480 AbstractCegarLoop]: Abstraction has 10564 states and 14050 transitions. [2018-12-08 09:25:36,074 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-08 09:25:36,074 INFO L276 IsEmpty]: Start isEmpty. Operand 10564 states and 14050 transitions. [2018-12-08 09:25:36,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 166 [2018-12-08 09:25:36,081 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:36,081 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:36,082 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:36,082 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:36,082 INFO L82 PathProgramCache]: Analyzing trace with hash -100635213, now seen corresponding path program 1 times [2018-12-08 09:25:36,082 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:36,082 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:36,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:36,083 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:36,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:36,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:36,130 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 19 proven. 20 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-12-08 09:25:36,130 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:36,130 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:36,137 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:36,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:36,186 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:36,222 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 58 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-12-08 09:25:36,237 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:25:36,238 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-12-08 09:25:36,238 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-08 09:25:36,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-08 09:25:36,238 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-12-08 09:25:36,238 INFO L87 Difference]: Start difference. First operand 10564 states and 14050 transitions. Second operand 9 states. [2018-12-08 09:25:36,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:36,593 INFO L93 Difference]: Finished difference Result 17912 states and 23709 transitions. [2018-12-08 09:25:36,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-08 09:25:36,594 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 165 [2018-12-08 09:25:36,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:36,620 INFO L225 Difference]: With dead ends: 17912 [2018-12-08 09:25:36,620 INFO L226 Difference]: Without dead ends: 6739 [2018-12-08 09:25:36,636 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 168 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2018-12-08 09:25:36,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6739 states. [2018-12-08 09:25:36,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6739 to 6213. [2018-12-08 09:25:36,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6213 states. [2018-12-08 09:25:36,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6213 states to 6213 states and 7934 transitions. [2018-12-08 09:25:36,862 INFO L78 Accepts]: Start accepts. Automaton has 6213 states and 7934 transitions. Word has length 165 [2018-12-08 09:25:36,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:36,863 INFO L480 AbstractCegarLoop]: Abstraction has 6213 states and 7934 transitions. [2018-12-08 09:25:36,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-08 09:25:36,863 INFO L276 IsEmpty]: Start isEmpty. Operand 6213 states and 7934 transitions. [2018-12-08 09:25:36,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2018-12-08 09:25:36,870 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:36,870 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:36,870 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:36,870 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:36,870 INFO L82 PathProgramCache]: Analyzing trace with hash 402763591, now seen corresponding path program 1 times [2018-12-08 09:25:36,870 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:36,870 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:36,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:36,871 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:36,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:36,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:36,932 INFO L134 CoverageAnalysis]: Checked inductivity of 101 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-12-08 09:25:36,932 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:36,932 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:25:36,932 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:25:36,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:25:36,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:36,933 INFO L87 Difference]: Start difference. First operand 6213 states and 7934 transitions. Second operand 4 states. [2018-12-08 09:25:37,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:37,239 INFO L93 Difference]: Finished difference Result 12260 states and 15721 transitions. [2018-12-08 09:25:37,240 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:25:37,240 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 169 [2018-12-08 09:25:37,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:37,294 INFO L225 Difference]: With dead ends: 12260 [2018-12-08 09:25:37,294 INFO L226 Difference]: Without dead ends: 6088 [2018-12-08 09:25:37,300 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:37,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6088 states. [2018-12-08 09:25:37,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6088 to 5481. [2018-12-08 09:25:37,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5481 states. [2018-12-08 09:25:37,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5481 states to 5481 states and 6710 transitions. [2018-12-08 09:25:37,486 INFO L78 Accepts]: Start accepts. Automaton has 5481 states and 6710 transitions. Word has length 169 [2018-12-08 09:25:37,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:37,486 INFO L480 AbstractCegarLoop]: Abstraction has 5481 states and 6710 transitions. [2018-12-08 09:25:37,486 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:25:37,486 INFO L276 IsEmpty]: Start isEmpty. Operand 5481 states and 6710 transitions. [2018-12-08 09:25:37,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-12-08 09:25:37,490 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:37,490 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:37,490 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:37,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:37,491 INFO L82 PathProgramCache]: Analyzing trace with hash 1136140360, now seen corresponding path program 1 times [2018-12-08 09:25:37,491 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:37,491 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:37,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:37,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:37,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:37,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:37,536 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 20 proven. 25 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-12-08 09:25:37,536 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:37,536 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:37,542 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:37,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:37,607 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:37,631 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 113 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-12-08 09:25:37,647 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:25:37,648 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-08 09:25:37,648 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:25:37,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:25:37,649 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:25:37,649 INFO L87 Difference]: Start difference. First operand 5481 states and 6710 transitions. Second operand 6 states. [2018-12-08 09:25:38,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:38,069 INFO L93 Difference]: Finished difference Result 9933 states and 12602 transitions. [2018-12-08 09:25:38,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-08 09:25:38,069 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 203 [2018-12-08 09:25:38,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:38,077 INFO L225 Difference]: With dead ends: 9933 [2018-12-08 09:25:38,077 INFO L226 Difference]: Without dead ends: 4123 [2018-12-08 09:25:38,082 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 207 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:25:38,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4123 states. [2018-12-08 09:25:38,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4123 to 3548. [2018-12-08 09:25:38,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3548 states. [2018-12-08 09:25:38,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3548 states to 3548 states and 4079 transitions. [2018-12-08 09:25:38,215 INFO L78 Accepts]: Start accepts. Automaton has 3548 states and 4079 transitions. Word has length 203 [2018-12-08 09:25:38,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:38,215 INFO L480 AbstractCegarLoop]: Abstraction has 3548 states and 4079 transitions. [2018-12-08 09:25:38,215 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:25:38,215 INFO L276 IsEmpty]: Start isEmpty. Operand 3548 states and 4079 transitions. [2018-12-08 09:25:38,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-12-08 09:25:38,217 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:38,217 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:38,218 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:38,218 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:38,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1452973386, now seen corresponding path program 1 times [2018-12-08 09:25:38,218 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:38,218 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:38,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:38,218 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:38,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:38,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:38,269 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-12-08 09:25:38,270 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:38,270 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 09:25:38,270 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-08 09:25:38,271 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 09:25:38,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:25:38,271 INFO L87 Difference]: Start difference. First operand 3548 states and 4079 transitions. Second operand 5 states. [2018-12-08 09:25:38,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:38,921 INFO L93 Difference]: Finished difference Result 8189 states and 10045 transitions. [2018-12-08 09:25:38,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-08 09:25:38,921 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 204 [2018-12-08 09:25:38,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:38,932 INFO L225 Difference]: With dead ends: 8189 [2018-12-08 09:25:38,933 INFO L226 Difference]: Without dead ends: 4905 [2018-12-08 09:25:38,937 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:25:38,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4905 states. [2018-12-08 09:25:39,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4905 to 4220. [2018-12-08 09:25:39,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4220 states. [2018-12-08 09:25:39,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4220 states to 4220 states and 4827 transitions. [2018-12-08 09:25:39,123 INFO L78 Accepts]: Start accepts. Automaton has 4220 states and 4827 transitions. Word has length 204 [2018-12-08 09:25:39,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:39,123 INFO L480 AbstractCegarLoop]: Abstraction has 4220 states and 4827 transitions. [2018-12-08 09:25:39,123 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-08 09:25:39,123 INFO L276 IsEmpty]: Start isEmpty. Operand 4220 states and 4827 transitions. [2018-12-08 09:25:39,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-12-08 09:25:39,126 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:39,126 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:39,127 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:39,127 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:39,127 INFO L82 PathProgramCache]: Analyzing trace with hash -555580108, now seen corresponding path program 1 times [2018-12-08 09:25:39,127 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:39,127 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:39,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:39,128 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:39,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:39,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:39,291 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 122 trivial. 0 not checked. [2018-12-08 09:25:39,291 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:39,291 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:39,297 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:39,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:39,351 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:39,400 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 109 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-12-08 09:25:39,415 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:25:39,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2018-12-08 09:25:39,416 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-08 09:25:39,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-08 09:25:39,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2018-12-08 09:25:39,416 INFO L87 Difference]: Start difference. First operand 4220 states and 4827 transitions. Second operand 12 states. [2018-12-08 09:25:40,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:40,856 INFO L93 Difference]: Finished difference Result 7056 states and 8192 transitions. [2018-12-08 09:25:40,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-12-08 09:25:40,856 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 204 [2018-12-08 09:25:40,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:40,862 INFO L225 Difference]: With dead ends: 7056 [2018-12-08 09:25:40,862 INFO L226 Difference]: Without dead ends: 3280 [2018-12-08 09:25:40,867 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 224 SyntacticMatches, 3 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=319, Invalid=1487, Unknown=0, NotChecked=0, Total=1806 [2018-12-08 09:25:40,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3280 states. [2018-12-08 09:25:41,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3280 to 3149. [2018-12-08 09:25:41,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3149 states. [2018-12-08 09:25:41,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3149 states to 3149 states and 3558 transitions. [2018-12-08 09:25:41,041 INFO L78 Accepts]: Start accepts. Automaton has 3149 states and 3558 transitions. Word has length 204 [2018-12-08 09:25:41,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:41,041 INFO L480 AbstractCegarLoop]: Abstraction has 3149 states and 3558 transitions. [2018-12-08 09:25:41,041 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-08 09:25:41,041 INFO L276 IsEmpty]: Start isEmpty. Operand 3149 states and 3558 transitions. [2018-12-08 09:25:41,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-12-08 09:25:41,044 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:41,044 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:41,044 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:41,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:41,044 INFO L82 PathProgramCache]: Analyzing trace with hash -1958697263, now seen corresponding path program 1 times [2018-12-08 09:25:41,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:41,045 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:41,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:41,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:41,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:41,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:41,105 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 27 proven. 7 refuted. 0 times theorem prover too weak. 110 trivial. 0 not checked. [2018-12-08 09:25:41,106 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:41,106 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:41,112 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:41,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:41,174 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:41,212 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 95 proven. 0 refuted. 0 times theorem prover too weak. 49 trivial. 0 not checked. [2018-12-08 09:25:41,228 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:25:41,228 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-12-08 09:25:41,229 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-08 09:25:41,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 09:25:41,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:25:41,229 INFO L87 Difference]: Start difference. First operand 3149 states and 3558 transitions. Second operand 5 states. [2018-12-08 09:25:41,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:41,438 INFO L93 Difference]: Finished difference Result 5104 states and 5780 transitions. [2018-12-08 09:25:41,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-08 09:25:41,438 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 221 [2018-12-08 09:25:41,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:41,442 INFO L225 Difference]: With dead ends: 5104 [2018-12-08 09:25:41,442 INFO L226 Difference]: Without dead ends: 2586 [2018-12-08 09:25:41,445 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 226 GetRequests, 222 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:25:41,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2586 states. [2018-12-08 09:25:41,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2586 to 2542. [2018-12-08 09:25:41,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2542 states. [2018-12-08 09:25:41,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2542 states to 2542 states and 2849 transitions. [2018-12-08 09:25:41,556 INFO L78 Accepts]: Start accepts. Automaton has 2542 states and 2849 transitions. Word has length 221 [2018-12-08 09:25:41,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:41,556 INFO L480 AbstractCegarLoop]: Abstraction has 2542 states and 2849 transitions. [2018-12-08 09:25:41,556 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-08 09:25:41,557 INFO L276 IsEmpty]: Start isEmpty. Operand 2542 states and 2849 transitions. [2018-12-08 09:25:41,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-12-08 09:25:41,558 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:41,558 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:41,558 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:41,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:41,558 INFO L82 PathProgramCache]: Analyzing trace with hash 1743806793, now seen corresponding path program 1 times [2018-12-08 09:25:41,558 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:41,558 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:41,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:41,559 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:41,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:41,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:41,676 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 5 proven. 19 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2018-12-08 09:25:41,676 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:41,676 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:41,681 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:41,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:41,733 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:41,811 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 33 proven. 15 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2018-12-08 09:25:41,825 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-08 09:25:41,826 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8] total 14 [2018-12-08 09:25:41,826 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-08 09:25:41,826 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-08 09:25:41,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2018-12-08 09:25:41,826 INFO L87 Difference]: Start difference. First operand 2542 states and 2849 transitions. Second operand 14 states. [2018-12-08 09:25:43,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:43,287 INFO L93 Difference]: Finished difference Result 5968 states and 7149 transitions. [2018-12-08 09:25:43,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-12-08 09:25:43,287 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 222 [2018-12-08 09:25:43,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:43,295 INFO L225 Difference]: With dead ends: 5968 [2018-12-08 09:25:43,296 INFO L226 Difference]: Without dead ends: 4198 [2018-12-08 09:25:43,298 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 222 SyntacticMatches, 9 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=158, Invalid=598, Unknown=0, NotChecked=0, Total=756 [2018-12-08 09:25:43,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4198 states. [2018-12-08 09:25:43,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4198 to 3664. [2018-12-08 09:25:43,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3664 states. [2018-12-08 09:25:43,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3664 states to 3664 states and 4246 transitions. [2018-12-08 09:25:43,478 INFO L78 Accepts]: Start accepts. Automaton has 3664 states and 4246 transitions. Word has length 222 [2018-12-08 09:25:43,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:43,479 INFO L480 AbstractCegarLoop]: Abstraction has 3664 states and 4246 transitions. [2018-12-08 09:25:43,479 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-08 09:25:43,479 INFO L276 IsEmpty]: Start isEmpty. Operand 3664 states and 4246 transitions. [2018-12-08 09:25:43,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2018-12-08 09:25:43,481 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:43,482 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:43,482 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:43,482 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:43,482 INFO L82 PathProgramCache]: Analyzing trace with hash -1527898798, now seen corresponding path program 1 times [2018-12-08 09:25:43,482 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:43,482 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:43,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:43,483 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:43,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:43,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:43,534 INFO L134 CoverageAnalysis]: Checked inductivity of 538 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 502 trivial. 0 not checked. [2018-12-08 09:25:43,534 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:25:43,534 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:25:43,534 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:25:43,534 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:25:43,534 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:43,535 INFO L87 Difference]: Start difference. First operand 3664 states and 4246 transitions. Second operand 4 states. [2018-12-08 09:25:43,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:43,753 INFO L93 Difference]: Finished difference Result 4068 states and 4681 transitions. [2018-12-08 09:25:43,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:25:43,753 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 336 [2018-12-08 09:25:43,753 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:43,758 INFO L225 Difference]: With dead ends: 4068 [2018-12-08 09:25:43,758 INFO L226 Difference]: Without dead ends: 3613 [2018-12-08 09:25:43,760 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:25:43,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3613 states. [2018-12-08 09:25:43,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3613 to 3613. [2018-12-08 09:25:43,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3613 states. [2018-12-08 09:25:43,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3613 states to 3613 states and 4189 transitions. [2018-12-08 09:25:43,934 INFO L78 Accepts]: Start accepts. Automaton has 3613 states and 4189 transitions. Word has length 336 [2018-12-08 09:25:43,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:43,934 INFO L480 AbstractCegarLoop]: Abstraction has 3613 states and 4189 transitions. [2018-12-08 09:25:43,934 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:25:43,934 INFO L276 IsEmpty]: Start isEmpty. Operand 3613 states and 4189 transitions. [2018-12-08 09:25:43,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 345 [2018-12-08 09:25:43,936 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:43,937 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:43,937 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:43,937 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:43,937 INFO L82 PathProgramCache]: Analyzing trace with hash -948129435, now seen corresponding path program 1 times [2018-12-08 09:25:43,937 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:43,937 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:43,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:43,937 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:43,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:43,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:44,029 INFO L134 CoverageAnalysis]: Checked inductivity of 538 backedges. 46 proven. 23 refuted. 0 times theorem prover too weak. 469 trivial. 0 not checked. [2018-12-08 09:25:44,029 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:25:44,029 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:25:44,036 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:44,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:25:44,114 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:25:44,211 INFO L134 CoverageAnalysis]: Checked inductivity of 538 backedges. 236 proven. 0 refuted. 0 times theorem prover too weak. 302 trivial. 0 not checked. [2018-12-08 09:25:44,226 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:25:44,226 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [5] total 10 [2018-12-08 09:25:44,226 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-08 09:25:44,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-08 09:25:44,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-12-08 09:25:44,227 INFO L87 Difference]: Start difference. First operand 3613 states and 4189 transitions. Second operand 10 states. [2018-12-08 09:25:44,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:25:44,876 INFO L93 Difference]: Finished difference Result 8912 states and 10510 transitions. [2018-12-08 09:25:44,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-08 09:25:44,877 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 344 [2018-12-08 09:25:44,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:25:44,884 INFO L225 Difference]: With dead ends: 8912 [2018-12-08 09:25:44,885 INFO L226 Difference]: Without dead ends: 2966 [2018-12-08 09:25:44,892 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 345 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2018-12-08 09:25:44,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2966 states. [2018-12-08 09:25:45,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2966 to 2720. [2018-12-08 09:25:45,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2720 states. [2018-12-08 09:25:45,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2720 states to 2720 states and 3078 transitions. [2018-12-08 09:25:45,036 INFO L78 Accepts]: Start accepts. Automaton has 2720 states and 3078 transitions. Word has length 344 [2018-12-08 09:25:45,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:25:45,036 INFO L480 AbstractCegarLoop]: Abstraction has 2720 states and 3078 transitions. [2018-12-08 09:25:45,037 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-08 09:25:45,037 INFO L276 IsEmpty]: Start isEmpty. Operand 2720 states and 3078 transitions. [2018-12-08 09:25:45,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-12-08 09:25:45,038 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:25:45,038 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:25:45,038 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:25:45,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:25:45,039 INFO L82 PathProgramCache]: Analyzing trace with hash -1394352896, now seen corresponding path program 1 times [2018-12-08 09:25:45,039 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:25:45,039 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:25:45,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:45,039 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:25:45,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:25:45,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 09:25:45,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 09:25:45,120 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-08 09:25:45,222 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 08.12 09:25:45 BoogieIcfgContainer [2018-12-08 09:25:45,223 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-08 09:25:45,223 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-08 09:25:45,223 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-08 09:25:45,223 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-08 09:25:45,223 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 09:25:29" (3/4) ... [2018-12-08 09:25:45,225 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-08 09:25:45,325 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_e13f1834-85cf-4154-bbac-0a8dea17602d/bin-2019/uautomizer/witness.graphml [2018-12-08 09:25:45,325 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-08 09:25:45,326 INFO L168 Benchmark]: Toolchain (without parser) took 16680.11 ms. Allocated memory was 1.0 GB in the beginning and 2.2 GB in the end (delta: 1.1 GB). Free memory was 956.0 MB in the beginning and 969.5 MB in the end (delta: -13.5 MB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2018-12-08 09:25:45,327 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-08 09:25:45,327 INFO L168 Benchmark]: CACSL2BoogieTranslator took 158.30 ms. Allocated memory is still 1.0 GB. Free memory was 956.0 MB in the beginning and 939.9 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-12-08 09:25:45,327 INFO L168 Benchmark]: Boogie Procedure Inliner took 43.15 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 103.3 MB). Free memory was 939.9 MB in the beginning and 1.1 GB in the end (delta: -161.3 MB). Peak memory consumption was 14.1 MB. Max. memory is 11.5 GB. [2018-12-08 09:25:45,327 INFO L168 Benchmark]: Boogie Preprocessor took 24.48 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-08 09:25:45,327 INFO L168 Benchmark]: RCFGBuilder took 276.69 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 30.4 MB). Peak memory consumption was 30.4 MB. Max. memory is 11.5 GB. [2018-12-08 09:25:45,328 INFO L168 Benchmark]: TraceAbstraction took 16071.98 ms. Allocated memory was 1.1 GB in the beginning and 2.2 GB in the end (delta: 1.0 GB). Free memory was 1.1 GB in the beginning and 994.7 MB in the end (delta: 73.4 MB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2018-12-08 09:25:45,328 INFO L168 Benchmark]: Witness Printer took 102.77 ms. Allocated memory is still 2.2 GB. Free memory was 994.7 MB in the beginning and 969.5 MB in the end (delta: 25.2 MB). Peak memory consumption was 25.2 MB. Max. memory is 11.5 GB. [2018-12-08 09:25:45,329 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 158.30 ms. Allocated memory is still 1.0 GB. Free memory was 956.0 MB in the beginning and 939.9 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 43.15 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 103.3 MB). Free memory was 939.9 MB in the beginning and 1.1 GB in the end (delta: -161.3 MB). Peak memory consumption was 14.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 24.48 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 276.69 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 30.4 MB). Peak memory consumption was 30.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 16071.98 ms. Allocated memory was 1.1 GB in the beginning and 2.2 GB in the end (delta: 1.0 GB). Free memory was 1.1 GB in the beginning and 994.7 MB in the end (delta: 73.4 MB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. * Witness Printer took 102.77 ms. Allocated memory is still 2.2 GB. Free memory was 994.7 MB in the beginning and 969.5 MB in the end (delta: 25.2 MB). Peak memory consumption was 25.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int C_1_pc ; [L123] int C_1_st ; [L124] int C_1_i ; [L125] int C_1_ev ; [L126] int C_1_pr ; VAL [\old(C_1_ev)=76, \old(C_1_i)=68, \old(C_1_pc)=81, \old(C_1_pr)=78, \old(C_1_st)=80, \old(data_0)=74, \old(data_1)=67, \old(e)=66, \old(i)=70, \old(max_loop)=79, \old(num)=69, \old(P_1_ev)=71, \old(P_1_i)=77, \old(P_1_pc)=72, \old(P_1_st)=75, \old(timer)=73, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L490] int count ; [L491] int __retres2 ; [L495] num = 0 [L496] i = 0 [L497] max_loop = 2 [L499] timer = 0 [L500] P_1_pc = 0 [L501] C_1_pc = 0 [L503] count = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, count=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L504] CALL init_model() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L483] P_1_i = 1 [L484] C_1_i = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L504] RET init_model() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, count=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L505] CALL start_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L421] int kernel_st ; [L422] int tmp ; [L423] int tmp___0 ; [L427] kernel_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L428] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L429] CALL init_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L226] COND TRUE (int )P_1_i == 1 [L227] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L231] COND TRUE (int )C_1_i == 1 [L232] C_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L429] RET init_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L430] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L431] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, is_P_1_triggered()=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L189] COND FALSE !((int )C_1_pc == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, is_C_1_triggered()=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=0] [L431] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L432] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, exists_runnable_thread()=1, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___2=1] [L294] COND TRUE (int )C_1_st == 0 [L296] tmp___1 = __VERIFIER_nondet_int() [L298] COND TRUE \read(tmp___1) [L300] C_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=1, tmp___2=1] [L301] CALL C_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L128] char c ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L131] COND TRUE (int )C_1_pc == 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L146] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L148] COND TRUE num == 0 [L149] timer = 1 [L150] i += 1 [L151] C_1_pc = 1 [L152] C_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=1, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L301] RET C_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1, tmp=0, tmp___1=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L72] COND TRUE (int )P_1_pc == 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(i___0)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(i___0)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, c=65, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, i___0=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L86] RET write_data(num, 'A') VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=1, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L286] RET P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___1=1, tmp___2=0] [L439] RET eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=2, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L443] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=2, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L447] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L448] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_P_1_triggered()=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___1=0] [L448] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L449] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=0, i=1, kernel_st=3, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L457] CALL fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L457] RET fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L458] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=1, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_P_1_triggered()=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1, tmp___1=0] [L458] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0] [L459] CALL reset_time_events() VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L459] RET reset_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0] [L465] CALL, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L417] return (__retres2); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L465] RET, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, stop_simulation()=0, timer=1, tmp=0] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=4, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, kernel_st=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1, tmp=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, i___0=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(i___0)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] RET write_data(num, 'A') VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L286] RET P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=0, \old(i)=1, \old(max_loop)=0, \old(num)=1, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=1, tmp___2=0] [L439] RET eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L442] kernel_st = 2 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L443] FCALL update_channels() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L446] kernel_st = 3 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L447] FCALL fire_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L448] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_P_1_triggered()=0, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___1=0] [L448] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L449] FCALL reset_delta_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L452] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres1=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=0, i=1, kernel_st=3, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L457] CALL fire_time_events() VAL [\old(C_1_ev)=2, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=2, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [\old(C_1_ev)=2, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=2, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L457] RET fire_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1, tmp=0, tmp___0=0] [L458] CALL activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] CALL, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L104] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=1, __retres1=1, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] RET, EXPR is_P_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_P_1_triggered()=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] CALL, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, \result=0, __retres1=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] RET, EXPR is_C_1_triggered() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, is_C_1_triggered()=0, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=2, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=2, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1, tmp___1=0] [L458] RET activate_threads() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L459] CALL reset_time_events() VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [\old(C_1_ev)=1, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=1, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L459] RET reset_time_events() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L465] CALL, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L417] return (__retres2); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, \result=0, __retres2=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=1] [L465] RET, EXPR stop_simulation() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, stop_simulation()=0, timer=1, tmp=0, tmp___0=0] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L435] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=4, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L438] kernel_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=0, \old(C_1_st)=0, \old(data_0)=0, \old(data_1)=0, \old(i)=0, \old(max_loop)=0, \old(num)=0, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=0, \old(P_1_st)=0, \old(timer)=0, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, kernel_st=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp=0, tmp___0=0] [L439] CALL eval() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] CALL, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, \result=1, __retres1=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] RET, EXPR exists_runnable_thread() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, exists_runnable_thread()=1, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1, tmp___2=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=0, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1, tmp=1, tmp___2=1] [L286] CALL P_1() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L86] CALL write_data(num, 'A') VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND FALSE !(i___0 == 1) VAL [\old(c)=65, \old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(i___0)=2, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, c=65, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, i___0=2, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L56] CALL error() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L9] __VERIFIER_error() VAL [\old(C_1_ev)=0, \old(C_1_i)=0, \old(C_1_pc)=1, \old(C_1_st)=2, \old(data_0)=65, \old(data_1)=65, \old(i)=1, \old(max_loop)=0, \old(num)=2, \old(P_1_ev)=0, \old(P_1_i)=0, \old(P_1_pc)=1, \old(P_1_st)=1, \old(timer)=1, C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 22 procedures, 150 locations, 1 error locations. UNSAFE Result, 16.0s OverallTime, 21 OverallIterations, 10 TraceHistogramMax, 10.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5190 SDtfs, 9451 SDslu, 7902 SDs, 0 SdLazy, 11873 SolverSat, 4381 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1954 GetRequests, 1739 SyntacticMatches, 24 SemanticMatches, 191 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 893 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=10564occurred in iteration=11, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 2.4s AutomataMinimizationTime, 20 MinimizatonAttempts, 6067 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 1.3s InterpolantComputationTime, 4963 NumberOfCodeBlocks, 4963 NumberOfCodeBlocksAsserted, 30 NumberOfCheckSat, 4574 ConstructedInterpolants, 0 QuantifiedInterpolants, 1638184 SizeOfPredicates, 13 NumberOfNonLiveVariables, 6681 ConjunctsInSsa, 73 ConjunctsInUnsatCore, 29 InterpolantComputations, 19 PerfectInterpolantSequences, 3176/3315 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...