./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-08 09:00:45,516 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-08 09:00:45,517 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-08 09:00:45,523 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-08 09:00:45,524 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-08 09:00:45,524 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-08 09:00:45,525 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-08 09:00:45,526 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-08 09:00:45,527 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-08 09:00:45,528 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-08 09:00:45,529 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-08 09:00:45,529 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-08 09:00:45,529 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-08 09:00:45,530 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-08 09:00:45,531 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-08 09:00:45,531 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-08 09:00:45,532 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-08 09:00:45,533 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-08 09:00:45,534 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-08 09:00:45,535 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-08 09:00:45,536 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-08 09:00:45,537 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-08 09:00:45,538 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-08 09:00:45,539 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-08 09:00:45,539 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-08 09:00:45,539 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-08 09:00:45,540 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-08 09:00:45,540 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-08 09:00:45,541 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-08 09:00:45,541 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-08 09:00:45,541 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-08 09:00:45,542 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-08 09:00:45,542 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-08 09:00:45,542 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-08 09:00:45,542 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-08 09:00:45,543 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-08 09:00:45,543 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-12-08 09:00:45,550 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-08 09:00:45,551 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-08 09:00:45,551 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-08 09:00:45,551 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-08 09:00:45,552 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-08 09:00:45,552 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-08 09:00:45,552 INFO L133 SettingsManager]: * Use SBE=true [2018-12-08 09:00:45,552 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-08 09:00:45,552 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-08 09:00:45,553 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-08 09:00:45,553 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-08 09:00:45,553 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-08 09:00:45,553 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-08 09:00:45,553 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-08 09:00:45,553 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-08 09:00:45,553 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-08 09:00:45,553 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-08 09:00:45,554 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-08 09:00:45,554 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-08 09:00:45,554 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-08 09:00:45,554 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-08 09:00:45,554 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-08 09:00:45,554 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-08 09:00:45,554 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-08 09:00:45,555 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-08 09:00:45,555 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-08 09:00:45,555 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-08 09:00:45,555 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-08 09:00:45,555 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-08 09:00:45,555 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-08 09:00:45,555 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 [2018-12-08 09:00:45,574 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-08 09:00:45,581 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-08 09:00:45,583 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-08 09:00:45,584 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-08 09:00:45,584 INFO L276 PluginConnector]: CDTParser initialized [2018-12-08 09:00:45,584 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c [2018-12-08 09:00:45,618 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/data/1b07cde87/043651179ee442909290f100921566d6/FLAG4b45b514a [2018-12-08 09:00:46,033 INFO L307 CDTParser]: Found 1 translation units. [2018-12-08 09:00:46,034 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c [2018-12-08 09:00:46,039 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/data/1b07cde87/043651179ee442909290f100921566d6/FLAG4b45b514a [2018-12-08 09:00:46,047 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/data/1b07cde87/043651179ee442909290f100921566d6 [2018-12-08 09:00:46,049 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-08 09:00:46,049 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-08 09:00:46,050 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-08 09:00:46,050 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-08 09:00:46,052 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-08 09:00:46,053 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,054 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@643265e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46, skipping insertion in model container [2018-12-08 09:00:46,054 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,059 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-08 09:00:46,076 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-08 09:00:46,186 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-08 09:00:46,190 INFO L191 MainTranslator]: Completed pre-run [2018-12-08 09:00:46,216 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-08 09:00:46,225 INFO L195 MainTranslator]: Completed translation [2018-12-08 09:00:46,226 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46 WrapperNode [2018-12-08 09:00:46,226 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-08 09:00:46,226 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-08 09:00:46,226 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-08 09:00:46,226 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-08 09:00:46,260 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,265 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,269 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-08 09:00:46,270 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-08 09:00:46,270 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-08 09:00:46,270 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-08 09:00:46,275 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,276 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,277 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,277 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,282 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,290 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,291 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... [2018-12-08 09:00:46,292 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-08 09:00:46,293 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-08 09:00:46,293 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-08 09:00:46,293 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-08 09:00:46,293 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-08 09:00:46,324 INFO L130 BoogieDeclarations]: Found specification of procedure read [2018-12-08 09:00:46,325 INFO L138 BoogieDeclarations]: Found implementation of procedure read [2018-12-08 09:00:46,325 INFO L130 BoogieDeclarations]: Found specification of procedure write_back [2018-12-08 09:00:46,325 INFO L138 BoogieDeclarations]: Found implementation of procedure write_back [2018-12-08 09:00:46,325 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-08 09:00:46,325 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-08 09:00:46,325 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-08 09:00:46,325 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-08 09:00:46,325 INFO L130 BoogieDeclarations]: Found specification of procedure compute2 [2018-12-08 09:00:46,325 INFO L138 BoogieDeclarations]: Found implementation of procedure compute2 [2018-12-08 09:00:46,325 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-08 09:00:46,325 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-08 09:00:46,325 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-08 09:00:46,325 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-08 09:00:46,326 INFO L130 BoogieDeclarations]: Found specification of procedure compute1 [2018-12-08 09:00:46,326 INFO L138 BoogieDeclarations]: Found implementation of procedure compute1 [2018-12-08 09:00:46,326 INFO L130 BoogieDeclarations]: Found specification of procedure write_loop [2018-12-08 09:00:46,326 INFO L138 BoogieDeclarations]: Found implementation of procedure write_loop [2018-12-08 09:00:46,326 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-08 09:00:46,326 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-08 09:00:46,326 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-08 09:00:46,326 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-08 09:00:46,616 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-08 09:00:46,616 INFO L280 CfgBuilder]: Removed 6 assue(true) statements. [2018-12-08 09:00:46,616 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 09:00:46 BoogieIcfgContainer [2018-12-08 09:00:46,616 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-08 09:00:46,617 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-08 09:00:46,617 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-08 09:00:46,619 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-08 09:00:46,619 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 08.12 09:00:46" (1/3) ... [2018-12-08 09:00:46,619 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@ea0e8e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.12 09:00:46, skipping insertion in model container [2018-12-08 09:00:46,619 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.12 09:00:46" (2/3) ... [2018-12-08 09:00:46,620 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@ea0e8e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.12 09:00:46, skipping insertion in model container [2018-12-08 09:00:46,620 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 09:00:46" (3/3) ... [2018-12-08 09:00:46,621 INFO L112 eAbstractionObserver]: Analyzing ICFG toy1_false-unreach-call_false-termination.cil.c [2018-12-08 09:00:46,626 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-08 09:00:46,631 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-08 09:00:46,640 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-08 09:00:46,658 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-08 09:00:46,658 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-08 09:00:46,658 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-08 09:00:46,659 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-08 09:00:46,659 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-08 09:00:46,659 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-08 09:00:46,659 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-08 09:00:46,659 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-08 09:00:46,659 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-08 09:00:46,671 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states. [2018-12-08 09:00:46,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:46,676 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:46,677 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:46,678 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:46,681 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:46,681 INFO L82 PathProgramCache]: Analyzing trace with hash -1366020299, now seen corresponding path program 1 times [2018-12-08 09:00:46,682 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:46,683 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:46,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:46,710 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:46,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:46,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:46,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:46,811 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:46,811 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 09:00:46,813 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 09:00:46,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 09:00:46,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:00:46,822 INFO L87 Difference]: Start difference. First operand 161 states. Second operand 3 states. [2018-12-08 09:00:46,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:46,857 INFO L93 Difference]: Finished difference Result 304 states and 521 transitions. [2018-12-08 09:00:46,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 09:00:46,858 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-08 09:00:46,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:46,865 INFO L225 Difference]: With dead ends: 304 [2018-12-08 09:00:46,865 INFO L226 Difference]: Without dead ends: 152 [2018-12-08 09:00:46,868 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:00:46,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-12-08 09:00:46,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 152. [2018-12-08 09:00:46,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-12-08 09:00:46,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 246 transitions. [2018-12-08 09:00:46,897 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 246 transitions. Word has length 47 [2018-12-08 09:00:46,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:46,898 INFO L480 AbstractCegarLoop]: Abstraction has 152 states and 246 transitions. [2018-12-08 09:00:46,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 09:00:46,898 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 246 transitions. [2018-12-08 09:00:46,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:46,899 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:46,899 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:46,899 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:46,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:46,899 INFO L82 PathProgramCache]: Analyzing trace with hash 684963699, now seen corresponding path program 1 times [2018-12-08 09:00:46,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:46,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:46,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:46,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:46,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:46,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:46,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:46,946 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:46,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:46,947 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:46,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:46,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:46,948 INFO L87 Difference]: Start difference. First operand 152 states and 246 transitions. Second operand 4 states. [2018-12-08 09:00:47,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:47,091 INFO L93 Difference]: Finished difference Result 394 states and 641 transitions. [2018-12-08 09:00:47,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-08 09:00:47,091 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-08 09:00:47,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:47,094 INFO L225 Difference]: With dead ends: 394 [2018-12-08 09:00:47,094 INFO L226 Difference]: Without dead ends: 259 [2018-12-08 09:00:47,095 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:47,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 259 states. [2018-12-08 09:00:47,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 259 to 249. [2018-12-08 09:00:47,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 249 states. [2018-12-08 09:00:47,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 402 transitions. [2018-12-08 09:00:47,118 INFO L78 Accepts]: Start accepts. Automaton has 249 states and 402 transitions. Word has length 47 [2018-12-08 09:00:47,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:47,118 INFO L480 AbstractCegarLoop]: Abstraction has 249 states and 402 transitions. [2018-12-08 09:00:47,118 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:47,118 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 402 transitions. [2018-12-08 09:00:47,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:47,120 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:47,120 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:47,120 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:47,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:47,120 INFO L82 PathProgramCache]: Analyzing trace with hash 959723313, now seen corresponding path program 1 times [2018-12-08 09:00:47,121 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:47,121 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:47,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:47,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:47,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:47,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:47,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:47,155 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:47,155 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:47,155 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:47,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:47,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:47,156 INFO L87 Difference]: Start difference. First operand 249 states and 402 transitions. Second operand 4 states. [2018-12-08 09:00:47,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:47,270 INFO L93 Difference]: Finished difference Result 675 states and 1099 transitions. [2018-12-08 09:00:47,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-08 09:00:47,271 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-08 09:00:47,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:47,273 INFO L225 Difference]: With dead ends: 675 [2018-12-08 09:00:47,273 INFO L226 Difference]: Without dead ends: 445 [2018-12-08 09:00:47,274 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:47,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445 states. [2018-12-08 09:00:47,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445 to 431. [2018-12-08 09:00:47,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 431 states. [2018-12-08 09:00:47,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431 states to 431 states and 699 transitions. [2018-12-08 09:00:47,296 INFO L78 Accepts]: Start accepts. Automaton has 431 states and 699 transitions. Word has length 47 [2018-12-08 09:00:47,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:47,296 INFO L480 AbstractCegarLoop]: Abstraction has 431 states and 699 transitions. [2018-12-08 09:00:47,297 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:47,297 INFO L276 IsEmpty]: Start isEmpty. Operand 431 states and 699 transitions. [2018-12-08 09:00:47,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:47,298 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:47,298 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:47,299 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:47,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:47,299 INFO L82 PathProgramCache]: Analyzing trace with hash 1661323187, now seen corresponding path program 1 times [2018-12-08 09:00:47,299 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:47,299 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:47,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:47,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:47,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:47,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:47,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:47,338 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:47,338 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:47,338 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:47,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:47,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:47,339 INFO L87 Difference]: Start difference. First operand 431 states and 699 transitions. Second operand 4 states. [2018-12-08 09:00:47,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:47,463 INFO L93 Difference]: Finished difference Result 1281 states and 2081 transitions. [2018-12-08 09:00:47,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-08 09:00:47,464 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-08 09:00:47,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:47,467 INFO L225 Difference]: With dead ends: 1281 [2018-12-08 09:00:47,467 INFO L226 Difference]: Without dead ends: 870 [2018-12-08 09:00:47,468 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:47,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 870 states. [2018-12-08 09:00:47,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 870 to 860. [2018-12-08 09:00:47,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 860 states. [2018-12-08 09:00:47,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 860 states to 860 states and 1387 transitions. [2018-12-08 09:00:47,502 INFO L78 Accepts]: Start accepts. Automaton has 860 states and 1387 transitions. Word has length 47 [2018-12-08 09:00:47,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:47,502 INFO L480 AbstractCegarLoop]: Abstraction has 860 states and 1387 transitions. [2018-12-08 09:00:47,502 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:47,502 INFO L276 IsEmpty]: Start isEmpty. Operand 860 states and 1387 transitions. [2018-12-08 09:00:47,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:47,504 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:47,504 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:47,504 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:47,504 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:47,504 INFO L82 PathProgramCache]: Analyzing trace with hash 1683955441, now seen corresponding path program 1 times [2018-12-08 09:00:47,504 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:47,504 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:47,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:47,505 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:47,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:47,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:47,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:47,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:47,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:47,538 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:47,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:47,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:47,539 INFO L87 Difference]: Start difference. First operand 860 states and 1387 transitions. Second operand 4 states. [2018-12-08 09:00:47,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:47,697 INFO L93 Difference]: Finished difference Result 3013 states and 4877 transitions. [2018-12-08 09:00:47,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-08 09:00:47,698 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-08 09:00:47,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:47,705 INFO L225 Difference]: With dead ends: 3013 [2018-12-08 09:00:47,705 INFO L226 Difference]: Without dead ends: 2185 [2018-12-08 09:00:47,707 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:47,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2185 states. [2018-12-08 09:00:47,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2185 to 2115. [2018-12-08 09:00:47,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2115 states. [2018-12-08 09:00:47,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2115 states to 2115 states and 3404 transitions. [2018-12-08 09:00:47,807 INFO L78 Accepts]: Start accepts. Automaton has 2115 states and 3404 transitions. Word has length 47 [2018-12-08 09:00:47,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:47,807 INFO L480 AbstractCegarLoop]: Abstraction has 2115 states and 3404 transitions. [2018-12-08 09:00:47,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:47,808 INFO L276 IsEmpty]: Start isEmpty. Operand 2115 states and 3404 transitions. [2018-12-08 09:00:47,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:47,810 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:47,810 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:47,810 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:47,810 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:47,811 INFO L82 PathProgramCache]: Analyzing trace with hash -1224808461, now seen corresponding path program 1 times [2018-12-08 09:00:47,811 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:47,811 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:47,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:47,811 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:47,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:47,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:47,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:47,875 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:47,876 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 09:00:47,876 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-08 09:00:47,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 09:00:47,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:47,876 INFO L87 Difference]: Start difference. First operand 2115 states and 3404 transitions. Second operand 5 states. [2018-12-08 09:00:48,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:48,142 INFO L93 Difference]: Finished difference Result 6477 states and 10462 transitions. [2018-12-08 09:00:48,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-08 09:00:48,142 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-12-08 09:00:48,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:48,152 INFO L225 Difference]: With dead ends: 6477 [2018-12-08 09:00:48,153 INFO L226 Difference]: Without dead ends: 4382 [2018-12-08 09:00:48,157 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:00:48,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4382 states. [2018-12-08 09:00:48,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4382 to 3296. [2018-12-08 09:00:48,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3296 states. [2018-12-08 09:00:48,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3296 states to 3296 states and 5300 transitions. [2018-12-08 09:00:48,260 INFO L78 Accepts]: Start accepts. Automaton has 3296 states and 5300 transitions. Word has length 47 [2018-12-08 09:00:48,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:48,260 INFO L480 AbstractCegarLoop]: Abstraction has 3296 states and 5300 transitions. [2018-12-08 09:00:48,260 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-08 09:00:48,260 INFO L276 IsEmpty]: Start isEmpty. Operand 3296 states and 5300 transitions. [2018-12-08 09:00:48,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:48,262 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:48,263 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:48,263 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:48,263 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:48,263 INFO L82 PathProgramCache]: Analyzing trace with hash -424223241, now seen corresponding path program 1 times [2018-12-08 09:00:48,263 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:48,263 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:48,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:48,264 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:48,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:48,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:48,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:48,297 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:48,297 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:48,297 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:48,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:48,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:48,298 INFO L87 Difference]: Start difference. First operand 3296 states and 5300 transitions. Second operand 4 states. [2018-12-08 09:00:48,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:48,520 INFO L93 Difference]: Finished difference Result 6609 states and 10702 transitions. [2018-12-08 09:00:48,520 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:00:48,520 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-08 09:00:48,520 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:48,532 INFO L225 Difference]: With dead ends: 6609 [2018-12-08 09:00:48,532 INFO L226 Difference]: Without dead ends: 3379 [2018-12-08 09:00:48,541 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:48,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3379 states. [2018-12-08 09:00:48,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3379 to 3359. [2018-12-08 09:00:48,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3359 states. [2018-12-08 09:00:48,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3359 states to 3359 states and 5291 transitions. [2018-12-08 09:00:48,662 INFO L78 Accepts]: Start accepts. Automaton has 3359 states and 5291 transitions. Word has length 47 [2018-12-08 09:00:48,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:48,663 INFO L480 AbstractCegarLoop]: Abstraction has 3359 states and 5291 transitions. [2018-12-08 09:00:48,663 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:48,663 INFO L276 IsEmpty]: Start isEmpty. Operand 3359 states and 5291 transitions. [2018-12-08 09:00:48,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:48,666 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:48,666 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:48,666 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:48,666 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:48,666 INFO L82 PathProgramCache]: Analyzing trace with hash -1521415, now seen corresponding path program 1 times [2018-12-08 09:00:48,666 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:48,666 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:48,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:48,667 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:48,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:48,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:48,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:48,698 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:48,698 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:48,698 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:48,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:48,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:48,699 INFO L87 Difference]: Start difference. First operand 3359 states and 5291 transitions. Second operand 4 states. [2018-12-08 09:00:48,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:48,914 INFO L93 Difference]: Finished difference Result 6871 states and 10809 transitions. [2018-12-08 09:00:48,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:00:48,915 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-08 09:00:48,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:48,925 INFO L225 Difference]: With dead ends: 6871 [2018-12-08 09:00:48,925 INFO L226 Difference]: Without dead ends: 3594 [2018-12-08 09:00:48,931 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:48,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3594 states. [2018-12-08 09:00:49,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3594 to 3554. [2018-12-08 09:00:49,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3554 states. [2018-12-08 09:00:49,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3554 states to 3554 states and 5523 transitions. [2018-12-08 09:00:49,025 INFO L78 Accepts]: Start accepts. Automaton has 3554 states and 5523 transitions. Word has length 47 [2018-12-08 09:00:49,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:49,026 INFO L480 AbstractCegarLoop]: Abstraction has 3554 states and 5523 transitions. [2018-12-08 09:00:49,026 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:49,026 INFO L276 IsEmpty]: Start isEmpty. Operand 3554 states and 5523 transitions. [2018-12-08 09:00:49,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:49,027 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:49,027 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:49,027 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:49,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:49,027 INFO L82 PathProgramCache]: Analyzing trace with hash -819169865, now seen corresponding path program 1 times [2018-12-08 09:00:49,027 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:49,027 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:49,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:49,028 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:49,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:49,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:49,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:49,060 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:49,060 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:49,060 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:49,060 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:49,060 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:49,060 INFO L87 Difference]: Start difference. First operand 3554 states and 5523 transitions. Second operand 4 states. [2018-12-08 09:00:49,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:49,272 INFO L93 Difference]: Finished difference Result 7652 states and 12054 transitions. [2018-12-08 09:00:49,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:00:49,273 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-12-08 09:00:49,273 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:49,282 INFO L225 Difference]: With dead ends: 7652 [2018-12-08 09:00:49,282 INFO L226 Difference]: Without dead ends: 4156 [2018-12-08 09:00:49,289 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:49,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4156 states. [2018-12-08 09:00:49,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4156 to 4146. [2018-12-08 09:00:49,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4146 states. [2018-12-08 09:00:49,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4146 states to 4146 states and 6362 transitions. [2018-12-08 09:00:49,398 INFO L78 Accepts]: Start accepts. Automaton has 4146 states and 6362 transitions. Word has length 47 [2018-12-08 09:00:49,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:49,398 INFO L480 AbstractCegarLoop]: Abstraction has 4146 states and 6362 transitions. [2018-12-08 09:00:49,398 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:49,398 INFO L276 IsEmpty]: Start isEmpty. Operand 4146 states and 6362 transitions. [2018-12-08 09:00:49,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-08 09:00:49,399 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:49,399 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:49,399 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:49,400 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:49,400 INFO L82 PathProgramCache]: Analyzing trace with hash 1481652725, now seen corresponding path program 1 times [2018-12-08 09:00:49,400 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:49,400 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:49,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:49,400 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:49,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:49,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:49,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:49,420 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:49,420 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 09:00:49,420 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 09:00:49,420 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 09:00:49,420 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:00:49,421 INFO L87 Difference]: Start difference. First operand 4146 states and 6362 transitions. Second operand 3 states. [2018-12-08 09:00:49,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:49,617 INFO L93 Difference]: Finished difference Result 9137 states and 14288 transitions. [2018-12-08 09:00:49,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 09:00:49,617 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-08 09:00:49,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:49,627 INFO L225 Difference]: With dead ends: 9137 [2018-12-08 09:00:49,628 INFO L226 Difference]: Without dead ends: 5045 [2018-12-08 09:00:49,634 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:00:49,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5045 states. [2018-12-08 09:00:49,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5045 to 4973. [2018-12-08 09:00:49,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4973 states. [2018-12-08 09:00:49,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4973 states to 4973 states and 7578 transitions. [2018-12-08 09:00:49,755 INFO L78 Accepts]: Start accepts. Automaton has 4973 states and 7578 transitions. Word has length 47 [2018-12-08 09:00:49,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:49,755 INFO L480 AbstractCegarLoop]: Abstraction has 4973 states and 7578 transitions. [2018-12-08 09:00:49,755 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 09:00:49,755 INFO L276 IsEmpty]: Start isEmpty. Operand 4973 states and 7578 transitions. [2018-12-08 09:00:49,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-12-08 09:00:49,759 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:49,759 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:49,759 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:49,759 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:49,759 INFO L82 PathProgramCache]: Analyzing trace with hash 584484674, now seen corresponding path program 1 times [2018-12-08 09:00:49,759 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:49,759 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:49,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:49,760 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:49,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:49,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:49,809 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:49,809 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:49,809 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-08 09:00:49,809 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-08 09:00:49,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 09:00:49,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:49,810 INFO L87 Difference]: Start difference. First operand 4973 states and 7578 transitions. Second operand 5 states. [2018-12-08 09:00:50,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:50,301 INFO L93 Difference]: Finished difference Result 12503 states and 19791 transitions. [2018-12-08 09:00:50,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-08 09:00:50,301 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2018-12-08 09:00:50,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:50,324 INFO L225 Difference]: With dead ends: 12503 [2018-12-08 09:00:50,324 INFO L226 Difference]: Without dead ends: 7576 [2018-12-08 09:00:50,337 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:00:50,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7576 states. [2018-12-08 09:00:50,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7576 to 7478. [2018-12-08 09:00:50,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7478 states. [2018-12-08 09:00:50,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7478 states to 7478 states and 11595 transitions. [2018-12-08 09:00:50,576 INFO L78 Accepts]: Start accepts. Automaton has 7478 states and 11595 transitions. Word has length 67 [2018-12-08 09:00:50,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:50,576 INFO L480 AbstractCegarLoop]: Abstraction has 7478 states and 11595 transitions. [2018-12-08 09:00:50,576 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-08 09:00:50,576 INFO L276 IsEmpty]: Start isEmpty. Operand 7478 states and 11595 transitions. [2018-12-08 09:00:50,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-12-08 09:00:50,581 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:50,581 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:50,581 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:50,581 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:50,582 INFO L82 PathProgramCache]: Analyzing trace with hash -923082464, now seen corresponding path program 1 times [2018-12-08 09:00:50,582 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:50,582 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:50,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:50,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:50,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:50,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:50,622 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 19 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-12-08 09:00:50,622 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:00:50,622 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:00:50,631 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:50,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:50,702 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:00:50,744 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-12-08 09:00:50,760 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:00:50,760 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-12-08 09:00:50,760 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-08 09:00:50,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-08 09:00:50,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:00:50,761 INFO L87 Difference]: Start difference. First operand 7478 states and 11595 transitions. Second operand 8 states. [2018-12-08 09:00:52,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:52,200 INFO L93 Difference]: Finished difference Result 25947 states and 42735 transitions. [2018-12-08 09:00:52,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-12-08 09:00:52,200 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 81 [2018-12-08 09:00:52,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:52,217 INFO L225 Difference]: With dead ends: 25947 [2018-12-08 09:00:52,217 INFO L226 Difference]: Without dead ends: 6445 [2018-12-08 09:00:52,255 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=124, Invalid=338, Unknown=0, NotChecked=0, Total=462 [2018-12-08 09:00:52,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6445 states. [2018-12-08 09:00:52,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6445 to 4635. [2018-12-08 09:00:52,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4635 states. [2018-12-08 09:00:52,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4635 states to 4635 states and 6932 transitions. [2018-12-08 09:00:52,457 INFO L78 Accepts]: Start accepts. Automaton has 4635 states and 6932 transitions. Word has length 81 [2018-12-08 09:00:52,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:52,457 INFO L480 AbstractCegarLoop]: Abstraction has 4635 states and 6932 transitions. [2018-12-08 09:00:52,457 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-08 09:00:52,457 INFO L276 IsEmpty]: Start isEmpty. Operand 4635 states and 6932 transitions. [2018-12-08 09:00:52,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-12-08 09:00:52,464 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:52,464 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:52,464 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:52,465 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:52,465 INFO L82 PathProgramCache]: Analyzing trace with hash -2147284885, now seen corresponding path program 1 times [2018-12-08 09:00:52,465 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:52,465 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:52,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:52,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:52,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:52,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:52,528 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-12-08 09:00:52,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:52,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-08 09:00:52,528 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:00:52,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:00:52,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:00:52,529 INFO L87 Difference]: Start difference. First operand 4635 states and 6932 transitions. Second operand 6 states. [2018-12-08 09:00:52,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:52,866 INFO L93 Difference]: Finished difference Result 8776 states and 13290 transitions. [2018-12-08 09:00:52,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-08 09:00:52,866 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2018-12-08 09:00:52,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:52,879 INFO L225 Difference]: With dead ends: 8776 [2018-12-08 09:00:52,879 INFO L226 Difference]: Without dead ends: 5256 [2018-12-08 09:00:52,885 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:00:52,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5256 states. [2018-12-08 09:00:53,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5256 to 4836. [2018-12-08 09:00:53,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4836 states. [2018-12-08 09:00:53,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4836 states to 4836 states and 7263 transitions. [2018-12-08 09:00:53,104 INFO L78 Accepts]: Start accepts. Automaton has 4836 states and 7263 transitions. Word has length 122 [2018-12-08 09:00:53,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:53,105 INFO L480 AbstractCegarLoop]: Abstraction has 4836 states and 7263 transitions. [2018-12-08 09:00:53,105 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:00:53,105 INFO L276 IsEmpty]: Start isEmpty. Operand 4836 states and 7263 transitions. [2018-12-08 09:00:53,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-12-08 09:00:53,110 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:53,111 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:53,111 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:53,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:53,111 INFO L82 PathProgramCache]: Analyzing trace with hash -608944855, now seen corresponding path program 1 times [2018-12-08 09:00:53,111 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:53,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:53,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:53,112 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:53,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:53,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:53,136 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-12-08 09:00:53,136 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:53,136 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 09:00:53,136 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 09:00:53,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 09:00:53,136 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:00:53,137 INFO L87 Difference]: Start difference. First operand 4836 states and 7263 transitions. Second operand 3 states. [2018-12-08 09:00:53,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:53,285 INFO L93 Difference]: Finished difference Result 9041 states and 13613 transitions. [2018-12-08 09:00:53,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 09:00:53,285 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 122 [2018-12-08 09:00:53,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:53,300 INFO L225 Difference]: With dead ends: 9041 [2018-12-08 09:00:53,300 INFO L226 Difference]: Without dead ends: 4836 [2018-12-08 09:00:53,308 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:00:53,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4836 states. [2018-12-08 09:00:53,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4836 to 4836. [2018-12-08 09:00:53,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4836 states. [2018-12-08 09:00:53,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4836 states to 4836 states and 7250 transitions. [2018-12-08 09:00:53,464 INFO L78 Accepts]: Start accepts. Automaton has 4836 states and 7250 transitions. Word has length 122 [2018-12-08 09:00:53,465 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:53,465 INFO L480 AbstractCegarLoop]: Abstraction has 4836 states and 7250 transitions. [2018-12-08 09:00:53,465 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 09:00:53,465 INFO L276 IsEmpty]: Start isEmpty. Operand 4836 states and 7250 transitions. [2018-12-08 09:00:53,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-12-08 09:00:53,471 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:53,471 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:53,471 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:53,471 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:53,471 INFO L82 PathProgramCache]: Analyzing trace with hash 1746860395, now seen corresponding path program 1 times [2018-12-08 09:00:53,471 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:53,471 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:53,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:53,472 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:53,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:53,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:53,545 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 17 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-08 09:00:53,545 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:00:53,545 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:00:53,551 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:53,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:53,619 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:00:53,649 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-12-08 09:00:53,664 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:00:53,664 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [9] total 10 [2018-12-08 09:00:53,664 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-08 09:00:53,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-08 09:00:53,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-12-08 09:00:53,665 INFO L87 Difference]: Start difference. First operand 4836 states and 7250 transitions. Second operand 10 states. [2018-12-08 09:00:54,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:54,622 INFO L93 Difference]: Finished difference Result 10019 states and 15148 transitions. [2018-12-08 09:00:54,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-12-08 09:00:54,622 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 122 [2018-12-08 09:00:54,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:54,631 INFO L225 Difference]: With dead ends: 10019 [2018-12-08 09:00:54,632 INFO L226 Difference]: Without dead ends: 5264 [2018-12-08 09:00:54,640 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 159 GetRequests, 135 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 125 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=162, Invalid=488, Unknown=0, NotChecked=0, Total=650 [2018-12-08 09:00:54,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5264 states. [2018-12-08 09:00:54,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5264 to 3734. [2018-12-08 09:00:54,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3734 states. [2018-12-08 09:00:54,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3734 states to 3734 states and 5348 transitions. [2018-12-08 09:00:54,781 INFO L78 Accepts]: Start accepts. Automaton has 3734 states and 5348 transitions. Word has length 122 [2018-12-08 09:00:54,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:54,782 INFO L480 AbstractCegarLoop]: Abstraction has 3734 states and 5348 transitions. [2018-12-08 09:00:54,782 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-08 09:00:54,782 INFO L276 IsEmpty]: Start isEmpty. Operand 3734 states and 5348 transitions. [2018-12-08 09:00:54,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-12-08 09:00:54,786 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:54,786 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:54,786 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:54,786 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:54,786 INFO L82 PathProgramCache]: Analyzing trace with hash -837113155, now seen corresponding path program 1 times [2018-12-08 09:00:54,786 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:54,787 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:54,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:54,787 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:54,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:54,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:54,813 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-12-08 09:00:54,813 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:54,813 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:54,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:54,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:54,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:54,814 INFO L87 Difference]: Start difference. First operand 3734 states and 5348 transitions. Second operand 4 states. [2018-12-08 09:00:55,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:55,123 INFO L93 Difference]: Finished difference Result 9142 states and 13232 transitions. [2018-12-08 09:00:55,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-08 09:00:55,123 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 124 [2018-12-08 09:00:55,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:55,136 INFO L225 Difference]: With dead ends: 9142 [2018-12-08 09:00:55,136 INFO L226 Difference]: Without dead ends: 5417 [2018-12-08 09:00:55,141 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:55,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5417 states. [2018-12-08 09:00:55,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5417 to 5222. [2018-12-08 09:00:55,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5222 states. [2018-12-08 09:00:55,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5222 states to 5222 states and 7627 transitions. [2018-12-08 09:00:55,353 INFO L78 Accepts]: Start accepts. Automaton has 5222 states and 7627 transitions. Word has length 124 [2018-12-08 09:00:55,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:55,353 INFO L480 AbstractCegarLoop]: Abstraction has 5222 states and 7627 transitions. [2018-12-08 09:00:55,353 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:55,353 INFO L276 IsEmpty]: Start isEmpty. Operand 5222 states and 7627 transitions. [2018-12-08 09:00:55,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-12-08 09:00:55,357 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:55,357 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:55,357 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:55,357 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:55,357 INFO L82 PathProgramCache]: Analyzing trace with hash 1908243549, now seen corresponding path program 1 times [2018-12-08 09:00:55,357 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:55,357 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:55,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:55,358 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:55,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:55,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:55,411 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 27 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-08 09:00:55,412 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:00:55,412 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:00:55,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:55,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:55,484 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:00:55,502 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-08 09:00:55,518 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:00:55,518 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-08 09:00:55,518 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:00:55,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:00:55,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:00:55,519 INFO L87 Difference]: Start difference. First operand 5222 states and 7627 transitions. Second operand 6 states. [2018-12-08 09:00:55,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:55,907 INFO L93 Difference]: Finished difference Result 10913 states and 16657 transitions. [2018-12-08 09:00:55,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-08 09:00:55,907 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 133 [2018-12-08 09:00:55,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:55,918 INFO L225 Difference]: With dead ends: 10913 [2018-12-08 09:00:55,918 INFO L226 Difference]: Without dead ends: 5717 [2018-12-08 09:00:55,927 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 137 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:00:55,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5717 states. [2018-12-08 09:00:56,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5717 to 5576. [2018-12-08 09:00:56,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5576 states. [2018-12-08 09:00:56,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5576 states to 5576 states and 8026 transitions. [2018-12-08 09:00:56,187 INFO L78 Accepts]: Start accepts. Automaton has 5576 states and 8026 transitions. Word has length 133 [2018-12-08 09:00:56,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:56,187 INFO L480 AbstractCegarLoop]: Abstraction has 5576 states and 8026 transitions. [2018-12-08 09:00:56,187 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:00:56,187 INFO L276 IsEmpty]: Start isEmpty. Operand 5576 states and 8026 transitions. [2018-12-08 09:00:56,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-12-08 09:00:56,191 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:56,192 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:56,192 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:56,192 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:56,192 INFO L82 PathProgramCache]: Analyzing trace with hash -1750678265, now seen corresponding path program 1 times [2018-12-08 09:00:56,192 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:56,192 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:56,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:56,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:56,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:56,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:56,222 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-12-08 09:00:56,222 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:56,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 09:00:56,223 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 09:00:56,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 09:00:56,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:00:56,223 INFO L87 Difference]: Start difference. First operand 5576 states and 8026 transitions. Second operand 3 states. [2018-12-08 09:00:56,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:56,499 INFO L93 Difference]: Finished difference Result 12623 states and 18377 transitions. [2018-12-08 09:00:56,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 09:00:56,499 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 149 [2018-12-08 09:00:56,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:56,511 INFO L225 Difference]: With dead ends: 12623 [2018-12-08 09:00:56,511 INFO L226 Difference]: Without dead ends: 7083 [2018-12-08 09:00:56,519 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:00:56,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7083 states. [2018-12-08 09:00:56,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7083 to 7079. [2018-12-08 09:00:56,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7079 states. [2018-12-08 09:00:56,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7079 states to 7079 states and 9983 transitions. [2018-12-08 09:00:56,861 INFO L78 Accepts]: Start accepts. Automaton has 7079 states and 9983 transitions. Word has length 149 [2018-12-08 09:00:56,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:56,861 INFO L480 AbstractCegarLoop]: Abstraction has 7079 states and 9983 transitions. [2018-12-08 09:00:56,861 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 09:00:56,861 INFO L276 IsEmpty]: Start isEmpty. Operand 7079 states and 9983 transitions. [2018-12-08 09:00:56,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-12-08 09:00:56,866 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:56,866 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:56,866 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:56,866 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:56,866 INFO L82 PathProgramCache]: Analyzing trace with hash -499469301, now seen corresponding path program 1 times [2018-12-08 09:00:56,866 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:56,866 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:56,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:56,867 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:56,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:56,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:56,891 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-12-08 09:00:56,892 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:00:56,892 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-08 09:00:56,892 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-08 09:00:56,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-08 09:00:56,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-08 09:00:56,893 INFO L87 Difference]: Start difference. First operand 7079 states and 9983 transitions. Second operand 4 states. [2018-12-08 09:00:57,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:57,197 INFO L93 Difference]: Finished difference Result 13633 states and 19236 transitions. [2018-12-08 09:00:57,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-08 09:00:57,197 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 149 [2018-12-08 09:00:57,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:57,208 INFO L225 Difference]: With dead ends: 13633 [2018-12-08 09:00:57,208 INFO L226 Difference]: Without dead ends: 7054 [2018-12-08 09:00:57,216 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:57,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7054 states. [2018-12-08 09:00:57,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7054 to 7054. [2018-12-08 09:00:57,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7054 states. [2018-12-08 09:00:57,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7054 states to 7054 states and 9948 transitions. [2018-12-08 09:00:57,485 INFO L78 Accepts]: Start accepts. Automaton has 7054 states and 9948 transitions. Word has length 149 [2018-12-08 09:00:57,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:57,486 INFO L480 AbstractCegarLoop]: Abstraction has 7054 states and 9948 transitions. [2018-12-08 09:00:57,486 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-08 09:00:57,486 INFO L276 IsEmpty]: Start isEmpty. Operand 7054 states and 9948 transitions. [2018-12-08 09:00:57,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-12-08 09:00:57,490 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:57,490 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:57,490 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:57,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:57,490 INFO L82 PathProgramCache]: Analyzing trace with hash 1288400521, now seen corresponding path program 1 times [2018-12-08 09:00:57,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:57,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:57,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:57,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:57,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:57,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:57,534 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 48 proven. 2 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-08 09:00:57,534 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:00:57,534 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:00:57,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:57,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:57,599 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:00:57,615 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-08 09:00:57,631 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:00:57,631 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-12-08 09:00:57,631 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-08 09:00:57,631 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 09:00:57,631 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:57,631 INFO L87 Difference]: Start difference. First operand 7054 states and 9948 transitions. Second operand 5 states. [2018-12-08 09:00:58,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:58,006 INFO L93 Difference]: Finished difference Result 13490 states and 19213 transitions. [2018-12-08 09:00:58,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-08 09:00:58,006 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 149 [2018-12-08 09:00:58,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:58,016 INFO L225 Difference]: With dead ends: 13490 [2018-12-08 09:00:58,016 INFO L226 Difference]: Without dead ends: 6966 [2018-12-08 09:00:58,022 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 152 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:00:58,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6966 states. [2018-12-08 09:00:58,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6966 to 5727. [2018-12-08 09:00:58,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5727 states. [2018-12-08 09:00:58,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5727 states to 5727 states and 7938 transitions. [2018-12-08 09:00:58,256 INFO L78 Accepts]: Start accepts. Automaton has 5727 states and 7938 transitions. Word has length 149 [2018-12-08 09:00:58,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:58,256 INFO L480 AbstractCegarLoop]: Abstraction has 5727 states and 7938 transitions. [2018-12-08 09:00:58,256 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-08 09:00:58,256 INFO L276 IsEmpty]: Start isEmpty. Operand 5727 states and 7938 transitions. [2018-12-08 09:00:58,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-12-08 09:00:58,259 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:58,259 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:58,260 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:58,260 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:58,260 INFO L82 PathProgramCache]: Analyzing trace with hash 219884168, now seen corresponding path program 1 times [2018-12-08 09:00:58,260 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:58,260 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:58,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:58,260 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:58,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:58,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:58,311 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 47 proven. 4 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-08 09:00:58,311 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:00:58,311 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:00:58,319 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:58,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:58,397 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:00:58,410 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 53 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-12-08 09:00:58,425 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:00:58,425 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-12-08 09:00:58,426 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-08 09:00:58,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-08 09:00:58,426 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-08 09:00:58,426 INFO L87 Difference]: Start difference. First operand 5727 states and 7938 transitions. Second operand 5 states. [2018-12-08 09:00:58,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:00:58,980 INFO L93 Difference]: Finished difference Result 15083 states and 21140 transitions. [2018-12-08 09:00:58,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-08 09:00:58,980 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 161 [2018-12-08 09:00:58,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:00:58,993 INFO L225 Difference]: With dead ends: 15083 [2018-12-08 09:00:58,993 INFO L226 Difference]: Without dead ends: 8750 [2018-12-08 09:00:59,003 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 166 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-12-08 09:00:59,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8750 states. [2018-12-08 09:00:59,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8750 to 8388. [2018-12-08 09:00:59,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8388 states. [2018-12-08 09:00:59,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8388 states to 8388 states and 10812 transitions. [2018-12-08 09:00:59,396 INFO L78 Accepts]: Start accepts. Automaton has 8388 states and 10812 transitions. Word has length 161 [2018-12-08 09:00:59,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:00:59,397 INFO L480 AbstractCegarLoop]: Abstraction has 8388 states and 10812 transitions. [2018-12-08 09:00:59,397 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-08 09:00:59,397 INFO L276 IsEmpty]: Start isEmpty. Operand 8388 states and 10812 transitions. [2018-12-08 09:00:59,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-12-08 09:00:59,402 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:00:59,402 INFO L402 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:00:59,403 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:00:59,403 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:00:59,403 INFO L82 PathProgramCache]: Analyzing trace with hash 87439354, now seen corresponding path program 1 times [2018-12-08 09:00:59,403 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:00:59,403 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:00:59,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:59,404 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:59,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:00:59,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:59,461 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 37 proven. 10 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-12-08 09:00:59,461 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:00:59,461 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:00:59,467 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:00:59,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:00:59,565 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:00:59,578 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 53 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-08 09:00:59,592 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:00:59,592 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-08 09:00:59,593 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:00:59,593 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:00:59,593 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:00:59,593 INFO L87 Difference]: Start difference. First operand 8388 states and 10812 transitions. Second operand 6 states. [2018-12-08 09:01:00,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:01:00,170 INFO L93 Difference]: Finished difference Result 17271 states and 22367 transitions. [2018-12-08 09:01:00,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-08 09:01:00,170 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 162 [2018-12-08 09:01:00,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:01:00,183 INFO L225 Difference]: With dead ends: 17271 [2018-12-08 09:01:00,183 INFO L226 Difference]: Without dead ends: 8915 [2018-12-08 09:01:00,193 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 166 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-12-08 09:01:00,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8915 states. [2018-12-08 09:01:00,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8915 to 8905. [2018-12-08 09:01:00,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8905 states. [2018-12-08 09:01:00,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8905 states to 8905 states and 11030 transitions. [2018-12-08 09:01:00,583 INFO L78 Accepts]: Start accepts. Automaton has 8905 states and 11030 transitions. Word has length 162 [2018-12-08 09:01:00,584 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:01:00,584 INFO L480 AbstractCegarLoop]: Abstraction has 8905 states and 11030 transitions. [2018-12-08 09:01:00,584 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:01:00,584 INFO L276 IsEmpty]: Start isEmpty. Operand 8905 states and 11030 transitions. [2018-12-08 09:01:00,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-12-08 09:01:00,587 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:01:00,588 INFO L402 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:01:00,588 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:01:00,588 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:01:00,588 INFO L82 PathProgramCache]: Analyzing trace with hash 2146619520, now seen corresponding path program 1 times [2018-12-08 09:01:00,588 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:01:00,588 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:01:00,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:00,588 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:01:00,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:00,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:01:00,644 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 39 proven. 8 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-08 09:01:00,644 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:01:00,644 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:01:00,651 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:01:00,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:01:00,720 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:01:00,734 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-12-08 09:01:00,750 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:01:00,750 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-08 09:01:00,750 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-08 09:01:00,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-08 09:01:00,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-08 09:01:00,750 INFO L87 Difference]: Start difference. First operand 8905 states and 11030 transitions. Second operand 6 states. [2018-12-08 09:01:01,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:01:01,316 INFO L93 Difference]: Finished difference Result 14050 states and 17408 transitions. [2018-12-08 09:01:01,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-08 09:01:01,317 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 164 [2018-12-08 09:01:01,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:01:01,324 INFO L225 Difference]: With dead ends: 14050 [2018-12-08 09:01:01,324 INFO L226 Difference]: Without dead ends: 6235 [2018-12-08 09:01:01,329 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 180 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-12-08 09:01:01,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6235 states. [2018-12-08 09:01:01,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6235 to 6021. [2018-12-08 09:01:01,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6021 states. [2018-12-08 09:01:01,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6021 states to 6021 states and 7251 transitions. [2018-12-08 09:01:01,604 INFO L78 Accepts]: Start accepts. Automaton has 6021 states and 7251 transitions. Word has length 164 [2018-12-08 09:01:01,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:01:01,605 INFO L480 AbstractCegarLoop]: Abstraction has 6021 states and 7251 transitions. [2018-12-08 09:01:01,605 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-08 09:01:01,605 INFO L276 IsEmpty]: Start isEmpty. Operand 6021 states and 7251 transitions. [2018-12-08 09:01:01,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-12-08 09:01:01,606 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:01:01,607 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:01:01,607 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:01:01,607 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:01:01,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1404636156, now seen corresponding path program 1 times [2018-12-08 09:01:01,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:01:01,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:01:01,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:01,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:01:01,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:01,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:01:01,823 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 43 proven. 65 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-08 09:01:01,823 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:01:01,823 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:01:01,831 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:01:01,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:01:01,916 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:01:01,979 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 71 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-08 09:01:02,004 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-08 09:01:02,004 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [16] total 20 [2018-12-08 09:01:02,005 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-12-08 09:01:02,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-12-08 09:01:02,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=340, Unknown=0, NotChecked=0, Total=380 [2018-12-08 09:01:02,005 INFO L87 Difference]: Start difference. First operand 6021 states and 7251 transitions. Second operand 20 states. [2018-12-08 09:01:13,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:01:13,100 INFO L93 Difference]: Finished difference Result 20049 states and 24726 transitions. [2018-12-08 09:01:13,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 189 states. [2018-12-08 09:01:13,100 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 212 [2018-12-08 09:01:13,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:01:13,121 INFO L225 Difference]: With dead ends: 20049 [2018-12-08 09:01:13,121 INFO L226 Difference]: Without dead ends: 15150 [2018-12-08 09:01:13,133 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 513 GetRequests, 308 SyntacticMatches, 1 SemanticMatches, 204 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17347 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=3050, Invalid=39180, Unknown=0, NotChecked=0, Total=42230 [2018-12-08 09:01:13,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15150 states. [2018-12-08 09:01:13,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15150 to 12458. [2018-12-08 09:01:13,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12458 states. [2018-12-08 09:01:13,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12458 states to 12458 states and 15070 transitions. [2018-12-08 09:01:13,804 INFO L78 Accepts]: Start accepts. Automaton has 12458 states and 15070 transitions. Word has length 212 [2018-12-08 09:01:13,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:01:13,804 INFO L480 AbstractCegarLoop]: Abstraction has 12458 states and 15070 transitions. [2018-12-08 09:01:13,804 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-12-08 09:01:13,804 INFO L276 IsEmpty]: Start isEmpty. Operand 12458 states and 15070 transitions. [2018-12-08 09:01:13,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-12-08 09:01:13,806 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:01:13,806 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:01:13,806 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:01:13,806 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:01:13,807 INFO L82 PathProgramCache]: Analyzing trace with hash -1746786478, now seen corresponding path program 1 times [2018-12-08 09:01:13,807 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:01:13,807 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:01:13,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:13,807 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:01:13,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:13,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:01:13,842 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 85 proven. 0 refuted. 0 times theorem prover too weak. 47 trivial. 0 not checked. [2018-12-08 09:01:13,842 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-08 09:01:13,842 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-08 09:01:13,843 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-08 09:01:13,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-08 09:01:13,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:01:13,843 INFO L87 Difference]: Start difference. First operand 12458 states and 15070 transitions. Second operand 3 states. [2018-12-08 09:01:14,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:01:14,446 INFO L93 Difference]: Finished difference Result 21224 states and 26099 transitions. [2018-12-08 09:01:14,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-08 09:01:14,446 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 234 [2018-12-08 09:01:14,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:01:14,463 INFO L225 Difference]: With dead ends: 21224 [2018-12-08 09:01:14,463 INFO L226 Difference]: Without dead ends: 11109 [2018-12-08 09:01:14,477 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-08 09:01:14,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11109 states. [2018-12-08 09:01:15,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11109 to 11001. [2018-12-08 09:01:15,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11001 states. [2018-12-08 09:01:15,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11001 states to 11001 states and 13140 transitions. [2018-12-08 09:01:15,175 INFO L78 Accepts]: Start accepts. Automaton has 11001 states and 13140 transitions. Word has length 234 [2018-12-08 09:01:15,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:01:15,175 INFO L480 AbstractCegarLoop]: Abstraction has 11001 states and 13140 transitions. [2018-12-08 09:01:15,175 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-08 09:01:15,175 INFO L276 IsEmpty]: Start isEmpty. Operand 11001 states and 13140 transitions. [2018-12-08 09:01:15,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-12-08 09:01:15,177 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:01:15,177 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:01:15,177 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:01:15,177 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:01:15,177 INFO L82 PathProgramCache]: Analyzing trace with hash -1718286188, now seen corresponding path program 1 times [2018-12-08 09:01:15,177 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:01:15,177 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:01:15,178 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:15,178 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:01:15,178 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:15,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:01:15,363 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 49 proven. 67 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-08 09:01:15,363 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-08 09:01:15,363 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-08 09:01:15,370 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:01:15,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-08 09:01:15,449 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-08 09:01:15,586 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 102 proven. 15 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-08 09:01:15,601 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-12-08 09:01:15,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 15] total 22 [2018-12-08 09:01:15,601 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-12-08 09:01:15,601 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-12-08 09:01:15,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=410, Unknown=0, NotChecked=0, Total=462 [2018-12-08 09:01:15,602 INFO L87 Difference]: Start difference. First operand 11001 states and 13140 transitions. Second operand 22 states. [2018-12-08 09:01:28,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-08 09:01:28,466 INFO L93 Difference]: Finished difference Result 24780 states and 29827 transitions. [2018-12-08 09:01:28,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2018-12-08 09:01:28,466 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 234 [2018-12-08 09:01:28,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-08 09:01:28,501 INFO L225 Difference]: With dead ends: 24780 [2018-12-08 09:01:28,501 INFO L226 Difference]: Without dead ends: 15696 [2018-12-08 09:01:28,516 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 446 GetRequests, 319 SyntacticMatches, 5 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5333 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1292, Invalid=13960, Unknown=0, NotChecked=0, Total=15252 [2018-12-08 09:01:28,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15696 states. [2018-12-08 09:01:29,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15696 to 14190. [2018-12-08 09:01:29,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14190 states. [2018-12-08 09:01:29,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14190 states to 14190 states and 16980 transitions. [2018-12-08 09:01:29,325 INFO L78 Accepts]: Start accepts. Automaton has 14190 states and 16980 transitions. Word has length 234 [2018-12-08 09:01:29,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-08 09:01:29,326 INFO L480 AbstractCegarLoop]: Abstraction has 14190 states and 16980 transitions. [2018-12-08 09:01:29,326 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-12-08 09:01:29,326 INFO L276 IsEmpty]: Start isEmpty. Operand 14190 states and 16980 transitions. [2018-12-08 09:01:29,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 236 [2018-12-08 09:01:29,328 INFO L394 BasicCegarLoop]: Found error trace [2018-12-08 09:01:29,328 INFO L402 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-08 09:01:29,328 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-08 09:01:29,328 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-08 09:01:29,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1727712869, now seen corresponding path program 1 times [2018-12-08 09:01:29,328 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-08 09:01:29,328 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-08 09:01:29,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:29,329 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-08 09:01:29,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-08 09:01:29,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 09:01:29,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-08 09:01:29,414 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-08 09:01:29,520 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 08.12 09:01:29 BoogieIcfgContainer [2018-12-08 09:01:29,520 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-08 09:01:29,520 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-08 09:01:29,520 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-08 09:01:29,520 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-08 09:01:29,521 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.12 09:00:46" (3/4) ... [2018-12-08 09:01:29,522 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-08 09:01:29,628 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_2ab5c0f8-4238-4f23-bfa6-63e855a1ea61/bin-2019/uautomizer/witness.graphml [2018-12-08 09:01:29,628 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-08 09:01:29,629 INFO L168 Benchmark]: Toolchain (without parser) took 43579.67 ms. Allocated memory was 1.0 GB in the beginning and 3.4 GB in the end (delta: 2.3 GB). Free memory was 957.1 MB in the beginning and 997.1 MB in the end (delta: -40.0 MB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2018-12-08 09:01:29,629 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-08 09:01:29,629 INFO L168 Benchmark]: CACSL2BoogieTranslator took 175.90 ms. Allocated memory is still 1.0 GB. Free memory was 957.1 MB in the beginning and 941.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-12-08 09:01:29,630 INFO L168 Benchmark]: Boogie Procedure Inliner took 43.39 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 129.5 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -179.8 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. [2018-12-08 09:01:29,630 INFO L168 Benchmark]: Boogie Preprocessor took 22.99 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-08 09:01:29,630 INFO L168 Benchmark]: RCFGBuilder took 323.71 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.8 MB). Peak memory consumption was 47.8 MB. Max. memory is 11.5 GB. [2018-12-08 09:01:29,630 INFO L168 Benchmark]: TraceAbstraction took 42903.07 ms. Allocated memory was 1.2 GB in the beginning and 3.4 GB in the end (delta: 2.2 GB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 28.2 MB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. [2018-12-08 09:01:29,630 INFO L168 Benchmark]: Witness Printer took 107.99 ms. Allocated memory is still 3.4 GB. Free memory was 1.0 GB in the beginning and 997.1 MB in the end (delta: 47.6 MB). Peak memory consumption was 47.6 MB. Max. memory is 11.5 GB. [2018-12-08 09:01:29,631 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 175.90 ms. Allocated memory is still 1.0 GB. Free memory was 957.1 MB in the beginning and 941.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 43.39 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 129.5 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -179.8 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 22.99 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 323.71 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.8 MB). Peak memory consumption was 47.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 42903.07 ms. Allocated memory was 1.2 GB in the beginning and 3.4 GB in the end (delta: 2.2 GB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 28.2 MB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. * Witness Printer took 107.99 ms. Allocated memory is still 3.4 GB. Free memory was 1.0 GB in the beginning and 997.1 MB in the end (delta: 47.6 MB). Peak memory consumption was 47.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [\old(c)=17, \old(c1_i)=4, \old(c1_pc)=29, \old(c1_st)=24, \old(c2_i)=14, \old(c2_pc)=28, \old(c2_st)=25, \old(c_req_up)=30, \old(c_t)=20, \old(d)=23, \old(data)=18, \old(e_c)=11, \old(e_e)=31, \old(e_f)=21, \old(e_g)=10, \old(e_p_in)=8, \old(e_wl)=13, \old(p_in)=15, \old(p_out)=9, \old(processed)=16, \old(r_i)=26, \old(r_st)=7, \old(t_b)=12, \old(wb_i)=5, \old(wb_pc)=19, \old(wb_st)=3, \old(wl_i)=27, \old(wl_pc)=22, \old(wl_st)=6, c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L691] int __retres1 ; [L695] e_wl = 2 [L696] e_c = e_wl [L697] e_g = e_c [L698] e_f = e_g [L699] e_e = e_f [L700] wl_pc = 0 [L701] c1_pc = 0 [L702] c2_pc = 0 [L703] wb_pc = 0 [L704] wb_i = 1 [L705] c2_i = wb_i [L706] c1_i = c2_i [L707] wl_i = c1_i [L708] r_i = 0 [L709] c_req_up = 0 [L710] d = 0 [L711] c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=0, \old(e_e)=0, \old(e_f)=0, \old(e_g)=0, \old(e_wl)=0, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L712] CALL start_simulation() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L402] int kernel_st ; [L405] kernel_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L406] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L417] COND TRUE (int )wl_i == 1 [L418] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L422] COND TRUE (int )c1_i == 1 [L423] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L427] COND TRUE (int )c2_i == 1 [L428] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L432] COND TRUE (int )wb_i == 1 [L433] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L437] COND FALSE !((int )r_i == 1) [L440] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L442] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L447] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L452] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L457] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L462] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L467] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L475] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L485] COND FALSE !((int )c1_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L494] COND FALSE !((int )c2_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L503] COND FALSE !((int )wb_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L512] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L517] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L522] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L527] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L532] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L537] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L326] RET write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L341] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L139] COND TRUE (int )c1_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L150] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L341] RET compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L356] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L184] COND TRUE (int )c2_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L195] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L356] RET compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L371] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L229] COND TRUE (int )wb_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L240] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L371] RET write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L547] RET eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L561] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L577] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L582] COND TRUE (int )e_wl == 0 [L583] e_wl = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L587] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L588] COND TRUE (int )e_wl == 1 [L589] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L605] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L606] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L614] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L615] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L623] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L624] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L632] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L637] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L642] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L647] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L652] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L657] COND TRUE (int )e_wl == 1 [L658] e_wl = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L662] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L326] RET write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L341] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L139] COND FALSE !((int )c1_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L142] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L157] COND TRUE ! processed [L158] data += 1 [L159] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L160] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L161] COND TRUE (int )e_g == 1 [L162] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L169] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L150] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L341] RET compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L356] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L184] COND FALSE !((int )c2_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L187] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] COND TRUE ! processed [L203] data += 1 [L204] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L205] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L206] COND TRUE (int )e_g == 1 [L207] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L214] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L195] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L356] RET compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L371] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L229] COND FALSE !((int )wb_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L232] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L247] c_t = data [L248] c_req_up = 1 [L249] processed = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L240] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L371] RET write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L547] RET eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND TRUE (int )c_req_up == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L551] COND TRUE c != c_t [L552] c = c_t [L553] e_c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L557] c_req_up = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L561] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L577] COND TRUE (int )e_c == 0 [L578] e_c = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L582] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L587] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L595] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L596] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L605] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L606] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L614] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L615] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L623] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L624] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L632] COND TRUE (int )e_c == 1 [L633] r_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L637] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L642] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L647] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L652] COND TRUE (int )e_c == 1 [L653] e_c = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L657] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L665] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L668] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L671] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L674] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L319] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L349] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L364] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND TRUE (int )r_st == 0 [L381] tmp___3 = __VERIFIER_nondet_int() [L383] COND TRUE \read(tmp___3) [L385] r_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L386] CALL read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L261] d = c [L262] e_e = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L263] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L271] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L272] COND TRUE (int )e_e == 1 [L273] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L281] e_e = 2 [L282] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L386] RET read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L112] COND TRUE d == t + 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L120] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L124] CALL error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 11 procedures, 161 locations, 1 error locations. UNSAFE Result, 42.8s OverallTime, 27 OverallIterations, 6 TraceHistogramMax, 33.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9297 SDtfs, 27694 SDslu, 29347 SDs, 0 SdLazy, 28055 SolverSat, 5283 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 15.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2162 GetRequests, 1697 SyntacticMatches, 15 SemanticMatches, 450 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22926 ImplicationChecksByTransitivity, 7.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=14190occurred in iteration=26, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 6.2s AutomataMinimizationTime, 26 MinimizatonAttempts, 11661 StatesRemovedByMinimization, 23 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 1.4s InterpolantComputationTime, 4508 NumberOfCodeBlocks, 4508 NumberOfCodeBlocksAsserted, 36 NumberOfCheckSat, 4238 ConstructedInterpolants, 0 QuantifiedInterpolants, 1616003 SizeOfPredicates, 12 NumberOfNonLiveVariables, 9317 ConjunctsInSsa, 65 ConjunctsInUnsatCore, 35 InterpolantComputations, 25 PerfectInterpolantSequences, 1442/1642 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...