./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0c244c639ec9718adcbacffa967b748c52a23cd0 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-09 12:31:33,197 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 12:31:33,198 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 12:31:33,203 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 12:31:33,204 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 12:31:33,204 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 12:31:33,205 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 12:31:33,206 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 12:31:33,206 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 12:31:33,207 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 12:31:33,207 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 12:31:33,207 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 12:31:33,208 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 12:31:33,208 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 12:31:33,209 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 12:31:33,209 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 12:31:33,209 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 12:31:33,210 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 12:31:33,211 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 12:31:33,212 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 12:31:33,212 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 12:31:33,213 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 12:31:33,214 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 12:31:33,214 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 12:31:33,214 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 12:31:33,215 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 12:31:33,215 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 12:31:33,215 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 12:31:33,216 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 12:31:33,216 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 12:31:33,216 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 12:31:33,217 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 12:31:33,217 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 12:31:33,217 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 12:31:33,217 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 12:31:33,218 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 12:31:33,218 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-12-09 12:31:33,224 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 12:31:33,225 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 12:31:33,225 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 12:31:33,225 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 12:31:33,226 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * Use SBE=true [2018-12-09 12:31:33,226 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 12:31:33,226 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-09 12:31:33,227 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 12:31:33,227 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 12:31:33,227 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 12:31:33,228 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-09 12:31:33,228 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-09 12:31:33,228 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 12:31:33,228 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-09 12:31:33,228 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0c244c639ec9718adcbacffa967b748c52a23cd0 [2018-12-09 12:31:33,245 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 12:31:33,253 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 12:31:33,255 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 12:31:33,256 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 12:31:33,256 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 12:31:33,256 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-12-09 12:31:33,293 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/data/4edfa0455/7d7c23a4c9e248faa383b6ed18e9fee7/FLAGc91ab1573 [2018-12-09 12:31:33,725 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 12:31:33,725 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-12-09 12:31:33,730 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/data/4edfa0455/7d7c23a4c9e248faa383b6ed18e9fee7/FLAGc91ab1573 [2018-12-09 12:31:33,738 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/data/4edfa0455/7d7c23a4c9e248faa383b6ed18e9fee7 [2018-12-09 12:31:33,740 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 12:31:33,741 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-09 12:31:33,741 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 12:31:33,741 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 12:31:33,744 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 12:31:33,744 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,746 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@643265e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33, skipping insertion in model container [2018-12-09 12:31:33,746 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,750 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 12:31:33,766 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 12:31:33,867 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 12:31:33,871 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 12:31:33,892 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 12:31:33,902 INFO L195 MainTranslator]: Completed translation [2018-12-09 12:31:33,902 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33 WrapperNode [2018-12-09 12:31:33,902 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 12:31:33,903 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-09 12:31:33,903 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-09 12:31:33,903 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-09 12:31:33,907 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,911 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,947 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-09 12:31:33,947 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 12:31:33,947 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 12:31:33,947 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 12:31:33,955 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,955 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,957 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,957 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,963 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,969 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,970 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... [2018-12-09 12:31:33,972 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 12:31:33,972 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 12:31:33,972 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 12:31:33,972 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 12:31:33,972 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 12:31:34,003 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-12-09 12:31:34,003 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-12-09 12:31:34,003 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-12-09 12:31:34,003 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-12-09 12:31:34,003 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 12:31:34,003 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 12:31:34,003 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-09 12:31:34,004 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-09 12:31:34,004 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-09 12:31:34,004 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-09 12:31:34,004 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-12-09 12:31:34,004 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-12-09 12:31:34,004 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-09 12:31:34,004 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-09 12:31:34,004 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-12-09 12:31:34,004 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-12-09 12:31:34,004 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-09 12:31:34,004 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-09 12:31:34,005 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-09 12:31:34,005 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-09 12:31:34,005 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-12-09 12:31:34,005 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-12-09 12:31:34,005 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-09 12:31:34,005 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-09 12:31:34,005 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-09 12:31:34,005 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-09 12:31:34,005 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-12-09 12:31:34,005 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-12-09 12:31:34,005 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-09 12:31:34,006 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-09 12:31:34,006 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-12-09 12:31:34,006 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-12-09 12:31:34,006 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-09 12:31:34,006 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-09 12:31:34,006 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 12:31:34,006 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 12:31:34,006 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-09 12:31:34,006 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-09 12:31:34,006 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-09 12:31:34,006 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-09 12:31:34,006 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-09 12:31:34,006 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-09 12:31:34,007 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 12:31:34,007 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 12:31:34,007 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-09 12:31:34,007 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-09 12:31:34,234 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 12:31:34,234 INFO L280 CfgBuilder]: Removed 6 assue(true) statements. [2018-12-09 12:31:34,234 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 12:31:34 BoogieIcfgContainer [2018-12-09 12:31:34,234 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 12:31:34,235 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 12:31:34,235 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 12:31:34,237 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 12:31:34,237 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 12:31:33" (1/3) ... [2018-12-09 12:31:34,237 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ac7c9db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 12:31:34, skipping insertion in model container [2018-12-09 12:31:34,237 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:31:33" (2/3) ... [2018-12-09 12:31:34,238 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ac7c9db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 12:31:34, skipping insertion in model container [2018-12-09 12:31:34,238 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 12:31:34" (3/3) ... [2018-12-09 12:31:34,239 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.02_false-unreach-call_false-termination.cil.c [2018-12-09 12:31:34,244 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 12:31:34,250 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-09 12:31:34,263 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-09 12:31:34,289 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-09 12:31:34,289 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 12:31:34,289 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-09 12:31:34,290 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 12:31:34,290 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 12:31:34,290 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 12:31:34,290 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 12:31:34,290 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 12:31:34,290 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 12:31:34,302 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states. [2018-12-09 12:31:34,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:34,307 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:34,308 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:34,309 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:34,312 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:34,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1029162199, now seen corresponding path program 1 times [2018-12-09 12:31:34,313 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:34,314 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:34,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:34,342 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:34,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:34,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:34,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:34,454 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:34,454 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:31:34,457 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:31:34,464 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:31:34,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:31:34,466 INFO L87 Difference]: Start difference. First operand 169 states. Second operand 4 states. [2018-12-09 12:31:34,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:34,581 INFO L93 Difference]: Finished difference Result 320 states and 454 transitions. [2018-12-09 12:31:34,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:31:34,583 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 90 [2018-12-09 12:31:34,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:34,593 INFO L225 Difference]: With dead ends: 320 [2018-12-09 12:31:34,594 INFO L226 Difference]: Without dead ends: 160 [2018-12-09 12:31:34,596 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:31:34,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-12-09 12:31:34,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 160. [2018-12-09 12:31:34,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-09 12:31:34,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 212 transitions. [2018-12-09 12:31:34,631 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 212 transitions. Word has length 90 [2018-12-09 12:31:34,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:34,632 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 212 transitions. [2018-12-09 12:31:34,632 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:31:34,632 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 212 transitions. [2018-12-09 12:31:34,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:34,634 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:34,634 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:34,634 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:34,634 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:34,634 INFO L82 PathProgramCache]: Analyzing trace with hash 881880359, now seen corresponding path program 1 times [2018-12-09 12:31:34,634 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:34,635 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:34,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:34,635 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:34,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:34,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:34,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:34,715 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:34,715 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:34,716 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:34,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:34,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:34,716 INFO L87 Difference]: Start difference. First operand 160 states and 212 transitions. Second operand 5 states. [2018-12-09 12:31:34,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:34,964 INFO L93 Difference]: Finished difference Result 328 states and 450 transitions. [2018-12-09 12:31:34,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:31:34,965 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:34,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:34,966 INFO L225 Difference]: With dead ends: 328 [2018-12-09 12:31:34,966 INFO L226 Difference]: Without dead ends: 188 [2018-12-09 12:31:34,967 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:34,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-12-09 12:31:34,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 160. [2018-12-09 12:31:34,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-09 12:31:34,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 211 transitions. [2018-12-09 12:31:34,980 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 211 transitions. Word has length 90 [2018-12-09 12:31:34,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:34,980 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 211 transitions. [2018-12-09 12:31:34,980 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:34,981 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 211 transitions. [2018-12-09 12:31:34,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:34,981 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:34,982 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:34,982 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:34,982 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:34,982 INFO L82 PathProgramCache]: Analyzing trace with hash 1835820517, now seen corresponding path program 1 times [2018-12-09 12:31:34,982 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:34,982 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:34,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:34,983 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:34,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:34,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:35,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:35,050 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:35,050 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:35,051 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:35,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:35,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:35,051 INFO L87 Difference]: Start difference. First operand 160 states and 211 transitions. Second operand 5 states. [2018-12-09 12:31:35,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:35,272 INFO L93 Difference]: Finished difference Result 328 states and 449 transitions. [2018-12-09 12:31:35,272 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:31:35,273 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:35,273 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:35,274 INFO L225 Difference]: With dead ends: 328 [2018-12-09 12:31:35,274 INFO L226 Difference]: Without dead ends: 188 [2018-12-09 12:31:35,274 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:35,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-12-09 12:31:35,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 160. [2018-12-09 12:31:35,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-09 12:31:35,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 210 transitions. [2018-12-09 12:31:35,285 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 210 transitions. Word has length 90 [2018-12-09 12:31:35,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:35,285 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 210 transitions. [2018-12-09 12:31:35,285 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:35,285 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 210 transitions. [2018-12-09 12:31:35,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:35,286 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:35,286 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:35,286 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:35,286 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:35,286 INFO L82 PathProgramCache]: Analyzing trace with hash 619666791, now seen corresponding path program 1 times [2018-12-09 12:31:35,286 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:35,286 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:35,287 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:35,287 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:35,287 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:35,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:35,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:35,329 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:35,329 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:35,329 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:35,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:35,330 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:35,330 INFO L87 Difference]: Start difference. First operand 160 states and 210 transitions. Second operand 5 states. [2018-12-09 12:31:35,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:35,561 INFO L93 Difference]: Finished difference Result 326 states and 443 transitions. [2018-12-09 12:31:35,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:31:35,561 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:35,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:35,562 INFO L225 Difference]: With dead ends: 326 [2018-12-09 12:31:35,562 INFO L226 Difference]: Without dead ends: 186 [2018-12-09 12:31:35,563 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:35,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-12-09 12:31:35,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 160. [2018-12-09 12:31:35,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-09 12:31:35,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 209 transitions. [2018-12-09 12:31:35,577 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 209 transitions. Word has length 90 [2018-12-09 12:31:35,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:35,577 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 209 transitions. [2018-12-09 12:31:35,577 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:35,577 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 209 transitions. [2018-12-09 12:31:35,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:35,578 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:35,578 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:35,579 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:35,579 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:35,579 INFO L82 PathProgramCache]: Analyzing trace with hash -112300635, now seen corresponding path program 1 times [2018-12-09 12:31:35,579 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:35,579 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:35,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:35,580 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:35,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:35,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:35,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:35,622 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:35,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:35,623 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:35,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:35,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:35,623 INFO L87 Difference]: Start difference. First operand 160 states and 209 transitions. Second operand 5 states. [2018-12-09 12:31:35,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:35,831 INFO L93 Difference]: Finished difference Result 343 states and 469 transitions. [2018-12-09 12:31:35,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:31:35,831 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:35,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:35,832 INFO L225 Difference]: With dead ends: 343 [2018-12-09 12:31:35,833 INFO L226 Difference]: Without dead ends: 203 [2018-12-09 12:31:35,833 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:35,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states. [2018-12-09 12:31:35,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 160. [2018-12-09 12:31:35,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-09 12:31:35,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 208 transitions. [2018-12-09 12:31:35,843 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 208 transitions. Word has length 90 [2018-12-09 12:31:35,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:35,844 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 208 transitions. [2018-12-09 12:31:35,844 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:35,844 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 208 transitions. [2018-12-09 12:31:35,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:35,845 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:35,845 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:35,845 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:35,845 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:35,845 INFO L82 PathProgramCache]: Analyzing trace with hash -1798480473, now seen corresponding path program 1 times [2018-12-09 12:31:35,845 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:35,845 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:35,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:35,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:35,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:35,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:35,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:35,891 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:35,891 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:35,892 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:35,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:35,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:35,892 INFO L87 Difference]: Start difference. First operand 160 states and 208 transitions. Second operand 5 states. [2018-12-09 12:31:36,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:36,114 INFO L93 Difference]: Finished difference Result 341 states and 463 transitions. [2018-12-09 12:31:36,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:31:36,114 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:36,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:36,116 INFO L225 Difference]: With dead ends: 341 [2018-12-09 12:31:36,116 INFO L226 Difference]: Without dead ends: 201 [2018-12-09 12:31:36,117 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:36,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-12-09 12:31:36,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 160. [2018-12-09 12:31:36,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-12-09 12:31:36,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 207 transitions. [2018-12-09 12:31:36,131 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 207 transitions. Word has length 90 [2018-12-09 12:31:36,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:36,131 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 207 transitions. [2018-12-09 12:31:36,131 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:36,131 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 207 transitions. [2018-12-09 12:31:36,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:36,132 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:36,132 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:36,132 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:36,132 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:36,132 INFO L82 PathProgramCache]: Analyzing trace with hash -1852873371, now seen corresponding path program 1 times [2018-12-09 12:31:36,132 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:36,132 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:36,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,133 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:36,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:36,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:36,166 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:36,166 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:31:36,166 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:31:36,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:31:36,167 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:36,167 INFO L87 Difference]: Start difference. First operand 160 states and 207 transitions. Second operand 6 states. [2018-12-09 12:31:36,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:36,205 INFO L93 Difference]: Finished difference Result 312 states and 418 transitions. [2018-12-09 12:31:36,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:31:36,205 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2018-12-09 12:31:36,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:36,207 INFO L225 Difference]: With dead ends: 312 [2018-12-09 12:31:36,207 INFO L226 Difference]: Without dead ends: 173 [2018-12-09 12:31:36,208 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:31:36,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-12-09 12:31:36,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 165. [2018-12-09 12:31:36,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-12-09 12:31:36,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 212 transitions. [2018-12-09 12:31:36,222 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 212 transitions. Word has length 90 [2018-12-09 12:31:36,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:36,222 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 212 transitions. [2018-12-09 12:31:36,223 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:31:36,223 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 212 transitions. [2018-12-09 12:31:36,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:36,223 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:36,223 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:36,223 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:36,223 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:36,224 INFO L82 PathProgramCache]: Analyzing trace with hash 413507815, now seen corresponding path program 1 times [2018-12-09 12:31:36,224 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:36,224 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:36,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,224 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:36,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:36,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:36,253 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:36,253 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:31:36,253 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:31:36,253 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:31:36,254 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:36,254 INFO L87 Difference]: Start difference. First operand 165 states and 212 transitions. Second operand 6 states. [2018-12-09 12:31:36,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:36,282 INFO L93 Difference]: Finished difference Result 319 states and 423 transitions. [2018-12-09 12:31:36,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:31:36,282 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2018-12-09 12:31:36,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:36,283 INFO L225 Difference]: With dead ends: 319 [2018-12-09 12:31:36,283 INFO L226 Difference]: Without dead ends: 175 [2018-12-09 12:31:36,284 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:31:36,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-12-09 12:31:36,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 170. [2018-12-09 12:31:36,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-12-09 12:31:36,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 217 transitions. [2018-12-09 12:31:36,297 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 217 transitions. Word has length 90 [2018-12-09 12:31:36,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:36,297 INFO L480 AbstractCegarLoop]: Abstraction has 170 states and 217 transitions. [2018-12-09 12:31:36,297 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:31:36,297 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 217 transitions. [2018-12-09 12:31:36,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:36,298 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:36,298 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:36,299 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:36,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:36,299 INFO L82 PathProgramCache]: Analyzing trace with hash 661654309, now seen corresponding path program 1 times [2018-12-09 12:31:36,299 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:36,299 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:36,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:36,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:36,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:36,337 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:36,337 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:31:36,337 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:31:36,337 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:31:36,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:36,337 INFO L87 Difference]: Start difference. First operand 170 states and 217 transitions. Second operand 6 states. [2018-12-09 12:31:36,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:36,362 INFO L93 Difference]: Finished difference Result 326 states and 428 transitions. [2018-12-09 12:31:36,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:31:36,362 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2018-12-09 12:31:36,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:36,363 INFO L225 Difference]: With dead ends: 326 [2018-12-09 12:31:36,364 INFO L226 Difference]: Without dead ends: 177 [2018-12-09 12:31:36,364 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:31:36,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-12-09 12:31:36,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 175. [2018-12-09 12:31:36,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-12-09 12:31:36,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 222 transitions. [2018-12-09 12:31:36,372 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 222 transitions. Word has length 90 [2018-12-09 12:31:36,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:36,373 INFO L480 AbstractCegarLoop]: Abstraction has 175 states and 222 transitions. [2018-12-09 12:31:36,373 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:31:36,373 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 222 transitions. [2018-12-09 12:31:36,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:36,374 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:36,374 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:36,374 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:36,374 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:36,374 INFO L82 PathProgramCache]: Analyzing trace with hash 589267751, now seen corresponding path program 1 times [2018-12-09 12:31:36,374 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:36,375 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:36,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,375 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:36,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:36,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:36,416 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:36,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:36,417 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:36,417 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:36,417 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:36,417 INFO L87 Difference]: Start difference. First operand 175 states and 222 transitions. Second operand 5 states. [2018-12-09 12:31:36,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:36,720 INFO L93 Difference]: Finished difference Result 428 states and 562 transitions. [2018-12-09 12:31:36,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 12:31:36,720 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:36,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:36,721 INFO L225 Difference]: With dead ends: 428 [2018-12-09 12:31:36,721 INFO L226 Difference]: Without dead ends: 274 [2018-12-09 12:31:36,722 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-09 12:31:36,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-12-09 12:31:36,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 226. [2018-12-09 12:31:36,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-12-09 12:31:36,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 285 transitions. [2018-12-09 12:31:36,736 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 285 transitions. Word has length 90 [2018-12-09 12:31:36,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:36,736 INFO L480 AbstractCegarLoop]: Abstraction has 226 states and 285 transitions. [2018-12-09 12:31:36,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:36,736 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 285 transitions. [2018-12-09 12:31:36,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:36,737 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:36,737 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:36,737 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:36,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:36,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1975471145, now seen corresponding path program 1 times [2018-12-09 12:31:36,738 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:36,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:36,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,738 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:36,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:36,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:36,792 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:36,792 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:36,792 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:36,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:36,792 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:36,792 INFO L87 Difference]: Start difference. First operand 226 states and 285 transitions. Second operand 5 states. [2018-12-09 12:31:36,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:36,956 INFO L93 Difference]: Finished difference Result 430 states and 547 transitions. [2018-12-09 12:31:36,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:31:36,956 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:36,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:36,957 INFO L225 Difference]: With dead ends: 430 [2018-12-09 12:31:36,957 INFO L226 Difference]: Without dead ends: 226 [2018-12-09 12:31:36,958 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:31:36,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-12-09 12:31:36,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 226. [2018-12-09 12:31:36,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-12-09 12:31:36,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 282 transitions. [2018-12-09 12:31:36,969 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 282 transitions. Word has length 90 [2018-12-09 12:31:36,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:36,969 INFO L480 AbstractCegarLoop]: Abstraction has 226 states and 282 transitions. [2018-12-09 12:31:36,970 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:36,970 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 282 transitions. [2018-12-09 12:31:36,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:36,970 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:36,970 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:36,971 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:36,971 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:36,971 INFO L82 PathProgramCache]: Analyzing trace with hash -396268117, now seen corresponding path program 1 times [2018-12-09 12:31:36,971 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:36,971 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:36,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,972 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:36,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:36,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:37,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:37,017 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:37,017 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:37,017 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:37,017 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:37,017 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:37,017 INFO L87 Difference]: Start difference. First operand 226 states and 282 transitions. Second operand 5 states. [2018-12-09 12:31:37,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:37,242 INFO L93 Difference]: Finished difference Result 525 states and 693 transitions. [2018-12-09 12:31:37,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:31:37,242 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:37,242 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:37,243 INFO L225 Difference]: With dead ends: 525 [2018-12-09 12:31:37,243 INFO L226 Difference]: Without dead ends: 320 [2018-12-09 12:31:37,244 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:31:37,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states. [2018-12-09 12:31:37,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 262. [2018-12-09 12:31:37,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2018-12-09 12:31:37,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 320 transitions. [2018-12-09 12:31:37,260 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 320 transitions. Word has length 90 [2018-12-09 12:31:37,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:37,261 INFO L480 AbstractCegarLoop]: Abstraction has 262 states and 320 transitions. [2018-12-09 12:31:37,261 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:37,261 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 320 transitions. [2018-12-09 12:31:37,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:37,261 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:37,262 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:37,262 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:37,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:37,262 INFO L82 PathProgramCache]: Analyzing trace with hash -334228503, now seen corresponding path program 1 times [2018-12-09 12:31:37,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:37,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:37,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:37,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:37,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:37,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:37,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:37,301 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:37,301 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:31:37,302 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:31:37,302 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:31:37,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:31:37,302 INFO L87 Difference]: Start difference. First operand 262 states and 320 transitions. Second operand 5 states. [2018-12-09 12:31:37,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:37,544 INFO L93 Difference]: Finished difference Result 571 states and 739 transitions. [2018-12-09 12:31:37,545 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:31:37,545 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-12-09 12:31:37,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:37,546 INFO L225 Difference]: With dead ends: 571 [2018-12-09 12:31:37,547 INFO L226 Difference]: Without dead ends: 330 [2018-12-09 12:31:37,547 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:31:37,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-12-09 12:31:37,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 287. [2018-12-09 12:31:37,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287 states. [2018-12-09 12:31:37,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287 states to 287 states and 342 transitions. [2018-12-09 12:31:37,563 INFO L78 Accepts]: Start accepts. Automaton has 287 states and 342 transitions. Word has length 90 [2018-12-09 12:31:37,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:37,563 INFO L480 AbstractCegarLoop]: Abstraction has 287 states and 342 transitions. [2018-12-09 12:31:37,563 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:31:37,563 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 342 transitions. [2018-12-09 12:31:37,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-12-09 12:31:37,564 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:37,564 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:37,564 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:37,564 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:37,564 INFO L82 PathProgramCache]: Analyzing trace with hash -193679893, now seen corresponding path program 1 times [2018-12-09 12:31:37,564 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:37,564 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:37,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:37,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:37,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:37,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:37,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:37,580 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:37,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 12:31:37,580 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 12:31:37,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 12:31:37,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:31:37,580 INFO L87 Difference]: Start difference. First operand 287 states and 342 transitions. Second operand 3 states. [2018-12-09 12:31:37,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:37,621 INFO L93 Difference]: Finished difference Result 769 states and 926 transitions. [2018-12-09 12:31:37,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 12:31:37,622 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 90 [2018-12-09 12:31:37,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:37,624 INFO L225 Difference]: With dead ends: 769 [2018-12-09 12:31:37,624 INFO L226 Difference]: Without dead ends: 504 [2018-12-09 12:31:37,625 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:31:37,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2018-12-09 12:31:37,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 499. [2018-12-09 12:31:37,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 499 states. [2018-12-09 12:31:37,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 499 states to 499 states and 600 transitions. [2018-12-09 12:31:37,662 INFO L78 Accepts]: Start accepts. Automaton has 499 states and 600 transitions. Word has length 90 [2018-12-09 12:31:37,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:37,662 INFO L480 AbstractCegarLoop]: Abstraction has 499 states and 600 transitions. [2018-12-09 12:31:37,662 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 12:31:37,662 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 600 transitions. [2018-12-09 12:31:37,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-12-09 12:31:37,663 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:37,663 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:37,664 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:37,664 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:37,664 INFO L82 PathProgramCache]: Analyzing trace with hash 1567785109, now seen corresponding path program 1 times [2018-12-09 12:31:37,664 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:37,664 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:37,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:37,665 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:37,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:37,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:37,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:31:37,689 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:37,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 12:31:37,689 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 12:31:37,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 12:31:37,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:31:37,690 INFO L87 Difference]: Start difference. First operand 499 states and 600 transitions. Second operand 3 states. [2018-12-09 12:31:37,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:37,743 INFO L93 Difference]: Finished difference Result 1401 states and 1753 transitions. [2018-12-09 12:31:37,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 12:31:37,744 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 91 [2018-12-09 12:31:37,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:37,746 INFO L225 Difference]: With dead ends: 1401 [2018-12-09 12:31:37,747 INFO L226 Difference]: Without dead ends: 929 [2018-12-09 12:31:37,748 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:31:37,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 929 states. [2018-12-09 12:31:37,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 929 to 927. [2018-12-09 12:31:37,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 927 states. [2018-12-09 12:31:37,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 927 states to 927 states and 1136 transitions. [2018-12-09 12:31:37,802 INFO L78 Accepts]: Start accepts. Automaton has 927 states and 1136 transitions. Word has length 91 [2018-12-09 12:31:37,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:37,803 INFO L480 AbstractCegarLoop]: Abstraction has 927 states and 1136 transitions. [2018-12-09 12:31:37,803 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 12:31:37,803 INFO L276 IsEmpty]: Start isEmpty. Operand 927 states and 1136 transitions. [2018-12-09 12:31:37,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-09 12:31:37,804 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:37,804 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:37,805 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:37,805 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:37,805 INFO L82 PathProgramCache]: Analyzing trace with hash 1900476813, now seen corresponding path program 1 times [2018-12-09 12:31:37,805 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:37,805 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:37,806 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:37,806 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:37,806 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:37,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:37,831 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 12:31:37,831 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:37,831 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:31:37,831 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:31:37,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:31:37,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:31:37,832 INFO L87 Difference]: Start difference. First operand 927 states and 1136 transitions. Second operand 4 states. [2018-12-09 12:31:37,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:37,956 INFO L93 Difference]: Finished difference Result 1825 states and 2233 transitions. [2018-12-09 12:31:37,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:31:37,956 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 111 [2018-12-09 12:31:37,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:37,960 INFO L225 Difference]: With dead ends: 1825 [2018-12-09 12:31:37,960 INFO L226 Difference]: Without dead ends: 920 [2018-12-09 12:31:37,962 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:31:37,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 920 states. [2018-12-09 12:31:38,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 920 to 920. [2018-12-09 12:31:38,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2018-12-09 12:31:38,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1124 transitions. [2018-12-09 12:31:38,005 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1124 transitions. Word has length 111 [2018-12-09 12:31:38,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:38,005 INFO L480 AbstractCegarLoop]: Abstraction has 920 states and 1124 transitions. [2018-12-09 12:31:38,005 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:31:38,005 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1124 transitions. [2018-12-09 12:31:38,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-09 12:31:38,005 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:38,006 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:38,006 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:38,006 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:38,006 INFO L82 PathProgramCache]: Analyzing trace with hash 549091595, now seen corresponding path program 1 times [2018-12-09 12:31:38,006 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:38,006 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:38,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:38,007 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:38,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:38,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:38,027 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-09 12:31:38,027 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:38,027 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 12:31:38,027 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 12:31:38,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 12:31:38,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:31:38,028 INFO L87 Difference]: Start difference. First operand 920 states and 1124 transitions. Second operand 3 states. [2018-12-09 12:31:38,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:38,116 INFO L93 Difference]: Finished difference Result 2694 states and 3354 transitions. [2018-12-09 12:31:38,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 12:31:38,116 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 111 [2018-12-09 12:31:38,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:38,119 INFO L225 Difference]: With dead ends: 2694 [2018-12-09 12:31:38,120 INFO L226 Difference]: Without dead ends: 1359 [2018-12-09 12:31:38,122 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:31:38,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1359 states. [2018-12-09 12:31:38,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1359 to 1359. [2018-12-09 12:31:38,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1359 states. [2018-12-09 12:31:38,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1359 states to 1359 states and 1660 transitions. [2018-12-09 12:31:38,184 INFO L78 Accepts]: Start accepts. Automaton has 1359 states and 1660 transitions. Word has length 111 [2018-12-09 12:31:38,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:38,184 INFO L480 AbstractCegarLoop]: Abstraction has 1359 states and 1660 transitions. [2018-12-09 12:31:38,185 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 12:31:38,185 INFO L276 IsEmpty]: Start isEmpty. Operand 1359 states and 1660 transitions. [2018-12-09 12:31:38,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-12-09 12:31:38,186 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:38,186 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:38,186 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:38,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:38,186 INFO L82 PathProgramCache]: Analyzing trace with hash 263914882, now seen corresponding path program 1 times [2018-12-09 12:31:38,186 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:38,186 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:38,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:38,187 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:38,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:38,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:38,212 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-12-09 12:31:38,213 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:38,213 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 12:31:38,213 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 12:31:38,213 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 12:31:38,213 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:31:38,213 INFO L87 Difference]: Start difference. First operand 1359 states and 1660 transitions. Second operand 3 states. [2018-12-09 12:31:38,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:38,327 INFO L93 Difference]: Finished difference Result 3754 states and 4763 transitions. [2018-12-09 12:31:38,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 12:31:38,328 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 155 [2018-12-09 12:31:38,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:38,338 INFO L225 Difference]: With dead ends: 3754 [2018-12-09 12:31:38,338 INFO L226 Difference]: Without dead ends: 2417 [2018-12-09 12:31:38,342 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:31:38,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2417 states. [2018-12-09 12:31:38,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2417 to 2414. [2018-12-09 12:31:38,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2414 states. [2018-12-09 12:31:38,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2414 states to 2414 states and 3034 transitions. [2018-12-09 12:31:38,460 INFO L78 Accepts]: Start accepts. Automaton has 2414 states and 3034 transitions. Word has length 155 [2018-12-09 12:31:38,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:38,460 INFO L480 AbstractCegarLoop]: Abstraction has 2414 states and 3034 transitions. [2018-12-09 12:31:38,460 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 12:31:38,460 INFO L276 IsEmpty]: Start isEmpty. Operand 2414 states and 3034 transitions. [2018-12-09 12:31:38,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-12-09 12:31:38,462 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:38,462 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:38,462 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:38,462 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:38,462 INFO L82 PathProgramCache]: Analyzing trace with hash -2013016935, now seen corresponding path program 1 times [2018-12-09 12:31:38,462 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:38,462 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:38,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:38,463 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:38,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:38,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:38,529 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-12-09 12:31:38,529 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 12:31:38,529 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 12:31:38,537 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:38,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:38,594 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 12:31:38,631 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 33 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-09 12:31:38,657 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 12:31:38,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [6] total 7 [2018-12-09 12:31:38,657 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-12-09 12:31:38,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-12-09 12:31:38,658 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:31:38,658 INFO L87 Difference]: Start difference. First operand 2414 states and 3034 transitions. Second operand 7 states. [2018-12-09 12:31:39,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:39,206 INFO L93 Difference]: Finished difference Result 6311 states and 8439 transitions. [2018-12-09 12:31:39,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 12:31:39,206 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 156 [2018-12-09 12:31:39,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:39,215 INFO L225 Difference]: With dead ends: 6311 [2018-12-09 12:31:39,215 INFO L226 Difference]: Without dead ends: 3237 [2018-12-09 12:31:39,222 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 158 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-12-09 12:31:39,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3237 states. [2018-12-09 12:31:39,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3237 to 3237. [2018-12-09 12:31:39,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3237 states. [2018-12-09 12:31:39,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3237 states to 3237 states and 4056 transitions. [2018-12-09 12:31:39,378 INFO L78 Accepts]: Start accepts. Automaton has 3237 states and 4056 transitions. Word has length 156 [2018-12-09 12:31:39,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:39,378 INFO L480 AbstractCegarLoop]: Abstraction has 3237 states and 4056 transitions. [2018-12-09 12:31:39,378 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-12-09 12:31:39,378 INFO L276 IsEmpty]: Start isEmpty. Operand 3237 states and 4056 transitions. [2018-12-09 12:31:39,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2018-12-09 12:31:39,382 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:39,383 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:39,383 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:39,383 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:39,383 INFO L82 PathProgramCache]: Analyzing trace with hash 97200738, now seen corresponding path program 1 times [2018-12-09 12:31:39,383 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:39,383 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:39,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:39,384 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:39,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:39,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:31:39,440 INFO L134 CoverageAnalysis]: Checked inductivity of 114 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-12-09 12:31:39,441 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:31:39,441 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:31:39,441 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:31:39,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:31:39,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:31:39,442 INFO L87 Difference]: Start difference. First operand 3237 states and 4056 transitions. Second operand 4 states. [2018-12-09 12:31:39,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:31:39,749 INFO L93 Difference]: Finished difference Result 6481 states and 8338 transitions. [2018-12-09 12:31:39,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:31:39,750 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 207 [2018-12-09 12:31:39,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:31:39,754 INFO L225 Difference]: With dead ends: 6481 [2018-12-09 12:31:39,754 INFO L226 Difference]: Without dead ends: 1756 [2018-12-09 12:31:39,762 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:31:39,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1756 states. [2018-12-09 12:31:39,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1756 to 1723. [2018-12-09 12:31:39,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1723 states. [2018-12-09 12:31:39,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1723 states to 1723 states and 1979 transitions. [2018-12-09 12:31:39,844 INFO L78 Accepts]: Start accepts. Automaton has 1723 states and 1979 transitions. Word has length 207 [2018-12-09 12:31:39,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:31:39,844 INFO L480 AbstractCegarLoop]: Abstraction has 1723 states and 1979 transitions. [2018-12-09 12:31:39,844 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:31:39,844 INFO L276 IsEmpty]: Start isEmpty. Operand 1723 states and 1979 transitions. [2018-12-09 12:31:39,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 209 [2018-12-09 12:31:39,846 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:31:39,846 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:31:39,846 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:31:39,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:31:39,846 INFO L82 PathProgramCache]: Analyzing trace with hash 1736392345, now seen corresponding path program 1 times [2018-12-09 12:31:39,846 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:31:39,847 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:31:39,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:39,847 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:31:39,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:31:39,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 12:31:39,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 12:31:39,899 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 12:31:39,971 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 12:31:39 BoogieIcfgContainer [2018-12-09 12:31:39,971 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 12:31:39,971 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 12:31:39,971 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 12:31:39,971 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 12:31:39,971 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 12:31:34" (3/4) ... [2018-12-09 12:31:39,973 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-09 12:31:40,048 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_4ae1bb9a-b7bb-4567-a6ee-a3e3866eb94f/bin-2019/uautomizer/witness.graphml [2018-12-09 12:31:40,048 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 12:31:40,048 INFO L168 Benchmark]: Toolchain (without parser) took 6307.98 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 388.5 MB). Free memory was 957.1 MB in the beginning and 1.1 GB in the end (delta: -133.0 MB). Peak memory consumption was 255.5 MB. Max. memory is 11.5 GB. [2018-12-09 12:31:40,049 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 12:31:40,049 INFO L168 Benchmark]: CACSL2BoogieTranslator took 161.00 ms. Allocated memory is still 1.0 GB. Free memory was 957.1 MB in the beginning and 941.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-12-09 12:31:40,049 INFO L168 Benchmark]: Boogie Procedure Inliner took 44.10 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 128.5 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -178.8 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. [2018-12-09 12:31:40,050 INFO L168 Benchmark]: Boogie Preprocessor took 24.73 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 12:31:40,050 INFO L168 Benchmark]: RCFGBuilder took 262.63 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 32.3 MB). Peak memory consumption was 32.3 MB. Max. memory is 11.5 GB. [2018-12-09 12:31:40,050 INFO L168 Benchmark]: TraceAbstraction took 5735.82 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 260.0 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -32.9 MB). Peak memory consumption was 227.2 MB. Max. memory is 11.5 GB. [2018-12-09 12:31:40,050 INFO L168 Benchmark]: Witness Printer took 76.99 ms. Allocated memory is still 1.4 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 23.3 MB). Peak memory consumption was 23.3 MB. Max. memory is 11.5 GB. [2018-12-09 12:31:40,051 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 161.00 ms. Allocated memory is still 1.0 GB. Free memory was 957.1 MB in the beginning and 941.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 44.10 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 128.5 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -178.8 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 24.73 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 262.63 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 32.3 MB). Peak memory consumption was 32.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 5735.82 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 260.0 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -32.9 MB). Peak memory consumption was 227.2 MB. Max. memory is 11.5 GB. * Witness Printer took 76.99 ms. Allocated memory is still 1.4 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 23.3 MB). Peak memory consumption was 23.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; VAL [\old(E_1)=16, \old(E_2)=5, \old(M_E)=13, \old(m_i)=7, \old(m_pc)=11, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=15, \old(t1_pc)=8, \old(t1_st)=4, \old(T2_E)=14, \old(t2_i)=6, \old(t2_pc)=9, \old(t2_st)=10, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L563] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L567] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L477] m_i = 1 [L478] t1_i = 1 [L479] t2_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L567] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L568] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L511] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L211] COND TRUE m_i == 1 [L212] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L221] COND TRUE t2_i == 1 [L222] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L324] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L329] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L334] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L514] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L165] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L184] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L514] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L357] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L362] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L367] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L518] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L521] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L522] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L257] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L252] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L78] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L91] t1_pc = 1 [L92] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L113] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L124] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L126] t2_pc = 1 [L127] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L305] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L252] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND TRUE \read(tmp_ndt_1) [L276] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L277] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L37] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L48] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L51] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND TRUE E_1 == 1 [L167] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND TRUE \read(tmp___0) [L404] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1, tmp___1=0] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L53] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L56] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L58] m_pc = 1 [L59] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L277] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L78] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L81] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L97] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L98] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L147] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND TRUE E_2 == 1 [L186] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND TRUE \read(tmp___1) [L412] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=0, tmp___0=0, tmp___1=1] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L98] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L99] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L91] t1_pc = 1 [L92] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L113] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L116] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L132] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 23 procedures, 169 locations, 1 error locations. UNSAFE Result, 5.6s OverallTime, 21 OverallIterations, 3 TraceHistogramMax, 3.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4582 SDtfs, 4916 SDslu, 4696 SDs, 0 SdLazy, 3196 SolverSat, 1256 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 307 GetRequests, 214 SyntacticMatches, 22 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3237occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 20 MinimizatonAttempts, 373 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 0.6s InterpolantComputationTime, 2455 NumberOfCodeBlocks, 2455 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 2226 ConstructedInterpolants, 0 QuantifiedInterpolants, 362345 SizeOfPredicates, 0 NumberOfNonLiveVariables, 657 ConjunctsInSsa, 3 ConjunctsInUnsatCore, 21 InterpolantComputations, 20 PerfectInterpolantSequences, 272/283 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...