./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7b5159bbdd5292a1bc0941c897062f30a665bf67 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-09 12:21:44,276 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 12:21:44,277 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 12:21:44,283 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 12:21:44,283 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 12:21:44,284 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 12:21:44,284 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 12:21:44,285 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 12:21:44,286 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 12:21:44,286 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 12:21:44,287 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 12:21:44,287 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 12:21:44,288 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 12:21:44,288 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 12:21:44,289 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 12:21:44,289 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 12:21:44,290 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 12:21:44,290 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 12:21:44,291 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 12:21:44,292 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 12:21:44,293 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 12:21:44,294 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 12:21:44,295 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 12:21:44,295 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 12:21:44,295 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 12:21:44,296 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 12:21:44,296 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 12:21:44,297 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 12:21:44,297 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 12:21:44,298 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 12:21:44,298 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 12:21:44,298 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 12:21:44,298 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 12:21:44,298 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 12:21:44,299 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 12:21:44,299 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 12:21:44,300 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-12-09 12:21:44,307 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 12:21:44,307 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 12:21:44,307 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 12:21:44,307 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 12:21:44,308 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-12-09 12:21:44,308 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-12-09 12:21:44,308 INFO L133 SettingsManager]: * Use SBE=true [2018-12-09 12:21:44,308 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 12:21:44,308 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-09 12:21:44,308 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-09 12:21:44,308 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-09 12:21:44,309 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 12:21:44,309 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-09 12:21:44,309 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 12:21:44,309 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-09 12:21:44,309 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-09 12:21:44,309 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-09 12:21:44,309 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-09 12:21:44,309 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-09 12:21:44,310 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 12:21:44,310 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 12:21:44,310 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 12:21:44,310 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 12:21:44,310 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 12:21:44,310 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 12:21:44,310 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 12:21:44,310 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-09 12:21:44,311 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-12-09 12:21:44,311 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 12:21:44,311 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-09 12:21:44,311 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7b5159bbdd5292a1bc0941c897062f30a665bf67 [2018-12-09 12:21:44,329 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 12:21:44,336 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 12:21:44,338 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 12:21:44,339 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 12:21:44,339 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 12:21:44,339 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c [2018-12-09 12:21:44,385 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/data/028e1bc42/79e625b1273c430ab15d833fbac01478/FLAGc21ee8e7f [2018-12-09 12:21:44,729 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 12:21:44,730 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c [2018-12-09 12:21:44,735 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/data/028e1bc42/79e625b1273c430ab15d833fbac01478/FLAGc21ee8e7f [2018-12-09 12:21:44,744 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/data/028e1bc42/79e625b1273c430ab15d833fbac01478 [2018-12-09 12:21:44,745 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 12:21:44,746 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-09 12:21:44,747 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 12:21:44,747 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 12:21:44,749 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 12:21:44,749 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:44,751 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@643265e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44, skipping insertion in model container [2018-12-09 12:21:44,751 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:44,755 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 12:21:44,780 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 12:21:44,910 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 12:21:44,914 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 12:21:44,943 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 12:21:44,990 INFO L195 MainTranslator]: Completed translation [2018-12-09 12:21:44,991 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44 WrapperNode [2018-12-09 12:21:44,991 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 12:21:44,991 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-09 12:21:44,992 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-09 12:21:44,992 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-09 12:21:44,998 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,004 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,009 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-09 12:21:45,009 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 12:21:45,009 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 12:21:45,009 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 12:21:45,015 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,015 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,017 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,017 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,025 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,036 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,038 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... [2018-12-09 12:21:45,041 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 12:21:45,041 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 12:21:45,041 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 12:21:45,041 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 12:21:45,042 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 12:21:45,075 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-12-09 12:21:45,075 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-12-09 12:21:45,075 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-12-09 12:21:45,075 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-12-09 12:21:45,075 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-12-09 12:21:45,076 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-12-09 12:21:45,076 INFO L130 BoogieDeclarations]: Found specification of procedure transmit5 [2018-12-09 12:21:45,076 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit5 [2018-12-09 12:21:45,076 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2018-12-09 12:21:45,076 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2018-12-09 12:21:45,076 INFO L130 BoogieDeclarations]: Found specification of procedure transmit6 [2018-12-09 12:21:45,076 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit6 [2018-12-09 12:21:45,076 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 12:21:45,076 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 12:21:45,076 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-09 12:21:45,076 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-09 12:21:45,076 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-09 12:21:45,076 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-09 12:21:45,076 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-12-09 12:21:45,076 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-12-09 12:21:45,077 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-09 12:21:45,077 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-09 12:21:45,077 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-12-09 12:21:45,077 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-12-09 12:21:45,077 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-09 12:21:45,077 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-09 12:21:45,077 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2018-12-09 12:21:45,077 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2018-12-09 12:21:45,077 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-09 12:21:45,077 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-09 12:21:45,077 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-12-09 12:21:45,077 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-12-09 12:21:45,077 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-09 12:21:45,077 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-09 12:21:45,077 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-09 12:21:45,077 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-09 12:21:45,078 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-12-09 12:21:45,078 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-12-09 12:21:45,078 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-09 12:21:45,078 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-09 12:21:45,078 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit6_triggered [2018-12-09 12:21:45,078 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit6_triggered [2018-12-09 12:21:45,078 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-12-09 12:21:45,078 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-12-09 12:21:45,078 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-09 12:21:45,078 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-09 12:21:45,078 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 12:21:45,078 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 12:21:45,078 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-09 12:21:45,078 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-09 12:21:45,078 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-12-09 12:21:45,078 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-12-09 12:21:45,079 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit5_triggered [2018-12-09 12:21:45,079 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit5_triggered [2018-12-09 12:21:45,079 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-09 12:21:45,079 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-09 12:21:45,079 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-09 12:21:45,079 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-09 12:21:45,079 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 12:21:45,079 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 12:21:45,079 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-09 12:21:45,079 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-09 12:21:45,428 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 12:21:45,428 INFO L280 CfgBuilder]: Removed 10 assue(true) statements. [2018-12-09 12:21:45,428 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 12:21:45 BoogieIcfgContainer [2018-12-09 12:21:45,428 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 12:21:45,429 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 12:21:45,429 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 12:21:45,432 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 12:21:45,432 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 12:21:44" (1/3) ... [2018-12-09 12:21:45,433 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6cd77694 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 12:21:45, skipping insertion in model container [2018-12-09 12:21:45,433 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 12:21:44" (2/3) ... [2018-12-09 12:21:45,433 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6cd77694 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 12:21:45, skipping insertion in model container [2018-12-09 12:21:45,433 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 12:21:45" (3/3) ... [2018-12-09 12:21:45,435 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.06_false-unreach-call_false-termination.cil.c [2018-12-09 12:21:45,443 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 12:21:45,449 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-09 12:21:45,460 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-09 12:21:45,480 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-09 12:21:45,480 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 12:21:45,480 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-09 12:21:45,480 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 12:21:45,480 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 12:21:45,480 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 12:21:45,480 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 12:21:45,481 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 12:21:45,481 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 12:21:45,495 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states. [2018-12-09 12:21:45,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:45,503 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:45,503 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:45,505 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:45,508 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:45,508 INFO L82 PathProgramCache]: Analyzing trace with hash 1949535280, now seen corresponding path program 1 times [2018-12-09 12:21:45,510 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:45,510 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:45,539 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:45,539 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:45,539 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:45,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:45,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:45,696 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:45,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:21:45,699 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:21:45,707 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:21:45,707 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:45,708 INFO L87 Difference]: Start difference. First operand 289 states. Second operand 4 states. [2018-12-09 12:21:45,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:45,870 INFO L93 Difference]: Finished difference Result 556 states and 834 transitions. [2018-12-09 12:21:45,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:21:45,871 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-12-09 12:21:45,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:45,883 INFO L225 Difference]: With dead ends: 556 [2018-12-09 12:21:45,883 INFO L226 Difference]: Without dead ends: 280 [2018-12-09 12:21:45,886 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:45,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280 states. [2018-12-09 12:21:45,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280 to 280. [2018-12-09 12:21:45,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:45,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 396 transitions. [2018-12-09 12:21:45,927 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 396 transitions. Word has length 150 [2018-12-09 12:21:45,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:45,929 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 396 transitions. [2018-12-09 12:21:45,929 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:21:45,929 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 396 transitions. [2018-12-09 12:21:45,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:45,933 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:45,933 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:45,933 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:45,933 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:45,934 INFO L82 PathProgramCache]: Analyzing trace with hash -1397380050, now seen corresponding path program 1 times [2018-12-09 12:21:45,934 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:45,934 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:45,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:45,935 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:45,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:45,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:46,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:46,061 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:46,061 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:46,063 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:46,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:46,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:46,063 INFO L87 Difference]: Start difference. First operand 280 states and 396 transitions. Second operand 5 states. [2018-12-09 12:21:46,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:46,406 INFO L93 Difference]: Finished difference Result 580 states and 842 transitions. [2018-12-09 12:21:46,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:46,407 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:46,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:46,408 INFO L225 Difference]: With dead ends: 580 [2018-12-09 12:21:46,408 INFO L226 Difference]: Without dead ends: 324 [2018-12-09 12:21:46,409 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:46,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states. [2018-12-09 12:21:46,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 280. [2018-12-09 12:21:46,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:46,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 395 transitions. [2018-12-09 12:21:46,424 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 395 transitions. Word has length 150 [2018-12-09 12:21:46,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:46,424 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 395 transitions. [2018-12-09 12:21:46,424 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:46,424 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 395 transitions. [2018-12-09 12:21:46,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:46,425 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:46,426 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:46,426 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:46,426 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:46,426 INFO L82 PathProgramCache]: Analyzing trace with hash -450342164, now seen corresponding path program 1 times [2018-12-09 12:21:46,426 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:46,426 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:46,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:46,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:46,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:46,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:46,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:46,483 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:46,483 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:46,484 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:46,484 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:46,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:46,484 INFO L87 Difference]: Start difference. First operand 280 states and 395 transitions. Second operand 5 states. [2018-12-09 12:21:46,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:46,847 INFO L93 Difference]: Finished difference Result 580 states and 841 transitions. [2018-12-09 12:21:46,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:46,847 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:46,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:46,849 INFO L225 Difference]: With dead ends: 580 [2018-12-09 12:21:46,849 INFO L226 Difference]: Without dead ends: 324 [2018-12-09 12:21:46,850 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:46,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states. [2018-12-09 12:21:46,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 280. [2018-12-09 12:21:46,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:46,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 394 transitions. [2018-12-09 12:21:46,863 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 394 transitions. Word has length 150 [2018-12-09 12:21:46,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:46,863 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 394 transitions. [2018-12-09 12:21:46,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:46,863 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 394 transitions. [2018-12-09 12:21:46,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:46,864 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:46,864 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:46,864 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:46,865 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:46,865 INFO L82 PathProgramCache]: Analyzing trace with hash 411491438, now seen corresponding path program 1 times [2018-12-09 12:21:46,865 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:46,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:46,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:46,865 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:46,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:46,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:46,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:46,914 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:46,914 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:46,914 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:46,914 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:46,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:46,915 INFO L87 Difference]: Start difference. First operand 280 states and 394 transitions. Second operand 5 states. [2018-12-09 12:21:47,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:47,254 INFO L93 Difference]: Finished difference Result 578 states and 835 transitions. [2018-12-09 12:21:47,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:47,254 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:47,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:47,255 INFO L225 Difference]: With dead ends: 578 [2018-12-09 12:21:47,255 INFO L226 Difference]: Without dead ends: 322 [2018-12-09 12:21:47,256 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:47,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states. [2018-12-09 12:21:47,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 280. [2018-12-09 12:21:47,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:47,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 393 transitions. [2018-12-09 12:21:47,268 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 393 transitions. Word has length 150 [2018-12-09 12:21:47,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:47,268 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 393 transitions. [2018-12-09 12:21:47,268 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:47,268 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 393 transitions. [2018-12-09 12:21:47,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:47,269 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:47,269 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:47,270 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:47,270 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:47,270 INFO L82 PathProgramCache]: Analyzing trace with hash -1638917460, now seen corresponding path program 1 times [2018-12-09 12:21:47,270 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:47,270 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:47,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:47,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:47,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:47,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:47,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:47,319 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:47,319 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:47,319 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:47,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:47,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:47,319 INFO L87 Difference]: Start difference. First operand 280 states and 393 transitions. Second operand 5 states. [2018-12-09 12:21:47,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:47,608 INFO L93 Difference]: Finished difference Result 576 states and 829 transitions. [2018-12-09 12:21:47,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:47,608 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:47,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:47,610 INFO L225 Difference]: With dead ends: 576 [2018-12-09 12:21:47,610 INFO L226 Difference]: Without dead ends: 320 [2018-12-09 12:21:47,611 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:47,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states. [2018-12-09 12:21:47,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 280. [2018-12-09 12:21:47,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:47,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 392 transitions. [2018-12-09 12:21:47,622 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 392 transitions. Word has length 150 [2018-12-09 12:21:47,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:47,623 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 392 transitions. [2018-12-09 12:21:47,623 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:47,623 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 392 transitions. [2018-12-09 12:21:47,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:47,624 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:47,624 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:47,624 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:47,624 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:47,624 INFO L82 PathProgramCache]: Analyzing trace with hash -1150870354, now seen corresponding path program 1 times [2018-12-09 12:21:47,625 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:47,625 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:47,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:47,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:47,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:47,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:47,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:47,672 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:47,672 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:47,672 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:47,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:47,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:47,673 INFO L87 Difference]: Start difference. First operand 280 states and 392 transitions. Second operand 5 states. [2018-12-09 12:21:47,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:47,963 INFO L93 Difference]: Finished difference Result 574 states and 823 transitions. [2018-12-09 12:21:47,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:47,963 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:47,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:47,964 INFO L225 Difference]: With dead ends: 574 [2018-12-09 12:21:47,964 INFO L226 Difference]: Without dead ends: 318 [2018-12-09 12:21:47,965 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:47,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states. [2018-12-09 12:21:47,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 280. [2018-12-09 12:21:47,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:47,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 391 transitions. [2018-12-09 12:21:47,979 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 391 transitions. Word has length 150 [2018-12-09 12:21:47,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:47,979 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 391 transitions. [2018-12-09 12:21:47,979 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:47,979 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 391 transitions. [2018-12-09 12:21:47,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:47,980 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:47,981 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:47,981 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:47,981 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:47,981 INFO L82 PathProgramCache]: Analyzing trace with hash 2051461740, now seen corresponding path program 1 times [2018-12-09 12:21:47,981 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:47,981 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:47,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:47,982 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:47,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:47,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:48,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:48,038 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:48,038 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:48,038 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:48,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:48,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:48,039 INFO L87 Difference]: Start difference. First operand 280 states and 391 transitions. Second operand 5 states. [2018-12-09 12:21:48,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:48,341 INFO L93 Difference]: Finished difference Result 570 states and 813 transitions. [2018-12-09 12:21:48,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:48,341 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:48,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:48,343 INFO L225 Difference]: With dead ends: 570 [2018-12-09 12:21:48,343 INFO L226 Difference]: Without dead ends: 314 [2018-12-09 12:21:48,344 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:48,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states. [2018-12-09 12:21:48,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 280. [2018-12-09 12:21:48,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:48,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 390 transitions. [2018-12-09 12:21:48,362 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 390 transitions. Word has length 150 [2018-12-09 12:21:48,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:48,362 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 390 transitions. [2018-12-09 12:21:48,362 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:48,362 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 390 transitions. [2018-12-09 12:21:48,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:48,363 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:48,364 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:48,364 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:48,364 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:48,364 INFO L82 PathProgramCache]: Analyzing trace with hash 208986026, now seen corresponding path program 1 times [2018-12-09 12:21:48,364 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:48,364 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:48,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:48,365 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:48,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:48,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:48,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:48,430 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:48,430 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:48,430 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:48,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:48,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:48,430 INFO L87 Difference]: Start difference. First operand 280 states and 390 transitions. Second operand 5 states. [2018-12-09 12:21:48,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:48,735 INFO L93 Difference]: Finished difference Result 599 states and 863 transitions. [2018-12-09 12:21:48,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:48,735 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:48,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:48,736 INFO L225 Difference]: With dead ends: 599 [2018-12-09 12:21:48,736 INFO L226 Difference]: Without dead ends: 343 [2018-12-09 12:21:48,737 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:48,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 343 states. [2018-12-09 12:21:48,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 343 to 280. [2018-12-09 12:21:48,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:48,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 389 transitions. [2018-12-09 12:21:48,749 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 389 transitions. Word has length 150 [2018-12-09 12:21:48,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:48,749 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 389 transitions. [2018-12-09 12:21:48,749 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:48,749 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 389 transitions. [2018-12-09 12:21:48,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:48,750 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:48,750 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:48,750 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:48,750 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:48,750 INFO L82 PathProgramCache]: Analyzing trace with hash -1513016660, now seen corresponding path program 1 times [2018-12-09 12:21:48,750 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:48,750 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:48,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:48,751 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:48,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:48,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:48,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:48,791 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:48,791 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:48,792 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:48,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:48,792 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:48,792 INFO L87 Difference]: Start difference. First operand 280 states and 389 transitions. Second operand 5 states. [2018-12-09 12:21:49,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:49,129 INFO L93 Difference]: Finished difference Result 597 states and 857 transitions. [2018-12-09 12:21:49,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:49,129 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:49,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:49,131 INFO L225 Difference]: With dead ends: 597 [2018-12-09 12:21:49,131 INFO L226 Difference]: Without dead ends: 341 [2018-12-09 12:21:49,132 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:49,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 341 states. [2018-12-09 12:21:49,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 341 to 280. [2018-12-09 12:21:49,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:49,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 388 transitions. [2018-12-09 12:21:49,147 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 388 transitions. Word has length 150 [2018-12-09 12:21:49,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:49,147 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 388 transitions. [2018-12-09 12:21:49,147 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:49,147 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 388 transitions. [2018-12-09 12:21:49,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:49,149 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:49,149 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:49,149 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:49,149 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:49,149 INFO L82 PathProgramCache]: Analyzing trace with hash -1845659798, now seen corresponding path program 1 times [2018-12-09 12:21:49,149 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:49,149 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:49,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:49,150 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:49,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:49,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:49,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:49,198 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:49,198 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:49,199 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:49,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:49,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:49,199 INFO L87 Difference]: Start difference. First operand 280 states and 388 transitions. Second operand 5 states. [2018-12-09 12:21:49,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:49,522 INFO L93 Difference]: Finished difference Result 595 states and 851 transitions. [2018-12-09 12:21:49,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:49,523 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:49,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:49,525 INFO L225 Difference]: With dead ends: 595 [2018-12-09 12:21:49,525 INFO L226 Difference]: Without dead ends: 339 [2018-12-09 12:21:49,526 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:49,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 339 states. [2018-12-09 12:21:49,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 339 to 280. [2018-12-09 12:21:49,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:49,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 387 transitions. [2018-12-09 12:21:49,559 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 387 transitions. Word has length 150 [2018-12-09 12:21:49,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:49,559 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 387 transitions. [2018-12-09 12:21:49,559 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:49,559 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 387 transitions. [2018-12-09 12:21:49,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:49,560 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:49,560 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:49,560 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:49,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:49,561 INFO L82 PathProgramCache]: Analyzing trace with hash 83272428, now seen corresponding path program 1 times [2018-12-09 12:21:49,561 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:49,561 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:49,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:49,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:49,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:49,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:49,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:49,609 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:49,609 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:49,609 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:49,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:49,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:49,609 INFO L87 Difference]: Start difference. First operand 280 states and 387 transitions. Second operand 5 states. [2018-12-09 12:21:49,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:49,880 INFO L93 Difference]: Finished difference Result 593 states and 845 transitions. [2018-12-09 12:21:49,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:49,880 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:49,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:49,881 INFO L225 Difference]: With dead ends: 593 [2018-12-09 12:21:49,881 INFO L226 Difference]: Without dead ends: 337 [2018-12-09 12:21:49,882 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:49,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337 states. [2018-12-09 12:21:49,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337 to 280. [2018-12-09 12:21:49,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:49,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 386 transitions. [2018-12-09 12:21:49,897 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 386 transitions. Word has length 150 [2018-12-09 12:21:49,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:49,898 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 386 transitions. [2018-12-09 12:21:49,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:49,898 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 386 transitions. [2018-12-09 12:21:49,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:49,899 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:49,899 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:49,899 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:49,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:49,899 INFO L82 PathProgramCache]: Analyzing trace with hash 2085158698, now seen corresponding path program 1 times [2018-12-09 12:21:49,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:49,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:49,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:49,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:49,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:49,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:49,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:49,936 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:49,937 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:49,937 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:49,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:49,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:49,937 INFO L87 Difference]: Start difference. First operand 280 states and 386 transitions. Second operand 5 states. [2018-12-09 12:21:50,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:50,233 INFO L93 Difference]: Finished difference Result 591 states and 839 transitions. [2018-12-09 12:21:50,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:50,233 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:50,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:50,235 INFO L225 Difference]: With dead ends: 591 [2018-12-09 12:21:50,235 INFO L226 Difference]: Without dead ends: 335 [2018-12-09 12:21:50,236 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:50,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 335 states. [2018-12-09 12:21:50,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 335 to 280. [2018-12-09 12:21:50,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:50,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 385 transitions. [2018-12-09 12:21:50,261 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 385 transitions. Word has length 150 [2018-12-09 12:21:50,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:50,261 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 385 transitions. [2018-12-09 12:21:50,261 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:50,261 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 385 transitions. [2018-12-09 12:21:50,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:50,262 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:50,262 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:50,262 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:50,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:50,262 INFO L82 PathProgramCache]: Analyzing trace with hash -482663636, now seen corresponding path program 1 times [2018-12-09 12:21:50,263 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:50,263 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:50,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:50,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:50,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:50,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:50,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:50,301 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:50,301 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:50,302 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:50,302 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:50,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:50,302 INFO L87 Difference]: Start difference. First operand 280 states and 385 transitions. Second operand 5 states. [2018-12-09 12:21:50,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:50,600 INFO L93 Difference]: Finished difference Result 589 states and 833 transitions. [2018-12-09 12:21:50,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:50,601 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:50,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:50,602 INFO L225 Difference]: With dead ends: 589 [2018-12-09 12:21:50,602 INFO L226 Difference]: Without dead ends: 333 [2018-12-09 12:21:50,603 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:50,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2018-12-09 12:21:50,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 280. [2018-12-09 12:21:50,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280 states. [2018-12-09 12:21:50,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 384 transitions. [2018-12-09 12:21:50,618 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 384 transitions. Word has length 150 [2018-12-09 12:21:50,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:50,619 INFO L480 AbstractCegarLoop]: Abstraction has 280 states and 384 transitions. [2018-12-09 12:21:50,619 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:50,619 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 384 transitions. [2018-12-09 12:21:50,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:50,620 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:50,620 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:50,620 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:50,620 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:50,620 INFO L82 PathProgramCache]: Analyzing trace with hash -11307286, now seen corresponding path program 1 times [2018-12-09 12:21:50,620 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:50,620 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:50,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:50,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:50,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:50,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:50,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:50,664 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:50,664 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:21:50,664 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:21:50,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:21:50,664 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:50,665 INFO L87 Difference]: Start difference. First operand 280 states and 384 transitions. Second operand 4 states. [2018-12-09 12:21:50,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:50,839 INFO L93 Difference]: Finished difference Result 782 states and 1109 transitions. [2018-12-09 12:21:50,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:21:50,839 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-12-09 12:21:50,839 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:50,841 INFO L225 Difference]: With dead ends: 782 [2018-12-09 12:21:50,841 INFO L226 Difference]: Without dead ends: 527 [2018-12-09 12:21:50,842 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:50,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2018-12-09 12:21:50,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 522. [2018-12-09 12:21:50,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 522 states. [2018-12-09 12:21:50,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 522 states to 522 states and 716 transitions. [2018-12-09 12:21:50,892 INFO L78 Accepts]: Start accepts. Automaton has 522 states and 716 transitions. Word has length 150 [2018-12-09 12:21:50,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:50,892 INFO L480 AbstractCegarLoop]: Abstraction has 522 states and 716 transitions. [2018-12-09 12:21:50,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:21:50,893 INFO L276 IsEmpty]: Start isEmpty. Operand 522 states and 716 transitions. [2018-12-09 12:21:50,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:50,893 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:50,894 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:50,894 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:50,894 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:50,894 INFO L82 PathProgramCache]: Analyzing trace with hash 276152619, now seen corresponding path program 1 times [2018-12-09 12:21:50,894 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:50,894 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:50,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:50,895 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:50,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:50,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:50,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:50,961 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:50,961 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:21:50,962 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:21:50,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:21:50,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:50,962 INFO L87 Difference]: Start difference. First operand 522 states and 716 transitions. Second operand 6 states. [2018-12-09 12:21:51,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:51,024 INFO L93 Difference]: Finished difference Result 1044 states and 1470 transitions. [2018-12-09 12:21:51,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:21:51,025 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-12-09 12:21:51,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:51,026 INFO L225 Difference]: With dead ends: 1044 [2018-12-09 12:21:51,026 INFO L226 Difference]: Without dead ends: 547 [2018-12-09 12:21:51,027 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:21:51,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-12-09 12:21:51,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 527. [2018-12-09 12:21:51,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2018-12-09 12:21:51,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 720 transitions. [2018-12-09 12:21:51,059 INFO L78 Accepts]: Start accepts. Automaton has 527 states and 720 transitions. Word has length 150 [2018-12-09 12:21:51,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:51,060 INFO L480 AbstractCegarLoop]: Abstraction has 527 states and 720 transitions. [2018-12-09 12:21:51,060 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:21:51,060 INFO L276 IsEmpty]: Start isEmpty. Operand 527 states and 720 transitions. [2018-12-09 12:21:51,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:51,060 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:51,061 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:51,061 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:51,061 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:51,061 INFO L82 PathProgramCache]: Analyzing trace with hash 1307193517, now seen corresponding path program 1 times [2018-12-09 12:21:51,061 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:51,061 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:51,061 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:51,061 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:51,061 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:51,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:51,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:51,105 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:51,105 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:21:51,106 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:21:51,106 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:21:51,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:51,106 INFO L87 Difference]: Start difference. First operand 527 states and 720 transitions. Second operand 4 states. [2018-12-09 12:21:51,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:51,360 INFO L93 Difference]: Finished difference Result 1518 states and 2144 transitions. [2018-12-09 12:21:51,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:21:51,361 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-12-09 12:21:51,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:51,363 INFO L225 Difference]: With dead ends: 1518 [2018-12-09 12:21:51,363 INFO L226 Difference]: Without dead ends: 1016 [2018-12-09 12:21:51,364 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:51,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1016 states. [2018-12-09 12:21:51,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1016 to 1009. [2018-12-09 12:21:51,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1009 states. [2018-12-09 12:21:51,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1009 states to 1009 states and 1377 transitions. [2018-12-09 12:21:51,420 INFO L78 Accepts]: Start accepts. Automaton has 1009 states and 1377 transitions. Word has length 150 [2018-12-09 12:21:51,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:51,420 INFO L480 AbstractCegarLoop]: Abstraction has 1009 states and 1377 transitions. [2018-12-09 12:21:51,420 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:21:51,420 INFO L276 IsEmpty]: Start isEmpty. Operand 1009 states and 1377 transitions. [2018-12-09 12:21:51,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:51,421 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:51,421 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:51,421 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:51,421 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:51,421 INFO L82 PathProgramCache]: Analyzing trace with hash 1662789964, now seen corresponding path program 1 times [2018-12-09 12:21:51,421 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:51,421 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:51,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:51,422 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:51,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:51,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:51,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:51,464 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:51,464 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:21:51,464 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:21:51,465 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:21:51,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:51,465 INFO L87 Difference]: Start difference. First operand 1009 states and 1377 transitions. Second operand 6 states. [2018-12-09 12:21:51,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:51,552 INFO L93 Difference]: Finished difference Result 2037 states and 2852 transitions. [2018-12-09 12:21:51,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:21:51,553 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-12-09 12:21:51,553 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:51,555 INFO L225 Difference]: With dead ends: 2037 [2018-12-09 12:21:51,556 INFO L226 Difference]: Without dead ends: 1053 [2018-12-09 12:21:51,558 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:21:51,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1053 states. [2018-12-09 12:21:51,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1053 to 1019. [2018-12-09 12:21:51,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1019 states. [2018-12-09 12:21:51,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1019 states to 1019 states and 1385 transitions. [2018-12-09 12:21:51,614 INFO L78 Accepts]: Start accepts. Automaton has 1019 states and 1385 transitions. Word has length 150 [2018-12-09 12:21:51,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:51,614 INFO L480 AbstractCegarLoop]: Abstraction has 1019 states and 1385 transitions. [2018-12-09 12:21:51,614 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:21:51,614 INFO L276 IsEmpty]: Start isEmpty. Operand 1019 states and 1385 transitions. [2018-12-09 12:21:51,615 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:51,615 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:51,615 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:51,615 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:51,615 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:51,615 INFO L82 PathProgramCache]: Analyzing trace with hash -755114102, now seen corresponding path program 1 times [2018-12-09 12:21:51,615 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:51,615 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:51,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:51,616 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:51,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:51,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:51,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:51,656 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:51,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:21:51,657 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:21:51,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:21:51,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:51,657 INFO L87 Difference]: Start difference. First operand 1019 states and 1385 transitions. Second operand 4 states. [2018-12-09 12:21:51,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:51,944 INFO L93 Difference]: Finished difference Result 2982 states and 4193 transitions. [2018-12-09 12:21:51,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:21:51,945 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-12-09 12:21:51,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:51,950 INFO L225 Difference]: With dead ends: 2982 [2018-12-09 12:21:51,950 INFO L226 Difference]: Without dead ends: 1988 [2018-12-09 12:21:51,953 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:51,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states. [2018-12-09 12:21:52,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1977. [2018-12-09 12:21:52,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1977 states. [2018-12-09 12:21:52,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1977 states to 1977 states and 2685 transitions. [2018-12-09 12:21:52,072 INFO L78 Accepts]: Start accepts. Automaton has 1977 states and 2685 transitions. Word has length 150 [2018-12-09 12:21:52,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:52,073 INFO L480 AbstractCegarLoop]: Abstraction has 1977 states and 2685 transitions. [2018-12-09 12:21:52,073 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:21:52,073 INFO L276 IsEmpty]: Start isEmpty. Operand 1977 states and 2685 transitions. [2018-12-09 12:21:52,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:52,074 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:52,074 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:52,074 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:52,074 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:52,074 INFO L82 PathProgramCache]: Analyzing trace with hash 2054613003, now seen corresponding path program 1 times [2018-12-09 12:21:52,074 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:52,074 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:52,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:52,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:52,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:52,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:52,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:52,119 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:52,119 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:21:52,119 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:21:52,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:21:52,119 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:52,120 INFO L87 Difference]: Start difference. First operand 1977 states and 2685 transitions. Second operand 6 states. [2018-12-09 12:21:52,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:52,284 INFO L93 Difference]: Finished difference Result 4005 states and 5580 transitions. [2018-12-09 12:21:52,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:21:52,285 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-12-09 12:21:52,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:52,292 INFO L225 Difference]: With dead ends: 4005 [2018-12-09 12:21:52,292 INFO L226 Difference]: Without dead ends: 2053 [2018-12-09 12:21:52,297 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:21:52,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2053 states. [2018-12-09 12:21:52,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2053 to 1997. [2018-12-09 12:21:52,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1997 states. [2018-12-09 12:21:52,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1997 states to 1997 states and 2701 transitions. [2018-12-09 12:21:52,426 INFO L78 Accepts]: Start accepts. Automaton has 1997 states and 2701 transitions. Word has length 150 [2018-12-09 12:21:52,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:52,426 INFO L480 AbstractCegarLoop]: Abstraction has 1997 states and 2701 transitions. [2018-12-09 12:21:52,426 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:21:52,426 INFO L276 IsEmpty]: Start isEmpty. Operand 1997 states and 2701 transitions. [2018-12-09 12:21:52,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:52,427 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:52,427 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:52,427 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:52,427 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:52,427 INFO L82 PathProgramCache]: Analyzing trace with hash 996774925, now seen corresponding path program 1 times [2018-12-09 12:21:52,427 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:52,427 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:52,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:52,428 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:52,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:52,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:52,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:52,476 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:52,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:21:52,477 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:21:52,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:21:52,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:52,477 INFO L87 Difference]: Start difference. First operand 1997 states and 2701 transitions. Second operand 6 states. [2018-12-09 12:21:52,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:52,614 INFO L93 Difference]: Finished difference Result 4097 states and 5693 transitions. [2018-12-09 12:21:52,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:21:52,614 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-12-09 12:21:52,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:52,620 INFO L225 Difference]: With dead ends: 4097 [2018-12-09 12:21:52,620 INFO L226 Difference]: Without dead ends: 2125 [2018-12-09 12:21:52,635 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:21:52,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2125 states. [2018-12-09 12:21:52,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2125 to 2037. [2018-12-09 12:21:52,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2037 states. [2018-12-09 12:21:52,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 2741 transitions. [2018-12-09 12:21:52,743 INFO L78 Accepts]: Start accepts. Automaton has 2037 states and 2741 transitions. Word has length 150 [2018-12-09 12:21:52,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:52,744 INFO L480 AbstractCegarLoop]: Abstraction has 2037 states and 2741 transitions. [2018-12-09 12:21:52,744 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:21:52,744 INFO L276 IsEmpty]: Start isEmpty. Operand 2037 states and 2741 transitions. [2018-12-09 12:21:52,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:52,744 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:52,744 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:52,744 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:52,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:52,745 INFO L82 PathProgramCache]: Analyzing trace with hash 1073675723, now seen corresponding path program 1 times [2018-12-09 12:21:52,745 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:52,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:52,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:52,745 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:52,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:52,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:52,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:52,791 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:52,791 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:21:52,792 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:21:52,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:21:52,792 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:52,792 INFO L87 Difference]: Start difference. First operand 2037 states and 2741 transitions. Second operand 4 states. [2018-12-09 12:21:53,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:53,158 INFO L93 Difference]: Finished difference Result 6012 states and 8379 transitions. [2018-12-09 12:21:53,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:21:53,159 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 150 [2018-12-09 12:21:53,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:53,170 INFO L225 Difference]: With dead ends: 6012 [2018-12-09 12:21:53,171 INFO L226 Difference]: Without dead ends: 4000 [2018-12-09 12:21:53,175 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:21:53,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4000 states. [2018-12-09 12:21:53,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4000 to 3981. [2018-12-09 12:21:53,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3981 states. [2018-12-09 12:21:53,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3981 states to 3981 states and 5359 transitions. [2018-12-09 12:21:53,398 INFO L78 Accepts]: Start accepts. Automaton has 3981 states and 5359 transitions. Word has length 150 [2018-12-09 12:21:53,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:53,398 INFO L480 AbstractCegarLoop]: Abstraction has 3981 states and 5359 transitions. [2018-12-09 12:21:53,398 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:21:53,398 INFO L276 IsEmpty]: Start isEmpty. Operand 3981 states and 5359 transitions. [2018-12-09 12:21:53,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:53,399 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:53,399 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:53,399 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:53,399 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:53,399 INFO L82 PathProgramCache]: Analyzing trace with hash -2083662708, now seen corresponding path program 1 times [2018-12-09 12:21:53,399 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:53,399 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:53,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:53,400 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:53,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:53,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:53,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:53,455 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:53,455 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:21:53,456 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:21:53,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:21:53,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:53,456 INFO L87 Difference]: Start difference. First operand 3981 states and 5359 transitions. Second operand 6 states. [2018-12-09 12:21:53,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:53,677 INFO L93 Difference]: Finished difference Result 8041 states and 11102 transitions. [2018-12-09 12:21:53,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:21:53,677 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-12-09 12:21:53,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:53,687 INFO L225 Difference]: With dead ends: 8041 [2018-12-09 12:21:53,687 INFO L226 Difference]: Without dead ends: 4085 [2018-12-09 12:21:53,694 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:21:53,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4085 states. [2018-12-09 12:21:53,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4085 to 4021. [2018-12-09 12:21:53,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4021 states. [2018-12-09 12:21:53,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4021 states to 4021 states and 5391 transitions. [2018-12-09 12:21:53,935 INFO L78 Accepts]: Start accepts. Automaton has 4021 states and 5391 transitions. Word has length 150 [2018-12-09 12:21:53,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:53,936 INFO L480 AbstractCegarLoop]: Abstraction has 4021 states and 5391 transitions. [2018-12-09 12:21:53,936 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:21:53,936 INFO L276 IsEmpty]: Start isEmpty. Operand 4021 states and 5391 transitions. [2018-12-09 12:21:53,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:53,936 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:53,936 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:53,936 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:53,937 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:53,937 INFO L82 PathProgramCache]: Analyzing trace with hash 1793907982, now seen corresponding path program 1 times [2018-12-09 12:21:53,937 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:53,937 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:53,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:53,937 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:53,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:53,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:53,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:53,972 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:53,973 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:21:53,973 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:21:53,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:21:53,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:53,973 INFO L87 Difference]: Start difference. First operand 4021 states and 5391 transitions. Second operand 6 states. [2018-12-09 12:21:54,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:54,213 INFO L93 Difference]: Finished difference Result 8177 states and 11247 transitions. [2018-12-09 12:21:54,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:21:54,214 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-12-09 12:21:54,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:54,223 INFO L225 Difference]: With dead ends: 8177 [2018-12-09 12:21:54,223 INFO L226 Difference]: Without dead ends: 4181 [2018-12-09 12:21:54,230 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:21:54,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4181 states. [2018-12-09 12:21:54,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4181 to 4101. [2018-12-09 12:21:54,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4101 states. [2018-12-09 12:21:54,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4101 states to 4101 states and 5471 transitions. [2018-12-09 12:21:54,440 INFO L78 Accepts]: Start accepts. Automaton has 4101 states and 5471 transitions. Word has length 150 [2018-12-09 12:21:54,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:54,440 INFO L480 AbstractCegarLoop]: Abstraction has 4101 states and 5471 transitions. [2018-12-09 12:21:54,440 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:21:54,440 INFO L276 IsEmpty]: Start isEmpty. Operand 4101 states and 5471 transitions. [2018-12-09 12:21:54,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:54,441 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:54,441 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:54,441 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:54,441 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:54,441 INFO L82 PathProgramCache]: Analyzing trace with hash -1625040308, now seen corresponding path program 1 times [2018-12-09 12:21:54,441 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:54,441 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:54,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:54,442 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:54,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:54,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:54,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:54,499 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:54,499 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 12:21:54,499 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:21:54,499 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:21:54,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:54,499 INFO L87 Difference]: Start difference. First operand 4101 states and 5471 transitions. Second operand 6 states. [2018-12-09 12:21:54,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:54,744 INFO L93 Difference]: Finished difference Result 8289 states and 11327 transitions. [2018-12-09 12:21:54,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:21:54,745 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 150 [2018-12-09 12:21:54,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:54,754 INFO L225 Difference]: With dead ends: 8289 [2018-12-09 12:21:54,754 INFO L226 Difference]: Without dead ends: 4213 [2018-12-09 12:21:54,760 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:21:54,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4213 states. [2018-12-09 12:21:54,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4213 to 4181. [2018-12-09 12:21:54,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4181 states. [2018-12-09 12:21:54,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4181 states to 4181 states and 5551 transitions. [2018-12-09 12:21:54,965 INFO L78 Accepts]: Start accepts. Automaton has 4181 states and 5551 transitions. Word has length 150 [2018-12-09 12:21:54,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:54,965 INFO L480 AbstractCegarLoop]: Abstraction has 4181 states and 5551 transitions. [2018-12-09 12:21:54,965 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:21:54,965 INFO L276 IsEmpty]: Start isEmpty. Operand 4181 states and 5551 transitions. [2018-12-09 12:21:54,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:54,965 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:54,966 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:54,966 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:54,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:54,966 INFO L82 PathProgramCache]: Analyzing trace with hash -731553970, now seen corresponding path program 1 times [2018-12-09 12:21:54,966 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:54,966 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:54,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:54,966 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:54,967 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:54,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:55,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:55,024 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:55,024 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:55,024 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:55,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:55,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:55,024 INFO L87 Difference]: Start difference. First operand 4181 states and 5551 transitions. Second operand 5 states. [2018-12-09 12:21:55,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:55,756 INFO L93 Difference]: Finished difference Result 10280 states and 13864 transitions. [2018-12-09 12:21:55,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 12:21:55,756 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:55,756 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:55,767 INFO L225 Difference]: With dead ends: 10280 [2018-12-09 12:21:55,767 INFO L226 Difference]: Without dead ends: 6125 [2018-12-09 12:21:55,773 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-12-09 12:21:55,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6125 states. [2018-12-09 12:21:56,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6125 to 5757. [2018-12-09 12:21:56,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-12-09 12:21:56,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 7407 transitions. [2018-12-09 12:21:56,038 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 7407 transitions. Word has length 150 [2018-12-09 12:21:56,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:56,038 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 7407 transitions. [2018-12-09 12:21:56,038 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:56,038 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 7407 transitions. [2018-12-09 12:21:56,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:56,039 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:56,039 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:56,039 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:56,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:56,039 INFO L82 PathProgramCache]: Analyzing trace with hash -307907248, now seen corresponding path program 1 times [2018-12-09 12:21:56,039 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:56,039 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:56,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:56,040 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:56,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:56,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:56,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:56,112 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:56,112 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:56,113 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:56,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:56,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:56,113 INFO L87 Difference]: Start difference. First operand 5757 states and 7407 transitions. Second operand 5 states. [2018-12-09 12:21:56,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:56,654 INFO L93 Difference]: Finished difference Result 11488 states and 14827 transitions. [2018-12-09 12:21:56,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:56,655 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:56,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:56,665 INFO L225 Difference]: With dead ends: 11488 [2018-12-09 12:21:56,665 INFO L226 Difference]: Without dead ends: 5757 [2018-12-09 12:21:56,670 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:56,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5757 states. [2018-12-09 12:21:56,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5757 to 5757. [2018-12-09 12:21:56,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-12-09 12:21:56,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 7367 transitions. [2018-12-09 12:21:56,939 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 7367 transitions. Word has length 150 [2018-12-09 12:21:56,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:56,940 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 7367 transitions. [2018-12-09 12:21:56,940 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:56,940 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 7367 transitions. [2018-12-09 12:21:56,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:56,940 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:56,940 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:56,940 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:56,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:56,941 INFO L82 PathProgramCache]: Analyzing trace with hash -1679714546, now seen corresponding path program 1 times [2018-12-09 12:21:56,941 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:56,941 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:56,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:56,941 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:56,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:56,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:57,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:57,011 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:57,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:57,012 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:57,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:57,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:57,012 INFO L87 Difference]: Start difference. First operand 5757 states and 7367 transitions. Second operand 5 states. [2018-12-09 12:21:57,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:57,586 INFO L93 Difference]: Finished difference Result 11488 states and 14747 transitions. [2018-12-09 12:21:57,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:57,587 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:57,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:57,596 INFO L225 Difference]: With dead ends: 11488 [2018-12-09 12:21:57,596 INFO L226 Difference]: Without dead ends: 5757 [2018-12-09 12:21:57,600 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:57,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5757 states. [2018-12-09 12:21:57,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5757 to 5757. [2018-12-09 12:21:57,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-12-09 12:21:57,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 7327 transitions. [2018-12-09 12:21:57,871 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 7327 transitions. Word has length 150 [2018-12-09 12:21:57,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:57,871 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 7327 transitions. [2018-12-09 12:21:57,871 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:57,872 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 7327 transitions. [2018-12-09 12:21:57,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:57,872 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:57,872 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:57,872 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:57,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:57,872 INFO L82 PathProgramCache]: Analyzing trace with hash 1585893452, now seen corresponding path program 1 times [2018-12-09 12:21:57,872 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:57,872 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:57,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:57,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:57,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:57,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:57,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:57,928 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:57,928 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:57,929 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:57,929 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:57,929 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:57,929 INFO L87 Difference]: Start difference. First operand 5757 states and 7327 transitions. Second operand 5 states. [2018-12-09 12:21:58,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:58,465 INFO L93 Difference]: Finished difference Result 11488 states and 14667 transitions. [2018-12-09 12:21:58,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:21:58,465 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:58,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:58,477 INFO L225 Difference]: With dead ends: 11488 [2018-12-09 12:21:58,477 INFO L226 Difference]: Without dead ends: 5757 [2018-12-09 12:21:58,486 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:21:58,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5757 states. [2018-12-09 12:21:58,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5757 to 5757. [2018-12-09 12:21:58,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-12-09 12:21:58,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 7287 transitions. [2018-12-09 12:21:58,797 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 7287 transitions. Word has length 150 [2018-12-09 12:21:58,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:21:58,797 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 7287 transitions. [2018-12-09 12:21:58,797 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:21:58,798 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 7287 transitions. [2018-12-09 12:21:58,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:21:58,798 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:21:58,798 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:21:58,798 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:21:58,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:21:58,798 INFO L82 PathProgramCache]: Analyzing trace with hash -2049542322, now seen corresponding path program 1 times [2018-12-09 12:21:58,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:21:58,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:21:58,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:58,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:21:58,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:21:58,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:21:58,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:21:58,852 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:21:58,852 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:21:58,852 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:21:58,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:21:58,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:21:58,852 INFO L87 Difference]: Start difference. First operand 5757 states and 7287 transitions. Second operand 5 states. [2018-12-09 12:21:59,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:21:59,630 INFO L93 Difference]: Finished difference Result 13698 states and 17482 transitions. [2018-12-09 12:21:59,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:21:59,630 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:21:59,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:21:59,645 INFO L225 Difference]: With dead ends: 13698 [2018-12-09 12:21:59,645 INFO L226 Difference]: Without dead ends: 7967 [2018-12-09 12:21:59,652 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:21:59,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7967 states. [2018-12-09 12:22:00,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7967 to 7671. [2018-12-09 12:22:00,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7671 states. [2018-12-09 12:22:00,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7671 states to 7671 states and 9517 transitions. [2018-12-09 12:22:00,060 INFO L78 Accepts]: Start accepts. Automaton has 7671 states and 9517 transitions. Word has length 150 [2018-12-09 12:22:00,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:00,060 INFO L480 AbstractCegarLoop]: Abstraction has 7671 states and 9517 transitions. [2018-12-09 12:22:00,060 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:22:00,060 INFO L276 IsEmpty]: Start isEmpty. Operand 7671 states and 9517 transitions. [2018-12-09 12:22:00,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:22:00,061 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:00,061 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:00,061 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:00,061 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:00,061 INFO L82 PathProgramCache]: Analyzing trace with hash 1851058188, now seen corresponding path program 1 times [2018-12-09 12:22:00,061 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:00,061 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:00,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:00,062 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:00,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:00,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:00,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:22:00,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:00,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:22:00,112 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:22:00,112 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:22:00,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:22:00,112 INFO L87 Difference]: Start difference. First operand 7671 states and 9517 transitions. Second operand 5 states. [2018-12-09 12:22:00,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:00,711 INFO L93 Difference]: Finished difference Result 15314 states and 19075 transitions. [2018-12-09 12:22:00,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 12:22:00,711 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:22:00,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:00,729 INFO L225 Difference]: With dead ends: 15314 [2018-12-09 12:22:00,729 INFO L226 Difference]: Without dead ends: 7671 [2018-12-09 12:22:00,740 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:22:00,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7671 states. [2018-12-09 12:22:01,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7671 to 7671. [2018-12-09 12:22:01,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7671 states. [2018-12-09 12:22:01,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7671 states to 7671 states and 9461 transitions. [2018-12-09 12:22:01,159 INFO L78 Accepts]: Start accepts. Automaton has 7671 states and 9461 transitions. Word has length 150 [2018-12-09 12:22:01,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:01,159 INFO L480 AbstractCegarLoop]: Abstraction has 7671 states and 9461 transitions. [2018-12-09 12:22:01,159 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:22:01,160 INFO L276 IsEmpty]: Start isEmpty. Operand 7671 states and 9461 transitions. [2018-12-09 12:22:01,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:22:01,160 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:01,161 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:01,161 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:01,161 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:01,161 INFO L82 PathProgramCache]: Analyzing trace with hash 1007052686, now seen corresponding path program 1 times [2018-12-09 12:22:01,161 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:01,161 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:01,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:01,162 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:01,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:01,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:01,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:22:01,216 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:01,216 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:22:01,216 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:22:01,217 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:22:01,217 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:22:01,217 INFO L87 Difference]: Start difference. First operand 7671 states and 9461 transitions. Second operand 5 states. [2018-12-09 12:22:02,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:02,019 INFO L93 Difference]: Finished difference Result 16190 states and 20277 transitions. [2018-12-09 12:22:02,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:22:02,019 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:22:02,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:02,032 INFO L225 Difference]: With dead ends: 16190 [2018-12-09 12:22:02,032 INFO L226 Difference]: Without dead ends: 8547 [2018-12-09 12:22:02,040 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:22:02,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8547 states. [2018-12-09 12:22:02,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8547 to 8543. [2018-12-09 12:22:02,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8543 states. [2018-12-09 12:22:02,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8543 states to 8543 states and 10497 transitions. [2018-12-09 12:22:02,504 INFO L78 Accepts]: Start accepts. Automaton has 8543 states and 10497 transitions. Word has length 150 [2018-12-09 12:22:02,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:02,505 INFO L480 AbstractCegarLoop]: Abstraction has 8543 states and 10497 transitions. [2018-12-09 12:22:02,505 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:22:02,505 INFO L276 IsEmpty]: Start isEmpty. Operand 8543 states and 10497 transitions. [2018-12-09 12:22:02,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:22:02,505 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:02,505 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:02,506 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:02,506 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:02,506 INFO L82 PathProgramCache]: Analyzing trace with hash -1236930612, now seen corresponding path program 1 times [2018-12-09 12:22:02,506 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:02,506 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:02,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:02,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:02,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:02,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:02,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:22:02,544 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:02,545 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:22:02,545 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:22:02,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:22:02,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:22:02,545 INFO L87 Difference]: Start difference. First operand 8543 states and 10497 transitions. Second operand 5 states. [2018-12-09 12:22:03,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:03,459 INFO L93 Difference]: Finished difference Result 18174 states and 23002 transitions. [2018-12-09 12:22:03,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:22:03,459 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:22:03,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:03,474 INFO L225 Difference]: With dead ends: 18174 [2018-12-09 12:22:03,474 INFO L226 Difference]: Without dead ends: 9659 [2018-12-09 12:22:03,484 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:22:03,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9659 states. [2018-12-09 12:22:03,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9659 to 9167. [2018-12-09 12:22:03,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9167 states. [2018-12-09 12:22:03,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9167 states to 9167 states and 11093 transitions. [2018-12-09 12:22:03,981 INFO L78 Accepts]: Start accepts. Automaton has 9167 states and 11093 transitions. Word has length 150 [2018-12-09 12:22:03,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:03,981 INFO L480 AbstractCegarLoop]: Abstraction has 9167 states and 11093 transitions. [2018-12-09 12:22:03,982 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:22:03,982 INFO L276 IsEmpty]: Start isEmpty. Operand 9167 states and 11093 transitions. [2018-12-09 12:22:03,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:22:03,982 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:03,982 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:03,982 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:03,982 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:03,982 INFO L82 PathProgramCache]: Analyzing trace with hash -1309317170, now seen corresponding path program 1 times [2018-12-09 12:22:03,982 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:03,983 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:03,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:03,983 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:03,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:03,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:04,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:22:04,022 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:04,022 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:22:04,023 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:22:04,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:22:04,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:22:04,023 INFO L87 Difference]: Start difference. First operand 9167 states and 11093 transitions. Second operand 5 states. [2018-12-09 12:22:05,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:05,014 INFO L93 Difference]: Finished difference Result 19620 states and 24642 transitions. [2018-12-09 12:22:05,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:22:05,015 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:22:05,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:05,031 INFO L225 Difference]: With dead ends: 19620 [2018-12-09 12:22:05,031 INFO L226 Difference]: Without dead ends: 10479 [2018-12-09 12:22:05,043 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:22:05,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10479 states. [2018-12-09 12:22:05,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10479 to 9615. [2018-12-09 12:22:05,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9615 states. [2018-12-09 12:22:05,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9615 states to 9615 states and 11445 transitions. [2018-12-09 12:22:05,604 INFO L78 Accepts]: Start accepts. Automaton has 9615 states and 11445 transitions. Word has length 150 [2018-12-09 12:22:05,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:05,605 INFO L480 AbstractCegarLoop]: Abstraction has 9615 states and 11445 transitions. [2018-12-09 12:22:05,605 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:22:05,605 INFO L276 IsEmpty]: Start isEmpty. Operand 9615 states and 11445 transitions. [2018-12-09 12:22:05,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:22:05,605 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:05,605 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:05,605 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:05,605 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:05,606 INFO L82 PathProgramCache]: Analyzing trace with hash -1034557556, now seen corresponding path program 1 times [2018-12-09 12:22:05,606 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:05,606 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:05,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:05,606 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:05,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:05,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:05,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:22:05,646 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:05,646 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:22:05,646 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:22:05,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:22:05,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:22:05,646 INFO L87 Difference]: Start difference. First operand 9615 states and 11445 transitions. Second operand 5 states. [2018-12-09 12:22:06,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:06,632 INFO L93 Difference]: Finished difference Result 20240 states and 25054 transitions. [2018-12-09 12:22:06,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:22:06,632 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:22:06,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:06,649 INFO L225 Difference]: With dead ends: 20240 [2018-12-09 12:22:06,649 INFO L226 Difference]: Without dead ends: 10651 [2018-12-09 12:22:06,662 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:22:06,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10651 states. [2018-12-09 12:22:07,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10651 to 10003. [2018-12-09 12:22:07,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10003 states. [2018-12-09 12:22:07,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10003 states to 10003 states and 11713 transitions. [2018-12-09 12:22:07,234 INFO L78 Accepts]: Start accepts. Automaton has 10003 states and 11713 transitions. Word has length 150 [2018-12-09 12:22:07,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:07,234 INFO L480 AbstractCegarLoop]: Abstraction has 10003 states and 11713 transitions. [2018-12-09 12:22:07,235 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:22:07,235 INFO L276 IsEmpty]: Start isEmpty. Operand 10003 states and 11713 transitions. [2018-12-09 12:22:07,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:22:07,235 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:07,235 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:07,235 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:07,235 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:07,235 INFO L82 PathProgramCache]: Analyzing trace with hash -1011925302, now seen corresponding path program 1 times [2018-12-09 12:22:07,235 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:07,236 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:07,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:07,236 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:07,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:07,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:07,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:22:07,281 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:07,281 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 12:22:07,281 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:22:07,281 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:22:07,281 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:22:07,281 INFO L87 Difference]: Start difference. First operand 10003 states and 11713 transitions. Second operand 5 states. [2018-12-09 12:22:08,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:08,433 INFO L93 Difference]: Finished difference Result 22004 states and 27311 transitions. [2018-12-09 12:22:08,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 12:22:08,434 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 150 [2018-12-09 12:22:08,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:08,455 INFO L225 Difference]: With dead ends: 22004 [2018-12-09 12:22:08,455 INFO L226 Difference]: Without dead ends: 12027 [2018-12-09 12:22:08,468 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 12:22:08,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12027 states. [2018-12-09 12:22:09,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12027 to 10907. [2018-12-09 12:22:09,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10907 states. [2018-12-09 12:22:09,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10907 states to 10907 states and 12529 transitions. [2018-12-09 12:22:09,139 INFO L78 Accepts]: Start accepts. Automaton has 10907 states and 12529 transitions. Word has length 150 [2018-12-09 12:22:09,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:09,140 INFO L480 AbstractCegarLoop]: Abstraction has 10907 states and 12529 transitions. [2018-12-09 12:22:09,140 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:22:09,140 INFO L276 IsEmpty]: Start isEmpty. Operand 10907 states and 12529 transitions. [2018-12-09 12:22:09,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-12-09 12:22:09,140 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:09,140 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:09,140 INFO L423 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:09,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:09,141 INFO L82 PathProgramCache]: Analyzing trace with hash 374278092, now seen corresponding path program 1 times [2018-12-09 12:22:09,141 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:09,141 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:09,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:09,141 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:09,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:09,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:09,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:22:09,161 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:09,161 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 12:22:09,161 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 12:22:09,161 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 12:22:09,161 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:22:09,161 INFO L87 Difference]: Start difference. First operand 10907 states and 12529 transitions. Second operand 3 states. [2018-12-09 12:22:10,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:10,311 INFO L93 Difference]: Finished difference Result 31802 states and 36913 transitions. [2018-12-09 12:22:10,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 12:22:10,312 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 150 [2018-12-09 12:22:10,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:10,347 INFO L225 Difference]: With dead ends: 31802 [2018-12-09 12:22:10,347 INFO L226 Difference]: Without dead ends: 20923 [2018-12-09 12:22:10,364 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:22:10,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20923 states. [2018-12-09 12:22:11,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20923 to 20920. [2018-12-09 12:22:11,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20920 states. [2018-12-09 12:22:11,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20920 states to 20920 states and 24150 transitions. [2018-12-09 12:22:11,557 INFO L78 Accepts]: Start accepts. Automaton has 20920 states and 24150 transitions. Word has length 150 [2018-12-09 12:22:11,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:11,557 INFO L480 AbstractCegarLoop]: Abstraction has 20920 states and 24150 transitions. [2018-12-09 12:22:11,557 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 12:22:11,557 INFO L276 IsEmpty]: Start isEmpty. Operand 20920 states and 24150 transitions. [2018-12-09 12:22:11,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-12-09 12:22:11,558 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:11,558 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:11,558 INFO L423 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:11,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:11,558 INFO L82 PathProgramCache]: Analyzing trace with hash -333800920, now seen corresponding path program 1 times [2018-12-09 12:22:11,558 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:11,558 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:11,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:11,559 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:11,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:11,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:11,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 12:22:11,587 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:11,587 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 12:22:11,587 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 12:22:11,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 12:22:11,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:22:11,587 INFO L87 Difference]: Start difference. First operand 20920 states and 24150 transitions. Second operand 3 states. [2018-12-09 12:22:13,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:13,993 INFO L93 Difference]: Finished difference Result 62015 states and 74436 transitions. [2018-12-09 12:22:13,993 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 12:22:13,993 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 151 [2018-12-09 12:22:13,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:14,061 INFO L225 Difference]: With dead ends: 62015 [2018-12-09 12:22:14,061 INFO L226 Difference]: Without dead ends: 41132 [2018-12-09 12:22:14,089 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:22:14,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41132 states. [2018-12-09 12:22:16,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41132 to 41132. [2018-12-09 12:22:16,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41132 states. [2018-12-09 12:22:16,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41132 states to 41132 states and 48625 transitions. [2018-12-09 12:22:16,503 INFO L78 Accepts]: Start accepts. Automaton has 41132 states and 48625 transitions. Word has length 151 [2018-12-09 12:22:16,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:16,503 INFO L480 AbstractCegarLoop]: Abstraction has 41132 states and 48625 transitions. [2018-12-09 12:22:16,503 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 12:22:16,503 INFO L276 IsEmpty]: Start isEmpty. Operand 41132 states and 48625 transitions. [2018-12-09 12:22:16,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 176 [2018-12-09 12:22:16,506 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:16,507 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:16,507 INFO L423 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:16,507 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:16,507 INFO L82 PathProgramCache]: Analyzing trace with hash -1702384506, now seen corresponding path program 1 times [2018-12-09 12:22:16,507 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:16,507 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:16,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:16,508 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:16,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:16,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:16,540 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-12-09 12:22:16,540 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:16,541 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 12:22:16,541 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 12:22:16,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 12:22:16,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:22:16,541 INFO L87 Difference]: Start difference. First operand 41132 states and 48625 transitions. Second operand 4 states. [2018-12-09 12:22:18,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:18,681 INFO L93 Difference]: Finished difference Result 73143 states and 86307 transitions. [2018-12-09 12:22:18,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:22:18,682 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 175 [2018-12-09 12:22:18,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:18,746 INFO L225 Difference]: With dead ends: 73143 [2018-12-09 12:22:18,746 INFO L226 Difference]: Without dead ends: 32039 [2018-12-09 12:22:18,795 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 12:22:18,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32039 states. [2018-12-09 12:22:20,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32039 to 31599. [2018-12-09 12:22:20,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31599 states. [2018-12-09 12:22:20,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31599 states to 31599 states and 37243 transitions. [2018-12-09 12:22:20,749 INFO L78 Accepts]: Start accepts. Automaton has 31599 states and 37243 transitions. Word has length 175 [2018-12-09 12:22:20,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:20,749 INFO L480 AbstractCegarLoop]: Abstraction has 31599 states and 37243 transitions. [2018-12-09 12:22:20,749 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 12:22:20,749 INFO L276 IsEmpty]: Start isEmpty. Operand 31599 states and 37243 transitions. [2018-12-09 12:22:20,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 176 [2018-12-09 12:22:20,751 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:20,751 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:20,751 INFO L423 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:20,751 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:20,751 INFO L82 PathProgramCache]: Analyzing trace with hash 1925200900, now seen corresponding path program 1 times [2018-12-09 12:22:20,752 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:20,752 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:20,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:20,752 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:20,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:20,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:20,776 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-09 12:22:20,776 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:20,776 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 12:22:20,777 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 12:22:20,777 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 12:22:20,777 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:22:20,777 INFO L87 Difference]: Start difference. First operand 31599 states and 37243 transitions. Second operand 3 states. [2018-12-09 12:22:24,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:24,516 INFO L93 Difference]: Finished difference Result 94393 states and 113724 transitions. [2018-12-09 12:22:24,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 12:22:24,517 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 175 [2018-12-09 12:22:24,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:24,618 INFO L225 Difference]: With dead ends: 94393 [2018-12-09 12:22:24,618 INFO L226 Difference]: Without dead ends: 47265 [2018-12-09 12:22:24,686 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:22:24,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47265 states. [2018-12-09 12:22:27,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47265 to 47265. [2018-12-09 12:22:27,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47265 states. [2018-12-09 12:22:27,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47265 states to 47265 states and 55903 transitions. [2018-12-09 12:22:27,707 INFO L78 Accepts]: Start accepts. Automaton has 47265 states and 55903 transitions. Word has length 175 [2018-12-09 12:22:27,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:27,707 INFO L480 AbstractCegarLoop]: Abstraction has 47265 states and 55903 transitions. [2018-12-09 12:22:27,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 12:22:27,707 INFO L276 IsEmpty]: Start isEmpty. Operand 47265 states and 55903 transitions. [2018-12-09 12:22:27,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 256 [2018-12-09 12:22:27,724 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:27,724 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:27,725 INFO L423 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:27,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:27,725 INFO L82 PathProgramCache]: Analyzing trace with hash 51667787, now seen corresponding path program 1 times [2018-12-09 12:22:27,725 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:27,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:27,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:27,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:27,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:27,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:27,767 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-12-09 12:22:27,767 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 12:22:27,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 12:22:27,768 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 12:22:27,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 12:22:27,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:22:27,768 INFO L87 Difference]: Start difference. First operand 47265 states and 55903 transitions. Second operand 3 states. [2018-12-09 12:22:32,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:32,697 INFO L93 Difference]: Finished difference Result 128312 states and 156988 transitions. [2018-12-09 12:22:32,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 12:22:32,698 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 255 [2018-12-09 12:22:32,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:32,879 INFO L225 Difference]: With dead ends: 128312 [2018-12-09 12:22:32,879 INFO L226 Difference]: Without dead ends: 81075 [2018-12-09 12:22:32,978 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 12:22:33,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81075 states. [2018-12-09 12:22:37,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81075 to 81072. [2018-12-09 12:22:37,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81072 states. [2018-12-09 12:22:38,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81072 states to 81072 states and 97835 transitions. [2018-12-09 12:22:38,149 INFO L78 Accepts]: Start accepts. Automaton has 81072 states and 97835 transitions. Word has length 255 [2018-12-09 12:22:38,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:38,149 INFO L480 AbstractCegarLoop]: Abstraction has 81072 states and 97835 transitions. [2018-12-09 12:22:38,149 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 12:22:38,149 INFO L276 IsEmpty]: Start isEmpty. Operand 81072 states and 97835 transitions. [2018-12-09 12:22:38,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 257 [2018-12-09 12:22:38,171 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:38,172 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:38,172 INFO L423 AbstractCegarLoop]: === Iteration 41 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:38,172 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:38,172 INFO L82 PathProgramCache]: Analyzing trace with hash 253056944, now seen corresponding path program 1 times [2018-12-09 12:22:38,172 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:38,172 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:38,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:38,173 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:38,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:38,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:38,220 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-12-09 12:22:38,220 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 12:22:38,220 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 12:22:38,226 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:38,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:38,339 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 12:22:38,394 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 69 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 12:22:38,410 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 12:22:38,410 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-12-09 12:22:38,410 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:22:38,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:22:38,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:22:38,411 INFO L87 Difference]: Start difference. First operand 81072 states and 97835 transitions. Second operand 6 states. [2018-12-09 12:22:47,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:22:47,254 INFO L93 Difference]: Finished difference Result 199169 states and 254180 transitions. [2018-12-09 12:22:47,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 12:22:47,254 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 256 [2018-12-09 12:22:47,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:22:47,466 INFO L225 Difference]: With dead ends: 199169 [2018-12-09 12:22:47,466 INFO L226 Difference]: Without dead ends: 91259 [2018-12-09 12:22:47,669 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 259 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-12-09 12:22:47,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91259 states. [2018-12-09 12:22:54,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91259 to 91259. [2018-12-09 12:22:54,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91259 states. [2018-12-09 12:22:55,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91259 states to 91259 states and 111267 transitions. [2018-12-09 12:22:55,197 INFO L78 Accepts]: Start accepts. Automaton has 91259 states and 111267 transitions. Word has length 256 [2018-12-09 12:22:55,198 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:22:55,198 INFO L480 AbstractCegarLoop]: Abstraction has 91259 states and 111267 transitions. [2018-12-09 12:22:55,198 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:22:55,198 INFO L276 IsEmpty]: Start isEmpty. Operand 91259 states and 111267 transitions. [2018-12-09 12:22:55,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 513 [2018-12-09 12:22:55,272 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:22:55,272 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:22:55,272 INFO L423 AbstractCegarLoop]: === Iteration 42 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:22:55,272 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:22:55,273 INFO L82 PathProgramCache]: Analyzing trace with hash 359452647, now seen corresponding path program 1 times [2018-12-09 12:22:55,273 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:22:55,273 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:22:55,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:55,274 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:55,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:22:55,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:55,460 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 41 proven. 26 refuted. 0 times theorem prover too weak. 504 trivial. 0 not checked. [2018-12-09 12:22:55,460 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 12:22:55,460 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 12:22:55,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:22:55,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:22:55,598 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 12:22:55,690 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 312 proven. 0 refuted. 0 times theorem prover too weak. 259 trivial. 0 not checked. [2018-12-09 12:22:55,706 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 12:22:55,706 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2018-12-09 12:22:55,707 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-09 12:22:55,707 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-09 12:22:55,707 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-12-09 12:22:55,708 INFO L87 Difference]: Start difference. First operand 91259 states and 111267 transitions. Second operand 12 states. [2018-12-09 12:23:00,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:23:00,121 INFO L93 Difference]: Finished difference Result 150324 states and 182065 transitions. [2018-12-09 12:23:00,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-09 12:23:00,121 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 512 [2018-12-09 12:23:00,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:23:00,279 INFO L225 Difference]: With dead ends: 150324 [2018-12-09 12:23:00,279 INFO L226 Difference]: Without dead ends: 59093 [2018-12-09 12:23:00,401 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 525 GetRequests, 510 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=50, Invalid=160, Unknown=0, NotChecked=0, Total=210 [2018-12-09 12:23:00,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59093 states. [2018-12-09 12:23:04,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59093 to 56934. [2018-12-09 12:23:04,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56934 states. [2018-12-09 12:23:04,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56934 states to 56934 states and 65178 transitions. [2018-12-09 12:23:04,224 INFO L78 Accepts]: Start accepts. Automaton has 56934 states and 65178 transitions. Word has length 512 [2018-12-09 12:23:04,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:23:04,224 INFO L480 AbstractCegarLoop]: Abstraction has 56934 states and 65178 transitions. [2018-12-09 12:23:04,224 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-09 12:23:04,224 INFO L276 IsEmpty]: Start isEmpty. Operand 56934 states and 65178 transitions. [2018-12-09 12:23:04,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 352 [2018-12-09 12:23:04,262 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:23:04,262 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:23:04,262 INFO L423 AbstractCegarLoop]: === Iteration 43 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:23:04,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:23:04,262 INFO L82 PathProgramCache]: Analyzing trace with hash -772722575, now seen corresponding path program 1 times [2018-12-09 12:23:04,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:23:04,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:23:04,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:23:04,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:23:04,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:23:04,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:23:04,335 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 19 proven. 7 refuted. 0 times theorem prover too weak. 205 trivial. 0 not checked. [2018-12-09 12:23:04,335 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 12:23:04,335 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 12:23:04,340 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:23:04,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:23:04,437 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 12:23:04,524 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 146 proven. 0 refuted. 0 times theorem prover too weak. 85 trivial. 0 not checked. [2018-12-09 12:23:04,539 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 12:23:04,540 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-12-09 12:23:04,540 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:23:04,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:23:04,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:23:04,540 INFO L87 Difference]: Start difference. First operand 56934 states and 65178 transitions. Second operand 6 states. [2018-12-09 12:23:13,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:23:13,159 INFO L93 Difference]: Finished difference Result 167344 states and 198823 transitions. [2018-12-09 12:23:13,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-12-09 12:23:13,160 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 351 [2018-12-09 12:23:13,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:23:13,339 INFO L225 Difference]: With dead ends: 167344 [2018-12-09 12:23:13,340 INFO L226 Difference]: Without dead ends: 92028 [2018-12-09 12:23:13,435 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 358 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=74, Invalid=166, Unknown=0, NotChecked=0, Total=240 [2018-12-09 12:23:13,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92028 states. [2018-12-09 12:23:19,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92028 to 86926. [2018-12-09 12:23:19,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86926 states. [2018-12-09 12:23:19,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86926 states to 86926 states and 98226 transitions. [2018-12-09 12:23:19,233 INFO L78 Accepts]: Start accepts. Automaton has 86926 states and 98226 transitions. Word has length 351 [2018-12-09 12:23:19,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:23:19,233 INFO L480 AbstractCegarLoop]: Abstraction has 86926 states and 98226 transitions. [2018-12-09 12:23:19,233 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:23:19,233 INFO L276 IsEmpty]: Start isEmpty. Operand 86926 states and 98226 transitions. [2018-12-09 12:23:19,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 436 [2018-12-09 12:23:19,286 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:23:19,287 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:23:19,287 INFO L423 AbstractCegarLoop]: === Iteration 44 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:23:19,287 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:23:19,287 INFO L82 PathProgramCache]: Analyzing trace with hash -1345235488, now seen corresponding path program 1 times [2018-12-09 12:23:19,287 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:23:19,287 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:23:19,288 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:23:19,288 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:23:19,288 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:23:19,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:23:19,381 INFO L134 CoverageAnalysis]: Checked inductivity of 439 backedges. 19 proven. 10 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2018-12-09 12:23:19,381 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 12:23:19,381 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 12:23:19,390 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:23:19,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:23:19,507 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 12:23:19,558 INFO L134 CoverageAnalysis]: Checked inductivity of 439 backedges. 279 proven. 0 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2018-12-09 12:23:19,573 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 12:23:19,573 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-12-09 12:23:19,573 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:23:19,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:23:19,573 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:23:19,573 INFO L87 Difference]: Start difference. First operand 86926 states and 98226 transitions. Second operand 5 states. [2018-12-09 12:23:32,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:23:32,416 INFO L93 Difference]: Finished difference Result 240362 states and 281781 transitions. [2018-12-09 12:23:32,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-12-09 12:23:32,417 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 435 [2018-12-09 12:23:32,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:23:32,708 INFO L225 Difference]: With dead ends: 240362 [2018-12-09 12:23:32,709 INFO L226 Difference]: Without dead ends: 153658 [2018-12-09 12:23:32,835 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 449 GetRequests, 442 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-12-09 12:23:32,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153658 states. [2018-12-09 12:23:43,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153658 to 149751. [2018-12-09 12:23:43,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149751 states. [2018-12-09 12:23:43,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149751 states to 149751 states and 168681 transitions. [2018-12-09 12:23:43,467 INFO L78 Accepts]: Start accepts. Automaton has 149751 states and 168681 transitions. Word has length 435 [2018-12-09 12:23:43,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:23:43,467 INFO L480 AbstractCegarLoop]: Abstraction has 149751 states and 168681 transitions. [2018-12-09 12:23:43,467 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:23:43,467 INFO L276 IsEmpty]: Start isEmpty. Operand 149751 states and 168681 transitions. [2018-12-09 12:23:43,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 441 [2018-12-09 12:23:43,593 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:23:43,594 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:23:43,594 INFO L423 AbstractCegarLoop]: === Iteration 45 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:23:43,594 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:23:43,594 INFO L82 PathProgramCache]: Analyzing trace with hash 1315021661, now seen corresponding path program 1 times [2018-12-09 12:23:43,594 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:23:43,594 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:23:43,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:23:43,595 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:23:43,595 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:23:43,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:23:43,674 INFO L134 CoverageAnalysis]: Checked inductivity of 446 backedges. 1 proven. 54 refuted. 0 times theorem prover too weak. 391 trivial. 0 not checked. [2018-12-09 12:23:43,674 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 12:23:43,674 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 12:23:43,680 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:23:43,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:23:43,934 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 12:23:43,988 INFO L134 CoverageAnalysis]: Checked inductivity of 446 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 353 trivial. 0 not checked. [2018-12-09 12:23:44,004 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 12:23:44,004 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-12-09 12:23:44,004 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 12:23:44,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 12:23:44,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:23:44,005 INFO L87 Difference]: Start difference. First operand 149751 states and 168681 transitions. Second operand 5 states. [2018-12-09 12:23:53,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:23:53,818 INFO L93 Difference]: Finished difference Result 244113 states and 274142 transitions. [2018-12-09 12:23:53,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 12:23:53,819 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 440 [2018-12-09 12:23:53,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:23:54,028 INFO L225 Difference]: With dead ends: 244113 [2018-12-09 12:23:54,028 INFO L226 Difference]: Without dead ends: 109894 [2018-12-09 12:23:54,164 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 439 SyntacticMatches, 3 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-12-09 12:23:54,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109894 states. [2018-12-09 12:24:01,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109894 to 109642. [2018-12-09 12:24:01,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109642 states. [2018-12-09 12:24:01,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109642 states to 109642 states and 122092 transitions. [2018-12-09 12:24:01,855 INFO L78 Accepts]: Start accepts. Automaton has 109642 states and 122092 transitions. Word has length 440 [2018-12-09 12:24:01,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:24:01,855 INFO L480 AbstractCegarLoop]: Abstraction has 109642 states and 122092 transitions. [2018-12-09 12:24:01,855 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 12:24:01,855 INFO L276 IsEmpty]: Start isEmpty. Operand 109642 states and 122092 transitions. [2018-12-09 12:24:01,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 540 [2018-12-09 12:24:01,928 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:24:01,929 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:24:01,929 INFO L423 AbstractCegarLoop]: === Iteration 46 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:24:01,929 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:24:01,929 INFO L82 PathProgramCache]: Analyzing trace with hash -807980157, now seen corresponding path program 1 times [2018-12-09 12:24:01,929 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:24:01,929 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:24:01,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:24:01,930 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:24:01,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:24:01,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:24:02,038 INFO L134 CoverageAnalysis]: Checked inductivity of 740 backedges. 23 proven. 17 refuted. 0 times theorem prover too weak. 700 trivial. 0 not checked. [2018-12-09 12:24:02,038 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 12:24:02,038 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 12:24:02,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:24:02,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:24:02,171 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 12:24:02,259 INFO L134 CoverageAnalysis]: Checked inductivity of 740 backedges. 308 proven. 0 refuted. 0 times theorem prover too weak. 432 trivial. 0 not checked. [2018-12-09 12:24:02,275 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 12:24:02,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-12-09 12:24:02,276 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:24:02,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:24:02,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:24:02,276 INFO L87 Difference]: Start difference. First operand 109642 states and 122092 transitions. Second operand 6 states. [2018-12-09 12:24:16,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:24:16,280 INFO L93 Difference]: Finished difference Result 292787 states and 326715 transitions. [2018-12-09 12:24:16,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 12:24:16,281 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 539 [2018-12-09 12:24:16,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:24:16,563 INFO L225 Difference]: With dead ends: 292787 [2018-12-09 12:24:16,563 INFO L226 Difference]: Without dead ends: 157476 [2018-12-09 12:24:16,699 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 551 GetRequests, 545 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-12-09 12:24:16,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157476 states. [2018-12-09 12:24:28,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157476 to 154188. [2018-12-09 12:24:28,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154188 states. [2018-12-09 12:24:29,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154188 states to 154188 states and 171809 transitions. [2018-12-09 12:24:29,225 INFO L78 Accepts]: Start accepts. Automaton has 154188 states and 171809 transitions. Word has length 539 [2018-12-09 12:24:29,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:24:29,225 INFO L480 AbstractCegarLoop]: Abstraction has 154188 states and 171809 transitions. [2018-12-09 12:24:29,225 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:24:29,226 INFO L276 IsEmpty]: Start isEmpty. Operand 154188 states and 171809 transitions. [2018-12-09 12:24:29,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 636 [2018-12-09 12:24:29,315 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:24:29,315 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:24:29,316 INFO L423 AbstractCegarLoop]: === Iteration 47 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:24:29,316 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:24:29,316 INFO L82 PathProgramCache]: Analyzing trace with hash 2032291581, now seen corresponding path program 1 times [2018-12-09 12:24:29,316 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:24:29,316 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:24:29,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:24:29,316 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:24:29,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:24:29,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:24:29,526 INFO L134 CoverageAnalysis]: Checked inductivity of 1110 backedges. 25 proven. 22 refuted. 0 times theorem prover too weak. 1063 trivial. 0 not checked. [2018-12-09 12:24:29,526 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 12:24:29,526 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 12:24:29,534 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:24:29,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 12:24:29,694 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 12:24:29,807 INFO L134 CoverageAnalysis]: Checked inductivity of 1110 backedges. 380 proven. 0 refuted. 0 times theorem prover too weak. 730 trivial. 0 not checked. [2018-12-09 12:24:29,823 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 12:24:29,823 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-12-09 12:24:29,823 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 12:24:29,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 12:24:29,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 12:24:29,824 INFO L87 Difference]: Start difference. First operand 154188 states and 171809 transitions. Second operand 6 states. [2018-12-09 12:24:36,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 12:24:36,246 INFO L93 Difference]: Finished difference Result 211269 states and 235860 transitions. [2018-12-09 12:24:36,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 12:24:36,246 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 635 [2018-12-09 12:24:36,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 12:24:36,298 INFO L225 Difference]: With dead ends: 211269 [2018-12-09 12:24:36,298 INFO L226 Difference]: Without dead ends: 16063 [2018-12-09 12:24:36,454 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 649 GetRequests, 643 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-12-09 12:24:36,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16063 states. [2018-12-09 12:24:37,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16063 to 16058. [2018-12-09 12:24:37,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16058 states. [2018-12-09 12:24:37,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16058 states to 16058 states and 17485 transitions. [2018-12-09 12:24:37,759 INFO L78 Accepts]: Start accepts. Automaton has 16058 states and 17485 transitions. Word has length 635 [2018-12-09 12:24:37,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 12:24:37,759 INFO L480 AbstractCegarLoop]: Abstraction has 16058 states and 17485 transitions. [2018-12-09 12:24:37,759 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 12:24:37,759 INFO L276 IsEmpty]: Start isEmpty. Operand 16058 states and 17485 transitions. [2018-12-09 12:24:37,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 725 [2018-12-09 12:24:37,772 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 12:24:37,773 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 12:24:37,773 INFO L423 AbstractCegarLoop]: === Iteration 48 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 12:24:37,773 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 12:24:37,773 INFO L82 PathProgramCache]: Analyzing trace with hash -2115959492, now seen corresponding path program 1 times [2018-12-09 12:24:37,773 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-12-09 12:24:37,773 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-12-09 12:24:37,774 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:24:37,774 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 12:24:37,774 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 12:24:37,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 12:24:37,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 12:24:38,065 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 12:24:38,325 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 12:24:38 BoogieIcfgContainer [2018-12-09 12:24:38,325 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 12:24:38,326 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 12:24:38,326 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 12:24:38,326 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 12:24:38,326 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 12:21:45" (3/4) ... [2018-12-09 12:24:38,328 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-09 12:24:38,534 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_90b4d637-a748-4d49-9455-d1febae4aad3/bin-2019/uautomizer/witness.graphml [2018-12-09 12:24:38,534 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 12:24:38,535 INFO L168 Benchmark]: Toolchain (without parser) took 173789.13 ms. Allocated memory was 1.0 GB in the beginning and 6.5 GB in the end (delta: 5.5 GB). Free memory was 956.0 MB in the beginning and 2.7 GB in the end (delta: -1.7 GB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. [2018-12-09 12:24:38,536 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 12:24:38,536 INFO L168 Benchmark]: CACSL2BoogieTranslator took 244.59 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 94.9 MB). Free memory was 956.0 MB in the beginning and 1.1 GB in the end (delta: -136.1 MB). Peak memory consumption was 36.0 MB. Max. memory is 11.5 GB. [2018-12-09 12:24:38,536 INFO L168 Benchmark]: Boogie Procedure Inliner took 17.39 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-12-09 12:24:38,536 INFO L168 Benchmark]: Boogie Preprocessor took 31.95 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-12-09 12:24:38,536 INFO L168 Benchmark]: RCFGBuilder took 387.29 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 58.4 MB). Peak memory consumption was 58.4 MB. Max. memory is 11.5 GB. [2018-12-09 12:24:38,536 INFO L168 Benchmark]: TraceAbstraction took 172896.55 ms. Allocated memory was 1.1 GB in the beginning and 6.5 GB in the end (delta: 5.4 GB). Free memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. [2018-12-09 12:24:38,537 INFO L168 Benchmark]: Witness Printer took 208.47 ms. Allocated memory is still 6.5 GB. Free memory was 2.8 GB in the beginning and 2.7 GB in the end (delta: 131.0 MB). Peak memory consumption was 131.0 MB. Max. memory is 11.5 GB. [2018-12-09 12:24:38,538 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 976.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 244.59 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 94.9 MB). Free memory was 956.0 MB in the beginning and 1.1 GB in the end (delta: -136.1 MB). Peak memory consumption was 36.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 17.39 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 31.95 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 387.29 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 58.4 MB). Peak memory consumption was 58.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 172896.55 ms. Allocated memory was 1.1 GB in the beginning and 6.5 GB in the end (delta: 5.4 GB). Free memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. * Witness Printer took 208.47 ms. Allocated memory is still 6.5 GB. Free memory was 2.8 GB in the beginning and 2.7 GB in the end (delta: 131.0 MB). Peak memory consumption was 131.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int t2_i ; [L32] int t3_i ; [L33] int t4_i ; [L34] int t5_i ; [L35] int t6_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int T4_E = 2; [L41] int T5_E = 2; [L42] int T6_E = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; VAL [\old(E_1)=34, \old(E_2)=25, \old(E_3)=24, \old(E_4)=8, \old(E_5)=4, \old(E_6)=15, \old(M_E)=14, \old(m_i)=7, \old(m_pc)=30, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=31, \old(t1_pc)=28, \old(t1_st)=5, \old(T2_E)=32, \old(t2_i)=6, \old(t2_pc)=27, \old(t2_st)=10, \old(T3_E)=23, \old(t3_i)=35, \old(t3_pc)=26, \old(t3_st)=11, \old(T4_E)=36, \old(t4_i)=17, \old(t4_pc)=22, \old(t4_st)=9, \old(T5_E)=20, \old(t5_i)=33, \old(t5_pc)=18, \old(t5_st)=19, \old(T6_E)=13, \old(t6_i)=29, \old(t6_pc)=21, \old(t6_st)=16, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L1059] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L1063] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0] [L969] m_i = 1 [L970] t1_i = 1 [L971] t2_i = 1 [L972] t3_i = 1 [L973] t4_i = 1 [L974] t5_i = 1 [L975] t6_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1063] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1064] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1000] int kernel_st ; [L1001] int tmp ; [L1002] int tmp___0 ; [L1006] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1007] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1008] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L451] COND TRUE m_i == 1 [L452] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L456] COND TRUE t1_i == 1 [L457] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L461] COND TRUE t2_i == 1 [L462] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t3_i == 1 [L467] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t4_i == 1 [L472] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t5_i == 1 [L477] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t6_i == 1 [L482] t6_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1008] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1009] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L660] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L665] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L670] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T5_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T6_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_5 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_6 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1009] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1010] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L310] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L329] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L348] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L367] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L386] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L405] COND FALSE !(t5_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L424] COND FALSE !(t6_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L1010] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1011] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L733] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L738] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L743] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T5_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T6_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1011] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1014] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1017] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L1018] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L537] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L541] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L491] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L532] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1] [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0] [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND TRUE \read(tmp_ndt_2) [L570] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L571] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L102] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L113] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L115] t1_pc = 1 [L116] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L571] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND TRUE \read(tmp_ndt_3) [L584] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L585] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L137] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L148] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L150] t2_pc = 1 [L151] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L585] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND TRUE \read(tmp_ndt_4) [L598] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L599] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L172] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L183] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L185] t3_pc = 1 [L186] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L599] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND TRUE \read(tmp_ndt_5) [L612] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L613] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L207] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L218] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L220] t4_pc = 1 [L221] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L613] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND TRUE \read(tmp_ndt_6) [L626] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L627] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L242] COND TRUE t5_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L253] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L255] t5_pc = 1 [L256] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=0] [L627] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND TRUE \read(tmp_ndt_7) [L640] t6_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L641] CALL transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L277] COND TRUE t6_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L288] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=0, t6_st=1] [L290] t6_pc = 1 [L291] t6_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L641] RET transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L541] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L544] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L491] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L532] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L544] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_1) [L556] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L557] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L61] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L72] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L75] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L76] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND TRUE E_1 == 1 [L331] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND TRUE \read(tmp___0) [L824] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L76] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L77] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L80] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L82] m_pc = 1 [L83] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L557] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND TRUE \read(tmp_ndt_2) [L570] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L571] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L102] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L105] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L121] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L122] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND TRUE E_2 == 1 [L350] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND TRUE \read(tmp___1) [L832] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L122] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L123] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L113] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L115] t1_pc = 1 [L116] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L571] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND TRUE \read(tmp_ndt_3) [L584] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L585] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L137] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L140] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L156] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L157] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND TRUE E_3 == 1 [L369] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND TRUE \read(tmp___2) [L840] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L157] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L158] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L148] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L150] t2_pc = 1 [L151] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L585] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND TRUE \read(tmp_ndt_4) [L598] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L599] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L172] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L175] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L191] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L192] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND TRUE E_4 == 1 [L388] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND TRUE \read(tmp___3) [L848] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L192] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L193] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L183] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L185] t3_pc = 1 [L186] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L599] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND TRUE \read(tmp_ndt_5) [L612] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L613] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L207] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L210] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L226] E_5 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L227] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND TRUE E_5 == 1 [L407] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit5_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND TRUE \read(tmp___4) [L856] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND FALSE !(E_6 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L434] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, is_transmit6_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1, tmp___5=0] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L227] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L228] E_5 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L218] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L220] t4_pc = 1 [L221] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L613] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND TRUE \read(tmp_ndt_6) [L626] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L627] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L242] COND FALSE !(t5_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L245] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L261] E_6 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L262] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L877] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L307] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L310] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L311] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L320] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L322] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L326] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L329] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L330] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L339] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L341] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L821] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0] [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L345] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L348] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L349] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L358] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L360] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L829] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0] [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L364] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L367] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L368] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L377] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L379] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L837] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0] [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L383] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L386] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L387] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L396] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L398] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L845] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L402] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L405] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L406] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L415] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L417] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L853] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] CALL, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L421] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L424] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L425] COND TRUE E_6 == 1 [L426] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L436] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2] [L861] RET, EXPR is_transmit6_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, is_transmit6_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L861] tmp___5 = is_transmit6_triggered() [L863] COND TRUE \read(tmp___5) [L864] t6_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=1] [L877] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L262] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L263] E_6 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L253] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L255] t5_pc = 1 [L256] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=0] [L627] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND TRUE \read(tmp_ndt_7) [L640] t6_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=0, \old(t6_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1, tmp_ndt_7=1] [L641] CALL transmit6() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L277] COND FALSE !(t6_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L280] COND TRUE t6_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L296] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \old(T6_E)=2, \old(t6_i)=0, \old(t6_pc)=1, \old(t6_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, T6_E=2, t6_i=1, t6_pc=1, t6_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 31 procedures, 289 locations, 1 error locations. UNSAFE Result, 172.8s OverallTime, 48 OverallIterations, 7 TraceHistogramMax, 97.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 21158 SDtfs, 26505 SDslu, 22712 SDs, 0 SdLazy, 14731 SolverSat, 5870 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 8.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 3595 GetRequests, 3318 SyntacticMatches, 71 SemanticMatches, 206 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=154188occurred in iteration=46, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 69.2s AutomataMinimizationTime, 47 MinimizatonAttempts, 19957 StatesRemovedByMinimization, 39 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 1.0s SatisfiabilityAnalysisTime, 2.2s InterpolantComputationTime, 13216 NumberOfCodeBlocks, 13216 NumberOfCodeBlocksAsserted, 55 NumberOfCheckSat, 12438 ConstructedInterpolants, 0 QuantifiedInterpolants, 5006656 SizeOfPredicates, 9 NumberOfNonLiveVariables, 14049 ConjunctsInSsa, 47 ConjunctsInUnsatCore, 54 InterpolantComputations, 47 PerfectInterpolantSequences, 7224/7371 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...