./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8bd4bc60 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e3d58fadf54daed6107b58402b79d250d23d0301 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-8bd4bc6 [2020-07-29 03:08:40,502 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-07-29 03:08:40,505 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-07-29 03:08:40,525 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-07-29 03:08:40,525 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-07-29 03:08:40,527 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-07-29 03:08:40,529 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-07-29 03:08:40,543 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-07-29 03:08:40,545 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-07-29 03:08:40,548 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-07-29 03:08:40,550 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-07-29 03:08:40,551 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-07-29 03:08:40,551 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-07-29 03:08:40,552 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-07-29 03:08:40,553 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-07-29 03:08:40,554 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-07-29 03:08:40,555 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-07-29 03:08:40,556 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-07-29 03:08:40,557 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-07-29 03:08:40,559 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-07-29 03:08:40,561 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-07-29 03:08:40,562 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-07-29 03:08:40,563 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-07-29 03:08:40,564 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-07-29 03:08:40,566 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-07-29 03:08:40,566 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-07-29 03:08:40,567 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-07-29 03:08:40,568 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-07-29 03:08:40,568 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-07-29 03:08:40,569 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-07-29 03:08:40,569 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-07-29 03:08:40,570 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-07-29 03:08:40,571 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-07-29 03:08:40,571 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-07-29 03:08:40,572 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-07-29 03:08:40,573 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-07-29 03:08:40,573 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-07-29 03:08:40,574 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-07-29 03:08:40,574 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-07-29 03:08:40,575 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-07-29 03:08:40,575 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-07-29 03:08:40,576 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-07-29 03:08:40,594 INFO L113 SettingsManager]: Loading preferences was successful [2020-07-29 03:08:40,594 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-07-29 03:08:40,595 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-07-29 03:08:40,596 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-07-29 03:08:40,596 INFO L138 SettingsManager]: * Use SBE=true [2020-07-29 03:08:40,596 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-07-29 03:08:40,596 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-07-29 03:08:40,596 INFO L138 SettingsManager]: * Use old map elimination=false [2020-07-29 03:08:40,597 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-07-29 03:08:40,597 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-07-29 03:08:40,597 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-07-29 03:08:40,597 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-07-29 03:08:40,598 INFO L138 SettingsManager]: * sizeof long=4 [2020-07-29 03:08:40,598 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-07-29 03:08:40,598 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-07-29 03:08:40,598 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-07-29 03:08:40,598 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-07-29 03:08:40,599 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-07-29 03:08:40,600 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-07-29 03:08:40,600 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-07-29 03:08:40,600 INFO L138 SettingsManager]: * sizeof long double=12 [2020-07-29 03:08:40,601 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-07-29 03:08:40,601 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-07-29 03:08:40,601 INFO L138 SettingsManager]: * Use constant arrays=true [2020-07-29 03:08:40,601 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-07-29 03:08:40,602 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-07-29 03:08:40,602 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-07-29 03:08:40,602 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-07-29 03:08:40,602 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-07-29 03:08:40,602 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-07-29 03:08:40,603 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-07-29 03:08:40,603 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-07-29 03:08:40,604 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-07-29 03:08:40,604 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e3d58fadf54daed6107b58402b79d250d23d0301 [2020-07-29 03:08:40,907 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-07-29 03:08:40,928 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-07-29 03:08:40,931 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-07-29 03:08:40,933 INFO L271 PluginConnector]: Initializing CDTParser... [2020-07-29 03:08:40,935 INFO L275 PluginConnector]: CDTParser initialized [2020-07-29 03:08:40,937 INFO L429 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2020-07-29 03:08:41,015 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0f6859b1f/9cae037232b04acbaa09c0b8cda03357/FLAGc17e9f619 [2020-07-29 03:08:41,414 INFO L306 CDTParser]: Found 1 translation units. [2020-07-29 03:08:41,415 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2020-07-29 03:08:41,425 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0f6859b1f/9cae037232b04acbaa09c0b8cda03357/FLAGc17e9f619 [2020-07-29 03:08:41,773 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0f6859b1f/9cae037232b04acbaa09c0b8cda03357 [2020-07-29 03:08:41,776 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-07-29 03:08:41,779 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-07-29 03:08:41,780 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-07-29 03:08:41,780 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-07-29 03:08:41,784 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-07-29 03:08:41,785 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.07 03:08:41" (1/1) ... [2020-07-29 03:08:41,788 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@aa3181c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:41, skipping insertion in model container [2020-07-29 03:08:41,788 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.07 03:08:41" (1/1) ... [2020-07-29 03:08:41,796 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-07-29 03:08:41,836 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-07-29 03:08:42,063 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-07-29 03:08:42,071 INFO L203 MainTranslator]: Completed pre-run [2020-07-29 03:08:42,145 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-07-29 03:08:42,264 INFO L208 MainTranslator]: Completed translation [2020-07-29 03:08:42,265 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42 WrapperNode [2020-07-29 03:08:42,266 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-07-29 03:08:42,268 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-07-29 03:08:42,269 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-07-29 03:08:42,269 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-07-29 03:08:42,278 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,304 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,382 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-07-29 03:08:42,383 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-07-29 03:08:42,383 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-07-29 03:08:42,383 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-07-29 03:08:42,394 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,395 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,400 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,402 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,425 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,447 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,449 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... [2020-07-29 03:08:42,454 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-07-29 03:08:42,455 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-07-29 03:08:42,455 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-07-29 03:08:42,455 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-07-29 03:08:42,457 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-07-29 03:08:42,540 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-07-29 03:08:42,541 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-07-29 03:08:43,646 INFO L290 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-07-29 03:08:43,646 INFO L295 CfgBuilder]: Removed 103 assume(true) statements. [2020-07-29 03:08:43,659 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.07 03:08:43 BoogieIcfgContainer [2020-07-29 03:08:43,660 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-07-29 03:08:43,661 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-07-29 03:08:43,661 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-07-29 03:08:43,665 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-07-29 03:08:43,667 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-07-29 03:08:43,667 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.07 03:08:41" (1/3) ... [2020-07-29 03:08:43,668 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@31fbfe54 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.07 03:08:43, skipping insertion in model container [2020-07-29 03:08:43,669 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-07-29 03:08:43,669 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.07 03:08:42" (2/3) ... [2020-07-29 03:08:43,670 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@31fbfe54 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.07 03:08:43, skipping insertion in model container [2020-07-29 03:08:43,670 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-07-29 03:08:43,670 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.07 03:08:43" (3/3) ... [2020-07-29 03:08:43,674 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2020-07-29 03:08:43,738 INFO L356 BuchiCegarLoop]: Interprodecural is true [2020-07-29 03:08:43,739 INFO L357 BuchiCegarLoop]: Hoare is false [2020-07-29 03:08:43,739 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-07-29 03:08:43,740 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-07-29 03:08:43,740 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-07-29 03:08:43,740 INFO L361 BuchiCegarLoop]: Difference is false [2020-07-29 03:08:43,740 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-07-29 03:08:43,741 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-07-29 03:08:43,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states. [2020-07-29 03:08:43,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2020-07-29 03:08:43,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:43,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:43,908 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:43,908 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:43,908 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2020-07-29 03:08:43,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states. [2020-07-29 03:08:43,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2020-07-29 03:08:43,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:43,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:43,958 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:43,958 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:43,970 INFO L794 eck$LassoCheckResult]: Stem: 50#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 9#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 71#L506true havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 82#L214true assume !(1 == ~m_i~0);~m_st~0 := 2; 121#L221-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 41#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 49#L231-1true assume !(0 == ~M_E~0); 25#L334-1true assume !(0 == ~T1_E~0); 34#L339-1true assume !(0 == ~T2_E~0); 149#L344-1true assume !(0 == ~E_M~0); 180#L349-1true assume !(0 == ~E_1~0); 93#L354-1true assume !(0 == ~E_2~0); 118#L359-1true havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 201#L156true assume 1 == ~m_pc~0; 138#L157true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 202#L167true is_master_triggered_#res := is_master_triggered_~__retres1~0; 139#L168true activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 208#L415true assume !(0 != activate_threads_~tmp~1); 176#L415-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3#L175true assume 1 == ~t1_pc~0; 47#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4#L186true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48#L187true activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 84#L423true assume !(0 != activate_threads_~tmp___0~0); 86#L423-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117#L194true assume !(1 == ~t2_pc~0); 113#L194-2true is_transmit2_triggered_~__retres1~2 := 0; 119#L205true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 188#L206true activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 107#L431true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 89#L431-2true assume !(1 == ~M_E~0); 33#L372-1true assume !(1 == ~T1_E~0); 148#L377-1true assume !(1 == ~T2_E~0); 177#L382-1true assume !(1 == ~E_M~0); 90#L387-1true assume 1 == ~E_1~0;~E_1~0 := 2; 115#L392-1true assume !(1 == ~E_2~0); 28#L543-1true [2020-07-29 03:08:43,972 INFO L796 eck$LassoCheckResult]: Loop: 28#L543-1true assume !false; 8#L544true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 126#L309true assume false; 72#L324true start_simulation_~kernel_st~0 := 2; 80#L214-1true start_simulation_~kernel_st~0 := 3; 26#L334-2true assume 0 == ~M_E~0;~M_E~0 := 1; 27#L334-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 36#L339-3true assume !(0 == ~T2_E~0); 151#L344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 190#L349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 101#L354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 109#L359-3true havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 162#L156-12true assume 1 == ~m_pc~0; 145#L157-4true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 217#L167-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 146#L168-4true activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 156#L415-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 157#L415-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 85#L175-12true assume !(1 == ~t1_pc~0); 83#L175-14true is_transmit1_triggered_~__retres1~1 := 0; 14#L186-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55#L187-4true activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 69#L423-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 62#L423-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 104#L194-12true assume !(1 == ~t2_pc~0); 210#L194-14true is_transmit2_triggered_~__retres1~2 := 0; 99#L205-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 170#L206-4true activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 196#L431-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 203#L431-14true assume !(1 == ~M_E~0); 35#L372-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 150#L377-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 185#L382-3true assume 1 == ~E_M~0;~E_M~0 := 2; 97#L387-3true assume 1 == ~E_1~0;~E_1~0 := 2; 120#L392-3true assume 1 == ~E_2~0;~E_2~0 := 2; 127#L397-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 205#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 192#L261-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 29#L262-1true start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 129#L562true assume !(0 == start_simulation_~tmp~3); 130#L562-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 204#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 187#L261-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 37#L262-2true stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 70#L517true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 122#L524true stop_simulation_#res := stop_simulation_~__retres2~0; 199#L525true start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 168#L575true assume !(0 != start_simulation_~tmp___0~1); 28#L543-1true [2020-07-29 03:08:43,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:43,980 INFO L82 PathProgramCache]: Analyzing trace with hash -1720133594, now seen corresponding path program 1 times [2020-07-29 03:08:43,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:43,994 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972530412] [2020-07-29 03:08:43,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:44,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:44,201 INFO L280 TraceCheckUtils]: 0: Hoare triple {221#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {221#true} is VALID [2020-07-29 03:08:44,202 INFO L280 TraceCheckUtils]: 1: Hoare triple {221#true} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {223#(= 1 ~m_i~0)} is VALID [2020-07-29 03:08:44,203 INFO L280 TraceCheckUtils]: 2: Hoare triple {223#(= 1 ~m_i~0)} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {223#(= 1 ~m_i~0)} is VALID [2020-07-29 03:08:44,204 INFO L280 TraceCheckUtils]: 3: Hoare triple {223#(= 1 ~m_i~0)} assume !(1 == ~m_i~0);~m_st~0 := 2; {222#false} is VALID [2020-07-29 03:08:44,205 INFO L280 TraceCheckUtils]: 4: Hoare triple {222#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {222#false} is VALID [2020-07-29 03:08:44,205 INFO L280 TraceCheckUtils]: 5: Hoare triple {222#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {222#false} is VALID [2020-07-29 03:08:44,206 INFO L280 TraceCheckUtils]: 6: Hoare triple {222#false} assume !(0 == ~M_E~0); {222#false} is VALID [2020-07-29 03:08:44,206 INFO L280 TraceCheckUtils]: 7: Hoare triple {222#false} assume !(0 == ~T1_E~0); {222#false} is VALID [2020-07-29 03:08:44,206 INFO L280 TraceCheckUtils]: 8: Hoare triple {222#false} assume !(0 == ~T2_E~0); {222#false} is VALID [2020-07-29 03:08:44,207 INFO L280 TraceCheckUtils]: 9: Hoare triple {222#false} assume !(0 == ~E_M~0); {222#false} is VALID [2020-07-29 03:08:44,207 INFO L280 TraceCheckUtils]: 10: Hoare triple {222#false} assume !(0 == ~E_1~0); {222#false} is VALID [2020-07-29 03:08:44,207 INFO L280 TraceCheckUtils]: 11: Hoare triple {222#false} assume !(0 == ~E_2~0); {222#false} is VALID [2020-07-29 03:08:44,208 INFO L280 TraceCheckUtils]: 12: Hoare triple {222#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {222#false} is VALID [2020-07-29 03:08:44,208 INFO L280 TraceCheckUtils]: 13: Hoare triple {222#false} assume 1 == ~m_pc~0; {222#false} is VALID [2020-07-29 03:08:44,209 INFO L280 TraceCheckUtils]: 14: Hoare triple {222#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; {222#false} is VALID [2020-07-29 03:08:44,209 INFO L280 TraceCheckUtils]: 15: Hoare triple {222#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {222#false} is VALID [2020-07-29 03:08:44,209 INFO L280 TraceCheckUtils]: 16: Hoare triple {222#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {222#false} is VALID [2020-07-29 03:08:44,210 INFO L280 TraceCheckUtils]: 17: Hoare triple {222#false} assume !(0 != activate_threads_~tmp~1); {222#false} is VALID [2020-07-29 03:08:44,210 INFO L280 TraceCheckUtils]: 18: Hoare triple {222#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {222#false} is VALID [2020-07-29 03:08:44,210 INFO L280 TraceCheckUtils]: 19: Hoare triple {222#false} assume 1 == ~t1_pc~0; {222#false} is VALID [2020-07-29 03:08:44,211 INFO L280 TraceCheckUtils]: 20: Hoare triple {222#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; {222#false} is VALID [2020-07-29 03:08:44,211 INFO L280 TraceCheckUtils]: 21: Hoare triple {222#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {222#false} is VALID [2020-07-29 03:08:44,211 INFO L280 TraceCheckUtils]: 22: Hoare triple {222#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {222#false} is VALID [2020-07-29 03:08:44,212 INFO L280 TraceCheckUtils]: 23: Hoare triple {222#false} assume !(0 != activate_threads_~tmp___0~0); {222#false} is VALID [2020-07-29 03:08:44,212 INFO L280 TraceCheckUtils]: 24: Hoare triple {222#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {222#false} is VALID [2020-07-29 03:08:44,213 INFO L280 TraceCheckUtils]: 25: Hoare triple {222#false} assume !(1 == ~t2_pc~0); {222#false} is VALID [2020-07-29 03:08:44,213 INFO L280 TraceCheckUtils]: 26: Hoare triple {222#false} is_transmit2_triggered_~__retres1~2 := 0; {222#false} is VALID [2020-07-29 03:08:44,213 INFO L280 TraceCheckUtils]: 27: Hoare triple {222#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {222#false} is VALID [2020-07-29 03:08:44,214 INFO L280 TraceCheckUtils]: 28: Hoare triple {222#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {222#false} is VALID [2020-07-29 03:08:44,214 INFO L280 TraceCheckUtils]: 29: Hoare triple {222#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {222#false} is VALID [2020-07-29 03:08:44,214 INFO L280 TraceCheckUtils]: 30: Hoare triple {222#false} assume !(1 == ~M_E~0); {222#false} is VALID [2020-07-29 03:08:44,215 INFO L280 TraceCheckUtils]: 31: Hoare triple {222#false} assume !(1 == ~T1_E~0); {222#false} is VALID [2020-07-29 03:08:44,215 INFO L280 TraceCheckUtils]: 32: Hoare triple {222#false} assume !(1 == ~T2_E~0); {222#false} is VALID [2020-07-29 03:08:44,215 INFO L280 TraceCheckUtils]: 33: Hoare triple {222#false} assume !(1 == ~E_M~0); {222#false} is VALID [2020-07-29 03:08:44,216 INFO L280 TraceCheckUtils]: 34: Hoare triple {222#false} assume 1 == ~E_1~0;~E_1~0 := 2; {222#false} is VALID [2020-07-29 03:08:44,216 INFO L280 TraceCheckUtils]: 35: Hoare triple {222#false} assume !(1 == ~E_2~0); {222#false} is VALID [2020-07-29 03:08:44,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:44,225 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [972530412] [2020-07-29 03:08:44,226 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:44,226 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-07-29 03:08:44,227 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016948745] [2020-07-29 03:08:44,233 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-07-29 03:08:44,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:44,234 INFO L82 PathProgramCache]: Analyzing trace with hash -1944420535, now seen corresponding path program 1 times [2020-07-29 03:08:44,235 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:44,235 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568061709] [2020-07-29 03:08:44,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:44,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:44,264 INFO L280 TraceCheckUtils]: 0: Hoare triple {224#true} assume !false; {224#true} is VALID [2020-07-29 03:08:44,265 INFO L280 TraceCheckUtils]: 1: Hoare triple {224#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {224#true} is VALID [2020-07-29 03:08:44,266 INFO L280 TraceCheckUtils]: 2: Hoare triple {224#true} assume false; {225#false} is VALID [2020-07-29 03:08:44,266 INFO L280 TraceCheckUtils]: 3: Hoare triple {225#false} start_simulation_~kernel_st~0 := 2; {225#false} is VALID [2020-07-29 03:08:44,266 INFO L280 TraceCheckUtils]: 4: Hoare triple {225#false} start_simulation_~kernel_st~0 := 3; {225#false} is VALID [2020-07-29 03:08:44,267 INFO L280 TraceCheckUtils]: 5: Hoare triple {225#false} assume 0 == ~M_E~0;~M_E~0 := 1; {225#false} is VALID [2020-07-29 03:08:44,267 INFO L280 TraceCheckUtils]: 6: Hoare triple {225#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {225#false} is VALID [2020-07-29 03:08:44,267 INFO L280 TraceCheckUtils]: 7: Hoare triple {225#false} assume !(0 == ~T2_E~0); {225#false} is VALID [2020-07-29 03:08:44,268 INFO L280 TraceCheckUtils]: 8: Hoare triple {225#false} assume 0 == ~E_M~0;~E_M~0 := 1; {225#false} is VALID [2020-07-29 03:08:44,268 INFO L280 TraceCheckUtils]: 9: Hoare triple {225#false} assume 0 == ~E_1~0;~E_1~0 := 1; {225#false} is VALID [2020-07-29 03:08:44,268 INFO L280 TraceCheckUtils]: 10: Hoare triple {225#false} assume 0 == ~E_2~0;~E_2~0 := 1; {225#false} is VALID [2020-07-29 03:08:44,269 INFO L280 TraceCheckUtils]: 11: Hoare triple {225#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {225#false} is VALID [2020-07-29 03:08:44,269 INFO L280 TraceCheckUtils]: 12: Hoare triple {225#false} assume 1 == ~m_pc~0; {225#false} is VALID [2020-07-29 03:08:44,269 INFO L280 TraceCheckUtils]: 13: Hoare triple {225#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; {225#false} is VALID [2020-07-29 03:08:44,270 INFO L280 TraceCheckUtils]: 14: Hoare triple {225#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {225#false} is VALID [2020-07-29 03:08:44,270 INFO L280 TraceCheckUtils]: 15: Hoare triple {225#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {225#false} is VALID [2020-07-29 03:08:44,270 INFO L280 TraceCheckUtils]: 16: Hoare triple {225#false} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {225#false} is VALID [2020-07-29 03:08:44,271 INFO L280 TraceCheckUtils]: 17: Hoare triple {225#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {225#false} is VALID [2020-07-29 03:08:44,271 INFO L280 TraceCheckUtils]: 18: Hoare triple {225#false} assume !(1 == ~t1_pc~0); {225#false} is VALID [2020-07-29 03:08:44,271 INFO L280 TraceCheckUtils]: 19: Hoare triple {225#false} is_transmit1_triggered_~__retres1~1 := 0; {225#false} is VALID [2020-07-29 03:08:44,272 INFO L280 TraceCheckUtils]: 20: Hoare triple {225#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {225#false} is VALID [2020-07-29 03:08:44,272 INFO L280 TraceCheckUtils]: 21: Hoare triple {225#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {225#false} is VALID [2020-07-29 03:08:44,272 INFO L280 TraceCheckUtils]: 22: Hoare triple {225#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {225#false} is VALID [2020-07-29 03:08:44,273 INFO L280 TraceCheckUtils]: 23: Hoare triple {225#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {225#false} is VALID [2020-07-29 03:08:44,273 INFO L280 TraceCheckUtils]: 24: Hoare triple {225#false} assume !(1 == ~t2_pc~0); {225#false} is VALID [2020-07-29 03:08:44,273 INFO L280 TraceCheckUtils]: 25: Hoare triple {225#false} is_transmit2_triggered_~__retres1~2 := 0; {225#false} is VALID [2020-07-29 03:08:44,274 INFO L280 TraceCheckUtils]: 26: Hoare triple {225#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {225#false} is VALID [2020-07-29 03:08:44,274 INFO L280 TraceCheckUtils]: 27: Hoare triple {225#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {225#false} is VALID [2020-07-29 03:08:44,274 INFO L280 TraceCheckUtils]: 28: Hoare triple {225#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {225#false} is VALID [2020-07-29 03:08:44,275 INFO L280 TraceCheckUtils]: 29: Hoare triple {225#false} assume !(1 == ~M_E~0); {225#false} is VALID [2020-07-29 03:08:44,275 INFO L280 TraceCheckUtils]: 30: Hoare triple {225#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {225#false} is VALID [2020-07-29 03:08:44,275 INFO L280 TraceCheckUtils]: 31: Hoare triple {225#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {225#false} is VALID [2020-07-29 03:08:44,276 INFO L280 TraceCheckUtils]: 32: Hoare triple {225#false} assume 1 == ~E_M~0;~E_M~0 := 2; {225#false} is VALID [2020-07-29 03:08:44,276 INFO L280 TraceCheckUtils]: 33: Hoare triple {225#false} assume 1 == ~E_1~0;~E_1~0 := 2; {225#false} is VALID [2020-07-29 03:08:44,276 INFO L280 TraceCheckUtils]: 34: Hoare triple {225#false} assume 1 == ~E_2~0;~E_2~0 := 2; {225#false} is VALID [2020-07-29 03:08:44,277 INFO L280 TraceCheckUtils]: 35: Hoare triple {225#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {225#false} is VALID [2020-07-29 03:08:44,280 INFO L280 TraceCheckUtils]: 36: Hoare triple {225#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {225#false} is VALID [2020-07-29 03:08:44,281 INFO L280 TraceCheckUtils]: 37: Hoare triple {225#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {225#false} is VALID [2020-07-29 03:08:44,282 INFO L280 TraceCheckUtils]: 38: Hoare triple {225#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {225#false} is VALID [2020-07-29 03:08:44,283 INFO L280 TraceCheckUtils]: 39: Hoare triple {225#false} assume !(0 == start_simulation_~tmp~3); {225#false} is VALID [2020-07-29 03:08:44,283 INFO L280 TraceCheckUtils]: 40: Hoare triple {225#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {225#false} is VALID [2020-07-29 03:08:44,284 INFO L280 TraceCheckUtils]: 41: Hoare triple {225#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {225#false} is VALID [2020-07-29 03:08:44,284 INFO L280 TraceCheckUtils]: 42: Hoare triple {225#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {225#false} is VALID [2020-07-29 03:08:44,285 INFO L280 TraceCheckUtils]: 43: Hoare triple {225#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {225#false} is VALID [2020-07-29 03:08:44,285 INFO L280 TraceCheckUtils]: 44: Hoare triple {225#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {225#false} is VALID [2020-07-29 03:08:44,286 INFO L280 TraceCheckUtils]: 45: Hoare triple {225#false} stop_simulation_#res := stop_simulation_~__retres2~0; {225#false} is VALID [2020-07-29 03:08:44,286 INFO L280 TraceCheckUtils]: 46: Hoare triple {225#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {225#false} is VALID [2020-07-29 03:08:44,287 INFO L280 TraceCheckUtils]: 47: Hoare triple {225#false} assume !(0 != start_simulation_~tmp___0~1); {225#false} is VALID [2020-07-29 03:08:44,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:44,293 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568061709] [2020-07-29 03:08:44,294 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:44,294 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-07-29 03:08:44,296 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883059999] [2020-07-29 03:08:44,302 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:44,303 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:44,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:44,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:44,323 INFO L87 Difference]: Start difference. First operand 217 states. Second operand 3 states. [2020-07-29 03:08:44,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:44,816 INFO L93 Difference]: Finished difference Result 217 states and 327 transitions. [2020-07-29 03:08:44,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:44,818 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:44,878 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:44,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 327 transitions. [2020-07-29 03:08:44,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2020-07-29 03:08:44,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 212 states and 322 transitions. [2020-07-29 03:08:44,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2020-07-29 03:08:44,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2020-07-29 03:08:44,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 322 transitions. [2020-07-29 03:08:44,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:44,926 INFO L688 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2020-07-29 03:08:44,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 322 transitions. [2020-07-29 03:08:44,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2020-07-29 03:08:44,993 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:44,993 INFO L82 GeneralOperation]: Start isEquivalent. First operand 212 states and 322 transitions. Second operand 212 states. [2020-07-29 03:08:44,994 INFO L74 IsIncluded]: Start isIncluded. First operand 212 states and 322 transitions. Second operand 212 states. [2020-07-29 03:08:44,996 INFO L87 Difference]: Start difference. First operand 212 states and 322 transitions. Second operand 212 states. [2020-07-29 03:08:45,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:45,016 INFO L93 Difference]: Finished difference Result 212 states and 322 transitions. [2020-07-29 03:08:45,017 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 322 transitions. [2020-07-29 03:08:45,022 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:45,022 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:45,023 INFO L74 IsIncluded]: Start isIncluded. First operand 212 states. Second operand 212 states and 322 transitions. [2020-07-29 03:08:45,023 INFO L87 Difference]: Start difference. First operand 212 states. Second operand 212 states and 322 transitions. [2020-07-29 03:08:45,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:45,036 INFO L93 Difference]: Finished difference Result 212 states and 322 transitions. [2020-07-29 03:08:45,036 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 322 transitions. [2020-07-29 03:08:45,043 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:45,044 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:45,044 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:45,045 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:45,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2020-07-29 03:08:45,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 322 transitions. [2020-07-29 03:08:45,058 INFO L711 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2020-07-29 03:08:45,059 INFO L591 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2020-07-29 03:08:45,059 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2020-07-29 03:08:45,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 322 transitions. [2020-07-29 03:08:45,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2020-07-29 03:08:45,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:45,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:45,065 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:45,066 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:45,066 INFO L794 eck$LassoCheckResult]: Stem: 517#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 456#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 457#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 539#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 549#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 511#L231-1 assume !(0 == ~M_E~0); 483#L334-1 assume !(0 == ~T1_E~0); 484#L339-1 assume !(0 == ~T2_E~0); 499#L344-1 assume !(0 == ~E_M~0); 634#L349-1 assume !(0 == ~E_1~0); 561#L354-1 assume !(0 == ~E_2~0); 562#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 592#L156 assume 1 == ~m_pc~0; 617#L157 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 618#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 620#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 621#L415 assume !(0 != activate_threads_~tmp~1); 649#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 443#L175 assume 1 == ~t1_pc~0; 444#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 446#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 447#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 516#L423 assume !(0 != activate_threads_~tmp___0~0); 550#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 552#L194 assume !(1 == ~t2_pc~0); 587#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 588#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 593#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 580#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 555#L431-2 assume !(1 == ~M_E~0); 497#L372-1 assume !(1 == ~T1_E~0); 498#L377-1 assume !(1 == ~T2_E~0); 633#L382-1 assume !(1 == ~E_M~0); 556#L387-1 assume 1 == ~E_1~0;~E_1~0 := 2; 557#L392-1 assume !(1 == ~E_2~0); 488#L543-1 [2020-07-29 03:08:45,074 INFO L796 eck$LassoCheckResult]: Loop: 488#L543-1 assume !false; 454#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 455#L309 assume !false; 597#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 644#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 453#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 491#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 492#L276 assume !(0 != eval_~tmp~0); 540#L324 start_simulation_~kernel_st~0 := 2; 541#L214-1 start_simulation_~kernel_st~0 := 3; 485#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 486#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 487#L339-3 assume !(0 == ~T2_E~0); 502#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 636#L349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 573#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 574#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 583#L156-12 assume 1 == ~m_pc~0; 627#L157-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 628#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 630#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 631#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 642#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 551#L175-12 assume 1 == ~t1_pc~0; 521#L176-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 465#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 466#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 523#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 531#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 532#L194-12 assume !(1 == ~t2_pc~0); 576#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 570#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 571#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 646#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 653#L431-14 assume !(1 == ~M_E~0); 500#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 501#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 635#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 567#L387-3 assume 1 == ~E_1~0;~E_1~0 := 2; 568#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 594#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 598#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 451#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 489#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 490#L562 assume !(0 == start_simulation_~tmp~3); 533#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 599#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 449#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 503#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 504#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 538#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 595#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 645#L575 assume !(0 != start_simulation_~tmp___0~1); 488#L543-1 [2020-07-29 03:08:45,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:45,075 INFO L82 PathProgramCache]: Analyzing trace with hash -1647747036, now seen corresponding path program 1 times [2020-07-29 03:08:45,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:45,076 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011154794] [2020-07-29 03:08:45,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:45,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:45,162 INFO L280 TraceCheckUtils]: 0: Hoare triple {1082#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {1082#true} is VALID [2020-07-29 03:08:45,163 INFO L280 TraceCheckUtils]: 1: Hoare triple {1082#true} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {1084#(= 1 ~t2_i~0)} is VALID [2020-07-29 03:08:45,164 INFO L280 TraceCheckUtils]: 2: Hoare triple {1084#(= 1 ~t2_i~0)} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {1084#(= 1 ~t2_i~0)} is VALID [2020-07-29 03:08:45,165 INFO L280 TraceCheckUtils]: 3: Hoare triple {1084#(= 1 ~t2_i~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {1084#(= 1 ~t2_i~0)} is VALID [2020-07-29 03:08:45,165 INFO L280 TraceCheckUtils]: 4: Hoare triple {1084#(= 1 ~t2_i~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1084#(= 1 ~t2_i~0)} is VALID [2020-07-29 03:08:45,166 INFO L280 TraceCheckUtils]: 5: Hoare triple {1084#(= 1 ~t2_i~0)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1083#false} is VALID [2020-07-29 03:08:45,166 INFO L280 TraceCheckUtils]: 6: Hoare triple {1083#false} assume !(0 == ~M_E~0); {1083#false} is VALID [2020-07-29 03:08:45,167 INFO L280 TraceCheckUtils]: 7: Hoare triple {1083#false} assume !(0 == ~T1_E~0); {1083#false} is VALID [2020-07-29 03:08:45,167 INFO L280 TraceCheckUtils]: 8: Hoare triple {1083#false} assume !(0 == ~T2_E~0); {1083#false} is VALID [2020-07-29 03:08:45,167 INFO L280 TraceCheckUtils]: 9: Hoare triple {1083#false} assume !(0 == ~E_M~0); {1083#false} is VALID [2020-07-29 03:08:45,168 INFO L280 TraceCheckUtils]: 10: Hoare triple {1083#false} assume !(0 == ~E_1~0); {1083#false} is VALID [2020-07-29 03:08:45,168 INFO L280 TraceCheckUtils]: 11: Hoare triple {1083#false} assume !(0 == ~E_2~0); {1083#false} is VALID [2020-07-29 03:08:45,168 INFO L280 TraceCheckUtils]: 12: Hoare triple {1083#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {1083#false} is VALID [2020-07-29 03:08:45,169 INFO L280 TraceCheckUtils]: 13: Hoare triple {1083#false} assume 1 == ~m_pc~0; {1083#false} is VALID [2020-07-29 03:08:45,169 INFO L280 TraceCheckUtils]: 14: Hoare triple {1083#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; {1083#false} is VALID [2020-07-29 03:08:45,169 INFO L280 TraceCheckUtils]: 15: Hoare triple {1083#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {1083#false} is VALID [2020-07-29 03:08:45,170 INFO L280 TraceCheckUtils]: 16: Hoare triple {1083#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {1083#false} is VALID [2020-07-29 03:08:45,170 INFO L280 TraceCheckUtils]: 17: Hoare triple {1083#false} assume !(0 != activate_threads_~tmp~1); {1083#false} is VALID [2020-07-29 03:08:45,170 INFO L280 TraceCheckUtils]: 18: Hoare triple {1083#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {1083#false} is VALID [2020-07-29 03:08:45,171 INFO L280 TraceCheckUtils]: 19: Hoare triple {1083#false} assume 1 == ~t1_pc~0; {1083#false} is VALID [2020-07-29 03:08:45,171 INFO L280 TraceCheckUtils]: 20: Hoare triple {1083#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; {1083#false} is VALID [2020-07-29 03:08:45,171 INFO L280 TraceCheckUtils]: 21: Hoare triple {1083#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {1083#false} is VALID [2020-07-29 03:08:45,172 INFO L280 TraceCheckUtils]: 22: Hoare triple {1083#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {1083#false} is VALID [2020-07-29 03:08:45,172 INFO L280 TraceCheckUtils]: 23: Hoare triple {1083#false} assume !(0 != activate_threads_~tmp___0~0); {1083#false} is VALID [2020-07-29 03:08:45,172 INFO L280 TraceCheckUtils]: 24: Hoare triple {1083#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {1083#false} is VALID [2020-07-29 03:08:45,173 INFO L280 TraceCheckUtils]: 25: Hoare triple {1083#false} assume !(1 == ~t2_pc~0); {1083#false} is VALID [2020-07-29 03:08:45,173 INFO L280 TraceCheckUtils]: 26: Hoare triple {1083#false} is_transmit2_triggered_~__retres1~2 := 0; {1083#false} is VALID [2020-07-29 03:08:45,173 INFO L280 TraceCheckUtils]: 27: Hoare triple {1083#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {1083#false} is VALID [2020-07-29 03:08:45,174 INFO L280 TraceCheckUtils]: 28: Hoare triple {1083#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {1083#false} is VALID [2020-07-29 03:08:45,174 INFO L280 TraceCheckUtils]: 29: Hoare triple {1083#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {1083#false} is VALID [2020-07-29 03:08:45,174 INFO L280 TraceCheckUtils]: 30: Hoare triple {1083#false} assume !(1 == ~M_E~0); {1083#false} is VALID [2020-07-29 03:08:45,174 INFO L280 TraceCheckUtils]: 31: Hoare triple {1083#false} assume !(1 == ~T1_E~0); {1083#false} is VALID [2020-07-29 03:08:45,175 INFO L280 TraceCheckUtils]: 32: Hoare triple {1083#false} assume !(1 == ~T2_E~0); {1083#false} is VALID [2020-07-29 03:08:45,175 INFO L280 TraceCheckUtils]: 33: Hoare triple {1083#false} assume !(1 == ~E_M~0); {1083#false} is VALID [2020-07-29 03:08:45,175 INFO L280 TraceCheckUtils]: 34: Hoare triple {1083#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1083#false} is VALID [2020-07-29 03:08:45,176 INFO L280 TraceCheckUtils]: 35: Hoare triple {1083#false} assume !(1 == ~E_2~0); {1083#false} is VALID [2020-07-29 03:08:45,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:45,179 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1011154794] [2020-07-29 03:08:45,179 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:45,179 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-07-29 03:08:45,180 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785062913] [2020-07-29 03:08:45,180 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-07-29 03:08:45,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:45,181 INFO L82 PathProgramCache]: Analyzing trace with hash -837799223, now seen corresponding path program 1 times [2020-07-29 03:08:45,181 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:45,181 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410883615] [2020-07-29 03:08:45,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:45,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:45,257 INFO L280 TraceCheckUtils]: 0: Hoare triple {1085#true} assume !false; {1085#true} is VALID [2020-07-29 03:08:45,258 INFO L280 TraceCheckUtils]: 1: Hoare triple {1085#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {1085#true} is VALID [2020-07-29 03:08:45,258 INFO L280 TraceCheckUtils]: 2: Hoare triple {1085#true} assume !false; {1085#true} is VALID [2020-07-29 03:08:45,258 INFO L280 TraceCheckUtils]: 3: Hoare triple {1085#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {1085#true} is VALID [2020-07-29 03:08:45,259 INFO L280 TraceCheckUtils]: 4: Hoare triple {1085#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {1087#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} is VALID [2020-07-29 03:08:45,260 INFO L280 TraceCheckUtils]: 5: Hoare triple {1087#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {1088#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} is VALID [2020-07-29 03:08:45,261 INFO L280 TraceCheckUtils]: 6: Hoare triple {1088#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {1089#(<= 1 ULTIMATE.start_eval_~tmp~0)} is VALID [2020-07-29 03:08:45,262 INFO L280 TraceCheckUtils]: 7: Hoare triple {1089#(<= 1 ULTIMATE.start_eval_~tmp~0)} assume !(0 != eval_~tmp~0); {1086#false} is VALID [2020-07-29 03:08:45,263 INFO L280 TraceCheckUtils]: 8: Hoare triple {1086#false} start_simulation_~kernel_st~0 := 2; {1086#false} is VALID [2020-07-29 03:08:45,263 INFO L280 TraceCheckUtils]: 9: Hoare triple {1086#false} start_simulation_~kernel_st~0 := 3; {1086#false} is VALID [2020-07-29 03:08:45,263 INFO L280 TraceCheckUtils]: 10: Hoare triple {1086#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1086#false} is VALID [2020-07-29 03:08:45,264 INFO L280 TraceCheckUtils]: 11: Hoare triple {1086#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1086#false} is VALID [2020-07-29 03:08:45,264 INFO L280 TraceCheckUtils]: 12: Hoare triple {1086#false} assume !(0 == ~T2_E~0); {1086#false} is VALID [2020-07-29 03:08:45,264 INFO L280 TraceCheckUtils]: 13: Hoare triple {1086#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1086#false} is VALID [2020-07-29 03:08:45,265 INFO L280 TraceCheckUtils]: 14: Hoare triple {1086#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1086#false} is VALID [2020-07-29 03:08:45,265 INFO L280 TraceCheckUtils]: 15: Hoare triple {1086#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1086#false} is VALID [2020-07-29 03:08:45,265 INFO L280 TraceCheckUtils]: 16: Hoare triple {1086#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {1086#false} is VALID [2020-07-29 03:08:45,265 INFO L280 TraceCheckUtils]: 17: Hoare triple {1086#false} assume 1 == ~m_pc~0; {1086#false} is VALID [2020-07-29 03:08:45,266 INFO L280 TraceCheckUtils]: 18: Hoare triple {1086#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; {1086#false} is VALID [2020-07-29 03:08:45,266 INFO L280 TraceCheckUtils]: 19: Hoare triple {1086#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {1086#false} is VALID [2020-07-29 03:08:45,266 INFO L280 TraceCheckUtils]: 20: Hoare triple {1086#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {1086#false} is VALID [2020-07-29 03:08:45,267 INFO L280 TraceCheckUtils]: 21: Hoare triple {1086#false} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {1086#false} is VALID [2020-07-29 03:08:45,267 INFO L280 TraceCheckUtils]: 22: Hoare triple {1086#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {1086#false} is VALID [2020-07-29 03:08:45,267 INFO L280 TraceCheckUtils]: 23: Hoare triple {1086#false} assume 1 == ~t1_pc~0; {1086#false} is VALID [2020-07-29 03:08:45,267 INFO L280 TraceCheckUtils]: 24: Hoare triple {1086#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; {1086#false} is VALID [2020-07-29 03:08:45,268 INFO L280 TraceCheckUtils]: 25: Hoare triple {1086#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {1086#false} is VALID [2020-07-29 03:08:45,268 INFO L280 TraceCheckUtils]: 26: Hoare triple {1086#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {1086#false} is VALID [2020-07-29 03:08:45,268 INFO L280 TraceCheckUtils]: 27: Hoare triple {1086#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {1086#false} is VALID [2020-07-29 03:08:45,269 INFO L280 TraceCheckUtils]: 28: Hoare triple {1086#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {1086#false} is VALID [2020-07-29 03:08:45,269 INFO L280 TraceCheckUtils]: 29: Hoare triple {1086#false} assume !(1 == ~t2_pc~0); {1086#false} is VALID [2020-07-29 03:08:45,269 INFO L280 TraceCheckUtils]: 30: Hoare triple {1086#false} is_transmit2_triggered_~__retres1~2 := 0; {1086#false} is VALID [2020-07-29 03:08:45,270 INFO L280 TraceCheckUtils]: 31: Hoare triple {1086#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {1086#false} is VALID [2020-07-29 03:08:45,270 INFO L280 TraceCheckUtils]: 32: Hoare triple {1086#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {1086#false} is VALID [2020-07-29 03:08:45,270 INFO L280 TraceCheckUtils]: 33: Hoare triple {1086#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {1086#false} is VALID [2020-07-29 03:08:45,271 INFO L280 TraceCheckUtils]: 34: Hoare triple {1086#false} assume !(1 == ~M_E~0); {1086#false} is VALID [2020-07-29 03:08:45,271 INFO L280 TraceCheckUtils]: 35: Hoare triple {1086#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1086#false} is VALID [2020-07-29 03:08:45,271 INFO L280 TraceCheckUtils]: 36: Hoare triple {1086#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1086#false} is VALID [2020-07-29 03:08:45,271 INFO L280 TraceCheckUtils]: 37: Hoare triple {1086#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1086#false} is VALID [2020-07-29 03:08:45,272 INFO L280 TraceCheckUtils]: 38: Hoare triple {1086#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1086#false} is VALID [2020-07-29 03:08:45,272 INFO L280 TraceCheckUtils]: 39: Hoare triple {1086#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1086#false} is VALID [2020-07-29 03:08:45,272 INFO L280 TraceCheckUtils]: 40: Hoare triple {1086#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {1086#false} is VALID [2020-07-29 03:08:45,273 INFO L280 TraceCheckUtils]: 41: Hoare triple {1086#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {1086#false} is VALID [2020-07-29 03:08:45,273 INFO L280 TraceCheckUtils]: 42: Hoare triple {1086#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {1086#false} is VALID [2020-07-29 03:08:45,273 INFO L280 TraceCheckUtils]: 43: Hoare triple {1086#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {1086#false} is VALID [2020-07-29 03:08:45,273 INFO L280 TraceCheckUtils]: 44: Hoare triple {1086#false} assume !(0 == start_simulation_~tmp~3); {1086#false} is VALID [2020-07-29 03:08:45,274 INFO L280 TraceCheckUtils]: 45: Hoare triple {1086#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {1086#false} is VALID [2020-07-29 03:08:45,274 INFO L280 TraceCheckUtils]: 46: Hoare triple {1086#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {1086#false} is VALID [2020-07-29 03:08:45,274 INFO L280 TraceCheckUtils]: 47: Hoare triple {1086#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {1086#false} is VALID [2020-07-29 03:08:45,275 INFO L280 TraceCheckUtils]: 48: Hoare triple {1086#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {1086#false} is VALID [2020-07-29 03:08:45,275 INFO L280 TraceCheckUtils]: 49: Hoare triple {1086#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {1086#false} is VALID [2020-07-29 03:08:45,275 INFO L280 TraceCheckUtils]: 50: Hoare triple {1086#false} stop_simulation_#res := stop_simulation_~__retres2~0; {1086#false} is VALID [2020-07-29 03:08:45,276 INFO L280 TraceCheckUtils]: 51: Hoare triple {1086#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {1086#false} is VALID [2020-07-29 03:08:45,276 INFO L280 TraceCheckUtils]: 52: Hoare triple {1086#false} assume !(0 != start_simulation_~tmp___0~1); {1086#false} is VALID [2020-07-29 03:08:45,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:45,281 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410883615] [2020-07-29 03:08:45,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:45,282 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:45,282 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685282309] [2020-07-29 03:08:45,283 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:45,283 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:45,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:45,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:45,284 INFO L87 Difference]: Start difference. First operand 212 states and 322 transitions. cyclomatic complexity: 111 Second operand 3 states. [2020-07-29 03:08:45,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:45,624 INFO L93 Difference]: Finished difference Result 212 states and 321 transitions. [2020-07-29 03:08:45,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:45,625 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:45,682 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:45,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 212 states and 321 transitions. [2020-07-29 03:08:45,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2020-07-29 03:08:45,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 212 states to 212 states and 321 transitions. [2020-07-29 03:08:45,704 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2020-07-29 03:08:45,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2020-07-29 03:08:45,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 321 transitions. [2020-07-29 03:08:45,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:45,706 INFO L688 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2020-07-29 03:08:45,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 321 transitions. [2020-07-29 03:08:45,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2020-07-29 03:08:45,716 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:45,716 INFO L82 GeneralOperation]: Start isEquivalent. First operand 212 states and 321 transitions. Second operand 212 states. [2020-07-29 03:08:45,716 INFO L74 IsIncluded]: Start isIncluded. First operand 212 states and 321 transitions. Second operand 212 states. [2020-07-29 03:08:45,716 INFO L87 Difference]: Start difference. First operand 212 states and 321 transitions. Second operand 212 states. [2020-07-29 03:08:45,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:45,725 INFO L93 Difference]: Finished difference Result 212 states and 321 transitions. [2020-07-29 03:08:45,725 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 321 transitions. [2020-07-29 03:08:45,726 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:45,726 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:45,726 INFO L74 IsIncluded]: Start isIncluded. First operand 212 states. Second operand 212 states and 321 transitions. [2020-07-29 03:08:45,726 INFO L87 Difference]: Start difference. First operand 212 states. Second operand 212 states and 321 transitions. [2020-07-29 03:08:45,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:45,735 INFO L93 Difference]: Finished difference Result 212 states and 321 transitions. [2020-07-29 03:08:45,735 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 321 transitions. [2020-07-29 03:08:45,736 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:45,736 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:45,736 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:45,737 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:45,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2020-07-29 03:08:45,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 321 transitions. [2020-07-29 03:08:45,745 INFO L711 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2020-07-29 03:08:45,745 INFO L591 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2020-07-29 03:08:45,745 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2020-07-29 03:08:45,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 321 transitions. [2020-07-29 03:08:45,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2020-07-29 03:08:45,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:45,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:45,749 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:45,749 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:45,750 INFO L794 eck$LassoCheckResult]: Stem: 1376#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1315#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1316#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1398#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 1408#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1369#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1370#L231-1 assume !(0 == ~M_E~0); 1342#L334-1 assume !(0 == ~T1_E~0); 1343#L339-1 assume !(0 == ~T2_E~0); 1358#L344-1 assume !(0 == ~E_M~0); 1493#L349-1 assume !(0 == ~E_1~0); 1420#L354-1 assume !(0 == ~E_2~0); 1421#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1451#L156 assume 1 == ~m_pc~0; 1476#L157 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1477#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1479#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1480#L415 assume !(0 != activate_threads_~tmp~1); 1508#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1302#L175 assume 1 == ~t1_pc~0; 1303#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1305#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1306#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1375#L423 assume !(0 != activate_threads_~tmp___0~0); 1409#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1411#L194 assume !(1 == ~t2_pc~0); 1446#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 1447#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1452#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1439#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1414#L431-2 assume !(1 == ~M_E~0); 1356#L372-1 assume !(1 == ~T1_E~0); 1357#L377-1 assume !(1 == ~T2_E~0); 1492#L382-1 assume !(1 == ~E_M~0); 1415#L387-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1416#L392-1 assume !(1 == ~E_2~0); 1347#L543-1 [2020-07-29 03:08:45,750 INFO L796 eck$LassoCheckResult]: Loop: 1347#L543-1 assume !false; 1313#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1314#L309 assume !false; 1456#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1503#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1312#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1350#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1351#L276 assume !(0 != eval_~tmp~0); 1399#L324 start_simulation_~kernel_st~0 := 2; 1400#L214-1 start_simulation_~kernel_st~0 := 3; 1344#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1345#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1346#L339-3 assume !(0 == ~T2_E~0); 1361#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1495#L349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1432#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1433#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1442#L156-12 assume !(1 == ~m_pc~0); 1488#L156-14 is_master_triggered_~__retres1~0 := 0; 1487#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1489#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1490#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1501#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1410#L175-12 assume 1 == ~t1_pc~0; 1380#L176-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1324#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1325#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1382#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1390#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1391#L194-12 assume 1 == ~t2_pc~0; 1434#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1429#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1430#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1505#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1512#L431-14 assume !(1 == ~M_E~0); 1359#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1360#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1494#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1426#L387-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1427#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1453#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1457#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1310#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1348#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1349#L562 assume !(0 == start_simulation_~tmp~3); 1392#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1458#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1308#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1362#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 1363#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1397#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 1454#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1504#L575 assume !(0 != start_simulation_~tmp___0~1); 1347#L543-1 [2020-07-29 03:08:45,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:45,751 INFO L82 PathProgramCache]: Analyzing trace with hash 1945620386, now seen corresponding path program 1 times [2020-07-29 03:08:45,751 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:45,751 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764712674] [2020-07-29 03:08:45,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:45,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:45,805 INFO L280 TraceCheckUtils]: 0: Hoare triple {1941#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,806 INFO L280 TraceCheckUtils]: 1: Hoare triple {1943#(<= ~m_pc~0 0)} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,806 INFO L280 TraceCheckUtils]: 2: Hoare triple {1943#(<= ~m_pc~0 0)} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,807 INFO L280 TraceCheckUtils]: 3: Hoare triple {1943#(<= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,808 INFO L280 TraceCheckUtils]: 4: Hoare triple {1943#(<= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,808 INFO L280 TraceCheckUtils]: 5: Hoare triple {1943#(<= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,809 INFO L280 TraceCheckUtils]: 6: Hoare triple {1943#(<= ~m_pc~0 0)} assume !(0 == ~M_E~0); {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,810 INFO L280 TraceCheckUtils]: 7: Hoare triple {1943#(<= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,811 INFO L280 TraceCheckUtils]: 8: Hoare triple {1943#(<= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,815 INFO L280 TraceCheckUtils]: 9: Hoare triple {1943#(<= ~m_pc~0 0)} assume !(0 == ~E_M~0); {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,816 INFO L280 TraceCheckUtils]: 10: Hoare triple {1943#(<= ~m_pc~0 0)} assume !(0 == ~E_1~0); {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,817 INFO L280 TraceCheckUtils]: 11: Hoare triple {1943#(<= ~m_pc~0 0)} assume !(0 == ~E_2~0); {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,821 INFO L280 TraceCheckUtils]: 12: Hoare triple {1943#(<= ~m_pc~0 0)} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {1943#(<= ~m_pc~0 0)} is VALID [2020-07-29 03:08:45,823 INFO L280 TraceCheckUtils]: 13: Hoare triple {1943#(<= ~m_pc~0 0)} assume 1 == ~m_pc~0; {1942#false} is VALID [2020-07-29 03:08:45,823 INFO L280 TraceCheckUtils]: 14: Hoare triple {1942#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; {1942#false} is VALID [2020-07-29 03:08:45,823 INFO L280 TraceCheckUtils]: 15: Hoare triple {1942#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {1942#false} is VALID [2020-07-29 03:08:45,823 INFO L280 TraceCheckUtils]: 16: Hoare triple {1942#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {1942#false} is VALID [2020-07-29 03:08:45,824 INFO L280 TraceCheckUtils]: 17: Hoare triple {1942#false} assume !(0 != activate_threads_~tmp~1); {1942#false} is VALID [2020-07-29 03:08:45,824 INFO L280 TraceCheckUtils]: 18: Hoare triple {1942#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {1942#false} is VALID [2020-07-29 03:08:45,824 INFO L280 TraceCheckUtils]: 19: Hoare triple {1942#false} assume 1 == ~t1_pc~0; {1942#false} is VALID [2020-07-29 03:08:45,824 INFO L280 TraceCheckUtils]: 20: Hoare triple {1942#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; {1942#false} is VALID [2020-07-29 03:08:45,825 INFO L280 TraceCheckUtils]: 21: Hoare triple {1942#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {1942#false} is VALID [2020-07-29 03:08:45,825 INFO L280 TraceCheckUtils]: 22: Hoare triple {1942#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {1942#false} is VALID [2020-07-29 03:08:45,825 INFO L280 TraceCheckUtils]: 23: Hoare triple {1942#false} assume !(0 != activate_threads_~tmp___0~0); {1942#false} is VALID [2020-07-29 03:08:45,826 INFO L280 TraceCheckUtils]: 24: Hoare triple {1942#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {1942#false} is VALID [2020-07-29 03:08:45,826 INFO L280 TraceCheckUtils]: 25: Hoare triple {1942#false} assume !(1 == ~t2_pc~0); {1942#false} is VALID [2020-07-29 03:08:45,826 INFO L280 TraceCheckUtils]: 26: Hoare triple {1942#false} is_transmit2_triggered_~__retres1~2 := 0; {1942#false} is VALID [2020-07-29 03:08:45,826 INFO L280 TraceCheckUtils]: 27: Hoare triple {1942#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {1942#false} is VALID [2020-07-29 03:08:45,827 INFO L280 TraceCheckUtils]: 28: Hoare triple {1942#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {1942#false} is VALID [2020-07-29 03:08:45,827 INFO L280 TraceCheckUtils]: 29: Hoare triple {1942#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {1942#false} is VALID [2020-07-29 03:08:45,827 INFO L280 TraceCheckUtils]: 30: Hoare triple {1942#false} assume !(1 == ~M_E~0); {1942#false} is VALID [2020-07-29 03:08:45,828 INFO L280 TraceCheckUtils]: 31: Hoare triple {1942#false} assume !(1 == ~T1_E~0); {1942#false} is VALID [2020-07-29 03:08:45,828 INFO L280 TraceCheckUtils]: 32: Hoare triple {1942#false} assume !(1 == ~T2_E~0); {1942#false} is VALID [2020-07-29 03:08:45,828 INFO L280 TraceCheckUtils]: 33: Hoare triple {1942#false} assume !(1 == ~E_M~0); {1942#false} is VALID [2020-07-29 03:08:45,828 INFO L280 TraceCheckUtils]: 34: Hoare triple {1942#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1942#false} is VALID [2020-07-29 03:08:45,829 INFO L280 TraceCheckUtils]: 35: Hoare triple {1942#false} assume !(1 == ~E_2~0); {1942#false} is VALID [2020-07-29 03:08:45,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:45,831 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [764712674] [2020-07-29 03:08:45,832 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:45,832 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-07-29 03:08:45,832 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702716461] [2020-07-29 03:08:45,832 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-07-29 03:08:45,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:45,833 INFO L82 PathProgramCache]: Analyzing trace with hash -1012220855, now seen corresponding path program 1 times [2020-07-29 03:08:45,833 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:45,833 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80298535] [2020-07-29 03:08:45,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:45,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:45,891 INFO L280 TraceCheckUtils]: 0: Hoare triple {1944#true} assume !false; {1944#true} is VALID [2020-07-29 03:08:45,892 INFO L280 TraceCheckUtils]: 1: Hoare triple {1944#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {1944#true} is VALID [2020-07-29 03:08:45,892 INFO L280 TraceCheckUtils]: 2: Hoare triple {1944#true} assume !false; {1944#true} is VALID [2020-07-29 03:08:45,892 INFO L280 TraceCheckUtils]: 3: Hoare triple {1944#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {1944#true} is VALID [2020-07-29 03:08:45,893 INFO L280 TraceCheckUtils]: 4: Hoare triple {1944#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {1946#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} is VALID [2020-07-29 03:08:45,894 INFO L280 TraceCheckUtils]: 5: Hoare triple {1946#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {1947#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} is VALID [2020-07-29 03:08:45,894 INFO L280 TraceCheckUtils]: 6: Hoare triple {1947#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {1948#(<= 1 ULTIMATE.start_eval_~tmp~0)} is VALID [2020-07-29 03:08:45,895 INFO L280 TraceCheckUtils]: 7: Hoare triple {1948#(<= 1 ULTIMATE.start_eval_~tmp~0)} assume !(0 != eval_~tmp~0); {1945#false} is VALID [2020-07-29 03:08:45,895 INFO L280 TraceCheckUtils]: 8: Hoare triple {1945#false} start_simulation_~kernel_st~0 := 2; {1945#false} is VALID [2020-07-29 03:08:45,896 INFO L280 TraceCheckUtils]: 9: Hoare triple {1945#false} start_simulation_~kernel_st~0 := 3; {1945#false} is VALID [2020-07-29 03:08:45,896 INFO L280 TraceCheckUtils]: 10: Hoare triple {1945#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1945#false} is VALID [2020-07-29 03:08:45,896 INFO L280 TraceCheckUtils]: 11: Hoare triple {1945#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1945#false} is VALID [2020-07-29 03:08:45,897 INFO L280 TraceCheckUtils]: 12: Hoare triple {1945#false} assume !(0 == ~T2_E~0); {1945#false} is VALID [2020-07-29 03:08:45,897 INFO L280 TraceCheckUtils]: 13: Hoare triple {1945#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1945#false} is VALID [2020-07-29 03:08:45,897 INFO L280 TraceCheckUtils]: 14: Hoare triple {1945#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1945#false} is VALID [2020-07-29 03:08:45,897 INFO L280 TraceCheckUtils]: 15: Hoare triple {1945#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1945#false} is VALID [2020-07-29 03:08:45,898 INFO L280 TraceCheckUtils]: 16: Hoare triple {1945#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {1945#false} is VALID [2020-07-29 03:08:45,898 INFO L280 TraceCheckUtils]: 17: Hoare triple {1945#false} assume !(1 == ~m_pc~0); {1945#false} is VALID [2020-07-29 03:08:45,898 INFO L280 TraceCheckUtils]: 18: Hoare triple {1945#false} is_master_triggered_~__retres1~0 := 0; {1945#false} is VALID [2020-07-29 03:08:45,898 INFO L280 TraceCheckUtils]: 19: Hoare triple {1945#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {1945#false} is VALID [2020-07-29 03:08:45,899 INFO L280 TraceCheckUtils]: 20: Hoare triple {1945#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {1945#false} is VALID [2020-07-29 03:08:45,899 INFO L280 TraceCheckUtils]: 21: Hoare triple {1945#false} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {1945#false} is VALID [2020-07-29 03:08:45,899 INFO L280 TraceCheckUtils]: 22: Hoare triple {1945#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {1945#false} is VALID [2020-07-29 03:08:45,899 INFO L280 TraceCheckUtils]: 23: Hoare triple {1945#false} assume 1 == ~t1_pc~0; {1945#false} is VALID [2020-07-29 03:08:45,900 INFO L280 TraceCheckUtils]: 24: Hoare triple {1945#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; {1945#false} is VALID [2020-07-29 03:08:45,900 INFO L280 TraceCheckUtils]: 25: Hoare triple {1945#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {1945#false} is VALID [2020-07-29 03:08:45,900 INFO L280 TraceCheckUtils]: 26: Hoare triple {1945#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {1945#false} is VALID [2020-07-29 03:08:45,900 INFO L280 TraceCheckUtils]: 27: Hoare triple {1945#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {1945#false} is VALID [2020-07-29 03:08:45,901 INFO L280 TraceCheckUtils]: 28: Hoare triple {1945#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {1945#false} is VALID [2020-07-29 03:08:45,901 INFO L280 TraceCheckUtils]: 29: Hoare triple {1945#false} assume 1 == ~t2_pc~0; {1945#false} is VALID [2020-07-29 03:08:45,901 INFO L280 TraceCheckUtils]: 30: Hoare triple {1945#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; {1945#false} is VALID [2020-07-29 03:08:45,901 INFO L280 TraceCheckUtils]: 31: Hoare triple {1945#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {1945#false} is VALID [2020-07-29 03:08:45,902 INFO L280 TraceCheckUtils]: 32: Hoare triple {1945#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {1945#false} is VALID [2020-07-29 03:08:45,902 INFO L280 TraceCheckUtils]: 33: Hoare triple {1945#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {1945#false} is VALID [2020-07-29 03:08:45,902 INFO L280 TraceCheckUtils]: 34: Hoare triple {1945#false} assume !(1 == ~M_E~0); {1945#false} is VALID [2020-07-29 03:08:45,902 INFO L280 TraceCheckUtils]: 35: Hoare triple {1945#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1945#false} is VALID [2020-07-29 03:08:45,923 INFO L280 TraceCheckUtils]: 36: Hoare triple {1945#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1945#false} is VALID [2020-07-29 03:08:45,923 INFO L280 TraceCheckUtils]: 37: Hoare triple {1945#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1945#false} is VALID [2020-07-29 03:08:45,923 INFO L280 TraceCheckUtils]: 38: Hoare triple {1945#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1945#false} is VALID [2020-07-29 03:08:45,924 INFO L280 TraceCheckUtils]: 39: Hoare triple {1945#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1945#false} is VALID [2020-07-29 03:08:45,924 INFO L280 TraceCheckUtils]: 40: Hoare triple {1945#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {1945#false} is VALID [2020-07-29 03:08:45,924 INFO L280 TraceCheckUtils]: 41: Hoare triple {1945#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {1945#false} is VALID [2020-07-29 03:08:45,924 INFO L280 TraceCheckUtils]: 42: Hoare triple {1945#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {1945#false} is VALID [2020-07-29 03:08:45,925 INFO L280 TraceCheckUtils]: 43: Hoare triple {1945#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {1945#false} is VALID [2020-07-29 03:08:45,925 INFO L280 TraceCheckUtils]: 44: Hoare triple {1945#false} assume !(0 == start_simulation_~tmp~3); {1945#false} is VALID [2020-07-29 03:08:45,925 INFO L280 TraceCheckUtils]: 45: Hoare triple {1945#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {1945#false} is VALID [2020-07-29 03:08:45,926 INFO L280 TraceCheckUtils]: 46: Hoare triple {1945#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {1945#false} is VALID [2020-07-29 03:08:45,927 INFO L280 TraceCheckUtils]: 47: Hoare triple {1945#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {1945#false} is VALID [2020-07-29 03:08:45,927 INFO L280 TraceCheckUtils]: 48: Hoare triple {1945#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {1945#false} is VALID [2020-07-29 03:08:45,927 INFO L280 TraceCheckUtils]: 49: Hoare triple {1945#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {1945#false} is VALID [2020-07-29 03:08:45,927 INFO L280 TraceCheckUtils]: 50: Hoare triple {1945#false} stop_simulation_#res := stop_simulation_~__retres2~0; {1945#false} is VALID [2020-07-29 03:08:45,928 INFO L280 TraceCheckUtils]: 51: Hoare triple {1945#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {1945#false} is VALID [2020-07-29 03:08:45,928 INFO L280 TraceCheckUtils]: 52: Hoare triple {1945#false} assume !(0 != start_simulation_~tmp___0~1); {1945#false} is VALID [2020-07-29 03:08:45,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:45,931 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [80298535] [2020-07-29 03:08:45,931 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:45,931 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:45,931 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336706147] [2020-07-29 03:08:45,932 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:45,932 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:45,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:45,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:45,932 INFO L87 Difference]: Start difference. First operand 212 states and 321 transitions. cyclomatic complexity: 110 Second operand 3 states. [2020-07-29 03:08:46,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:46,414 INFO L93 Difference]: Finished difference Result 378 states and 561 transitions. [2020-07-29 03:08:46,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:46,415 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:46,458 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:46,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 378 states and 561 transitions. [2020-07-29 03:08:46,475 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 338 [2020-07-29 03:08:46,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 378 states to 378 states and 561 transitions. [2020-07-29 03:08:46,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 378 [2020-07-29 03:08:46,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 378 [2020-07-29 03:08:46,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 378 states and 561 transitions. [2020-07-29 03:08:46,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:46,493 INFO L688 BuchiCegarLoop]: Abstraction has 378 states and 561 transitions. [2020-07-29 03:08:46,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378 states and 561 transitions. [2020-07-29 03:08:46,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378 to 359. [2020-07-29 03:08:46,505 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:46,505 INFO L82 GeneralOperation]: Start isEquivalent. First operand 378 states and 561 transitions. Second operand 359 states. [2020-07-29 03:08:46,505 INFO L74 IsIncluded]: Start isIncluded. First operand 378 states and 561 transitions. Second operand 359 states. [2020-07-29 03:08:46,505 INFO L87 Difference]: Start difference. First operand 378 states and 561 transitions. Second operand 359 states. [2020-07-29 03:08:46,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:46,520 INFO L93 Difference]: Finished difference Result 378 states and 561 transitions. [2020-07-29 03:08:46,520 INFO L276 IsEmpty]: Start isEmpty. Operand 378 states and 561 transitions. [2020-07-29 03:08:46,521 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:46,521 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:46,521 INFO L74 IsIncluded]: Start isIncluded. First operand 359 states. Second operand 378 states and 561 transitions. [2020-07-29 03:08:46,521 INFO L87 Difference]: Start difference. First operand 359 states. Second operand 378 states and 561 transitions. [2020-07-29 03:08:46,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:46,537 INFO L93 Difference]: Finished difference Result 378 states and 561 transitions. [2020-07-29 03:08:46,537 INFO L276 IsEmpty]: Start isEmpty. Operand 378 states and 561 transitions. [2020-07-29 03:08:46,538 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:46,538 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:46,538 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:46,538 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:46,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 359 states. [2020-07-29 03:08:46,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 359 states to 359 states and 535 transitions. [2020-07-29 03:08:46,552 INFO L711 BuchiCegarLoop]: Abstraction has 359 states and 535 transitions. [2020-07-29 03:08:46,552 INFO L591 BuchiCegarLoop]: Abstraction has 359 states and 535 transitions. [2020-07-29 03:08:46,552 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2020-07-29 03:08:46,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 359 states and 535 transitions. [2020-07-29 03:08:46,559 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 319 [2020-07-29 03:08:46,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:46,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:46,560 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:46,560 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:46,560 INFO L794 eck$LassoCheckResult]: Stem: 2401#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2340#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2341#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2425#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 2435#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2394#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2395#L231-1 assume !(0 == ~M_E~0); 2367#L334-1 assume !(0 == ~T1_E~0); 2368#L339-1 assume !(0 == ~T2_E~0); 2383#L344-1 assume !(0 == ~E_M~0); 2521#L349-1 assume !(0 == ~E_1~0); 2447#L354-1 assume !(0 == ~E_2~0); 2448#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2481#L156 assume !(1 == ~m_pc~0); 2547#L156-2 is_master_triggered_~__retres1~0 := 0; 2548#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2507#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2508#L415 assume !(0 != activate_threads_~tmp~1); 2543#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2327#L175 assume 1 == ~t1_pc~0; 2328#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2332#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2333#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2400#L423 assume !(0 != activate_threads_~tmp___0~0); 2436#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2438#L194 assume !(1 == ~t2_pc~0); 2476#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 2477#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2482#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2471#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2441#L431-2 assume !(1 == ~M_E~0); 2381#L372-1 assume !(1 == ~T1_E~0); 2382#L377-1 assume !(1 == ~T2_E~0); 2520#L382-1 assume !(1 == ~E_M~0); 2442#L387-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2443#L392-1 assume !(1 == ~E_2~0); 2372#L543-1 [2020-07-29 03:08:46,561 INFO L796 eck$LassoCheckResult]: Loop: 2372#L543-1 assume !false; 2338#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2339#L309 assume !false; 2486#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2532#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2337#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2375#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2376#L276 assume !(0 != eval_~tmp~0); 2427#L324 start_simulation_~kernel_st~0 := 2; 2428#L214-1 start_simulation_~kernel_st~0 := 3; 2369#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2370#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2371#L339-3 assume !(0 == ~T2_E~0); 2386#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2523#L349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2462#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2463#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2472#L156-12 assume !(1 == ~m_pc~0); 2533#L156-14 is_master_triggered_~__retres1~0 := 0; 2669#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2668#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2667#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2666#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2665#L175-12 assume 1 == ~t1_pc~0; 2663#L176-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2662#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2661#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2423#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2416#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2417#L194-12 assume 1 == ~t2_pc~0; 2464#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2459#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2460#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2537#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2549#L431-14 assume !(1 == ~M_E~0); 2384#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2385#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2522#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2455#L387-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2456#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2483#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2487#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2335#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2373#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2374#L562 assume !(0 == start_simulation_~tmp~3); 2418#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2489#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2331#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2387#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 2388#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2424#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 2484#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 2536#L575 assume !(0 != start_simulation_~tmp___0~1); 2372#L543-1 [2020-07-29 03:08:46,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:46,561 INFO L82 PathProgramCache]: Analyzing trace with hash -1569365981, now seen corresponding path program 1 times [2020-07-29 03:08:46,561 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:46,562 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870639653] [2020-07-29 03:08:46,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:46,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:46,653 INFO L280 TraceCheckUtils]: 0: Hoare triple {3445#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,653 INFO L280 TraceCheckUtils]: 1: Hoare triple {3447#(<= ~t1_pc~0 0)} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,654 INFO L280 TraceCheckUtils]: 2: Hoare triple {3447#(<= ~t1_pc~0 0)} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,655 INFO L280 TraceCheckUtils]: 3: Hoare triple {3447#(<= ~t1_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,655 INFO L280 TraceCheckUtils]: 4: Hoare triple {3447#(<= ~t1_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,656 INFO L280 TraceCheckUtils]: 5: Hoare triple {3447#(<= ~t1_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,656 INFO L280 TraceCheckUtils]: 6: Hoare triple {3447#(<= ~t1_pc~0 0)} assume !(0 == ~M_E~0); {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,657 INFO L280 TraceCheckUtils]: 7: Hoare triple {3447#(<= ~t1_pc~0 0)} assume !(0 == ~T1_E~0); {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,657 INFO L280 TraceCheckUtils]: 8: Hoare triple {3447#(<= ~t1_pc~0 0)} assume !(0 == ~T2_E~0); {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,658 INFO L280 TraceCheckUtils]: 9: Hoare triple {3447#(<= ~t1_pc~0 0)} assume !(0 == ~E_M~0); {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,658 INFO L280 TraceCheckUtils]: 10: Hoare triple {3447#(<= ~t1_pc~0 0)} assume !(0 == ~E_1~0); {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,659 INFO L280 TraceCheckUtils]: 11: Hoare triple {3447#(<= ~t1_pc~0 0)} assume !(0 == ~E_2~0); {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,660 INFO L280 TraceCheckUtils]: 12: Hoare triple {3447#(<= ~t1_pc~0 0)} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,660 INFO L280 TraceCheckUtils]: 13: Hoare triple {3447#(<= ~t1_pc~0 0)} assume !(1 == ~m_pc~0); {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,661 INFO L280 TraceCheckUtils]: 14: Hoare triple {3447#(<= ~t1_pc~0 0)} is_master_triggered_~__retres1~0 := 0; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,661 INFO L280 TraceCheckUtils]: 15: Hoare triple {3447#(<= ~t1_pc~0 0)} is_master_triggered_#res := is_master_triggered_~__retres1~0; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,662 INFO L280 TraceCheckUtils]: 16: Hoare triple {3447#(<= ~t1_pc~0 0)} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,662 INFO L280 TraceCheckUtils]: 17: Hoare triple {3447#(<= ~t1_pc~0 0)} assume !(0 != activate_threads_~tmp~1); {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,663 INFO L280 TraceCheckUtils]: 18: Hoare triple {3447#(<= ~t1_pc~0 0)} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {3447#(<= ~t1_pc~0 0)} is VALID [2020-07-29 03:08:46,664 INFO L280 TraceCheckUtils]: 19: Hoare triple {3447#(<= ~t1_pc~0 0)} assume 1 == ~t1_pc~0; {3446#false} is VALID [2020-07-29 03:08:46,664 INFO L280 TraceCheckUtils]: 20: Hoare triple {3446#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; {3446#false} is VALID [2020-07-29 03:08:46,664 INFO L280 TraceCheckUtils]: 21: Hoare triple {3446#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {3446#false} is VALID [2020-07-29 03:08:46,664 INFO L280 TraceCheckUtils]: 22: Hoare triple {3446#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {3446#false} is VALID [2020-07-29 03:08:46,664 INFO L280 TraceCheckUtils]: 23: Hoare triple {3446#false} assume !(0 != activate_threads_~tmp___0~0); {3446#false} is VALID [2020-07-29 03:08:46,665 INFO L280 TraceCheckUtils]: 24: Hoare triple {3446#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {3446#false} is VALID [2020-07-29 03:08:46,665 INFO L280 TraceCheckUtils]: 25: Hoare triple {3446#false} assume !(1 == ~t2_pc~0); {3446#false} is VALID [2020-07-29 03:08:46,665 INFO L280 TraceCheckUtils]: 26: Hoare triple {3446#false} is_transmit2_triggered_~__retres1~2 := 0; {3446#false} is VALID [2020-07-29 03:08:46,665 INFO L280 TraceCheckUtils]: 27: Hoare triple {3446#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {3446#false} is VALID [2020-07-29 03:08:46,665 INFO L280 TraceCheckUtils]: 28: Hoare triple {3446#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {3446#false} is VALID [2020-07-29 03:08:46,665 INFO L280 TraceCheckUtils]: 29: Hoare triple {3446#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {3446#false} is VALID [2020-07-29 03:08:46,666 INFO L280 TraceCheckUtils]: 30: Hoare triple {3446#false} assume !(1 == ~M_E~0); {3446#false} is VALID [2020-07-29 03:08:46,666 INFO L280 TraceCheckUtils]: 31: Hoare triple {3446#false} assume !(1 == ~T1_E~0); {3446#false} is VALID [2020-07-29 03:08:46,666 INFO L280 TraceCheckUtils]: 32: Hoare triple {3446#false} assume !(1 == ~T2_E~0); {3446#false} is VALID [2020-07-29 03:08:46,666 INFO L280 TraceCheckUtils]: 33: Hoare triple {3446#false} assume !(1 == ~E_M~0); {3446#false} is VALID [2020-07-29 03:08:46,666 INFO L280 TraceCheckUtils]: 34: Hoare triple {3446#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3446#false} is VALID [2020-07-29 03:08:46,666 INFO L280 TraceCheckUtils]: 35: Hoare triple {3446#false} assume !(1 == ~E_2~0); {3446#false} is VALID [2020-07-29 03:08:46,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:46,668 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870639653] [2020-07-29 03:08:46,668 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:46,668 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-07-29 03:08:46,668 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783097606] [2020-07-29 03:08:46,669 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-07-29 03:08:46,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:46,669 INFO L82 PathProgramCache]: Analyzing trace with hash -1012220855, now seen corresponding path program 2 times [2020-07-29 03:08:46,669 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:46,669 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45027964] [2020-07-29 03:08:46,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:46,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:46,719 INFO L280 TraceCheckUtils]: 0: Hoare triple {3448#true} assume !false; {3448#true} is VALID [2020-07-29 03:08:46,719 INFO L280 TraceCheckUtils]: 1: Hoare triple {3448#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {3448#true} is VALID [2020-07-29 03:08:46,719 INFO L280 TraceCheckUtils]: 2: Hoare triple {3448#true} assume !false; {3448#true} is VALID [2020-07-29 03:08:46,720 INFO L280 TraceCheckUtils]: 3: Hoare triple {3448#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {3448#true} is VALID [2020-07-29 03:08:46,721 INFO L280 TraceCheckUtils]: 4: Hoare triple {3448#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {3450#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} is VALID [2020-07-29 03:08:46,722 INFO L280 TraceCheckUtils]: 5: Hoare triple {3450#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {3451#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} is VALID [2020-07-29 03:08:46,723 INFO L280 TraceCheckUtils]: 6: Hoare triple {3451#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {3452#(<= 1 ULTIMATE.start_eval_~tmp~0)} is VALID [2020-07-29 03:08:46,724 INFO L280 TraceCheckUtils]: 7: Hoare triple {3452#(<= 1 ULTIMATE.start_eval_~tmp~0)} assume !(0 != eval_~tmp~0); {3449#false} is VALID [2020-07-29 03:08:46,724 INFO L280 TraceCheckUtils]: 8: Hoare triple {3449#false} start_simulation_~kernel_st~0 := 2; {3449#false} is VALID [2020-07-29 03:08:46,724 INFO L280 TraceCheckUtils]: 9: Hoare triple {3449#false} start_simulation_~kernel_st~0 := 3; {3449#false} is VALID [2020-07-29 03:08:46,724 INFO L280 TraceCheckUtils]: 10: Hoare triple {3449#false} assume 0 == ~M_E~0;~M_E~0 := 1; {3449#false} is VALID [2020-07-29 03:08:46,724 INFO L280 TraceCheckUtils]: 11: Hoare triple {3449#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3449#false} is VALID [2020-07-29 03:08:46,724 INFO L280 TraceCheckUtils]: 12: Hoare triple {3449#false} assume !(0 == ~T2_E~0); {3449#false} is VALID [2020-07-29 03:08:46,725 INFO L280 TraceCheckUtils]: 13: Hoare triple {3449#false} assume 0 == ~E_M~0;~E_M~0 := 1; {3449#false} is VALID [2020-07-29 03:08:46,725 INFO L280 TraceCheckUtils]: 14: Hoare triple {3449#false} assume 0 == ~E_1~0;~E_1~0 := 1; {3449#false} is VALID [2020-07-29 03:08:46,725 INFO L280 TraceCheckUtils]: 15: Hoare triple {3449#false} assume 0 == ~E_2~0;~E_2~0 := 1; {3449#false} is VALID [2020-07-29 03:08:46,725 INFO L280 TraceCheckUtils]: 16: Hoare triple {3449#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {3449#false} is VALID [2020-07-29 03:08:46,728 INFO L280 TraceCheckUtils]: 17: Hoare triple {3449#false} assume !(1 == ~m_pc~0); {3449#false} is VALID [2020-07-29 03:08:46,729 INFO L280 TraceCheckUtils]: 18: Hoare triple {3449#false} is_master_triggered_~__retres1~0 := 0; {3449#false} is VALID [2020-07-29 03:08:46,729 INFO L280 TraceCheckUtils]: 19: Hoare triple {3449#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {3449#false} is VALID [2020-07-29 03:08:46,729 INFO L280 TraceCheckUtils]: 20: Hoare triple {3449#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {3449#false} is VALID [2020-07-29 03:08:46,729 INFO L280 TraceCheckUtils]: 21: Hoare triple {3449#false} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {3449#false} is VALID [2020-07-29 03:08:46,729 INFO L280 TraceCheckUtils]: 22: Hoare triple {3449#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {3449#false} is VALID [2020-07-29 03:08:46,729 INFO L280 TraceCheckUtils]: 23: Hoare triple {3449#false} assume 1 == ~t1_pc~0; {3449#false} is VALID [2020-07-29 03:08:46,730 INFO L280 TraceCheckUtils]: 24: Hoare triple {3449#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; {3449#false} is VALID [2020-07-29 03:08:46,730 INFO L280 TraceCheckUtils]: 25: Hoare triple {3449#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {3449#false} is VALID [2020-07-29 03:08:46,730 INFO L280 TraceCheckUtils]: 26: Hoare triple {3449#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {3449#false} is VALID [2020-07-29 03:08:46,730 INFO L280 TraceCheckUtils]: 27: Hoare triple {3449#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {3449#false} is VALID [2020-07-29 03:08:46,730 INFO L280 TraceCheckUtils]: 28: Hoare triple {3449#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {3449#false} is VALID [2020-07-29 03:08:46,730 INFO L280 TraceCheckUtils]: 29: Hoare triple {3449#false} assume 1 == ~t2_pc~0; {3449#false} is VALID [2020-07-29 03:08:46,731 INFO L280 TraceCheckUtils]: 30: Hoare triple {3449#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; {3449#false} is VALID [2020-07-29 03:08:46,731 INFO L280 TraceCheckUtils]: 31: Hoare triple {3449#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {3449#false} is VALID [2020-07-29 03:08:46,731 INFO L280 TraceCheckUtils]: 32: Hoare triple {3449#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {3449#false} is VALID [2020-07-29 03:08:46,731 INFO L280 TraceCheckUtils]: 33: Hoare triple {3449#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {3449#false} is VALID [2020-07-29 03:08:46,731 INFO L280 TraceCheckUtils]: 34: Hoare triple {3449#false} assume !(1 == ~M_E~0); {3449#false} is VALID [2020-07-29 03:08:46,731 INFO L280 TraceCheckUtils]: 35: Hoare triple {3449#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3449#false} is VALID [2020-07-29 03:08:46,732 INFO L280 TraceCheckUtils]: 36: Hoare triple {3449#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {3449#false} is VALID [2020-07-29 03:08:46,732 INFO L280 TraceCheckUtils]: 37: Hoare triple {3449#false} assume 1 == ~E_M~0;~E_M~0 := 2; {3449#false} is VALID [2020-07-29 03:08:46,732 INFO L280 TraceCheckUtils]: 38: Hoare triple {3449#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3449#false} is VALID [2020-07-29 03:08:46,732 INFO L280 TraceCheckUtils]: 39: Hoare triple {3449#false} assume 1 == ~E_2~0;~E_2~0 := 2; {3449#false} is VALID [2020-07-29 03:08:46,737 INFO L280 TraceCheckUtils]: 40: Hoare triple {3449#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {3449#false} is VALID [2020-07-29 03:08:46,738 INFO L280 TraceCheckUtils]: 41: Hoare triple {3449#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {3449#false} is VALID [2020-07-29 03:08:46,738 INFO L280 TraceCheckUtils]: 42: Hoare triple {3449#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {3449#false} is VALID [2020-07-29 03:08:46,738 INFO L280 TraceCheckUtils]: 43: Hoare triple {3449#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {3449#false} is VALID [2020-07-29 03:08:46,738 INFO L280 TraceCheckUtils]: 44: Hoare triple {3449#false} assume !(0 == start_simulation_~tmp~3); {3449#false} is VALID [2020-07-29 03:08:46,738 INFO L280 TraceCheckUtils]: 45: Hoare triple {3449#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {3449#false} is VALID [2020-07-29 03:08:46,738 INFO L280 TraceCheckUtils]: 46: Hoare triple {3449#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {3449#false} is VALID [2020-07-29 03:08:46,739 INFO L280 TraceCheckUtils]: 47: Hoare triple {3449#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {3449#false} is VALID [2020-07-29 03:08:46,739 INFO L280 TraceCheckUtils]: 48: Hoare triple {3449#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {3449#false} is VALID [2020-07-29 03:08:46,739 INFO L280 TraceCheckUtils]: 49: Hoare triple {3449#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {3449#false} is VALID [2020-07-29 03:08:46,739 INFO L280 TraceCheckUtils]: 50: Hoare triple {3449#false} stop_simulation_#res := stop_simulation_~__retres2~0; {3449#false} is VALID [2020-07-29 03:08:46,739 INFO L280 TraceCheckUtils]: 51: Hoare triple {3449#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {3449#false} is VALID [2020-07-29 03:08:46,740 INFO L280 TraceCheckUtils]: 52: Hoare triple {3449#false} assume !(0 != start_simulation_~tmp___0~1); {3449#false} is VALID [2020-07-29 03:08:46,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:46,741 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45027964] [2020-07-29 03:08:46,741 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:46,741 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:46,741 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292852961] [2020-07-29 03:08:46,742 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:46,742 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:46,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:46,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:46,742 INFO L87 Difference]: Start difference. First operand 359 states and 535 transitions. cyclomatic complexity: 178 Second operand 3 states. [2020-07-29 03:08:47,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:47,246 INFO L93 Difference]: Finished difference Result 629 states and 927 transitions. [2020-07-29 03:08:47,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:47,247 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:47,286 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:47,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 629 states and 927 transitions. [2020-07-29 03:08:47,319 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 584 [2020-07-29 03:08:47,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 629 states to 629 states and 927 transitions. [2020-07-29 03:08:47,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 629 [2020-07-29 03:08:47,344 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 629 [2020-07-29 03:08:47,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 629 states and 927 transitions. [2020-07-29 03:08:47,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:47,345 INFO L688 BuchiCegarLoop]: Abstraction has 629 states and 927 transitions. [2020-07-29 03:08:47,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 629 states and 927 transitions. [2020-07-29 03:08:47,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 629 to 625. [2020-07-29 03:08:47,359 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:47,359 INFO L82 GeneralOperation]: Start isEquivalent. First operand 629 states and 927 transitions. Second operand 625 states. [2020-07-29 03:08:47,359 INFO L74 IsIncluded]: Start isIncluded. First operand 629 states and 927 transitions. Second operand 625 states. [2020-07-29 03:08:47,359 INFO L87 Difference]: Start difference. First operand 629 states and 927 transitions. Second operand 625 states. [2020-07-29 03:08:47,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:47,383 INFO L93 Difference]: Finished difference Result 629 states and 927 transitions. [2020-07-29 03:08:47,383 INFO L276 IsEmpty]: Start isEmpty. Operand 629 states and 927 transitions. [2020-07-29 03:08:47,385 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:47,385 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:47,385 INFO L74 IsIncluded]: Start isIncluded. First operand 625 states. Second operand 629 states and 927 transitions. [2020-07-29 03:08:47,385 INFO L87 Difference]: Start difference. First operand 625 states. Second operand 629 states and 927 transitions. [2020-07-29 03:08:47,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:47,413 INFO L93 Difference]: Finished difference Result 629 states and 927 transitions. [2020-07-29 03:08:47,413 INFO L276 IsEmpty]: Start isEmpty. Operand 629 states and 927 transitions. [2020-07-29 03:08:47,415 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:47,415 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:47,415 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:47,415 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:47,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 625 states. [2020-07-29 03:08:47,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 625 states to 625 states and 923 transitions. [2020-07-29 03:08:47,447 INFO L711 BuchiCegarLoop]: Abstraction has 625 states and 923 transitions. [2020-07-29 03:08:47,447 INFO L591 BuchiCegarLoop]: Abstraction has 625 states and 923 transitions. [2020-07-29 03:08:47,447 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2020-07-29 03:08:47,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 625 states and 923 transitions. [2020-07-29 03:08:47,452 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 580 [2020-07-29 03:08:47,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:47,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:47,454 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:47,454 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:47,454 INFO L794 eck$LassoCheckResult]: Stem: 4159#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4094#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4095#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4186#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 4197#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4147#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4148#L231-1 assume !(0 == ~M_E~0); 4119#L334-1 assume !(0 == ~T1_E~0); 4120#L339-1 assume !(0 == ~T2_E~0); 4136#L344-1 assume !(0 == ~E_M~0); 4284#L349-1 assume !(0 == ~E_1~0); 4210#L354-1 assume !(0 == ~E_2~0); 4211#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4243#L156 assume !(1 == ~m_pc~0); 4315#L156-2 is_master_triggered_~__retres1~0 := 0; 4316#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4269#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4270#L415 assume !(0 != activate_threads_~tmp~1); 4306#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4082#L175 assume !(1 == ~t1_pc~0); 4083#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 4084#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4085#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4158#L423 assume !(0 != activate_threads_~tmp___0~0); 4198#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4201#L194 assume !(1 == ~t2_pc~0); 4238#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 4239#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4244#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4230#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4204#L431-2 assume !(1 == ~M_E~0); 4134#L372-1 assume !(1 == ~T1_E~0); 4135#L377-1 assume !(1 == ~T2_E~0); 4283#L382-1 assume !(1 == ~E_M~0); 4205#L387-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4206#L392-1 assume !(1 == ~E_2~0); 4124#L543-1 [2020-07-29 03:08:47,454 INFO L796 eck$LassoCheckResult]: Loop: 4124#L543-1 assume !false; 4125#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4531#L309 assume !false; 4528#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4525#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4524#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4523#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4519#L276 assume !(0 != eval_~tmp~0); 4187#L324 start_simulation_~kernel_st~0 := 2; 4188#L214-1 start_simulation_~kernel_st~0 := 3; 4121#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4122#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4123#L339-3 assume !(0 == ~T2_E~0); 4139#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4286#L349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4223#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4224#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4233#L156-12 assume !(1 == ~m_pc~0); 4296#L156-14 is_master_triggered_~__retres1~0 := 0; 4696#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4694#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4292#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4293#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4199#L175-12 assume !(1 == ~t1_pc~0); 4200#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 4697#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4695#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4693#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4692#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4691#L194-12 assume !(1 == ~t2_pc~0); 4688#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 4686#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4685#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4684#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4683#L431-14 assume !(1 == ~M_E~0); 4682#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4681#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4680#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4679#L387-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4661#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4660#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4604#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4600#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4596#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 4592#L562 assume !(0 == start_simulation_~tmp~3); 4589#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4585#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4582#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4581#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 4580#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4579#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 4578#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 4576#L575 assume !(0 != start_simulation_~tmp___0~1); 4124#L543-1 [2020-07-29 03:08:47,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:47,455 INFO L82 PathProgramCache]: Analyzing trace with hash 545629540, now seen corresponding path program 1 times [2020-07-29 03:08:47,455 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:47,456 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347172917] [2020-07-29 03:08:47,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:47,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:47,537 INFO L280 TraceCheckUtils]: 0: Hoare triple {5968#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,538 INFO L280 TraceCheckUtils]: 1: Hoare triple {5970#(<= 2 ~E_1~0)} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,539 INFO L280 TraceCheckUtils]: 2: Hoare triple {5970#(<= 2 ~E_1~0)} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,539 INFO L280 TraceCheckUtils]: 3: Hoare triple {5970#(<= 2 ~E_1~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,540 INFO L280 TraceCheckUtils]: 4: Hoare triple {5970#(<= 2 ~E_1~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,540 INFO L280 TraceCheckUtils]: 5: Hoare triple {5970#(<= 2 ~E_1~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,541 INFO L280 TraceCheckUtils]: 6: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(0 == ~M_E~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,541 INFO L280 TraceCheckUtils]: 7: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(0 == ~T1_E~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,542 INFO L280 TraceCheckUtils]: 8: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(0 == ~T2_E~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,542 INFO L280 TraceCheckUtils]: 9: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(0 == ~E_M~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,543 INFO L280 TraceCheckUtils]: 10: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(0 == ~E_1~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,543 INFO L280 TraceCheckUtils]: 11: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(0 == ~E_2~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,544 INFO L280 TraceCheckUtils]: 12: Hoare triple {5970#(<= 2 ~E_1~0)} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,544 INFO L280 TraceCheckUtils]: 13: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(1 == ~m_pc~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,545 INFO L280 TraceCheckUtils]: 14: Hoare triple {5970#(<= 2 ~E_1~0)} is_master_triggered_~__retres1~0 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,546 INFO L280 TraceCheckUtils]: 15: Hoare triple {5970#(<= 2 ~E_1~0)} is_master_triggered_#res := is_master_triggered_~__retres1~0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,546 INFO L280 TraceCheckUtils]: 16: Hoare triple {5970#(<= 2 ~E_1~0)} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,547 INFO L280 TraceCheckUtils]: 17: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(0 != activate_threads_~tmp~1); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,547 INFO L280 TraceCheckUtils]: 18: Hoare triple {5970#(<= 2 ~E_1~0)} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,548 INFO L280 TraceCheckUtils]: 19: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(1 == ~t1_pc~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,548 INFO L280 TraceCheckUtils]: 20: Hoare triple {5970#(<= 2 ~E_1~0)} is_transmit1_triggered_~__retres1~1 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,549 INFO L280 TraceCheckUtils]: 21: Hoare triple {5970#(<= 2 ~E_1~0)} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,549 INFO L280 TraceCheckUtils]: 22: Hoare triple {5970#(<= 2 ~E_1~0)} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,550 INFO L280 TraceCheckUtils]: 23: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(0 != activate_threads_~tmp___0~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,551 INFO L280 TraceCheckUtils]: 24: Hoare triple {5970#(<= 2 ~E_1~0)} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,554 INFO L280 TraceCheckUtils]: 25: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(1 == ~t2_pc~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,554 INFO L280 TraceCheckUtils]: 26: Hoare triple {5970#(<= 2 ~E_1~0)} is_transmit2_triggered_~__retres1~2 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,555 INFO L280 TraceCheckUtils]: 27: Hoare triple {5970#(<= 2 ~E_1~0)} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,555 INFO L280 TraceCheckUtils]: 28: Hoare triple {5970#(<= 2 ~E_1~0)} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,558 INFO L280 TraceCheckUtils]: 29: Hoare triple {5970#(<= 2 ~E_1~0)} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,559 INFO L280 TraceCheckUtils]: 30: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(1 == ~M_E~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,560 INFO L280 TraceCheckUtils]: 31: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(1 == ~T1_E~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,563 INFO L280 TraceCheckUtils]: 32: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(1 == ~T2_E~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,566 INFO L280 TraceCheckUtils]: 33: Hoare triple {5970#(<= 2 ~E_1~0)} assume !(1 == ~E_M~0); {5970#(<= 2 ~E_1~0)} is VALID [2020-07-29 03:08:47,568 INFO L280 TraceCheckUtils]: 34: Hoare triple {5970#(<= 2 ~E_1~0)} assume 1 == ~E_1~0;~E_1~0 := 2; {5969#false} is VALID [2020-07-29 03:08:47,568 INFO L280 TraceCheckUtils]: 35: Hoare triple {5969#false} assume !(1 == ~E_2~0); {5969#false} is VALID [2020-07-29 03:08:47,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:47,573 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347172917] [2020-07-29 03:08:47,573 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:47,573 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-07-29 03:08:47,573 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416951934] [2020-07-29 03:08:47,574 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-07-29 03:08:47,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:47,574 INFO L82 PathProgramCache]: Analyzing trace with hash 1635207239, now seen corresponding path program 1 times [2020-07-29 03:08:47,574 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:47,575 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694615941] [2020-07-29 03:08:47,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:47,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:47,650 INFO L280 TraceCheckUtils]: 0: Hoare triple {5971#true} assume !false; {5971#true} is VALID [2020-07-29 03:08:47,650 INFO L280 TraceCheckUtils]: 1: Hoare triple {5971#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {5971#true} is VALID [2020-07-29 03:08:47,651 INFO L280 TraceCheckUtils]: 2: Hoare triple {5971#true} assume !false; {5971#true} is VALID [2020-07-29 03:08:47,651 INFO L280 TraceCheckUtils]: 3: Hoare triple {5971#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {5971#true} is VALID [2020-07-29 03:08:47,652 INFO L280 TraceCheckUtils]: 4: Hoare triple {5971#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {5973#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} is VALID [2020-07-29 03:08:47,652 INFO L280 TraceCheckUtils]: 5: Hoare triple {5973#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {5974#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} is VALID [2020-07-29 03:08:47,653 INFO L280 TraceCheckUtils]: 6: Hoare triple {5974#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {5975#(<= 1 ULTIMATE.start_eval_~tmp~0)} is VALID [2020-07-29 03:08:47,653 INFO L280 TraceCheckUtils]: 7: Hoare triple {5975#(<= 1 ULTIMATE.start_eval_~tmp~0)} assume !(0 != eval_~tmp~0); {5972#false} is VALID [2020-07-29 03:08:47,654 INFO L280 TraceCheckUtils]: 8: Hoare triple {5972#false} start_simulation_~kernel_st~0 := 2; {5972#false} is VALID [2020-07-29 03:08:47,654 INFO L280 TraceCheckUtils]: 9: Hoare triple {5972#false} start_simulation_~kernel_st~0 := 3; {5972#false} is VALID [2020-07-29 03:08:47,654 INFO L280 TraceCheckUtils]: 10: Hoare triple {5972#false} assume 0 == ~M_E~0;~M_E~0 := 1; {5972#false} is VALID [2020-07-29 03:08:47,654 INFO L280 TraceCheckUtils]: 11: Hoare triple {5972#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5972#false} is VALID [2020-07-29 03:08:47,654 INFO L280 TraceCheckUtils]: 12: Hoare triple {5972#false} assume !(0 == ~T2_E~0); {5972#false} is VALID [2020-07-29 03:08:47,654 INFO L280 TraceCheckUtils]: 13: Hoare triple {5972#false} assume 0 == ~E_M~0;~E_M~0 := 1; {5972#false} is VALID [2020-07-29 03:08:47,655 INFO L280 TraceCheckUtils]: 14: Hoare triple {5972#false} assume 0 == ~E_1~0;~E_1~0 := 1; {5972#false} is VALID [2020-07-29 03:08:47,655 INFO L280 TraceCheckUtils]: 15: Hoare triple {5972#false} assume 0 == ~E_2~0;~E_2~0 := 1; {5972#false} is VALID [2020-07-29 03:08:47,655 INFO L280 TraceCheckUtils]: 16: Hoare triple {5972#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {5972#false} is VALID [2020-07-29 03:08:47,655 INFO L280 TraceCheckUtils]: 17: Hoare triple {5972#false} assume !(1 == ~m_pc~0); {5972#false} is VALID [2020-07-29 03:08:47,655 INFO L280 TraceCheckUtils]: 18: Hoare triple {5972#false} is_master_triggered_~__retres1~0 := 0; {5972#false} is VALID [2020-07-29 03:08:47,656 INFO L280 TraceCheckUtils]: 19: Hoare triple {5972#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {5972#false} is VALID [2020-07-29 03:08:47,656 INFO L280 TraceCheckUtils]: 20: Hoare triple {5972#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {5972#false} is VALID [2020-07-29 03:08:47,656 INFO L280 TraceCheckUtils]: 21: Hoare triple {5972#false} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {5972#false} is VALID [2020-07-29 03:08:47,656 INFO L280 TraceCheckUtils]: 22: Hoare triple {5972#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {5972#false} is VALID [2020-07-29 03:08:47,656 INFO L280 TraceCheckUtils]: 23: Hoare triple {5972#false} assume !(1 == ~t1_pc~0); {5972#false} is VALID [2020-07-29 03:08:47,657 INFO L280 TraceCheckUtils]: 24: Hoare triple {5972#false} is_transmit1_triggered_~__retres1~1 := 0; {5972#false} is VALID [2020-07-29 03:08:47,657 INFO L280 TraceCheckUtils]: 25: Hoare triple {5972#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {5972#false} is VALID [2020-07-29 03:08:47,657 INFO L280 TraceCheckUtils]: 26: Hoare triple {5972#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {5972#false} is VALID [2020-07-29 03:08:47,657 INFO L280 TraceCheckUtils]: 27: Hoare triple {5972#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {5972#false} is VALID [2020-07-29 03:08:47,657 INFO L280 TraceCheckUtils]: 28: Hoare triple {5972#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {5972#false} is VALID [2020-07-29 03:08:47,657 INFO L280 TraceCheckUtils]: 29: Hoare triple {5972#false} assume !(1 == ~t2_pc~0); {5972#false} is VALID [2020-07-29 03:08:47,658 INFO L280 TraceCheckUtils]: 30: Hoare triple {5972#false} is_transmit2_triggered_~__retres1~2 := 0; {5972#false} is VALID [2020-07-29 03:08:47,658 INFO L280 TraceCheckUtils]: 31: Hoare triple {5972#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {5972#false} is VALID [2020-07-29 03:08:47,658 INFO L280 TraceCheckUtils]: 32: Hoare triple {5972#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {5972#false} is VALID [2020-07-29 03:08:47,658 INFO L280 TraceCheckUtils]: 33: Hoare triple {5972#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {5972#false} is VALID [2020-07-29 03:08:47,658 INFO L280 TraceCheckUtils]: 34: Hoare triple {5972#false} assume !(1 == ~M_E~0); {5972#false} is VALID [2020-07-29 03:08:47,659 INFO L280 TraceCheckUtils]: 35: Hoare triple {5972#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5972#false} is VALID [2020-07-29 03:08:47,659 INFO L280 TraceCheckUtils]: 36: Hoare triple {5972#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {5972#false} is VALID [2020-07-29 03:08:47,659 INFO L280 TraceCheckUtils]: 37: Hoare triple {5972#false} assume 1 == ~E_M~0;~E_M~0 := 2; {5972#false} is VALID [2020-07-29 03:08:47,659 INFO L280 TraceCheckUtils]: 38: Hoare triple {5972#false} assume 1 == ~E_1~0;~E_1~0 := 2; {5972#false} is VALID [2020-07-29 03:08:47,659 INFO L280 TraceCheckUtils]: 39: Hoare triple {5972#false} assume 1 == ~E_2~0;~E_2~0 := 2; {5972#false} is VALID [2020-07-29 03:08:47,660 INFO L280 TraceCheckUtils]: 40: Hoare triple {5972#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {5972#false} is VALID [2020-07-29 03:08:47,660 INFO L280 TraceCheckUtils]: 41: Hoare triple {5972#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {5972#false} is VALID [2020-07-29 03:08:47,660 INFO L280 TraceCheckUtils]: 42: Hoare triple {5972#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {5972#false} is VALID [2020-07-29 03:08:47,660 INFO L280 TraceCheckUtils]: 43: Hoare triple {5972#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {5972#false} is VALID [2020-07-29 03:08:47,660 INFO L280 TraceCheckUtils]: 44: Hoare triple {5972#false} assume !(0 == start_simulation_~tmp~3); {5972#false} is VALID [2020-07-29 03:08:47,660 INFO L280 TraceCheckUtils]: 45: Hoare triple {5972#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {5972#false} is VALID [2020-07-29 03:08:47,661 INFO L280 TraceCheckUtils]: 46: Hoare triple {5972#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {5972#false} is VALID [2020-07-29 03:08:47,661 INFO L280 TraceCheckUtils]: 47: Hoare triple {5972#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {5972#false} is VALID [2020-07-29 03:08:47,661 INFO L280 TraceCheckUtils]: 48: Hoare triple {5972#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {5972#false} is VALID [2020-07-29 03:08:47,661 INFO L280 TraceCheckUtils]: 49: Hoare triple {5972#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {5972#false} is VALID [2020-07-29 03:08:47,661 INFO L280 TraceCheckUtils]: 50: Hoare triple {5972#false} stop_simulation_#res := stop_simulation_~__retres2~0; {5972#false} is VALID [2020-07-29 03:08:47,662 INFO L280 TraceCheckUtils]: 51: Hoare triple {5972#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {5972#false} is VALID [2020-07-29 03:08:47,662 INFO L280 TraceCheckUtils]: 52: Hoare triple {5972#false} assume !(0 != start_simulation_~tmp___0~1); {5972#false} is VALID [2020-07-29 03:08:47,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:47,664 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694615941] [2020-07-29 03:08:47,664 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:47,664 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:47,665 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387194050] [2020-07-29 03:08:47,665 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:47,665 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:47,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:47,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:47,666 INFO L87 Difference]: Start difference. First operand 625 states and 923 transitions. cyclomatic complexity: 302 Second operand 3 states. [2020-07-29 03:08:47,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:47,997 INFO L93 Difference]: Finished difference Result 625 states and 901 transitions. [2020-07-29 03:08:47,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:47,997 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:48,049 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:48,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 625 states and 901 transitions. [2020-07-29 03:08:48,077 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 580 [2020-07-29 03:08:48,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 625 states to 625 states and 901 transitions. [2020-07-29 03:08:48,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 625 [2020-07-29 03:08:48,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 625 [2020-07-29 03:08:48,105 INFO L73 IsDeterministic]: Start isDeterministic. Operand 625 states and 901 transitions. [2020-07-29 03:08:48,106 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:48,106 INFO L688 BuchiCegarLoop]: Abstraction has 625 states and 901 transitions. [2020-07-29 03:08:48,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 625 states and 901 transitions. [2020-07-29 03:08:48,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 625 to 625. [2020-07-29 03:08:48,118 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:48,118 INFO L82 GeneralOperation]: Start isEquivalent. First operand 625 states and 901 transitions. Second operand 625 states. [2020-07-29 03:08:48,118 INFO L74 IsIncluded]: Start isIncluded. First operand 625 states and 901 transitions. Second operand 625 states. [2020-07-29 03:08:48,118 INFO L87 Difference]: Start difference. First operand 625 states and 901 transitions. Second operand 625 states. [2020-07-29 03:08:48,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:48,154 INFO L93 Difference]: Finished difference Result 625 states and 901 transitions. [2020-07-29 03:08:48,154 INFO L276 IsEmpty]: Start isEmpty. Operand 625 states and 901 transitions. [2020-07-29 03:08:48,156 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:48,156 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:48,156 INFO L74 IsIncluded]: Start isIncluded. First operand 625 states. Second operand 625 states and 901 transitions. [2020-07-29 03:08:48,156 INFO L87 Difference]: Start difference. First operand 625 states. Second operand 625 states and 901 transitions. [2020-07-29 03:08:48,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:48,186 INFO L93 Difference]: Finished difference Result 625 states and 901 transitions. [2020-07-29 03:08:48,186 INFO L276 IsEmpty]: Start isEmpty. Operand 625 states and 901 transitions. [2020-07-29 03:08:48,187 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:48,188 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:48,188 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:48,188 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:48,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 625 states. [2020-07-29 03:08:48,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 625 states to 625 states and 901 transitions. [2020-07-29 03:08:48,220 INFO L711 BuchiCegarLoop]: Abstraction has 625 states and 901 transitions. [2020-07-29 03:08:48,220 INFO L591 BuchiCegarLoop]: Abstraction has 625 states and 901 transitions. [2020-07-29 03:08:48,220 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2020-07-29 03:08:48,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 625 states and 901 transitions. [2020-07-29 03:08:48,224 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 580 [2020-07-29 03:08:48,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:48,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:48,226 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:48,226 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:48,226 INFO L794 eck$LassoCheckResult]: Stem: 6675#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 6613#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6614#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6702#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 6712#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6665#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6666#L231-1 assume !(0 == ~M_E~0); 6638#L334-1 assume !(0 == ~T1_E~0); 6639#L339-1 assume !(0 == ~T2_E~0); 6654#L344-1 assume !(0 == ~E_M~0); 6798#L349-1 assume !(0 == ~E_1~0); 6725#L354-1 assume !(0 == ~E_2~0); 6726#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6758#L156 assume !(1 == ~m_pc~0); 6824#L156-2 is_master_triggered_~__retres1~0 := 0; 6825#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6784#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6785#L415 assume !(0 != activate_threads_~tmp~1); 6818#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6601#L175 assume !(1 == ~t1_pc~0); 6602#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 6605#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6606#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6674#L423 assume !(0 != activate_threads_~tmp___0~0); 6714#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6716#L194 assume !(1 == ~t2_pc~0); 6752#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 6753#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6759#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6747#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6719#L431-2 assume !(1 == ~M_E~0); 6652#L372-1 assume !(1 == ~T1_E~0); 6653#L377-1 assume !(1 == ~T2_E~0); 6797#L382-1 assume !(1 == ~E_M~0); 6720#L387-1 assume !(1 == ~E_1~0); 6721#L392-1 assume !(1 == ~E_2~0); 6756#L543-1 [2020-07-29 03:08:48,226 INFO L796 eck$LassoCheckResult]: Loop: 6756#L543-1 assume !false; 6932#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6930#L309 assume !false; 6928#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6922#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6920#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6919#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 6915#L276 assume !(0 != eval_~tmp~0); 6704#L324 start_simulation_~kernel_st~0 := 2; 6705#L214-1 start_simulation_~kernel_st~0 := 3; 6640#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6641#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6642#L339-3 assume !(0 == ~T2_E~0); 6657#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6800#L349-3 assume !(0 == ~E_1~0); 6738#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6739#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6748#L156-12 assume !(1 == ~m_pc~0); 6808#L156-14 is_master_triggered_~__retres1~0 := 0; 6821#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6794#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6795#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6806#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6715#L175-12 assume !(1 == ~t1_pc~0); 6713#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 6621#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6622#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6683#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6692#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6693#L194-12 assume 1 == ~t2_pc~0; 6740#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6735#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6736#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6813#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6826#L431-14 assume !(1 == ~M_E~0); 6655#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6656#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6799#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6731#L387-3 assume !(1 == ~E_1~0); 6732#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6760#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6765#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6608#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6644#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 6645#L562 assume !(0 == start_simulation_~tmp~3); 6694#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6766#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6604#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6658#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 6659#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6946#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 6944#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 6942#L575 assume !(0 != start_simulation_~tmp___0~1); 6756#L543-1 [2020-07-29 03:08:48,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:48,227 INFO L82 PathProgramCache]: Analyzing trace with hash 545629602, now seen corresponding path program 1 times [2020-07-29 03:08:48,227 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:48,227 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691538731] [2020-07-29 03:08:48,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:48,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:48,326 INFO L280 TraceCheckUtils]: 0: Hoare triple {8479#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {8479#true} is VALID [2020-07-29 03:08:48,327 INFO L280 TraceCheckUtils]: 1: Hoare triple {8479#true} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {8479#true} is VALID [2020-07-29 03:08:48,327 INFO L280 TraceCheckUtils]: 2: Hoare triple {8479#true} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {8479#true} is VALID [2020-07-29 03:08:48,327 INFO L280 TraceCheckUtils]: 3: Hoare triple {8479#true} assume 1 == ~m_i~0;~m_st~0 := 0; {8479#true} is VALID [2020-07-29 03:08:48,327 INFO L280 TraceCheckUtils]: 4: Hoare triple {8479#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8479#true} is VALID [2020-07-29 03:08:48,328 INFO L280 TraceCheckUtils]: 5: Hoare triple {8479#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {8479#true} is VALID [2020-07-29 03:08:48,328 INFO L280 TraceCheckUtils]: 6: Hoare triple {8479#true} assume !(0 == ~M_E~0); {8479#true} is VALID [2020-07-29 03:08:48,328 INFO L280 TraceCheckUtils]: 7: Hoare triple {8479#true} assume !(0 == ~T1_E~0); {8479#true} is VALID [2020-07-29 03:08:48,328 INFO L280 TraceCheckUtils]: 8: Hoare triple {8479#true} assume !(0 == ~T2_E~0); {8479#true} is VALID [2020-07-29 03:08:48,328 INFO L280 TraceCheckUtils]: 9: Hoare triple {8479#true} assume !(0 == ~E_M~0); {8479#true} is VALID [2020-07-29 03:08:48,328 INFO L280 TraceCheckUtils]: 10: Hoare triple {8479#true} assume !(0 == ~E_1~0); {8479#true} is VALID [2020-07-29 03:08:48,329 INFO L280 TraceCheckUtils]: 11: Hoare triple {8479#true} assume !(0 == ~E_2~0); {8479#true} is VALID [2020-07-29 03:08:48,329 INFO L280 TraceCheckUtils]: 12: Hoare triple {8479#true} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {8479#true} is VALID [2020-07-29 03:08:48,329 INFO L280 TraceCheckUtils]: 13: Hoare triple {8479#true} assume !(1 == ~m_pc~0); {8479#true} is VALID [2020-07-29 03:08:48,329 INFO L280 TraceCheckUtils]: 14: Hoare triple {8479#true} is_master_triggered_~__retres1~0 := 0; {8479#true} is VALID [2020-07-29 03:08:48,329 INFO L280 TraceCheckUtils]: 15: Hoare triple {8479#true} is_master_triggered_#res := is_master_triggered_~__retres1~0; {8479#true} is VALID [2020-07-29 03:08:48,329 INFO L280 TraceCheckUtils]: 16: Hoare triple {8479#true} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {8479#true} is VALID [2020-07-29 03:08:48,330 INFO L280 TraceCheckUtils]: 17: Hoare triple {8479#true} assume !(0 != activate_threads_~tmp~1); {8479#true} is VALID [2020-07-29 03:08:48,330 INFO L280 TraceCheckUtils]: 18: Hoare triple {8479#true} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {8479#true} is VALID [2020-07-29 03:08:48,330 INFO L280 TraceCheckUtils]: 19: Hoare triple {8479#true} assume !(1 == ~t1_pc~0); {8479#true} is VALID [2020-07-29 03:08:48,330 INFO L280 TraceCheckUtils]: 20: Hoare triple {8479#true} is_transmit1_triggered_~__retres1~1 := 0; {8479#true} is VALID [2020-07-29 03:08:48,330 INFO L280 TraceCheckUtils]: 21: Hoare triple {8479#true} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {8479#true} is VALID [2020-07-29 03:08:48,331 INFO L280 TraceCheckUtils]: 22: Hoare triple {8479#true} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {8479#true} is VALID [2020-07-29 03:08:48,331 INFO L280 TraceCheckUtils]: 23: Hoare triple {8479#true} assume !(0 != activate_threads_~tmp___0~0); {8479#true} is VALID [2020-07-29 03:08:48,331 INFO L280 TraceCheckUtils]: 24: Hoare triple {8479#true} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {8479#true} is VALID [2020-07-29 03:08:48,331 INFO L280 TraceCheckUtils]: 25: Hoare triple {8479#true} assume !(1 == ~t2_pc~0); {8479#true} is VALID [2020-07-29 03:08:48,332 INFO L280 TraceCheckUtils]: 26: Hoare triple {8479#true} is_transmit2_triggered_~__retres1~2 := 0; {8481#(and (<= ULTIMATE.start_is_transmit2_triggered_~__retres1~2 0) (<= 0 ULTIMATE.start_is_transmit2_triggered_~__retres1~2))} is VALID [2020-07-29 03:08:48,333 INFO L280 TraceCheckUtils]: 27: Hoare triple {8481#(and (<= ULTIMATE.start_is_transmit2_triggered_~__retres1~2 0) (<= 0 ULTIMATE.start_is_transmit2_triggered_~__retres1~2))} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {8482#(and (<= 0 |ULTIMATE.start_is_transmit2_triggered_#res|) (<= |ULTIMATE.start_is_transmit2_triggered_#res| 0))} is VALID [2020-07-29 03:08:48,334 INFO L280 TraceCheckUtils]: 28: Hoare triple {8482#(and (<= 0 |ULTIMATE.start_is_transmit2_triggered_#res|) (<= |ULTIMATE.start_is_transmit2_triggered_#res| 0))} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {8483#(and (<= ULTIMATE.start_activate_threads_~tmp___1~0 0) (<= 0 ULTIMATE.start_activate_threads_~tmp___1~0))} is VALID [2020-07-29 03:08:48,334 INFO L280 TraceCheckUtils]: 29: Hoare triple {8483#(and (<= ULTIMATE.start_activate_threads_~tmp___1~0 0) (<= 0 ULTIMATE.start_activate_threads_~tmp___1~0))} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {8480#false} is VALID [2020-07-29 03:08:48,335 INFO L280 TraceCheckUtils]: 30: Hoare triple {8480#false} assume !(1 == ~M_E~0); {8480#false} is VALID [2020-07-29 03:08:48,335 INFO L280 TraceCheckUtils]: 31: Hoare triple {8480#false} assume !(1 == ~T1_E~0); {8480#false} is VALID [2020-07-29 03:08:48,335 INFO L280 TraceCheckUtils]: 32: Hoare triple {8480#false} assume !(1 == ~T2_E~0); {8480#false} is VALID [2020-07-29 03:08:48,335 INFO L280 TraceCheckUtils]: 33: Hoare triple {8480#false} assume !(1 == ~E_M~0); {8480#false} is VALID [2020-07-29 03:08:48,336 INFO L280 TraceCheckUtils]: 34: Hoare triple {8480#false} assume !(1 == ~E_1~0); {8480#false} is VALID [2020-07-29 03:08:48,336 INFO L280 TraceCheckUtils]: 35: Hoare triple {8480#false} assume !(1 == ~E_2~0); {8480#false} is VALID [2020-07-29 03:08:48,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:48,340 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [691538731] [2020-07-29 03:08:48,341 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:48,341 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:48,341 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993090941] [2020-07-29 03:08:48,342 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-07-29 03:08:48,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:48,342 INFO L82 PathProgramCache]: Analyzing trace with hash 100371372, now seen corresponding path program 1 times [2020-07-29 03:08:48,342 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:48,343 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898556699] [2020-07-29 03:08:48,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:48,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:48,417 INFO L280 TraceCheckUtils]: 0: Hoare triple {8484#true} assume !false; {8484#true} is VALID [2020-07-29 03:08:48,418 INFO L280 TraceCheckUtils]: 1: Hoare triple {8484#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {8484#true} is VALID [2020-07-29 03:08:48,418 INFO L280 TraceCheckUtils]: 2: Hoare triple {8484#true} assume !false; {8484#true} is VALID [2020-07-29 03:08:48,418 INFO L280 TraceCheckUtils]: 3: Hoare triple {8484#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {8484#true} is VALID [2020-07-29 03:08:48,419 INFO L280 TraceCheckUtils]: 4: Hoare triple {8484#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {8486#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} is VALID [2020-07-29 03:08:48,420 INFO L280 TraceCheckUtils]: 5: Hoare triple {8486#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {8487#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} is VALID [2020-07-29 03:08:48,421 INFO L280 TraceCheckUtils]: 6: Hoare triple {8487#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {8488#(<= 1 ULTIMATE.start_eval_~tmp~0)} is VALID [2020-07-29 03:08:48,422 INFO L280 TraceCheckUtils]: 7: Hoare triple {8488#(<= 1 ULTIMATE.start_eval_~tmp~0)} assume !(0 != eval_~tmp~0); {8485#false} is VALID [2020-07-29 03:08:48,422 INFO L280 TraceCheckUtils]: 8: Hoare triple {8485#false} start_simulation_~kernel_st~0 := 2; {8485#false} is VALID [2020-07-29 03:08:48,422 INFO L280 TraceCheckUtils]: 9: Hoare triple {8485#false} start_simulation_~kernel_st~0 := 3; {8485#false} is VALID [2020-07-29 03:08:48,422 INFO L280 TraceCheckUtils]: 10: Hoare triple {8485#false} assume 0 == ~M_E~0;~M_E~0 := 1; {8485#false} is VALID [2020-07-29 03:08:48,422 INFO L280 TraceCheckUtils]: 11: Hoare triple {8485#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8485#false} is VALID [2020-07-29 03:08:48,423 INFO L280 TraceCheckUtils]: 12: Hoare triple {8485#false} assume !(0 == ~T2_E~0); {8485#false} is VALID [2020-07-29 03:08:48,423 INFO L280 TraceCheckUtils]: 13: Hoare triple {8485#false} assume 0 == ~E_M~0;~E_M~0 := 1; {8485#false} is VALID [2020-07-29 03:08:48,423 INFO L280 TraceCheckUtils]: 14: Hoare triple {8485#false} assume !(0 == ~E_1~0); {8485#false} is VALID [2020-07-29 03:08:48,423 INFO L280 TraceCheckUtils]: 15: Hoare triple {8485#false} assume 0 == ~E_2~0;~E_2~0 := 1; {8485#false} is VALID [2020-07-29 03:08:48,424 INFO L280 TraceCheckUtils]: 16: Hoare triple {8485#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {8485#false} is VALID [2020-07-29 03:08:48,424 INFO L280 TraceCheckUtils]: 17: Hoare triple {8485#false} assume !(1 == ~m_pc~0); {8485#false} is VALID [2020-07-29 03:08:48,424 INFO L280 TraceCheckUtils]: 18: Hoare triple {8485#false} is_master_triggered_~__retres1~0 := 0; {8485#false} is VALID [2020-07-29 03:08:48,424 INFO L280 TraceCheckUtils]: 19: Hoare triple {8485#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {8485#false} is VALID [2020-07-29 03:08:48,424 INFO L280 TraceCheckUtils]: 20: Hoare triple {8485#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {8485#false} is VALID [2020-07-29 03:08:48,425 INFO L280 TraceCheckUtils]: 21: Hoare triple {8485#false} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {8485#false} is VALID [2020-07-29 03:08:48,425 INFO L280 TraceCheckUtils]: 22: Hoare triple {8485#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {8485#false} is VALID [2020-07-29 03:08:48,425 INFO L280 TraceCheckUtils]: 23: Hoare triple {8485#false} assume !(1 == ~t1_pc~0); {8485#false} is VALID [2020-07-29 03:08:48,425 INFO L280 TraceCheckUtils]: 24: Hoare triple {8485#false} is_transmit1_triggered_~__retres1~1 := 0; {8485#false} is VALID [2020-07-29 03:08:48,426 INFO L280 TraceCheckUtils]: 25: Hoare triple {8485#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {8485#false} is VALID [2020-07-29 03:08:48,426 INFO L280 TraceCheckUtils]: 26: Hoare triple {8485#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {8485#false} is VALID [2020-07-29 03:08:48,426 INFO L280 TraceCheckUtils]: 27: Hoare triple {8485#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {8485#false} is VALID [2020-07-29 03:08:48,426 INFO L280 TraceCheckUtils]: 28: Hoare triple {8485#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {8485#false} is VALID [2020-07-29 03:08:48,426 INFO L280 TraceCheckUtils]: 29: Hoare triple {8485#false} assume 1 == ~t2_pc~0; {8485#false} is VALID [2020-07-29 03:08:48,427 INFO L280 TraceCheckUtils]: 30: Hoare triple {8485#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; {8485#false} is VALID [2020-07-29 03:08:48,427 INFO L280 TraceCheckUtils]: 31: Hoare triple {8485#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {8485#false} is VALID [2020-07-29 03:08:48,427 INFO L280 TraceCheckUtils]: 32: Hoare triple {8485#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {8485#false} is VALID [2020-07-29 03:08:48,427 INFO L280 TraceCheckUtils]: 33: Hoare triple {8485#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {8485#false} is VALID [2020-07-29 03:08:48,428 INFO L280 TraceCheckUtils]: 34: Hoare triple {8485#false} assume !(1 == ~M_E~0); {8485#false} is VALID [2020-07-29 03:08:48,431 INFO L280 TraceCheckUtils]: 35: Hoare triple {8485#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8485#false} is VALID [2020-07-29 03:08:48,431 INFO L280 TraceCheckUtils]: 36: Hoare triple {8485#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8485#false} is VALID [2020-07-29 03:08:48,432 INFO L280 TraceCheckUtils]: 37: Hoare triple {8485#false} assume 1 == ~E_M~0;~E_M~0 := 2; {8485#false} is VALID [2020-07-29 03:08:48,432 INFO L280 TraceCheckUtils]: 38: Hoare triple {8485#false} assume !(1 == ~E_1~0); {8485#false} is VALID [2020-07-29 03:08:48,432 INFO L280 TraceCheckUtils]: 39: Hoare triple {8485#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8485#false} is VALID [2020-07-29 03:08:48,432 INFO L280 TraceCheckUtils]: 40: Hoare triple {8485#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {8485#false} is VALID [2020-07-29 03:08:48,432 INFO L280 TraceCheckUtils]: 41: Hoare triple {8485#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {8485#false} is VALID [2020-07-29 03:08:48,433 INFO L280 TraceCheckUtils]: 42: Hoare triple {8485#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {8485#false} is VALID [2020-07-29 03:08:48,433 INFO L280 TraceCheckUtils]: 43: Hoare triple {8485#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {8485#false} is VALID [2020-07-29 03:08:48,434 INFO L280 TraceCheckUtils]: 44: Hoare triple {8485#false} assume !(0 == start_simulation_~tmp~3); {8485#false} is VALID [2020-07-29 03:08:48,434 INFO L280 TraceCheckUtils]: 45: Hoare triple {8485#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {8485#false} is VALID [2020-07-29 03:08:48,435 INFO L280 TraceCheckUtils]: 46: Hoare triple {8485#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {8485#false} is VALID [2020-07-29 03:08:48,435 INFO L280 TraceCheckUtils]: 47: Hoare triple {8485#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {8485#false} is VALID [2020-07-29 03:08:48,435 INFO L280 TraceCheckUtils]: 48: Hoare triple {8485#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {8485#false} is VALID [2020-07-29 03:08:48,435 INFO L280 TraceCheckUtils]: 49: Hoare triple {8485#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {8485#false} is VALID [2020-07-29 03:08:48,436 INFO L280 TraceCheckUtils]: 50: Hoare triple {8485#false} stop_simulation_#res := stop_simulation_~__retres2~0; {8485#false} is VALID [2020-07-29 03:08:48,436 INFO L280 TraceCheckUtils]: 51: Hoare triple {8485#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {8485#false} is VALID [2020-07-29 03:08:48,436 INFO L280 TraceCheckUtils]: 52: Hoare triple {8485#false} assume !(0 != start_simulation_~tmp___0~1); {8485#false} is VALID [2020-07-29 03:08:48,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:48,440 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898556699] [2020-07-29 03:08:48,440 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:48,440 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:48,441 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823335427] [2020-07-29 03:08:48,441 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:48,442 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:48,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-07-29 03:08:48,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-07-29 03:08:48,443 INFO L87 Difference]: Start difference. First operand 625 states and 901 transitions. cyclomatic complexity: 280 Second operand 5 states. [2020-07-29 03:08:50,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:50,088 INFO L93 Difference]: Finished difference Result 1460 states and 2110 transitions. [2020-07-29 03:08:50,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-07-29 03:08:50,089 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2020-07-29 03:08:50,148 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:50,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1460 states and 2110 transitions. [2020-07-29 03:08:50,224 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1384 [2020-07-29 03:08:50,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1460 states to 1460 states and 2110 transitions. [2020-07-29 03:08:50,313 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1460 [2020-07-29 03:08:50,314 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1460 [2020-07-29 03:08:50,314 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1460 states and 2110 transitions. [2020-07-29 03:08:50,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:50,316 INFO L688 BuchiCegarLoop]: Abstraction has 1460 states and 2110 transitions. [2020-07-29 03:08:50,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1460 states and 2110 transitions. [2020-07-29 03:08:50,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1460 to 676. [2020-07-29 03:08:50,332 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:50,333 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1460 states and 2110 transitions. Second operand 676 states. [2020-07-29 03:08:50,333 INFO L74 IsIncluded]: Start isIncluded. First operand 1460 states and 2110 transitions. Second operand 676 states. [2020-07-29 03:08:50,333 INFO L87 Difference]: Start difference. First operand 1460 states and 2110 transitions. Second operand 676 states. [2020-07-29 03:08:50,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:50,441 INFO L93 Difference]: Finished difference Result 1460 states and 2110 transitions. [2020-07-29 03:08:50,442 INFO L276 IsEmpty]: Start isEmpty. Operand 1460 states and 2110 transitions. [2020-07-29 03:08:50,445 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:50,445 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:50,445 INFO L74 IsIncluded]: Start isIncluded. First operand 676 states. Second operand 1460 states and 2110 transitions. [2020-07-29 03:08:50,445 INFO L87 Difference]: Start difference. First operand 676 states. Second operand 1460 states and 2110 transitions. [2020-07-29 03:08:50,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:50,533 INFO L93 Difference]: Finished difference Result 1460 states and 2110 transitions. [2020-07-29 03:08:50,533 INFO L276 IsEmpty]: Start isEmpty. Operand 1460 states and 2110 transitions. [2020-07-29 03:08:50,535 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:50,536 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:50,536 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:50,536 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:50,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 676 states. [2020-07-29 03:08:50,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 676 states to 676 states and 952 transitions. [2020-07-29 03:08:50,552 INFO L711 BuchiCegarLoop]: Abstraction has 676 states and 952 transitions. [2020-07-29 03:08:50,552 INFO L591 BuchiCegarLoop]: Abstraction has 676 states and 952 transitions. [2020-07-29 03:08:50,552 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2020-07-29 03:08:50,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 676 states and 952 transitions. [2020-07-29 03:08:50,556 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 628 [2020-07-29 03:08:50,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:50,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:50,557 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:50,557 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:50,557 INFO L794 eck$LassoCheckResult]: Stem: 10028#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 9965#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9966#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10054#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 10071#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10019#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10020#L231-1 assume !(0 == ~M_E~0); 9992#L334-1 assume !(0 == ~T1_E~0); 9993#L339-1 assume !(0 == ~T2_E~0); 10008#L344-1 assume !(0 == ~E_M~0); 10170#L349-1 assume !(0 == ~E_1~0); 10086#L354-1 assume !(0 == ~E_2~0); 10087#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10126#L156 assume !(1 == ~m_pc~0); 10219#L156-2 is_master_triggered_~__retres1~0 := 0; 10220#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10156#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10157#L415 assume !(0 != activate_threads_~tmp~1); 10202#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9953#L175 assume !(1 == ~t1_pc~0); 9954#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 9955#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9956#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10027#L423 assume !(0 != activate_threads_~tmp___0~0); 10073#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10075#L194 assume !(1 == ~t2_pc~0); 10120#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 10121#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10127#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10110#L431 assume !(0 != activate_threads_~tmp___1~0); 10078#L431-2 assume !(1 == ~M_E~0); 10006#L372-1 assume !(1 == ~T1_E~0); 10007#L377-1 assume !(1 == ~T2_E~0); 10169#L382-1 assume !(1 == ~E_M~0); 10079#L387-1 assume !(1 == ~E_1~0); 10080#L392-1 assume !(1 == ~E_2~0); 10123#L543-1 [2020-07-29 03:08:50,557 INFO L796 eck$LassoCheckResult]: Loop: 10123#L543-1 assume !false; 10575#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 10359#L309 assume !false; 10568#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10564#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10534#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10408#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 10404#L276 assume !(0 != eval_~tmp~0); 10055#L324 start_simulation_~kernel_st~0 := 2; 10056#L214-1 start_simulation_~kernel_st~0 := 3; 9994#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9995#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9996#L339-3 assume !(0 == ~T2_E~0); 10011#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10172#L349-3 assume !(0 == ~E_1~0); 10100#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10101#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10113#L156-12 assume !(1 == ~m_pc~0); 10185#L156-14 is_master_triggered_~__retres1~0 := 0; 10217#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10563#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10562#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10561#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10560#L175-12 assume !(1 == ~t1_pc~0); 10559#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 10558#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10557#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10556#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10555#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10102#L194-12 assume 1 == ~t2_pc~0; 10103#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10553#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10551#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10549#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10547#L431-14 assume !(1 == ~M_E~0); 10545#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10543#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10541#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10539#L387-3 assume !(1 == ~E_1~0); 10537#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10535#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10529#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10515#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10489#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 10136#L562 assume !(0 == start_simulation_~tmp~3); 10137#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10596#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10594#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10593#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 10592#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10591#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 10590#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 10578#L575 assume !(0 != start_simulation_~tmp___0~1); 10123#L543-1 [2020-07-29 03:08:50,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:50,558 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 1 times [2020-07-29 03:08:50,558 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:50,558 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533110313] [2020-07-29 03:08:50,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:50,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:50,566 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:50,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:50,573 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:50,609 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:50,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:50,609 INFO L82 PathProgramCache]: Analyzing trace with hash 100371372, now seen corresponding path program 2 times [2020-07-29 03:08:50,610 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:50,611 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261229465] [2020-07-29 03:08:50,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:50,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:50,667 INFO L280 TraceCheckUtils]: 0: Hoare triple {13554#true} assume !false; {13554#true} is VALID [2020-07-29 03:08:50,668 INFO L280 TraceCheckUtils]: 1: Hoare triple {13554#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {13554#true} is VALID [2020-07-29 03:08:50,668 INFO L280 TraceCheckUtils]: 2: Hoare triple {13554#true} assume !false; {13554#true} is VALID [2020-07-29 03:08:50,668 INFO L280 TraceCheckUtils]: 3: Hoare triple {13554#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {13554#true} is VALID [2020-07-29 03:08:50,669 INFO L280 TraceCheckUtils]: 4: Hoare triple {13554#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {13556#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} is VALID [2020-07-29 03:08:50,670 INFO L280 TraceCheckUtils]: 5: Hoare triple {13556#(<= 1 ULTIMATE.start_exists_runnable_thread_~__retres1~3)} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {13557#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} is VALID [2020-07-29 03:08:50,670 INFO L280 TraceCheckUtils]: 6: Hoare triple {13557#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res|)} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {13558#(<= 1 ULTIMATE.start_eval_~tmp~0)} is VALID [2020-07-29 03:08:50,671 INFO L280 TraceCheckUtils]: 7: Hoare triple {13558#(<= 1 ULTIMATE.start_eval_~tmp~0)} assume !(0 != eval_~tmp~0); {13555#false} is VALID [2020-07-29 03:08:50,671 INFO L280 TraceCheckUtils]: 8: Hoare triple {13555#false} start_simulation_~kernel_st~0 := 2; {13555#false} is VALID [2020-07-29 03:08:50,671 INFO L280 TraceCheckUtils]: 9: Hoare triple {13555#false} start_simulation_~kernel_st~0 := 3; {13555#false} is VALID [2020-07-29 03:08:50,671 INFO L280 TraceCheckUtils]: 10: Hoare triple {13555#false} assume 0 == ~M_E~0;~M_E~0 := 1; {13555#false} is VALID [2020-07-29 03:08:50,671 INFO L280 TraceCheckUtils]: 11: Hoare triple {13555#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {13555#false} is VALID [2020-07-29 03:08:50,671 INFO L280 TraceCheckUtils]: 12: Hoare triple {13555#false} assume !(0 == ~T2_E~0); {13555#false} is VALID [2020-07-29 03:08:50,672 INFO L280 TraceCheckUtils]: 13: Hoare triple {13555#false} assume 0 == ~E_M~0;~E_M~0 := 1; {13555#false} is VALID [2020-07-29 03:08:50,672 INFO L280 TraceCheckUtils]: 14: Hoare triple {13555#false} assume !(0 == ~E_1~0); {13555#false} is VALID [2020-07-29 03:08:50,672 INFO L280 TraceCheckUtils]: 15: Hoare triple {13555#false} assume 0 == ~E_2~0;~E_2~0 := 1; {13555#false} is VALID [2020-07-29 03:08:50,672 INFO L280 TraceCheckUtils]: 16: Hoare triple {13555#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {13555#false} is VALID [2020-07-29 03:08:50,673 INFO L280 TraceCheckUtils]: 17: Hoare triple {13555#false} assume !(1 == ~m_pc~0); {13555#false} is VALID [2020-07-29 03:08:50,673 INFO L280 TraceCheckUtils]: 18: Hoare triple {13555#false} is_master_triggered_~__retres1~0 := 0; {13555#false} is VALID [2020-07-29 03:08:50,673 INFO L280 TraceCheckUtils]: 19: Hoare triple {13555#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {13555#false} is VALID [2020-07-29 03:08:50,673 INFO L280 TraceCheckUtils]: 20: Hoare triple {13555#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {13555#false} is VALID [2020-07-29 03:08:50,674 INFO L280 TraceCheckUtils]: 21: Hoare triple {13555#false} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {13555#false} is VALID [2020-07-29 03:08:50,674 INFO L280 TraceCheckUtils]: 22: Hoare triple {13555#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {13555#false} is VALID [2020-07-29 03:08:50,674 INFO L280 TraceCheckUtils]: 23: Hoare triple {13555#false} assume !(1 == ~t1_pc~0); {13555#false} is VALID [2020-07-29 03:08:50,674 INFO L280 TraceCheckUtils]: 24: Hoare triple {13555#false} is_transmit1_triggered_~__retres1~1 := 0; {13555#false} is VALID [2020-07-29 03:08:50,674 INFO L280 TraceCheckUtils]: 25: Hoare triple {13555#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {13555#false} is VALID [2020-07-29 03:08:50,675 INFO L280 TraceCheckUtils]: 26: Hoare triple {13555#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {13555#false} is VALID [2020-07-29 03:08:50,675 INFO L280 TraceCheckUtils]: 27: Hoare triple {13555#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {13555#false} is VALID [2020-07-29 03:08:50,675 INFO L280 TraceCheckUtils]: 28: Hoare triple {13555#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {13555#false} is VALID [2020-07-29 03:08:50,675 INFO L280 TraceCheckUtils]: 29: Hoare triple {13555#false} assume 1 == ~t2_pc~0; {13555#false} is VALID [2020-07-29 03:08:50,675 INFO L280 TraceCheckUtils]: 30: Hoare triple {13555#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; {13555#false} is VALID [2020-07-29 03:08:50,675 INFO L280 TraceCheckUtils]: 31: Hoare triple {13555#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {13555#false} is VALID [2020-07-29 03:08:50,675 INFO L280 TraceCheckUtils]: 32: Hoare triple {13555#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {13555#false} is VALID [2020-07-29 03:08:50,676 INFO L280 TraceCheckUtils]: 33: Hoare triple {13555#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {13555#false} is VALID [2020-07-29 03:08:50,676 INFO L280 TraceCheckUtils]: 34: Hoare triple {13555#false} assume !(1 == ~M_E~0); {13555#false} is VALID [2020-07-29 03:08:50,676 INFO L280 TraceCheckUtils]: 35: Hoare triple {13555#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {13555#false} is VALID [2020-07-29 03:08:50,676 INFO L280 TraceCheckUtils]: 36: Hoare triple {13555#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {13555#false} is VALID [2020-07-29 03:08:50,676 INFO L280 TraceCheckUtils]: 37: Hoare triple {13555#false} assume 1 == ~E_M~0;~E_M~0 := 2; {13555#false} is VALID [2020-07-29 03:08:50,676 INFO L280 TraceCheckUtils]: 38: Hoare triple {13555#false} assume !(1 == ~E_1~0); {13555#false} is VALID [2020-07-29 03:08:50,676 INFO L280 TraceCheckUtils]: 39: Hoare triple {13555#false} assume 1 == ~E_2~0;~E_2~0 := 2; {13555#false} is VALID [2020-07-29 03:08:50,677 INFO L280 TraceCheckUtils]: 40: Hoare triple {13555#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {13555#false} is VALID [2020-07-29 03:08:50,677 INFO L280 TraceCheckUtils]: 41: Hoare triple {13555#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {13555#false} is VALID [2020-07-29 03:08:50,677 INFO L280 TraceCheckUtils]: 42: Hoare triple {13555#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {13555#false} is VALID [2020-07-29 03:08:50,677 INFO L280 TraceCheckUtils]: 43: Hoare triple {13555#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {13555#false} is VALID [2020-07-29 03:08:50,677 INFO L280 TraceCheckUtils]: 44: Hoare triple {13555#false} assume !(0 == start_simulation_~tmp~3); {13555#false} is VALID [2020-07-29 03:08:50,677 INFO L280 TraceCheckUtils]: 45: Hoare triple {13555#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {13555#false} is VALID [2020-07-29 03:08:50,677 INFO L280 TraceCheckUtils]: 46: Hoare triple {13555#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {13555#false} is VALID [2020-07-29 03:08:50,678 INFO L280 TraceCheckUtils]: 47: Hoare triple {13555#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {13555#false} is VALID [2020-07-29 03:08:50,678 INFO L280 TraceCheckUtils]: 48: Hoare triple {13555#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {13555#false} is VALID [2020-07-29 03:08:50,678 INFO L280 TraceCheckUtils]: 49: Hoare triple {13555#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {13555#false} is VALID [2020-07-29 03:08:50,678 INFO L280 TraceCheckUtils]: 50: Hoare triple {13555#false} stop_simulation_#res := stop_simulation_~__retres2~0; {13555#false} is VALID [2020-07-29 03:08:50,678 INFO L280 TraceCheckUtils]: 51: Hoare triple {13555#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {13555#false} is VALID [2020-07-29 03:08:50,678 INFO L280 TraceCheckUtils]: 52: Hoare triple {13555#false} assume !(0 != start_simulation_~tmp___0~1); {13555#false} is VALID [2020-07-29 03:08:50,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:50,680 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261229465] [2020-07-29 03:08:50,680 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:50,680 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:50,681 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217075592] [2020-07-29 03:08:50,681 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:50,681 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:50,681 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-07-29 03:08:50,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-07-29 03:08:50,682 INFO L87 Difference]: Start difference. First operand 676 states and 952 transitions. cyclomatic complexity: 280 Second operand 5 states. [2020-07-29 03:08:51,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:51,734 INFO L93 Difference]: Finished difference Result 1160 states and 1602 transitions. [2020-07-29 03:08:51,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-07-29 03:08:51,735 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2020-07-29 03:08:51,792 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 53 edges. 53 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:51,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1160 states and 1602 transitions. [2020-07-29 03:08:51,875 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1104 [2020-07-29 03:08:51,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1160 states to 1160 states and 1602 transitions. [2020-07-29 03:08:51,940 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1160 [2020-07-29 03:08:51,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1160 [2020-07-29 03:08:51,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1160 states and 1602 transitions. [2020-07-29 03:08:51,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:51,943 INFO L688 BuchiCegarLoop]: Abstraction has 1160 states and 1602 transitions. [2020-07-29 03:08:51,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1160 states and 1602 transitions. [2020-07-29 03:08:51,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1160 to 688. [2020-07-29 03:08:51,955 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:51,956 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1160 states and 1602 transitions. Second operand 688 states. [2020-07-29 03:08:51,956 INFO L74 IsIncluded]: Start isIncluded. First operand 1160 states and 1602 transitions. Second operand 688 states. [2020-07-29 03:08:51,956 INFO L87 Difference]: Start difference. First operand 1160 states and 1602 transitions. Second operand 688 states. [2020-07-29 03:08:52,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:52,001 INFO L93 Difference]: Finished difference Result 1160 states and 1602 transitions. [2020-07-29 03:08:52,001 INFO L276 IsEmpty]: Start isEmpty. Operand 1160 states and 1602 transitions. [2020-07-29 03:08:52,003 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:52,003 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:52,003 INFO L74 IsIncluded]: Start isIncluded. First operand 688 states. Second operand 1160 states and 1602 transitions. [2020-07-29 03:08:52,003 INFO L87 Difference]: Start difference. First operand 688 states. Second operand 1160 states and 1602 transitions. [2020-07-29 03:08:52,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:52,048 INFO L93 Difference]: Finished difference Result 1160 states and 1602 transitions. [2020-07-29 03:08:52,048 INFO L276 IsEmpty]: Start isEmpty. Operand 1160 states and 1602 transitions. [2020-07-29 03:08:52,050 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:52,050 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:52,050 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:52,051 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:52,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 688 states. [2020-07-29 03:08:52,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 964 transitions. [2020-07-29 03:08:52,074 INFO L711 BuchiCegarLoop]: Abstraction has 688 states and 964 transitions. [2020-07-29 03:08:52,074 INFO L591 BuchiCegarLoop]: Abstraction has 688 states and 964 transitions. [2020-07-29 03:08:52,074 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2020-07-29 03:08:52,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 964 transitions. [2020-07-29 03:08:52,077 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 640 [2020-07-29 03:08:52,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:52,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:52,078 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:52,079 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:52,079 INFO L794 eck$LassoCheckResult]: Stem: 14804#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 14740#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14741#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14831#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 14842#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14794#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14795#L231-1 assume !(0 == ~M_E~0); 14767#L334-1 assume !(0 == ~T1_E~0); 14768#L339-1 assume !(0 == ~T2_E~0); 14783#L344-1 assume !(0 == ~E_M~0); 14931#L349-1 assume !(0 == ~E_1~0); 14855#L354-1 assume !(0 == ~E_2~0); 14856#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14890#L156 assume !(1 == ~m_pc~0); 14969#L156-2 is_master_triggered_~__retres1~0 := 0; 14970#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14917#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 14918#L415 assume !(0 != activate_threads_~tmp~1); 14960#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14727#L175 assume !(1 == ~t1_pc~0); 14728#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 14731#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14732#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 14803#L423 assume !(0 != activate_threads_~tmp___0~0); 14844#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14846#L194 assume !(1 == ~t2_pc~0); 14884#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 14885#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14891#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14877#L431 assume !(0 != activate_threads_~tmp___1~0); 14849#L431-2 assume !(1 == ~M_E~0); 14781#L372-1 assume !(1 == ~T1_E~0); 14782#L377-1 assume !(1 == ~T2_E~0); 14930#L382-1 assume !(1 == ~E_M~0); 14850#L387-1 assume !(1 == ~E_1~0); 14851#L392-1 assume !(1 == ~E_2~0); 14887#L543-1 [2020-07-29 03:08:52,079 INFO L796 eck$LassoCheckResult]: Loop: 14887#L543-1 assume !false; 15231#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 15153#L309 assume !false; 15123#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15121#L244 assume !(0 == ~m_st~0); 15119#L248 assume !(0 == ~t1_st~0); 15103#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 15096#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15089#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 15088#L276 assume !(0 != eval_~tmp~0); 15087#L324 start_simulation_~kernel_st~0 := 2; 15086#L214-1 start_simulation_~kernel_st~0 := 3; 15085#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15084#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15083#L339-3 assume !(0 == ~T2_E~0); 15082#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15081#L349-3 assume !(0 == ~E_1~0); 15080#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15079#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15077#L156-12 assume !(1 == ~m_pc~0); 15078#L156-14 is_master_triggered_~__retres1~0 := 0; 15305#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15304#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 15303#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15302#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14845#L175-12 assume !(1 == ~t1_pc~0); 14843#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 14748#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14749#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 14812#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15366#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15365#L194-12 assume 1 == ~t2_pc~0; 15363#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15361#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15359#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15357#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15356#L431-14 assume !(1 == ~M_E~0); 14784#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14785#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15355#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15354#L387-3 assume !(1 == ~E_1~0); 15353#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15352#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15350#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15343#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15339#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 15333#L562 assume !(0 == start_simulation_~tmp~3); 15331#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15328#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15325#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15323#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 15320#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15318#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 15316#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 15313#L575 assume !(0 != start_simulation_~tmp___0~1); 14887#L543-1 [2020-07-29 03:08:52,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:52,079 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 2 times [2020-07-29 03:08:52,080 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:52,080 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337299356] [2020-07-29 03:08:52,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:52,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:52,088 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:52,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:52,095 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:52,102 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:52,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:52,103 INFO L82 PathProgramCache]: Analyzing trace with hash 257205043, now seen corresponding path program 1 times [2020-07-29 03:08:52,103 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:52,103 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992343013] [2020-07-29 03:08:52,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:52,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:52,142 INFO L280 TraceCheckUtils]: 0: Hoare triple {17740#true} assume !false; {17740#true} is VALID [2020-07-29 03:08:52,142 INFO L280 TraceCheckUtils]: 1: Hoare triple {17740#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {17740#true} is VALID [2020-07-29 03:08:52,142 INFO L280 TraceCheckUtils]: 2: Hoare triple {17740#true} assume !false; {17740#true} is VALID [2020-07-29 03:08:52,143 INFO L280 TraceCheckUtils]: 3: Hoare triple {17740#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {17740#true} is VALID [2020-07-29 03:08:52,143 INFO L280 TraceCheckUtils]: 4: Hoare triple {17740#true} assume !(0 == ~m_st~0); {17740#true} is VALID [2020-07-29 03:08:52,143 INFO L280 TraceCheckUtils]: 5: Hoare triple {17740#true} assume !(0 == ~t1_st~0); {17740#true} is VALID [2020-07-29 03:08:52,143 INFO L280 TraceCheckUtils]: 6: Hoare triple {17740#true} assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; {17740#true} is VALID [2020-07-29 03:08:52,144 INFO L280 TraceCheckUtils]: 7: Hoare triple {17740#true} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {17740#true} is VALID [2020-07-29 03:08:52,144 INFO L280 TraceCheckUtils]: 8: Hoare triple {17740#true} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {17740#true} is VALID [2020-07-29 03:08:52,144 INFO L280 TraceCheckUtils]: 9: Hoare triple {17740#true} assume !(0 != eval_~tmp~0); {17740#true} is VALID [2020-07-29 03:08:52,144 INFO L280 TraceCheckUtils]: 10: Hoare triple {17740#true} start_simulation_~kernel_st~0 := 2; {17740#true} is VALID [2020-07-29 03:08:52,145 INFO L280 TraceCheckUtils]: 11: Hoare triple {17740#true} start_simulation_~kernel_st~0 := 3; {17740#true} is VALID [2020-07-29 03:08:52,145 INFO L280 TraceCheckUtils]: 12: Hoare triple {17740#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,146 INFO L280 TraceCheckUtils]: 13: Hoare triple {17742#(= ~M_E~0 1)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,147 INFO L280 TraceCheckUtils]: 14: Hoare triple {17742#(= ~M_E~0 1)} assume !(0 == ~T2_E~0); {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,148 INFO L280 TraceCheckUtils]: 15: Hoare triple {17742#(= ~M_E~0 1)} assume 0 == ~E_M~0;~E_M~0 := 1; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,148 INFO L280 TraceCheckUtils]: 16: Hoare triple {17742#(= ~M_E~0 1)} assume !(0 == ~E_1~0); {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,149 INFO L280 TraceCheckUtils]: 17: Hoare triple {17742#(= ~M_E~0 1)} assume 0 == ~E_2~0;~E_2~0 := 1; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,150 INFO L280 TraceCheckUtils]: 18: Hoare triple {17742#(= ~M_E~0 1)} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,150 INFO L280 TraceCheckUtils]: 19: Hoare triple {17742#(= ~M_E~0 1)} assume !(1 == ~m_pc~0); {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,151 INFO L280 TraceCheckUtils]: 20: Hoare triple {17742#(= ~M_E~0 1)} is_master_triggered_~__retres1~0 := 0; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,152 INFO L280 TraceCheckUtils]: 21: Hoare triple {17742#(= ~M_E~0 1)} is_master_triggered_#res := is_master_triggered_~__retres1~0; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,152 INFO L280 TraceCheckUtils]: 22: Hoare triple {17742#(= ~M_E~0 1)} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,153 INFO L280 TraceCheckUtils]: 23: Hoare triple {17742#(= ~M_E~0 1)} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,153 INFO L280 TraceCheckUtils]: 24: Hoare triple {17742#(= ~M_E~0 1)} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,154 INFO L280 TraceCheckUtils]: 25: Hoare triple {17742#(= ~M_E~0 1)} assume !(1 == ~t1_pc~0); {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,154 INFO L280 TraceCheckUtils]: 26: Hoare triple {17742#(= ~M_E~0 1)} is_transmit1_triggered_~__retres1~1 := 0; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,155 INFO L280 TraceCheckUtils]: 27: Hoare triple {17742#(= ~M_E~0 1)} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,156 INFO L280 TraceCheckUtils]: 28: Hoare triple {17742#(= ~M_E~0 1)} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,156 INFO L280 TraceCheckUtils]: 29: Hoare triple {17742#(= ~M_E~0 1)} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,157 INFO L280 TraceCheckUtils]: 30: Hoare triple {17742#(= ~M_E~0 1)} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,157 INFO L280 TraceCheckUtils]: 31: Hoare triple {17742#(= ~M_E~0 1)} assume 1 == ~t2_pc~0; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,158 INFO L280 TraceCheckUtils]: 32: Hoare triple {17742#(= ~M_E~0 1)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,159 INFO L280 TraceCheckUtils]: 33: Hoare triple {17742#(= ~M_E~0 1)} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,159 INFO L280 TraceCheckUtils]: 34: Hoare triple {17742#(= ~M_E~0 1)} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,160 INFO L280 TraceCheckUtils]: 35: Hoare triple {17742#(= ~M_E~0 1)} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {17742#(= ~M_E~0 1)} is VALID [2020-07-29 03:08:52,161 INFO L280 TraceCheckUtils]: 36: Hoare triple {17742#(= ~M_E~0 1)} assume !(1 == ~M_E~0); {17741#false} is VALID [2020-07-29 03:08:52,161 INFO L280 TraceCheckUtils]: 37: Hoare triple {17741#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17741#false} is VALID [2020-07-29 03:08:52,161 INFO L280 TraceCheckUtils]: 38: Hoare triple {17741#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {17741#false} is VALID [2020-07-29 03:08:52,162 INFO L280 TraceCheckUtils]: 39: Hoare triple {17741#false} assume 1 == ~E_M~0;~E_M~0 := 2; {17741#false} is VALID [2020-07-29 03:08:52,162 INFO L280 TraceCheckUtils]: 40: Hoare triple {17741#false} assume !(1 == ~E_1~0); {17741#false} is VALID [2020-07-29 03:08:52,162 INFO L280 TraceCheckUtils]: 41: Hoare triple {17741#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17741#false} is VALID [2020-07-29 03:08:52,162 INFO L280 TraceCheckUtils]: 42: Hoare triple {17741#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {17741#false} is VALID [2020-07-29 03:08:52,163 INFO L280 TraceCheckUtils]: 43: Hoare triple {17741#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {17741#false} is VALID [2020-07-29 03:08:52,163 INFO L280 TraceCheckUtils]: 44: Hoare triple {17741#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {17741#false} is VALID [2020-07-29 03:08:52,163 INFO L280 TraceCheckUtils]: 45: Hoare triple {17741#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {17741#false} is VALID [2020-07-29 03:08:52,163 INFO L280 TraceCheckUtils]: 46: Hoare triple {17741#false} assume !(0 == start_simulation_~tmp~3); {17741#false} is VALID [2020-07-29 03:08:52,163 INFO L280 TraceCheckUtils]: 47: Hoare triple {17741#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {17741#false} is VALID [2020-07-29 03:08:52,164 INFO L280 TraceCheckUtils]: 48: Hoare triple {17741#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {17741#false} is VALID [2020-07-29 03:08:52,164 INFO L280 TraceCheckUtils]: 49: Hoare triple {17741#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {17741#false} is VALID [2020-07-29 03:08:52,164 INFO L280 TraceCheckUtils]: 50: Hoare triple {17741#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {17741#false} is VALID [2020-07-29 03:08:52,164 INFO L280 TraceCheckUtils]: 51: Hoare triple {17741#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {17741#false} is VALID [2020-07-29 03:08:52,165 INFO L280 TraceCheckUtils]: 52: Hoare triple {17741#false} stop_simulation_#res := stop_simulation_~__retres2~0; {17741#false} is VALID [2020-07-29 03:08:52,165 INFO L280 TraceCheckUtils]: 53: Hoare triple {17741#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {17741#false} is VALID [2020-07-29 03:08:52,165 INFO L280 TraceCheckUtils]: 54: Hoare triple {17741#false} assume !(0 != start_simulation_~tmp___0~1); {17741#false} is VALID [2020-07-29 03:08:52,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:52,171 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992343013] [2020-07-29 03:08:52,171 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:52,171 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-07-29 03:08:52,171 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237881897] [2020-07-29 03:08:52,172 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:52,172 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:52,172 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:52,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:52,173 INFO L87 Difference]: Start difference. First operand 688 states and 964 transitions. cyclomatic complexity: 280 Second operand 3 states. [2020-07-29 03:08:52,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:52,612 INFO L93 Difference]: Finished difference Result 832 states and 1155 transitions. [2020-07-29 03:08:52,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:52,613 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:52,683 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:52,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 832 states and 1155 transitions. [2020-07-29 03:08:52,720 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 756 [2020-07-29 03:08:52,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 832 states to 832 states and 1155 transitions. [2020-07-29 03:08:52,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 832 [2020-07-29 03:08:52,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 832 [2020-07-29 03:08:52,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 832 states and 1155 transitions. [2020-07-29 03:08:52,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:52,751 INFO L688 BuchiCegarLoop]: Abstraction has 832 states and 1155 transitions. [2020-07-29 03:08:52,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 832 states and 1155 transitions. [2020-07-29 03:08:52,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 832 to 832. [2020-07-29 03:08:52,763 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:52,763 INFO L82 GeneralOperation]: Start isEquivalent. First operand 832 states and 1155 transitions. Second operand 832 states. [2020-07-29 03:08:52,764 INFO L74 IsIncluded]: Start isIncluded. First operand 832 states and 1155 transitions. Second operand 832 states. [2020-07-29 03:08:52,764 INFO L87 Difference]: Start difference. First operand 832 states and 1155 transitions. Second operand 832 states. [2020-07-29 03:08:52,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:52,799 INFO L93 Difference]: Finished difference Result 832 states and 1155 transitions. [2020-07-29 03:08:52,799 INFO L276 IsEmpty]: Start isEmpty. Operand 832 states and 1155 transitions. [2020-07-29 03:08:52,800 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:52,800 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:52,801 INFO L74 IsIncluded]: Start isIncluded. First operand 832 states. Second operand 832 states and 1155 transitions. [2020-07-29 03:08:52,801 INFO L87 Difference]: Start difference. First operand 832 states. Second operand 832 states and 1155 transitions. [2020-07-29 03:08:52,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:52,836 INFO L93 Difference]: Finished difference Result 832 states and 1155 transitions. [2020-07-29 03:08:52,836 INFO L276 IsEmpty]: Start isEmpty. Operand 832 states and 1155 transitions. [2020-07-29 03:08:52,837 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:52,837 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:52,838 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:52,838 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:52,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 832 states. [2020-07-29 03:08:52,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 832 states to 832 states and 1155 transitions. [2020-07-29 03:08:52,879 INFO L711 BuchiCegarLoop]: Abstraction has 832 states and 1155 transitions. [2020-07-29 03:08:52,879 INFO L591 BuchiCegarLoop]: Abstraction has 832 states and 1155 transitions. [2020-07-29 03:08:52,879 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2020-07-29 03:08:52,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 832 states and 1155 transitions. [2020-07-29 03:08:52,885 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 756 [2020-07-29 03:08:52,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:52,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:52,886 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:52,886 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:52,886 INFO L794 eck$LassoCheckResult]: Stem: 18655#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 18588#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 18589#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18681#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 18695#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18644#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18645#L231-1 assume 0 == ~M_E~0;~M_E~0 := 1; 18616#L334-1 assume !(0 == ~T1_E~0); 18617#L339-1 assume !(0 == ~T2_E~0); 18633#L344-1 assume !(0 == ~E_M~0); 18787#L349-1 assume !(0 == ~E_1~0); 18859#L354-1 assume !(0 == ~E_2~0); 18858#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18857#L156 assume !(1 == ~m_pc~0); 18856#L156-2 is_master_triggered_~__retres1~0 := 0; 18855#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18773#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 18774#L415 assume !(0 != activate_threads_~tmp~1); 18835#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18853#L175 assume !(1 == ~t1_pc~0); 18606#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 18579#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18580#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 18653#L423 assume !(0 != activate_threads_~tmp___0~0); 18697#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18849#L194 assume !(1 == ~t2_pc~0); 18848#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 18864#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18863#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 18843#L431 assume !(0 != activate_threads_~tmp___1~0); 18703#L431-2 assume 1 == ~M_E~0;~M_E~0 := 2; 18631#L372-1 assume !(1 == ~T1_E~0); 18632#L377-1 assume !(1 == ~T2_E~0); 18786#L382-1 assume !(1 == ~E_M~0); 18704#L387-1 assume !(1 == ~E_1~0); 18705#L392-1 assume !(1 == ~E_2~0); 18744#L543-1 [2020-07-29 03:08:52,887 INFO L796 eck$LassoCheckResult]: Loop: 18744#L543-1 assume !false; 19130#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 19127#L309 assume !false; 19123#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 19120#L244 assume !(0 == ~m_st~0); 19117#L248 assume !(0 == ~t1_st~0); 19114#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 19111#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18903#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 18904#L276 assume !(0 != eval_~tmp~0); 19100#L324 start_simulation_~kernel_st~0 := 2; 19099#L214-1 start_simulation_~kernel_st~0 := 3; 19097#L334-2 assume !(0 == ~M_E~0); 19096#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19095#L339-3 assume !(0 == ~T2_E~0); 19094#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19092#L349-3 assume !(0 == ~E_1~0); 19090#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19088#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19086#L156-12 assume !(1 == ~m_pc~0); 19083#L156-14 is_master_triggered_~__retres1~0 := 0; 19081#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19079#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 19077#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19075#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19073#L175-12 assume !(1 == ~t1_pc~0); 19071#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 19069#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19067#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 19065#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19063#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19061#L194-12 assume 1 == ~t2_pc~0; 19058#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 19051#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19044#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 19024#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 19019#L431-14 assume !(1 == ~M_E~0); 19016#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19013#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19010#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19006#L387-3 assume !(1 == ~E_1~0); 19003#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19000#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 18975#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 18905#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18906#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 18885#L562 assume !(0 == start_simulation_~tmp~3); 18886#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 19178#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 19173#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 19169#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 19165#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 19161#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 19157#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 19141#L575 assume !(0 != start_simulation_~tmp___0~1); 18744#L543-1 [2020-07-29 03:08:52,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:52,887 INFO L82 PathProgramCache]: Analyzing trace with hash -2054220888, now seen corresponding path program 1 times [2020-07-29 03:08:52,887 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:52,888 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523074177] [2020-07-29 03:08:52,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:52,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:52,914 INFO L280 TraceCheckUtils]: 0: Hoare triple {21074#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {21076#(<= 2 ~M_E~0)} is VALID [2020-07-29 03:08:52,915 INFO L280 TraceCheckUtils]: 1: Hoare triple {21076#(<= 2 ~M_E~0)} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {21076#(<= 2 ~M_E~0)} is VALID [2020-07-29 03:08:52,929 INFO L280 TraceCheckUtils]: 2: Hoare triple {21076#(<= 2 ~M_E~0)} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {21076#(<= 2 ~M_E~0)} is VALID [2020-07-29 03:08:52,930 INFO L280 TraceCheckUtils]: 3: Hoare triple {21076#(<= 2 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {21076#(<= 2 ~M_E~0)} is VALID [2020-07-29 03:08:52,930 INFO L280 TraceCheckUtils]: 4: Hoare triple {21076#(<= 2 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {21076#(<= 2 ~M_E~0)} is VALID [2020-07-29 03:08:52,931 INFO L280 TraceCheckUtils]: 5: Hoare triple {21076#(<= 2 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {21076#(<= 2 ~M_E~0)} is VALID [2020-07-29 03:08:52,932 INFO L280 TraceCheckUtils]: 6: Hoare triple {21076#(<= 2 ~M_E~0)} assume 0 == ~M_E~0;~M_E~0 := 1; {21075#false} is VALID [2020-07-29 03:08:52,932 INFO L280 TraceCheckUtils]: 7: Hoare triple {21075#false} assume !(0 == ~T1_E~0); {21075#false} is VALID [2020-07-29 03:08:52,933 INFO L280 TraceCheckUtils]: 8: Hoare triple {21075#false} assume !(0 == ~T2_E~0); {21075#false} is VALID [2020-07-29 03:08:52,933 INFO L280 TraceCheckUtils]: 9: Hoare triple {21075#false} assume !(0 == ~E_M~0); {21075#false} is VALID [2020-07-29 03:08:52,933 INFO L280 TraceCheckUtils]: 10: Hoare triple {21075#false} assume !(0 == ~E_1~0); {21075#false} is VALID [2020-07-29 03:08:52,933 INFO L280 TraceCheckUtils]: 11: Hoare triple {21075#false} assume !(0 == ~E_2~0); {21075#false} is VALID [2020-07-29 03:08:52,933 INFO L280 TraceCheckUtils]: 12: Hoare triple {21075#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {21075#false} is VALID [2020-07-29 03:08:52,934 INFO L280 TraceCheckUtils]: 13: Hoare triple {21075#false} assume !(1 == ~m_pc~0); {21075#false} is VALID [2020-07-29 03:08:52,934 INFO L280 TraceCheckUtils]: 14: Hoare triple {21075#false} is_master_triggered_~__retres1~0 := 0; {21075#false} is VALID [2020-07-29 03:08:52,934 INFO L280 TraceCheckUtils]: 15: Hoare triple {21075#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {21075#false} is VALID [2020-07-29 03:08:52,934 INFO L280 TraceCheckUtils]: 16: Hoare triple {21075#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {21075#false} is VALID [2020-07-29 03:08:52,934 INFO L280 TraceCheckUtils]: 17: Hoare triple {21075#false} assume !(0 != activate_threads_~tmp~1); {21075#false} is VALID [2020-07-29 03:08:52,935 INFO L280 TraceCheckUtils]: 18: Hoare triple {21075#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {21075#false} is VALID [2020-07-29 03:08:52,935 INFO L280 TraceCheckUtils]: 19: Hoare triple {21075#false} assume !(1 == ~t1_pc~0); {21075#false} is VALID [2020-07-29 03:08:52,935 INFO L280 TraceCheckUtils]: 20: Hoare triple {21075#false} is_transmit1_triggered_~__retres1~1 := 0; {21075#false} is VALID [2020-07-29 03:08:52,936 INFO L280 TraceCheckUtils]: 21: Hoare triple {21075#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {21075#false} is VALID [2020-07-29 03:08:52,936 INFO L280 TraceCheckUtils]: 22: Hoare triple {21075#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {21075#false} is VALID [2020-07-29 03:08:52,936 INFO L280 TraceCheckUtils]: 23: Hoare triple {21075#false} assume !(0 != activate_threads_~tmp___0~0); {21075#false} is VALID [2020-07-29 03:08:52,936 INFO L280 TraceCheckUtils]: 24: Hoare triple {21075#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {21075#false} is VALID [2020-07-29 03:08:52,937 INFO L280 TraceCheckUtils]: 25: Hoare triple {21075#false} assume !(1 == ~t2_pc~0); {21075#false} is VALID [2020-07-29 03:08:52,937 INFO L280 TraceCheckUtils]: 26: Hoare triple {21075#false} is_transmit2_triggered_~__retres1~2 := 0; {21075#false} is VALID [2020-07-29 03:08:52,937 INFO L280 TraceCheckUtils]: 27: Hoare triple {21075#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {21075#false} is VALID [2020-07-29 03:08:52,937 INFO L280 TraceCheckUtils]: 28: Hoare triple {21075#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {21075#false} is VALID [2020-07-29 03:08:52,938 INFO L280 TraceCheckUtils]: 29: Hoare triple {21075#false} assume !(0 != activate_threads_~tmp___1~0); {21075#false} is VALID [2020-07-29 03:08:52,938 INFO L280 TraceCheckUtils]: 30: Hoare triple {21075#false} assume 1 == ~M_E~0;~M_E~0 := 2; {21075#false} is VALID [2020-07-29 03:08:52,938 INFO L280 TraceCheckUtils]: 31: Hoare triple {21075#false} assume !(1 == ~T1_E~0); {21075#false} is VALID [2020-07-29 03:08:52,938 INFO L280 TraceCheckUtils]: 32: Hoare triple {21075#false} assume !(1 == ~T2_E~0); {21075#false} is VALID [2020-07-29 03:08:52,939 INFO L280 TraceCheckUtils]: 33: Hoare triple {21075#false} assume !(1 == ~E_M~0); {21075#false} is VALID [2020-07-29 03:08:52,939 INFO L280 TraceCheckUtils]: 34: Hoare triple {21075#false} assume !(1 == ~E_1~0); {21075#false} is VALID [2020-07-29 03:08:52,939 INFO L280 TraceCheckUtils]: 35: Hoare triple {21075#false} assume !(1 == ~E_2~0); {21075#false} is VALID [2020-07-29 03:08:52,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:52,940 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523074177] [2020-07-29 03:08:52,941 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:52,941 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-07-29 03:08:52,941 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838332729] [2020-07-29 03:08:52,942 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-07-29 03:08:52,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:52,942 INFO L82 PathProgramCache]: Analyzing trace with hash -640188235, now seen corresponding path program 1 times [2020-07-29 03:08:52,942 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:52,942 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811432407] [2020-07-29 03:08:52,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:52,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:53,024 INFO L280 TraceCheckUtils]: 0: Hoare triple {21077#true} assume !false; {21077#true} is VALID [2020-07-29 03:08:53,024 INFO L280 TraceCheckUtils]: 1: Hoare triple {21077#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {21077#true} is VALID [2020-07-29 03:08:53,024 INFO L280 TraceCheckUtils]: 2: Hoare triple {21077#true} assume !false; {21077#true} is VALID [2020-07-29 03:08:53,024 INFO L280 TraceCheckUtils]: 3: Hoare triple {21077#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {21077#true} is VALID [2020-07-29 03:08:53,024 INFO L280 TraceCheckUtils]: 4: Hoare triple {21077#true} assume !(0 == ~m_st~0); {21077#true} is VALID [2020-07-29 03:08:53,025 INFO L280 TraceCheckUtils]: 5: Hoare triple {21077#true} assume !(0 == ~t1_st~0); {21077#true} is VALID [2020-07-29 03:08:53,025 INFO L280 TraceCheckUtils]: 6: Hoare triple {21077#true} assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; {21077#true} is VALID [2020-07-29 03:08:53,025 INFO L280 TraceCheckUtils]: 7: Hoare triple {21077#true} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {21077#true} is VALID [2020-07-29 03:08:53,025 INFO L280 TraceCheckUtils]: 8: Hoare triple {21077#true} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {21077#true} is VALID [2020-07-29 03:08:53,025 INFO L280 TraceCheckUtils]: 9: Hoare triple {21077#true} assume !(0 != eval_~tmp~0); {21077#true} is VALID [2020-07-29 03:08:53,025 INFO L280 TraceCheckUtils]: 10: Hoare triple {21077#true} start_simulation_~kernel_st~0 := 2; {21077#true} is VALID [2020-07-29 03:08:53,026 INFO L280 TraceCheckUtils]: 11: Hoare triple {21077#true} start_simulation_~kernel_st~0 := 3; {21077#true} is VALID [2020-07-29 03:08:53,026 INFO L280 TraceCheckUtils]: 12: Hoare triple {21077#true} assume !(0 == ~M_E~0); {21077#true} is VALID [2020-07-29 03:08:53,026 INFO L280 TraceCheckUtils]: 13: Hoare triple {21077#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {21077#true} is VALID [2020-07-29 03:08:53,026 INFO L280 TraceCheckUtils]: 14: Hoare triple {21077#true} assume !(0 == ~T2_E~0); {21077#true} is VALID [2020-07-29 03:08:53,026 INFO L280 TraceCheckUtils]: 15: Hoare triple {21077#true} assume 0 == ~E_M~0;~E_M~0 := 1; {21077#true} is VALID [2020-07-29 03:08:53,027 INFO L280 TraceCheckUtils]: 16: Hoare triple {21077#true} assume !(0 == ~E_1~0); {21077#true} is VALID [2020-07-29 03:08:53,027 INFO L280 TraceCheckUtils]: 17: Hoare triple {21077#true} assume 0 == ~E_2~0;~E_2~0 := 1; {21077#true} is VALID [2020-07-29 03:08:53,027 INFO L280 TraceCheckUtils]: 18: Hoare triple {21077#true} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {21077#true} is VALID [2020-07-29 03:08:53,027 INFO L280 TraceCheckUtils]: 19: Hoare triple {21077#true} assume !(1 == ~m_pc~0); {21077#true} is VALID [2020-07-29 03:08:53,028 INFO L280 TraceCheckUtils]: 20: Hoare triple {21077#true} is_master_triggered_~__retres1~0 := 0; {21079#(and (<= ULTIMATE.start_is_master_triggered_~__retres1~0 0) (<= 0 ULTIMATE.start_is_master_triggered_~__retres1~0))} is VALID [2020-07-29 03:08:53,028 INFO L280 TraceCheckUtils]: 21: Hoare triple {21079#(and (<= ULTIMATE.start_is_master_triggered_~__retres1~0 0) (<= 0 ULTIMATE.start_is_master_triggered_~__retres1~0))} is_master_triggered_#res := is_master_triggered_~__retres1~0; {21080#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res|) (<= |ULTIMATE.start_is_master_triggered_#res| 0))} is VALID [2020-07-29 03:08:53,029 INFO L280 TraceCheckUtils]: 22: Hoare triple {21080#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res|) (<= |ULTIMATE.start_is_master_triggered_#res| 0))} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {21081#(and (<= 0 ULTIMATE.start_activate_threads_~tmp~1) (<= ULTIMATE.start_activate_threads_~tmp~1 0))} is VALID [2020-07-29 03:08:53,030 INFO L280 TraceCheckUtils]: 23: Hoare triple {21081#(and (<= 0 ULTIMATE.start_activate_threads_~tmp~1) (<= ULTIMATE.start_activate_threads_~tmp~1 0))} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {21078#false} is VALID [2020-07-29 03:08:53,030 INFO L280 TraceCheckUtils]: 24: Hoare triple {21078#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {21078#false} is VALID [2020-07-29 03:08:53,030 INFO L280 TraceCheckUtils]: 25: Hoare triple {21078#false} assume !(1 == ~t1_pc~0); {21078#false} is VALID [2020-07-29 03:08:53,030 INFO L280 TraceCheckUtils]: 26: Hoare triple {21078#false} is_transmit1_triggered_~__retres1~1 := 0; {21078#false} is VALID [2020-07-29 03:08:53,030 INFO L280 TraceCheckUtils]: 27: Hoare triple {21078#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {21078#false} is VALID [2020-07-29 03:08:53,030 INFO L280 TraceCheckUtils]: 28: Hoare triple {21078#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {21078#false} is VALID [2020-07-29 03:08:53,031 INFO L280 TraceCheckUtils]: 29: Hoare triple {21078#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {21078#false} is VALID [2020-07-29 03:08:53,031 INFO L280 TraceCheckUtils]: 30: Hoare triple {21078#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {21078#false} is VALID [2020-07-29 03:08:53,031 INFO L280 TraceCheckUtils]: 31: Hoare triple {21078#false} assume 1 == ~t2_pc~0; {21078#false} is VALID [2020-07-29 03:08:53,031 INFO L280 TraceCheckUtils]: 32: Hoare triple {21078#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; {21078#false} is VALID [2020-07-29 03:08:53,031 INFO L280 TraceCheckUtils]: 33: Hoare triple {21078#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {21078#false} is VALID [2020-07-29 03:08:53,032 INFO L280 TraceCheckUtils]: 34: Hoare triple {21078#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {21078#false} is VALID [2020-07-29 03:08:53,032 INFO L280 TraceCheckUtils]: 35: Hoare triple {21078#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {21078#false} is VALID [2020-07-29 03:08:53,032 INFO L280 TraceCheckUtils]: 36: Hoare triple {21078#false} assume !(1 == ~M_E~0); {21078#false} is VALID [2020-07-29 03:08:53,032 INFO L280 TraceCheckUtils]: 37: Hoare triple {21078#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {21078#false} is VALID [2020-07-29 03:08:53,032 INFO L280 TraceCheckUtils]: 38: Hoare triple {21078#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {21078#false} is VALID [2020-07-29 03:08:53,032 INFO L280 TraceCheckUtils]: 39: Hoare triple {21078#false} assume 1 == ~E_M~0;~E_M~0 := 2; {21078#false} is VALID [2020-07-29 03:08:53,033 INFO L280 TraceCheckUtils]: 40: Hoare triple {21078#false} assume !(1 == ~E_1~0); {21078#false} is VALID [2020-07-29 03:08:53,033 INFO L280 TraceCheckUtils]: 41: Hoare triple {21078#false} assume 1 == ~E_2~0;~E_2~0 := 2; {21078#false} is VALID [2020-07-29 03:08:53,033 INFO L280 TraceCheckUtils]: 42: Hoare triple {21078#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {21078#false} is VALID [2020-07-29 03:08:53,033 INFO L280 TraceCheckUtils]: 43: Hoare triple {21078#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {21078#false} is VALID [2020-07-29 03:08:53,033 INFO L280 TraceCheckUtils]: 44: Hoare triple {21078#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {21078#false} is VALID [2020-07-29 03:08:53,033 INFO L280 TraceCheckUtils]: 45: Hoare triple {21078#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {21078#false} is VALID [2020-07-29 03:08:53,034 INFO L280 TraceCheckUtils]: 46: Hoare triple {21078#false} assume !(0 == start_simulation_~tmp~3); {21078#false} is VALID [2020-07-29 03:08:53,034 INFO L280 TraceCheckUtils]: 47: Hoare triple {21078#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {21078#false} is VALID [2020-07-29 03:08:53,034 INFO L280 TraceCheckUtils]: 48: Hoare triple {21078#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {21078#false} is VALID [2020-07-29 03:08:53,034 INFO L280 TraceCheckUtils]: 49: Hoare triple {21078#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {21078#false} is VALID [2020-07-29 03:08:53,034 INFO L280 TraceCheckUtils]: 50: Hoare triple {21078#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {21078#false} is VALID [2020-07-29 03:08:53,035 INFO L280 TraceCheckUtils]: 51: Hoare triple {21078#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {21078#false} is VALID [2020-07-29 03:08:53,035 INFO L280 TraceCheckUtils]: 52: Hoare triple {21078#false} stop_simulation_#res := stop_simulation_~__retres2~0; {21078#false} is VALID [2020-07-29 03:08:53,035 INFO L280 TraceCheckUtils]: 53: Hoare triple {21078#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {21078#false} is VALID [2020-07-29 03:08:53,035 INFO L280 TraceCheckUtils]: 54: Hoare triple {21078#false} assume !(0 != start_simulation_~tmp___0~1); {21078#false} is VALID [2020-07-29 03:08:53,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:53,037 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1811432407] [2020-07-29 03:08:53,038 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:53,038 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:53,038 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080129295] [2020-07-29 03:08:53,038 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:53,038 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:53,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:53,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:53,039 INFO L87 Difference]: Start difference. First operand 832 states and 1155 transitions. cyclomatic complexity: 327 Second operand 3 states. [2020-07-29 03:08:53,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:53,304 INFO L93 Difference]: Finished difference Result 688 states and 950 transitions. [2020-07-29 03:08:53,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:53,305 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:53,350 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:53,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 950 transitions. [2020-07-29 03:08:53,396 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 640 [2020-07-29 03:08:53,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 950 transitions. [2020-07-29 03:08:53,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2020-07-29 03:08:53,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2020-07-29 03:08:53,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 950 transitions. [2020-07-29 03:08:53,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:53,438 INFO L688 BuchiCegarLoop]: Abstraction has 688 states and 950 transitions. [2020-07-29 03:08:53,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 950 transitions. [2020-07-29 03:08:53,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2020-07-29 03:08:53,452 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:53,452 INFO L82 GeneralOperation]: Start isEquivalent. First operand 688 states and 950 transitions. Second operand 688 states. [2020-07-29 03:08:53,452 INFO L74 IsIncluded]: Start isIncluded. First operand 688 states and 950 transitions. Second operand 688 states. [2020-07-29 03:08:53,452 INFO L87 Difference]: Start difference. First operand 688 states and 950 transitions. Second operand 688 states. [2020-07-29 03:08:53,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:53,488 INFO L93 Difference]: Finished difference Result 688 states and 950 transitions. [2020-07-29 03:08:53,489 INFO L276 IsEmpty]: Start isEmpty. Operand 688 states and 950 transitions. [2020-07-29 03:08:53,490 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:53,490 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:53,490 INFO L74 IsIncluded]: Start isIncluded. First operand 688 states. Second operand 688 states and 950 transitions. [2020-07-29 03:08:53,490 INFO L87 Difference]: Start difference. First operand 688 states. Second operand 688 states and 950 transitions. [2020-07-29 03:08:53,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:53,519 INFO L93 Difference]: Finished difference Result 688 states and 950 transitions. [2020-07-29 03:08:53,519 INFO L276 IsEmpty]: Start isEmpty. Operand 688 states and 950 transitions. [2020-07-29 03:08:53,520 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:53,520 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:53,520 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:53,520 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:53,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 688 states. [2020-07-29 03:08:53,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 950 transitions. [2020-07-29 03:08:53,550 INFO L711 BuchiCegarLoop]: Abstraction has 688 states and 950 transitions. [2020-07-29 03:08:53,550 INFO L591 BuchiCegarLoop]: Abstraction has 688 states and 950 transitions. [2020-07-29 03:08:53,550 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2020-07-29 03:08:53,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 950 transitions. [2020-07-29 03:08:53,553 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 640 [2020-07-29 03:08:53,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:53,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:53,556 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:53,556 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:53,556 INFO L794 eck$LassoCheckResult]: Stem: 21847#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21783#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21784#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21872#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 21890#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21838#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21839#L231-1 assume !(0 == ~M_E~0); 21811#L334-1 assume !(0 == ~T1_E~0); 21812#L339-1 assume !(0 == ~T2_E~0); 21827#L344-1 assume !(0 == ~E_M~0); 21981#L349-1 assume !(0 == ~E_1~0); 21904#L354-1 assume !(0 == ~E_2~0); 21905#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21940#L156 assume !(1 == ~m_pc~0); 22022#L156-2 is_master_triggered_~__retres1~0 := 0; 22023#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21967#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 21968#L415 assume !(0 != activate_threads_~tmp~1); 22013#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21770#L175 assume !(1 == ~t1_pc~0); 21771#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 21774#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21775#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 21846#L423 assume !(0 != activate_threads_~tmp___0~0); 21892#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21894#L194 assume !(1 == ~t2_pc~0); 21934#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 21935#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21941#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 21927#L431 assume !(0 != activate_threads_~tmp___1~0); 21897#L431-2 assume !(1 == ~M_E~0); 21825#L372-1 assume !(1 == ~T1_E~0); 21826#L377-1 assume !(1 == ~T2_E~0); 21980#L382-1 assume !(1 == ~E_M~0); 21898#L387-1 assume !(1 == ~E_1~0); 21899#L392-1 assume !(1 == ~E_2~0); 21937#L543-1 [2020-07-29 03:08:53,556 INFO L796 eck$LassoCheckResult]: Loop: 21937#L543-1 assume !false; 22293#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 22288#L309 assume !false; 22284#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22277#L244 assume !(0 == ~m_st~0); 22278#L248 assume !(0 == ~t1_st~0); 22279#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 22280#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 21819#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 21820#L276 assume !(0 != eval_~tmp~0); 22261#L324 start_simulation_~kernel_st~0 := 2; 22258#L214-1 start_simulation_~kernel_st~0 := 3; 22255#L334-2 assume !(0 == ~M_E~0); 22252#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22249#L339-3 assume !(0 == ~T2_E~0); 22248#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22247#L349-3 assume !(0 == ~E_1~0); 22246#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21928#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21929#L156-12 assume !(1 == ~m_pc~0); 21996#L156-14 is_master_triggered_~__retres1~0 := 0; 22318#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22316#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22314#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22312#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22310#L175-12 assume !(1 == ~t1_pc~0); 22309#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 22307#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22306#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22305#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22303#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22301#L194-12 assume 1 == ~t2_pc~0; 22298#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 22291#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22286#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22282#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22276#L431-14 assume !(1 == ~M_E~0); 22273#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22270#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22019#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21912#L387-3 assume !(1 == ~E_1~0); 21913#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21942#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 21947#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 21777#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 21817#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 21818#L562 assume !(0 == start_simulation_~tmp~3); 21948#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22322#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22320#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22319#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 22317#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22315#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 22313#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 22311#L575 assume !(0 != start_simulation_~tmp___0~1); 21937#L543-1 [2020-07-29 03:08:53,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:53,557 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 3 times [2020-07-29 03:08:53,557 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:53,557 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791586050] [2020-07-29 03:08:53,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:53,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:53,566 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:53,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:53,571 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:53,587 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:53,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:53,589 INFO L82 PathProgramCache]: Analyzing trace with hash -640188235, now seen corresponding path program 2 times [2020-07-29 03:08:53,589 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:53,589 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813414106] [2020-07-29 03:08:53,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:53,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:53,678 INFO L280 TraceCheckUtils]: 0: Hoare triple {23839#true} assume !false; {23839#true} is VALID [2020-07-29 03:08:53,678 INFO L280 TraceCheckUtils]: 1: Hoare triple {23839#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {23839#true} is VALID [2020-07-29 03:08:53,678 INFO L280 TraceCheckUtils]: 2: Hoare triple {23839#true} assume !false; {23839#true} is VALID [2020-07-29 03:08:53,679 INFO L280 TraceCheckUtils]: 3: Hoare triple {23839#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {23839#true} is VALID [2020-07-29 03:08:53,679 INFO L280 TraceCheckUtils]: 4: Hoare triple {23839#true} assume !(0 == ~m_st~0); {23839#true} is VALID [2020-07-29 03:08:53,679 INFO L280 TraceCheckUtils]: 5: Hoare triple {23839#true} assume !(0 == ~t1_st~0); {23839#true} is VALID [2020-07-29 03:08:53,679 INFO L280 TraceCheckUtils]: 6: Hoare triple {23839#true} assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; {23839#true} is VALID [2020-07-29 03:08:53,679 INFO L280 TraceCheckUtils]: 7: Hoare triple {23839#true} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {23839#true} is VALID [2020-07-29 03:08:53,680 INFO L280 TraceCheckUtils]: 8: Hoare triple {23839#true} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {23839#true} is VALID [2020-07-29 03:08:53,680 INFO L280 TraceCheckUtils]: 9: Hoare triple {23839#true} assume !(0 != eval_~tmp~0); {23839#true} is VALID [2020-07-29 03:08:53,680 INFO L280 TraceCheckUtils]: 10: Hoare triple {23839#true} start_simulation_~kernel_st~0 := 2; {23839#true} is VALID [2020-07-29 03:08:53,680 INFO L280 TraceCheckUtils]: 11: Hoare triple {23839#true} start_simulation_~kernel_st~0 := 3; {23839#true} is VALID [2020-07-29 03:08:53,680 INFO L280 TraceCheckUtils]: 12: Hoare triple {23839#true} assume !(0 == ~M_E~0); {23839#true} is VALID [2020-07-29 03:08:53,681 INFO L280 TraceCheckUtils]: 13: Hoare triple {23839#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23839#true} is VALID [2020-07-29 03:08:53,681 INFO L280 TraceCheckUtils]: 14: Hoare triple {23839#true} assume !(0 == ~T2_E~0); {23839#true} is VALID [2020-07-29 03:08:53,681 INFO L280 TraceCheckUtils]: 15: Hoare triple {23839#true} assume 0 == ~E_M~0;~E_M~0 := 1; {23839#true} is VALID [2020-07-29 03:08:53,681 INFO L280 TraceCheckUtils]: 16: Hoare triple {23839#true} assume !(0 == ~E_1~0); {23839#true} is VALID [2020-07-29 03:08:53,681 INFO L280 TraceCheckUtils]: 17: Hoare triple {23839#true} assume 0 == ~E_2~0;~E_2~0 := 1; {23839#true} is VALID [2020-07-29 03:08:53,681 INFO L280 TraceCheckUtils]: 18: Hoare triple {23839#true} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {23839#true} is VALID [2020-07-29 03:08:53,682 INFO L280 TraceCheckUtils]: 19: Hoare triple {23839#true} assume !(1 == ~m_pc~0); {23839#true} is VALID [2020-07-29 03:08:53,682 INFO L280 TraceCheckUtils]: 20: Hoare triple {23839#true} is_master_triggered_~__retres1~0 := 0; {23841#(and (<= ULTIMATE.start_is_master_triggered_~__retres1~0 0) (<= 0 ULTIMATE.start_is_master_triggered_~__retres1~0))} is VALID [2020-07-29 03:08:53,683 INFO L280 TraceCheckUtils]: 21: Hoare triple {23841#(and (<= ULTIMATE.start_is_master_triggered_~__retres1~0 0) (<= 0 ULTIMATE.start_is_master_triggered_~__retres1~0))} is_master_triggered_#res := is_master_triggered_~__retres1~0; {23842#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res|) (<= |ULTIMATE.start_is_master_triggered_#res| 0))} is VALID [2020-07-29 03:08:53,684 INFO L280 TraceCheckUtils]: 22: Hoare triple {23842#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res|) (<= |ULTIMATE.start_is_master_triggered_#res| 0))} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {23843#(and (<= 0 ULTIMATE.start_activate_threads_~tmp~1) (<= ULTIMATE.start_activate_threads_~tmp~1 0))} is VALID [2020-07-29 03:08:53,685 INFO L280 TraceCheckUtils]: 23: Hoare triple {23843#(and (<= 0 ULTIMATE.start_activate_threads_~tmp~1) (<= ULTIMATE.start_activate_threads_~tmp~1 0))} assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; {23840#false} is VALID [2020-07-29 03:08:53,685 INFO L280 TraceCheckUtils]: 24: Hoare triple {23840#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {23840#false} is VALID [2020-07-29 03:08:53,685 INFO L280 TraceCheckUtils]: 25: Hoare triple {23840#false} assume !(1 == ~t1_pc~0); {23840#false} is VALID [2020-07-29 03:08:53,685 INFO L280 TraceCheckUtils]: 26: Hoare triple {23840#false} is_transmit1_triggered_~__retres1~1 := 0; {23840#false} is VALID [2020-07-29 03:08:53,685 INFO L280 TraceCheckUtils]: 27: Hoare triple {23840#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {23840#false} is VALID [2020-07-29 03:08:53,686 INFO L280 TraceCheckUtils]: 28: Hoare triple {23840#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {23840#false} is VALID [2020-07-29 03:08:53,686 INFO L280 TraceCheckUtils]: 29: Hoare triple {23840#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {23840#false} is VALID [2020-07-29 03:08:53,686 INFO L280 TraceCheckUtils]: 30: Hoare triple {23840#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {23840#false} is VALID [2020-07-29 03:08:53,686 INFO L280 TraceCheckUtils]: 31: Hoare triple {23840#false} assume 1 == ~t2_pc~0; {23840#false} is VALID [2020-07-29 03:08:53,686 INFO L280 TraceCheckUtils]: 32: Hoare triple {23840#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; {23840#false} is VALID [2020-07-29 03:08:53,686 INFO L280 TraceCheckUtils]: 33: Hoare triple {23840#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {23840#false} is VALID [2020-07-29 03:08:53,687 INFO L280 TraceCheckUtils]: 34: Hoare triple {23840#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {23840#false} is VALID [2020-07-29 03:08:53,687 INFO L280 TraceCheckUtils]: 35: Hoare triple {23840#false} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {23840#false} is VALID [2020-07-29 03:08:53,687 INFO L280 TraceCheckUtils]: 36: Hoare triple {23840#false} assume !(1 == ~M_E~0); {23840#false} is VALID [2020-07-29 03:08:53,687 INFO L280 TraceCheckUtils]: 37: Hoare triple {23840#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {23840#false} is VALID [2020-07-29 03:08:53,687 INFO L280 TraceCheckUtils]: 38: Hoare triple {23840#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23840#false} is VALID [2020-07-29 03:08:53,687 INFO L280 TraceCheckUtils]: 39: Hoare triple {23840#false} assume 1 == ~E_M~0;~E_M~0 := 2; {23840#false} is VALID [2020-07-29 03:08:53,688 INFO L280 TraceCheckUtils]: 40: Hoare triple {23840#false} assume !(1 == ~E_1~0); {23840#false} is VALID [2020-07-29 03:08:53,688 INFO L280 TraceCheckUtils]: 41: Hoare triple {23840#false} assume 1 == ~E_2~0;~E_2~0 := 2; {23840#false} is VALID [2020-07-29 03:08:53,688 INFO L280 TraceCheckUtils]: 42: Hoare triple {23840#false} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {23840#false} is VALID [2020-07-29 03:08:53,688 INFO L280 TraceCheckUtils]: 43: Hoare triple {23840#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {23840#false} is VALID [2020-07-29 03:08:53,688 INFO L280 TraceCheckUtils]: 44: Hoare triple {23840#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {23840#false} is VALID [2020-07-29 03:08:53,689 INFO L280 TraceCheckUtils]: 45: Hoare triple {23840#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {23840#false} is VALID [2020-07-29 03:08:53,689 INFO L280 TraceCheckUtils]: 46: Hoare triple {23840#false} assume !(0 == start_simulation_~tmp~3); {23840#false} is VALID [2020-07-29 03:08:53,689 INFO L280 TraceCheckUtils]: 47: Hoare triple {23840#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {23840#false} is VALID [2020-07-29 03:08:53,689 INFO L280 TraceCheckUtils]: 48: Hoare triple {23840#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {23840#false} is VALID [2020-07-29 03:08:53,689 INFO L280 TraceCheckUtils]: 49: Hoare triple {23840#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {23840#false} is VALID [2020-07-29 03:08:53,689 INFO L280 TraceCheckUtils]: 50: Hoare triple {23840#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {23840#false} is VALID [2020-07-29 03:08:53,690 INFO L280 TraceCheckUtils]: 51: Hoare triple {23840#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {23840#false} is VALID [2020-07-29 03:08:53,690 INFO L280 TraceCheckUtils]: 52: Hoare triple {23840#false} stop_simulation_#res := stop_simulation_~__retres2~0; {23840#false} is VALID [2020-07-29 03:08:53,690 INFO L280 TraceCheckUtils]: 53: Hoare triple {23840#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {23840#false} is VALID [2020-07-29 03:08:53,690 INFO L280 TraceCheckUtils]: 54: Hoare triple {23840#false} assume !(0 != start_simulation_~tmp___0~1); {23840#false} is VALID [2020-07-29 03:08:53,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:53,692 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813414106] [2020-07-29 03:08:53,692 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:53,693 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-07-29 03:08:53,693 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552373740] [2020-07-29 03:08:53,693 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:53,693 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:53,693 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-07-29 03:08:53,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-07-29 03:08:53,694 INFO L87 Difference]: Start difference. First operand 688 states and 950 transitions. cyclomatic complexity: 266 Second operand 5 states. [2020-07-29 03:08:55,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:55,268 INFO L93 Difference]: Finished difference Result 1317 states and 1797 transitions. [2020-07-29 03:08:55,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-07-29 03:08:55,268 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2020-07-29 03:08:55,331 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:55,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1317 states and 1797 transitions. [2020-07-29 03:08:55,409 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1265 [2020-07-29 03:08:55,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1317 states to 1317 states and 1797 transitions. [2020-07-29 03:08:55,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1317 [2020-07-29 03:08:55,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1317 [2020-07-29 03:08:55,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1317 states and 1797 transitions. [2020-07-29 03:08:55,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:55,502 INFO L688 BuchiCegarLoop]: Abstraction has 1317 states and 1797 transitions. [2020-07-29 03:08:55,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1317 states and 1797 transitions. [2020-07-29 03:08:55,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1317 to 715. [2020-07-29 03:08:55,515 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:55,515 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1317 states and 1797 transitions. Second operand 715 states. [2020-07-29 03:08:55,515 INFO L74 IsIncluded]: Start isIncluded. First operand 1317 states and 1797 transitions. Second operand 715 states. [2020-07-29 03:08:55,516 INFO L87 Difference]: Start difference. First operand 1317 states and 1797 transitions. Second operand 715 states. [2020-07-29 03:08:55,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:55,593 INFO L93 Difference]: Finished difference Result 1317 states and 1797 transitions. [2020-07-29 03:08:55,593 INFO L276 IsEmpty]: Start isEmpty. Operand 1317 states and 1797 transitions. [2020-07-29 03:08:55,595 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:55,595 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:55,595 INFO L74 IsIncluded]: Start isIncluded. First operand 715 states. Second operand 1317 states and 1797 transitions. [2020-07-29 03:08:55,595 INFO L87 Difference]: Start difference. First operand 715 states. Second operand 1317 states and 1797 transitions. [2020-07-29 03:08:55,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:55,650 INFO L93 Difference]: Finished difference Result 1317 states and 1797 transitions. [2020-07-29 03:08:55,650 INFO L276 IsEmpty]: Start isEmpty. Operand 1317 states and 1797 transitions. [2020-07-29 03:08:55,651 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:55,652 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:55,652 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:55,652 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:55,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 715 states. [2020-07-29 03:08:55,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 715 states to 715 states and 969 transitions. [2020-07-29 03:08:55,675 INFO L711 BuchiCegarLoop]: Abstraction has 715 states and 969 transitions. [2020-07-29 03:08:55,675 INFO L591 BuchiCegarLoop]: Abstraction has 715 states and 969 transitions. [2020-07-29 03:08:55,675 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2020-07-29 03:08:55,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 715 states and 969 transitions. [2020-07-29 03:08:55,678 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 667 [2020-07-29 03:08:55,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:55,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:55,679 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:55,679 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:55,680 INFO L794 eck$LassoCheckResult]: Stem: 25243#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 25179#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 25180#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25268#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 25280#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25232#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25233#L231-1 assume !(0 == ~M_E~0); 25205#L334-1 assume !(0 == ~T1_E~0); 25206#L339-1 assume !(0 == ~T2_E~0); 25221#L344-1 assume !(0 == ~E_M~0); 25371#L349-1 assume !(0 == ~E_1~0); 25293#L354-1 assume !(0 == ~E_2~0); 25294#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25327#L156 assume !(1 == ~m_pc~0); 25411#L156-2 is_master_triggered_~__retres1~0 := 0; 25412#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25357#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 25358#L415 assume !(0 != activate_threads_~tmp~1); 25400#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25166#L175 assume !(1 == ~t1_pc~0); 25167#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 25170#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25171#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 25242#L423 assume !(0 != activate_threads_~tmp___0~0); 25282#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25284#L194 assume !(1 == ~t2_pc~0); 25321#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 25322#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25407#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 25315#L431 assume !(0 != activate_threads_~tmp___1~0); 25287#L431-2 assume !(1 == ~M_E~0); 25219#L372-1 assume !(1 == ~T1_E~0); 25220#L377-1 assume !(1 == ~T2_E~0); 25370#L382-1 assume !(1 == ~E_M~0); 25288#L387-1 assume !(1 == ~E_1~0); 25289#L392-1 assume !(1 == ~E_2~0); 25325#L543-1 [2020-07-29 03:08:55,680 INFO L796 eck$LassoCheckResult]: Loop: 25325#L543-1 assume !false; 25614#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 25613#L309 assume !false; 25612#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 25610#L244 assume !(0 == ~m_st~0); 25611#L248 assume !(0 == ~t1_st~0); 25609#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 25607#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 25592#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 25593#L276 assume !(0 != eval_~tmp~0); 25605#L324 start_simulation_~kernel_st~0 := 2; 25604#L214-1 start_simulation_~kernel_st~0 := 3; 25603#L334-2 assume !(0 == ~M_E~0); 25602#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25601#L339-3 assume !(0 == ~T2_E~0); 25600#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25599#L349-3 assume !(0 == ~E_1~0); 25598#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25597#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25385#L156-12 assume !(1 == ~m_pc~0); 25386#L156-14 is_master_triggered_~__retres1~0 := 0; 25706#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25705#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 25704#L415-12 assume !(0 != activate_threads_~tmp~1); 25703#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25702#L175-12 assume !(1 == ~t1_pc~0); 25701#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 25699#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25697#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 25695#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25693#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25691#L194-12 assume 1 == ~t2_pc~0; 25688#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25685#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25682#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 25679#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25677#L431-14 assume !(1 == ~M_E~0); 25675#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25672#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25668#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25664#L387-3 assume !(1 == ~E_1~0); 25660#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25657#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 25653#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 25649#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 25646#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 25643#L562 assume !(0 == start_simulation_~tmp~3); 25640#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 25637#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 25634#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 25631#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 25628#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25625#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 25622#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 25619#L575 assume !(0 != start_simulation_~tmp___0~1); 25325#L543-1 [2020-07-29 03:08:55,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:55,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 4 times [2020-07-29 03:08:55,681 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:55,681 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176495273] [2020-07-29 03:08:55,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:55,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:55,687 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:55,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:55,692 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:55,697 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:55,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:55,698 INFO L82 PathProgramCache]: Analyzing trace with hash -365428621, now seen corresponding path program 1 times [2020-07-29 03:08:55,698 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:55,698 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812988756] [2020-07-29 03:08:55,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:55,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:55,722 INFO L280 TraceCheckUtils]: 0: Hoare triple {28520#true} assume !false; {28520#true} is VALID [2020-07-29 03:08:55,722 INFO L280 TraceCheckUtils]: 1: Hoare triple {28520#true} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {28520#true} is VALID [2020-07-29 03:08:55,723 INFO L280 TraceCheckUtils]: 2: Hoare triple {28520#true} assume !false; {28520#true} is VALID [2020-07-29 03:08:55,723 INFO L280 TraceCheckUtils]: 3: Hoare triple {28520#true} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {28520#true} is VALID [2020-07-29 03:08:55,723 INFO L280 TraceCheckUtils]: 4: Hoare triple {28520#true} assume !(0 == ~m_st~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,725 INFO L280 TraceCheckUtils]: 5: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(0 == ~t1_st~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,728 INFO L280 TraceCheckUtils]: 6: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,729 INFO L280 TraceCheckUtils]: 7: Hoare triple {28522#(not (= 0 ~m_st~0))} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,729 INFO L280 TraceCheckUtils]: 8: Hoare triple {28522#(not (= 0 ~m_st~0))} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,730 INFO L280 TraceCheckUtils]: 9: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(0 != eval_~tmp~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,730 INFO L280 TraceCheckUtils]: 10: Hoare triple {28522#(not (= 0 ~m_st~0))} start_simulation_~kernel_st~0 := 2; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,731 INFO L280 TraceCheckUtils]: 11: Hoare triple {28522#(not (= 0 ~m_st~0))} start_simulation_~kernel_st~0 := 3; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,731 INFO L280 TraceCheckUtils]: 12: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(0 == ~M_E~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,732 INFO L280 TraceCheckUtils]: 13: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 0 == ~T1_E~0;~T1_E~0 := 1; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,732 INFO L280 TraceCheckUtils]: 14: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(0 == ~T2_E~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,733 INFO L280 TraceCheckUtils]: 15: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 0 == ~E_M~0;~E_M~0 := 1; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,733 INFO L280 TraceCheckUtils]: 16: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(0 == ~E_1~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,734 INFO L280 TraceCheckUtils]: 17: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 0 == ~E_2~0;~E_2~0 := 1; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,734 INFO L280 TraceCheckUtils]: 18: Hoare triple {28522#(not (= 0 ~m_st~0))} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,735 INFO L280 TraceCheckUtils]: 19: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(1 == ~m_pc~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,735 INFO L280 TraceCheckUtils]: 20: Hoare triple {28522#(not (= 0 ~m_st~0))} is_master_triggered_~__retres1~0 := 0; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,736 INFO L280 TraceCheckUtils]: 21: Hoare triple {28522#(not (= 0 ~m_st~0))} is_master_triggered_#res := is_master_triggered_~__retres1~0; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,736 INFO L280 TraceCheckUtils]: 22: Hoare triple {28522#(not (= 0 ~m_st~0))} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,737 INFO L280 TraceCheckUtils]: 23: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(0 != activate_threads_~tmp~1); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,737 INFO L280 TraceCheckUtils]: 24: Hoare triple {28522#(not (= 0 ~m_st~0))} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,738 INFO L280 TraceCheckUtils]: 25: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(1 == ~t1_pc~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,738 INFO L280 TraceCheckUtils]: 26: Hoare triple {28522#(not (= 0 ~m_st~0))} is_transmit1_triggered_~__retres1~1 := 0; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,739 INFO L280 TraceCheckUtils]: 27: Hoare triple {28522#(not (= 0 ~m_st~0))} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,739 INFO L280 TraceCheckUtils]: 28: Hoare triple {28522#(not (= 0 ~m_st~0))} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,740 INFO L280 TraceCheckUtils]: 29: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,740 INFO L280 TraceCheckUtils]: 30: Hoare triple {28522#(not (= 0 ~m_st~0))} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,741 INFO L280 TraceCheckUtils]: 31: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 1 == ~t2_pc~0; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,742 INFO L280 TraceCheckUtils]: 32: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,742 INFO L280 TraceCheckUtils]: 33: Hoare triple {28522#(not (= 0 ~m_st~0))} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,742 INFO L280 TraceCheckUtils]: 34: Hoare triple {28522#(not (= 0 ~m_st~0))} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,743 INFO L280 TraceCheckUtils]: 35: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,743 INFO L280 TraceCheckUtils]: 36: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(1 == ~M_E~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,744 INFO L280 TraceCheckUtils]: 37: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 1 == ~T1_E~0;~T1_E~0 := 2; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,744 INFO L280 TraceCheckUtils]: 38: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 1 == ~T2_E~0;~T2_E~0 := 2; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,745 INFO L280 TraceCheckUtils]: 39: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 1 == ~E_M~0;~E_M~0 := 2; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,745 INFO L280 TraceCheckUtils]: 40: Hoare triple {28522#(not (= 0 ~m_st~0))} assume !(1 == ~E_1~0); {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,746 INFO L280 TraceCheckUtils]: 41: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 1 == ~E_2~0;~E_2~0 := 2; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,746 INFO L280 TraceCheckUtils]: 42: Hoare triple {28522#(not (= 0 ~m_st~0))} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {28522#(not (= 0 ~m_st~0))} is VALID [2020-07-29 03:08:55,747 INFO L280 TraceCheckUtils]: 43: Hoare triple {28522#(not (= 0 ~m_st~0))} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {28521#false} is VALID [2020-07-29 03:08:55,747 INFO L280 TraceCheckUtils]: 44: Hoare triple {28521#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {28521#false} is VALID [2020-07-29 03:08:55,747 INFO L280 TraceCheckUtils]: 45: Hoare triple {28521#false} start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; {28521#false} is VALID [2020-07-29 03:08:55,747 INFO L280 TraceCheckUtils]: 46: Hoare triple {28521#false} assume !(0 == start_simulation_~tmp~3); {28521#false} is VALID [2020-07-29 03:08:55,748 INFO L280 TraceCheckUtils]: 47: Hoare triple {28521#false} havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {28521#false} is VALID [2020-07-29 03:08:55,748 INFO L280 TraceCheckUtils]: 48: Hoare triple {28521#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {28521#false} is VALID [2020-07-29 03:08:55,748 INFO L280 TraceCheckUtils]: 49: Hoare triple {28521#false} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {28521#false} is VALID [2020-07-29 03:08:55,748 INFO L280 TraceCheckUtils]: 50: Hoare triple {28521#false} stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; {28521#false} is VALID [2020-07-29 03:08:55,748 INFO L280 TraceCheckUtils]: 51: Hoare triple {28521#false} assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; {28521#false} is VALID [2020-07-29 03:08:55,748 INFO L280 TraceCheckUtils]: 52: Hoare triple {28521#false} stop_simulation_#res := stop_simulation_~__retres2~0; {28521#false} is VALID [2020-07-29 03:08:55,749 INFO L280 TraceCheckUtils]: 53: Hoare triple {28521#false} start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; {28521#false} is VALID [2020-07-29 03:08:55,749 INFO L280 TraceCheckUtils]: 54: Hoare triple {28521#false} assume !(0 != start_simulation_~tmp___0~1); {28521#false} is VALID [2020-07-29 03:08:55,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:55,753 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812988756] [2020-07-29 03:08:55,753 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:55,753 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-07-29 03:08:55,753 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305493274] [2020-07-29 03:08:55,754 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-07-29 03:08:55,754 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:55,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:55,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:55,754 INFO L87 Difference]: Start difference. First operand 715 states and 969 transitions. cyclomatic complexity: 258 Second operand 3 states. [2020-07-29 03:08:56,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:56,160 INFO L93 Difference]: Finished difference Result 1118 states and 1489 transitions. [2020-07-29 03:08:56,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:56,160 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:56,224 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:56,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1118 states and 1489 transitions. [2020-07-29 03:08:56,267 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1064 [2020-07-29 03:08:56,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1118 states to 1118 states and 1489 transitions. [2020-07-29 03:08:56,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1118 [2020-07-29 03:08:56,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1118 [2020-07-29 03:08:56,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1118 states and 1489 transitions. [2020-07-29 03:08:56,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:56,325 INFO L688 BuchiCegarLoop]: Abstraction has 1118 states and 1489 transitions. [2020-07-29 03:08:56,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1118 states and 1489 transitions. [2020-07-29 03:08:56,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1118 to 1083. [2020-07-29 03:08:56,339 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:56,339 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1118 states and 1489 transitions. Second operand 1083 states. [2020-07-29 03:08:56,339 INFO L74 IsIncluded]: Start isIncluded. First operand 1118 states and 1489 transitions. Second operand 1083 states. [2020-07-29 03:08:56,339 INFO L87 Difference]: Start difference. First operand 1118 states and 1489 transitions. Second operand 1083 states. [2020-07-29 03:08:56,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:56,397 INFO L93 Difference]: Finished difference Result 1118 states and 1489 transitions. [2020-07-29 03:08:56,397 INFO L276 IsEmpty]: Start isEmpty. Operand 1118 states and 1489 transitions. [2020-07-29 03:08:56,398 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:56,399 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:56,399 INFO L74 IsIncluded]: Start isIncluded. First operand 1083 states. Second operand 1118 states and 1489 transitions. [2020-07-29 03:08:56,399 INFO L87 Difference]: Start difference. First operand 1083 states. Second operand 1118 states and 1489 transitions. [2020-07-29 03:08:56,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:56,445 INFO L93 Difference]: Finished difference Result 1118 states and 1489 transitions. [2020-07-29 03:08:56,445 INFO L276 IsEmpty]: Start isEmpty. Operand 1118 states and 1489 transitions. [2020-07-29 03:08:56,447 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:56,447 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:56,447 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:56,447 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:56,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1083 states. [2020-07-29 03:08:56,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1083 states to 1083 states and 1444 transitions. [2020-07-29 03:08:56,495 INFO L711 BuchiCegarLoop]: Abstraction has 1083 states and 1444 transitions. [2020-07-29 03:08:56,495 INFO L591 BuchiCegarLoop]: Abstraction has 1083 states and 1444 transitions. [2020-07-29 03:08:56,496 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2020-07-29 03:08:56,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1083 states and 1444 transitions. [2020-07-29 03:08:56,500 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1029 [2020-07-29 03:08:56,500 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:56,500 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:56,500 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:56,500 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:56,501 INFO L794 eck$LassoCheckResult]: Stem: 29719#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 29654#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 29655#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29744#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 29757#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29710#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29711#L231-1 assume !(0 == ~M_E~0); 29681#L334-1 assume !(0 == ~T1_E~0); 29682#L339-1 assume !(0 == ~T2_E~0); 29698#L344-1 assume !(0 == ~E_M~0); 29849#L349-1 assume !(0 == ~E_1~0); 29770#L354-1 assume !(0 == ~E_2~0); 29771#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29806#L156 assume !(1 == ~m_pc~0); 29894#L156-2 is_master_triggered_~__retres1~0 := 0; 29895#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29835#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 29836#L415 assume !(0 != activate_threads_~tmp~1); 29880#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29641#L175 assume !(1 == ~t1_pc~0); 29642#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 29645#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29646#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 29718#L423 assume !(0 != activate_threads_~tmp___0~0); 29758#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29761#L194 assume !(1 == ~t2_pc~0); 29800#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 29801#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29807#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 29795#L431 assume !(0 != activate_threads_~tmp___1~0); 29764#L431-2 assume !(1 == ~M_E~0); 29696#L372-1 assume !(1 == ~T1_E~0); 29697#L377-1 assume !(1 == ~T2_E~0); 29848#L382-1 assume !(1 == ~E_M~0); 29765#L387-1 assume !(1 == ~E_1~0); 29766#L392-1 assume !(1 == ~E_2~0); 29804#L543-1 assume !false; 30532#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 30530#L309 [2020-07-29 03:08:56,501 INFO L796 eck$LassoCheckResult]: Loop: 30530#L309 assume !false; 30528#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 30526#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 30523#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 30524#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 30720#L276 assume 0 != eval_~tmp~0; 30718#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 29692#L284 assume !(0 != eval_~tmp_ndt_1~0); 29693#L281 assume !(0 == ~t1_st~0); 30331#L295 assume !(0 == ~t2_st~0); 30530#L309 [2020-07-29 03:08:56,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:56,501 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 1 times [2020-07-29 03:08:56,501 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:56,501 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132034086] [2020-07-29 03:08:56,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:56,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:56,507 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:56,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:56,512 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:56,518 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:56,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:56,519 INFO L82 PathProgramCache]: Analyzing trace with hash -1924965839, now seen corresponding path program 1 times [2020-07-29 03:08:56,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:56,519 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929069258] [2020-07-29 03:08:56,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:56,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:56,522 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:56,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:56,524 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:56,526 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:56,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:56,527 INFO L82 PathProgramCache]: Analyzing trace with hash -460324554, now seen corresponding path program 1 times [2020-07-29 03:08:56,527 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:56,527 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45815113] [2020-07-29 03:08:56,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:56,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:56,551 INFO L280 TraceCheckUtils]: 0: Hoare triple {32967#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {32967#true} is VALID [2020-07-29 03:08:56,551 INFO L280 TraceCheckUtils]: 1: Hoare triple {32967#true} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {32967#true} is VALID [2020-07-29 03:08:56,551 INFO L280 TraceCheckUtils]: 2: Hoare triple {32967#true} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {32967#true} is VALID [2020-07-29 03:08:56,551 INFO L280 TraceCheckUtils]: 3: Hoare triple {32967#true} assume 1 == ~m_i~0;~m_st~0 := 0; {32967#true} is VALID [2020-07-29 03:08:56,552 INFO L280 TraceCheckUtils]: 4: Hoare triple {32967#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,552 INFO L280 TraceCheckUtils]: 5: Hoare triple {32969#(= 0 ~t1_st~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,553 INFO L280 TraceCheckUtils]: 6: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 == ~M_E~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,554 INFO L280 TraceCheckUtils]: 7: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 == ~T1_E~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,554 INFO L280 TraceCheckUtils]: 8: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 == ~T2_E~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,555 INFO L280 TraceCheckUtils]: 9: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 == ~E_M~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,555 INFO L280 TraceCheckUtils]: 10: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 == ~E_1~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,555 INFO L280 TraceCheckUtils]: 11: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 == ~E_2~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,556 INFO L280 TraceCheckUtils]: 12: Hoare triple {32969#(= 0 ~t1_st~0)} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,556 INFO L280 TraceCheckUtils]: 13: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~m_pc~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,557 INFO L280 TraceCheckUtils]: 14: Hoare triple {32969#(= 0 ~t1_st~0)} is_master_triggered_~__retres1~0 := 0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,557 INFO L280 TraceCheckUtils]: 15: Hoare triple {32969#(= 0 ~t1_st~0)} is_master_triggered_#res := is_master_triggered_~__retres1~0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,558 INFO L280 TraceCheckUtils]: 16: Hoare triple {32969#(= 0 ~t1_st~0)} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,558 INFO L280 TraceCheckUtils]: 17: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 != activate_threads_~tmp~1); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,559 INFO L280 TraceCheckUtils]: 18: Hoare triple {32969#(= 0 ~t1_st~0)} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,559 INFO L280 TraceCheckUtils]: 19: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~t1_pc~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,560 INFO L280 TraceCheckUtils]: 20: Hoare triple {32969#(= 0 ~t1_st~0)} is_transmit1_triggered_~__retres1~1 := 0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,560 INFO L280 TraceCheckUtils]: 21: Hoare triple {32969#(= 0 ~t1_st~0)} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,561 INFO L280 TraceCheckUtils]: 22: Hoare triple {32969#(= 0 ~t1_st~0)} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,561 INFO L280 TraceCheckUtils]: 23: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 != activate_threads_~tmp___0~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,562 INFO L280 TraceCheckUtils]: 24: Hoare triple {32969#(= 0 ~t1_st~0)} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,562 INFO L280 TraceCheckUtils]: 25: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~t2_pc~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,563 INFO L280 TraceCheckUtils]: 26: Hoare triple {32969#(= 0 ~t1_st~0)} is_transmit2_triggered_~__retres1~2 := 0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,563 INFO L280 TraceCheckUtils]: 27: Hoare triple {32969#(= 0 ~t1_st~0)} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,564 INFO L280 TraceCheckUtils]: 28: Hoare triple {32969#(= 0 ~t1_st~0)} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,564 INFO L280 TraceCheckUtils]: 29: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 != activate_threads_~tmp___1~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,565 INFO L280 TraceCheckUtils]: 30: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~M_E~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,565 INFO L280 TraceCheckUtils]: 31: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~T1_E~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,566 INFO L280 TraceCheckUtils]: 32: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~T2_E~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,566 INFO L280 TraceCheckUtils]: 33: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~E_M~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,567 INFO L280 TraceCheckUtils]: 34: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~E_1~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,567 INFO L280 TraceCheckUtils]: 35: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(1 == ~E_2~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,568 INFO L280 TraceCheckUtils]: 36: Hoare triple {32969#(= 0 ~t1_st~0)} assume !false; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,568 INFO L280 TraceCheckUtils]: 37: Hoare triple {32969#(= 0 ~t1_st~0)} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,569 INFO L280 TraceCheckUtils]: 38: Hoare triple {32969#(= 0 ~t1_st~0)} assume !false; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,569 INFO L280 TraceCheckUtils]: 39: Hoare triple {32969#(= 0 ~t1_st~0)} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,570 INFO L280 TraceCheckUtils]: 40: Hoare triple {32969#(= 0 ~t1_st~0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,570 INFO L280 TraceCheckUtils]: 41: Hoare triple {32969#(= 0 ~t1_st~0)} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,571 INFO L280 TraceCheckUtils]: 42: Hoare triple {32969#(= 0 ~t1_st~0)} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,571 INFO L280 TraceCheckUtils]: 43: Hoare triple {32969#(= 0 ~t1_st~0)} assume 0 != eval_~tmp~0; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,572 INFO L280 TraceCheckUtils]: 44: Hoare triple {32969#(= 0 ~t1_st~0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,572 INFO L280 TraceCheckUtils]: 45: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 != eval_~tmp_ndt_1~0); {32969#(= 0 ~t1_st~0)} is VALID [2020-07-29 03:08:56,573 INFO L280 TraceCheckUtils]: 46: Hoare triple {32969#(= 0 ~t1_st~0)} assume !(0 == ~t1_st~0); {32968#false} is VALID [2020-07-29 03:08:56,573 INFO L280 TraceCheckUtils]: 47: Hoare triple {32968#false} assume !(0 == ~t2_st~0); {32968#false} is VALID [2020-07-29 03:08:56,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:56,575 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45815113] [2020-07-29 03:08:56,575 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:56,576 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-07-29 03:08:56,576 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1937663490] [2020-07-29 03:08:56,654 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:56,655 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:56,655 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:56,655 INFO L87 Difference]: Start difference. First operand 1083 states and 1444 transitions. cyclomatic complexity: 367 Second operand 3 states. [2020-07-29 03:08:57,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:57,499 INFO L93 Difference]: Finished difference Result 1950 states and 2570 transitions. [2020-07-29 03:08:57,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:57,499 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:57,554 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 48 edges. 48 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:57,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1950 states and 2570 transitions. [2020-07-29 03:08:57,811 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1666 [2020-07-29 03:08:58,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1950 states to 1950 states and 2570 transitions. [2020-07-29 03:08:58,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1950 [2020-07-29 03:08:58,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1950 [2020-07-29 03:08:58,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1950 states and 2570 transitions. [2020-07-29 03:08:58,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:58,024 INFO L688 BuchiCegarLoop]: Abstraction has 1950 states and 2570 transitions. [2020-07-29 03:08:58,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1950 states and 2570 transitions. [2020-07-29 03:08:58,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1950 to 1898. [2020-07-29 03:08:58,049 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:58,049 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1950 states and 2570 transitions. Second operand 1898 states. [2020-07-29 03:08:58,049 INFO L74 IsIncluded]: Start isIncluded. First operand 1950 states and 2570 transitions. Second operand 1898 states. [2020-07-29 03:08:58,049 INFO L87 Difference]: Start difference. First operand 1950 states and 2570 transitions. Second operand 1898 states. [2020-07-29 03:08:58,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:58,188 INFO L93 Difference]: Finished difference Result 1950 states and 2570 transitions. [2020-07-29 03:08:58,189 INFO L276 IsEmpty]: Start isEmpty. Operand 1950 states and 2570 transitions. [2020-07-29 03:08:58,190 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:58,191 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:58,191 INFO L74 IsIncluded]: Start isIncluded. First operand 1898 states. Second operand 1950 states and 2570 transitions. [2020-07-29 03:08:58,191 INFO L87 Difference]: Start difference. First operand 1898 states. Second operand 1950 states and 2570 transitions. [2020-07-29 03:08:58,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:58,308 INFO L93 Difference]: Finished difference Result 1950 states and 2570 transitions. [2020-07-29 03:08:58,309 INFO L276 IsEmpty]: Start isEmpty. Operand 1950 states and 2570 transitions. [2020-07-29 03:08:58,311 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:58,311 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:58,311 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:58,311 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:58,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1898 states. [2020-07-29 03:08:58,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1898 states to 1898 states and 2506 transitions. [2020-07-29 03:08:58,424 INFO L711 BuchiCegarLoop]: Abstraction has 1898 states and 2506 transitions. [2020-07-29 03:08:58,424 INFO L591 BuchiCegarLoop]: Abstraction has 1898 states and 2506 transitions. [2020-07-29 03:08:58,424 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2020-07-29 03:08:58,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1898 states and 2506 transitions. [2020-07-29 03:08:58,432 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1614 [2020-07-29 03:08:58,432 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:58,432 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:58,433 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:58,433 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:58,433 INFO L794 eck$LassoCheckResult]: Stem: 35004#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 34933#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 34934#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 35040#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 35051#L221-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 35111#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35537#L231-1 assume !(0 == ~M_E~0); 35536#L334-1 assume !(0 == ~T1_E~0); 35535#L339-1 assume !(0 == ~T2_E~0); 35534#L344-1 assume !(0 == ~E_M~0); 35533#L349-1 assume !(0 == ~E_1~0); 35532#L354-1 assume !(0 == ~E_2~0); 35531#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35530#L156 assume !(1 == ~m_pc~0); 35529#L156-2 is_master_triggered_~__retres1~0 := 0; 35528#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35527#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 35526#L415 assume !(0 != activate_threads_~tmp~1); 35525#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35524#L175 assume !(1 == ~t1_pc~0); 35523#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 35522#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35521#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 35520#L423 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35053#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35056#L194 assume !(1 == ~t2_pc~0); 35105#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 35108#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35109#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 35419#L431 assume !(0 != activate_threads_~tmp___1~0); 35418#L431-2 assume !(1 == ~M_E~0); 34975#L372-1 assume !(1 == ~T1_E~0); 34976#L377-1 assume !(1 == ~T2_E~0); 35190#L382-1 assume !(1 == ~E_M~0); 35191#L387-1 assume !(1 == ~E_1~0); 35102#L392-1 assume !(1 == ~E_2~0); 35103#L543-1 assume !false; 35324#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 35315#L309 [2020-07-29 03:08:58,433 INFO L796 eck$LassoCheckResult]: Loop: 35315#L309 assume !false; 35310#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 35304#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 35298#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 35294#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 35288#L276 assume 0 != eval_~tmp~0; 35289#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 35277#L284 assume !(0 != eval_~tmp_ndt_1~0); 35278#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 35347#L298 assume !(0 != eval_~tmp_ndt_2~0); 35328#L295 assume !(0 == ~t2_st~0); 35315#L309 [2020-07-29 03:08:58,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:58,434 INFO L82 PathProgramCache]: Analyzing trace with hash 79981826, now seen corresponding path program 1 times [2020-07-29 03:08:58,434 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:58,434 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456939949] [2020-07-29 03:08:58,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:58,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:58,451 INFO L280 TraceCheckUtils]: 0: Hoare triple {40721#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {40721#true} is VALID [2020-07-29 03:08:58,452 INFO L280 TraceCheckUtils]: 1: Hoare triple {40721#true} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {40723#(= 1 ~t1_i~0)} is VALID [2020-07-29 03:08:58,452 INFO L280 TraceCheckUtils]: 2: Hoare triple {40723#(= 1 ~t1_i~0)} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {40723#(= 1 ~t1_i~0)} is VALID [2020-07-29 03:08:58,453 INFO L280 TraceCheckUtils]: 3: Hoare triple {40723#(= 1 ~t1_i~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {40723#(= 1 ~t1_i~0)} is VALID [2020-07-29 03:08:58,453 INFO L280 TraceCheckUtils]: 4: Hoare triple {40723#(= 1 ~t1_i~0)} assume !(1 == ~t1_i~0);~t1_st~0 := 2; {40722#false} is VALID [2020-07-29 03:08:58,453 INFO L280 TraceCheckUtils]: 5: Hoare triple {40722#false} assume 1 == ~t2_i~0;~t2_st~0 := 0; {40722#false} is VALID [2020-07-29 03:08:58,454 INFO L280 TraceCheckUtils]: 6: Hoare triple {40722#false} assume !(0 == ~M_E~0); {40722#false} is VALID [2020-07-29 03:08:58,454 INFO L280 TraceCheckUtils]: 7: Hoare triple {40722#false} assume !(0 == ~T1_E~0); {40722#false} is VALID [2020-07-29 03:08:58,454 INFO L280 TraceCheckUtils]: 8: Hoare triple {40722#false} assume !(0 == ~T2_E~0); {40722#false} is VALID [2020-07-29 03:08:58,454 INFO L280 TraceCheckUtils]: 9: Hoare triple {40722#false} assume !(0 == ~E_M~0); {40722#false} is VALID [2020-07-29 03:08:58,454 INFO L280 TraceCheckUtils]: 10: Hoare triple {40722#false} assume !(0 == ~E_1~0); {40722#false} is VALID [2020-07-29 03:08:58,454 INFO L280 TraceCheckUtils]: 11: Hoare triple {40722#false} assume !(0 == ~E_2~0); {40722#false} is VALID [2020-07-29 03:08:58,455 INFO L280 TraceCheckUtils]: 12: Hoare triple {40722#false} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {40722#false} is VALID [2020-07-29 03:08:58,455 INFO L280 TraceCheckUtils]: 13: Hoare triple {40722#false} assume !(1 == ~m_pc~0); {40722#false} is VALID [2020-07-29 03:08:58,455 INFO L280 TraceCheckUtils]: 14: Hoare triple {40722#false} is_master_triggered_~__retres1~0 := 0; {40722#false} is VALID [2020-07-29 03:08:58,455 INFO L280 TraceCheckUtils]: 15: Hoare triple {40722#false} is_master_triggered_#res := is_master_triggered_~__retres1~0; {40722#false} is VALID [2020-07-29 03:08:58,455 INFO L280 TraceCheckUtils]: 16: Hoare triple {40722#false} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {40722#false} is VALID [2020-07-29 03:08:58,455 INFO L280 TraceCheckUtils]: 17: Hoare triple {40722#false} assume !(0 != activate_threads_~tmp~1); {40722#false} is VALID [2020-07-29 03:08:58,456 INFO L280 TraceCheckUtils]: 18: Hoare triple {40722#false} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {40722#false} is VALID [2020-07-29 03:08:58,456 INFO L280 TraceCheckUtils]: 19: Hoare triple {40722#false} assume !(1 == ~t1_pc~0); {40722#false} is VALID [2020-07-29 03:08:58,456 INFO L280 TraceCheckUtils]: 20: Hoare triple {40722#false} is_transmit1_triggered_~__retres1~1 := 0; {40722#false} is VALID [2020-07-29 03:08:58,456 INFO L280 TraceCheckUtils]: 21: Hoare triple {40722#false} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {40722#false} is VALID [2020-07-29 03:08:58,456 INFO L280 TraceCheckUtils]: 22: Hoare triple {40722#false} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {40722#false} is VALID [2020-07-29 03:08:58,456 INFO L280 TraceCheckUtils]: 23: Hoare triple {40722#false} assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; {40722#false} is VALID [2020-07-29 03:08:58,457 INFO L280 TraceCheckUtils]: 24: Hoare triple {40722#false} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {40722#false} is VALID [2020-07-29 03:08:58,457 INFO L280 TraceCheckUtils]: 25: Hoare triple {40722#false} assume !(1 == ~t2_pc~0); {40722#false} is VALID [2020-07-29 03:08:58,457 INFO L280 TraceCheckUtils]: 26: Hoare triple {40722#false} is_transmit2_triggered_~__retres1~2 := 0; {40722#false} is VALID [2020-07-29 03:08:58,457 INFO L280 TraceCheckUtils]: 27: Hoare triple {40722#false} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {40722#false} is VALID [2020-07-29 03:08:58,457 INFO L280 TraceCheckUtils]: 28: Hoare triple {40722#false} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {40722#false} is VALID [2020-07-29 03:08:58,458 INFO L280 TraceCheckUtils]: 29: Hoare triple {40722#false} assume !(0 != activate_threads_~tmp___1~0); {40722#false} is VALID [2020-07-29 03:08:58,458 INFO L280 TraceCheckUtils]: 30: Hoare triple {40722#false} assume !(1 == ~M_E~0); {40722#false} is VALID [2020-07-29 03:08:58,458 INFO L280 TraceCheckUtils]: 31: Hoare triple {40722#false} assume !(1 == ~T1_E~0); {40722#false} is VALID [2020-07-29 03:08:58,458 INFO L280 TraceCheckUtils]: 32: Hoare triple {40722#false} assume !(1 == ~T2_E~0); {40722#false} is VALID [2020-07-29 03:08:58,458 INFO L280 TraceCheckUtils]: 33: Hoare triple {40722#false} assume !(1 == ~E_M~0); {40722#false} is VALID [2020-07-29 03:08:58,458 INFO L280 TraceCheckUtils]: 34: Hoare triple {40722#false} assume !(1 == ~E_1~0); {40722#false} is VALID [2020-07-29 03:08:58,459 INFO L280 TraceCheckUtils]: 35: Hoare triple {40722#false} assume !(1 == ~E_2~0); {40722#false} is VALID [2020-07-29 03:08:58,459 INFO L280 TraceCheckUtils]: 36: Hoare triple {40722#false} assume !false; {40722#false} is VALID [2020-07-29 03:08:58,459 INFO L280 TraceCheckUtils]: 37: Hoare triple {40722#false} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {40722#false} is VALID [2020-07-29 03:08:58,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:58,460 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456939949] [2020-07-29 03:08:58,460 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:58,460 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-07-29 03:08:58,461 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160450320] [2020-07-29 03:08:58,461 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-07-29 03:08:58,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:58,461 INFO L82 PathProgramCache]: Analyzing trace with hash 455496318, now seen corresponding path program 1 times [2020-07-29 03:08:58,462 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:58,462 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561474874] [2020-07-29 03:08:58,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:58,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:58,465 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:58,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:58,467 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:58,469 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:58,539 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:58,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:58,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:58,539 INFO L87 Difference]: Start difference. First operand 1898 states and 2506 transitions. cyclomatic complexity: 617 Second operand 3 states. [2020-07-29 03:08:58,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:58,815 INFO L93 Difference]: Finished difference Result 1225 states and 1616 transitions. [2020-07-29 03:08:58,815 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:58,815 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:58,855 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:58,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1225 states and 1616 transitions. [2020-07-29 03:08:58,906 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1169 [2020-07-29 03:08:58,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1225 states to 1225 states and 1616 transitions. [2020-07-29 03:08:58,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1225 [2020-07-29 03:08:58,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1225 [2020-07-29 03:08:58,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1225 states and 1616 transitions. [2020-07-29 03:08:58,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:08:58,982 INFO L688 BuchiCegarLoop]: Abstraction has 1225 states and 1616 transitions. [2020-07-29 03:08:58,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1225 states and 1616 transitions. [2020-07-29 03:08:58,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1225 to 1225. [2020-07-29 03:08:58,997 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:08:58,997 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1225 states and 1616 transitions. Second operand 1225 states. [2020-07-29 03:08:58,997 INFO L74 IsIncluded]: Start isIncluded. First operand 1225 states and 1616 transitions. Second operand 1225 states. [2020-07-29 03:08:58,998 INFO L87 Difference]: Start difference. First operand 1225 states and 1616 transitions. Second operand 1225 states. [2020-07-29 03:08:59,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:59,066 INFO L93 Difference]: Finished difference Result 1225 states and 1616 transitions. [2020-07-29 03:08:59,066 INFO L276 IsEmpty]: Start isEmpty. Operand 1225 states and 1616 transitions. [2020-07-29 03:08:59,067 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:59,067 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:59,068 INFO L74 IsIncluded]: Start isIncluded. First operand 1225 states. Second operand 1225 states and 1616 transitions. [2020-07-29 03:08:59,068 INFO L87 Difference]: Start difference. First operand 1225 states. Second operand 1225 states and 1616 transitions. [2020-07-29 03:08:59,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:59,120 INFO L93 Difference]: Finished difference Result 1225 states and 1616 transitions. [2020-07-29 03:08:59,120 INFO L276 IsEmpty]: Start isEmpty. Operand 1225 states and 1616 transitions. [2020-07-29 03:08:59,121 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:08:59,121 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:08:59,121 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:08:59,122 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:08:59,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1225 states. [2020-07-29 03:08:59,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1225 states to 1225 states and 1616 transitions. [2020-07-29 03:08:59,164 INFO L711 BuchiCegarLoop]: Abstraction has 1225 states and 1616 transitions. [2020-07-29 03:08:59,164 INFO L591 BuchiCegarLoop]: Abstraction has 1225 states and 1616 transitions. [2020-07-29 03:08:59,165 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2020-07-29 03:08:59,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1225 states and 1616 transitions. [2020-07-29 03:08:59,168 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1169 [2020-07-29 03:08:59,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:08:59,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:08:59,169 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:59,169 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:08:59,169 INFO L794 eck$LassoCheckResult]: Stem: 42028#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 41964#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 41965#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 42055#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 42068#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42018#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42019#L231-1 assume !(0 == ~M_E~0); 41989#L334-1 assume !(0 == ~T1_E~0); 41990#L339-1 assume !(0 == ~T2_E~0); 42005#L344-1 assume !(0 == ~E_M~0); 42160#L349-1 assume !(0 == ~E_1~0); 42081#L354-1 assume !(0 == ~E_2~0); 42082#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42117#L156 assume !(1 == ~m_pc~0); 42203#L156-2 is_master_triggered_~__retres1~0 := 0; 42204#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42146#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 42147#L415 assume !(0 != activate_threads_~tmp~1); 42191#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41951#L175 assume !(1 == ~t1_pc~0); 41952#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 41955#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41956#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 42027#L423 assume !(0 != activate_threads_~tmp___0~0); 42070#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42072#L194 assume !(1 == ~t2_pc~0); 42111#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 42112#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42118#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 42104#L431 assume !(0 != activate_threads_~tmp___1~0); 42075#L431-2 assume !(1 == ~M_E~0); 42003#L372-1 assume !(1 == ~T1_E~0); 42004#L377-1 assume !(1 == ~T2_E~0); 42159#L382-1 assume !(1 == ~E_M~0); 42076#L387-1 assume !(1 == ~E_1~0); 42077#L392-1 assume !(1 == ~E_2~0); 42115#L543-1 assume !false; 42297#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 42295#L309 [2020-07-29 03:08:59,169 INFO L796 eck$LassoCheckResult]: Loop: 42295#L309 assume !false; 42293#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 42289#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 42287#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 42285#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 42283#L276 assume 0 != eval_~tmp~0; 42279#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 42275#L284 assume !(0 != eval_~tmp_ndt_1~0); 42276#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 42307#L298 assume !(0 != eval_~tmp_ndt_2~0); 42301#L295 assume !(0 == ~t2_st~0); 42295#L309 [2020-07-29 03:08:59,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:59,170 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 2 times [2020-07-29 03:08:59,170 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:59,170 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [645768531] [2020-07-29 03:08:59,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:59,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:59,176 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:59,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:59,180 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:59,185 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:59,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:59,186 INFO L82 PathProgramCache]: Analyzing trace with hash 455496318, now seen corresponding path program 2 times [2020-07-29 03:08:59,186 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:59,187 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864624340] [2020-07-29 03:08:59,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:59,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:59,190 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:59,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:08:59,192 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:08:59,193 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:08:59,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:08:59,194 INFO L82 PathProgramCache]: Analyzing trace with hash -1385264103, now seen corresponding path program 1 times [2020-07-29 03:08:59,194 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:08:59,194 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188987037] [2020-07-29 03:08:59,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:08:59,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-29 03:08:59,222 INFO L280 TraceCheckUtils]: 0: Hoare triple {45633#true} ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {45633#true} is VALID [2020-07-29 03:08:59,223 INFO L280 TraceCheckUtils]: 1: Hoare triple {45633#true} havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {45633#true} is VALID [2020-07-29 03:08:59,223 INFO L280 TraceCheckUtils]: 2: Hoare triple {45633#true} havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; {45633#true} is VALID [2020-07-29 03:08:59,223 INFO L280 TraceCheckUtils]: 3: Hoare triple {45633#true} assume 1 == ~m_i~0;~m_st~0 := 0; {45633#true} is VALID [2020-07-29 03:08:59,223 INFO L280 TraceCheckUtils]: 4: Hoare triple {45633#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {45633#true} is VALID [2020-07-29 03:08:59,224 INFO L280 TraceCheckUtils]: 5: Hoare triple {45633#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,225 INFO L280 TraceCheckUtils]: 6: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 == ~M_E~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,227 INFO L280 TraceCheckUtils]: 7: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 == ~T1_E~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,228 INFO L280 TraceCheckUtils]: 8: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 == ~T2_E~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,229 INFO L280 TraceCheckUtils]: 9: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 == ~E_M~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,229 INFO L280 TraceCheckUtils]: 10: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 == ~E_1~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,230 INFO L280 TraceCheckUtils]: 11: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 == ~E_2~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,232 INFO L280 TraceCheckUtils]: 12: Hoare triple {45635#(= 0 ~t2_st~0)} havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,233 INFO L280 TraceCheckUtils]: 13: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~m_pc~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,234 INFO L280 TraceCheckUtils]: 14: Hoare triple {45635#(= 0 ~t2_st~0)} is_master_triggered_~__retres1~0 := 0; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,234 INFO L280 TraceCheckUtils]: 15: Hoare triple {45635#(= 0 ~t2_st~0)} is_master_triggered_#res := is_master_triggered_~__retres1~0; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,235 INFO L280 TraceCheckUtils]: 16: Hoare triple {45635#(= 0 ~t2_st~0)} activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,235 INFO L280 TraceCheckUtils]: 17: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp~1); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,236 INFO L280 TraceCheckUtils]: 18: Hoare triple {45635#(= 0 ~t2_st~0)} havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,236 INFO L280 TraceCheckUtils]: 19: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~t1_pc~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,237 INFO L280 TraceCheckUtils]: 20: Hoare triple {45635#(= 0 ~t2_st~0)} is_transmit1_triggered_~__retres1~1 := 0; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,237 INFO L280 TraceCheckUtils]: 21: Hoare triple {45635#(= 0 ~t2_st~0)} is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,238 INFO L280 TraceCheckUtils]: 22: Hoare triple {45635#(= 0 ~t2_st~0)} activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,238 INFO L280 TraceCheckUtils]: 23: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___0~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,239 INFO L280 TraceCheckUtils]: 24: Hoare triple {45635#(= 0 ~t2_st~0)} havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,239 INFO L280 TraceCheckUtils]: 25: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~t2_pc~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,240 INFO L280 TraceCheckUtils]: 26: Hoare triple {45635#(= 0 ~t2_st~0)} is_transmit2_triggered_~__retres1~2 := 0; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,240 INFO L280 TraceCheckUtils]: 27: Hoare triple {45635#(= 0 ~t2_st~0)} is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,241 INFO L280 TraceCheckUtils]: 28: Hoare triple {45635#(= 0 ~t2_st~0)} activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,242 INFO L280 TraceCheckUtils]: 29: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___1~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,242 INFO L280 TraceCheckUtils]: 30: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~M_E~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,243 INFO L280 TraceCheckUtils]: 31: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~T1_E~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,243 INFO L280 TraceCheckUtils]: 32: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~T2_E~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,244 INFO L280 TraceCheckUtils]: 33: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~E_M~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,244 INFO L280 TraceCheckUtils]: 34: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~E_1~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,245 INFO L280 TraceCheckUtils]: 35: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(1 == ~E_2~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,245 INFO L280 TraceCheckUtils]: 36: Hoare triple {45635#(= 0 ~t2_st~0)} assume !false; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,246 INFO L280 TraceCheckUtils]: 37: Hoare triple {45635#(= 0 ~t2_st~0)} start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,246 INFO L280 TraceCheckUtils]: 38: Hoare triple {45635#(= 0 ~t2_st~0)} assume !false; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,247 INFO L280 TraceCheckUtils]: 39: Hoare triple {45635#(= 0 ~t2_st~0)} havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,247 INFO L280 TraceCheckUtils]: 40: Hoare triple {45635#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,248 INFO L280 TraceCheckUtils]: 41: Hoare triple {45635#(= 0 ~t2_st~0)} exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,248 INFO L280 TraceCheckUtils]: 42: Hoare triple {45635#(= 0 ~t2_st~0)} eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,249 INFO L280 TraceCheckUtils]: 43: Hoare triple {45635#(= 0 ~t2_st~0)} assume 0 != eval_~tmp~0; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,249 INFO L280 TraceCheckUtils]: 44: Hoare triple {45635#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,250 INFO L280 TraceCheckUtils]: 45: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_1~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,250 INFO L280 TraceCheckUtils]: 46: Hoare triple {45635#(= 0 ~t2_st~0)} assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,251 INFO L280 TraceCheckUtils]: 47: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_2~0); {45635#(= 0 ~t2_st~0)} is VALID [2020-07-29 03:08:59,251 INFO L280 TraceCheckUtils]: 48: Hoare triple {45635#(= 0 ~t2_st~0)} assume !(0 == ~t2_st~0); {45634#false} is VALID [2020-07-29 03:08:59,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-29 03:08:59,254 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188987037] [2020-07-29 03:08:59,254 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-29 03:08:59,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-07-29 03:08:59,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404073029] [2020-07-29 03:08:59,318 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-29 03:08:59,318 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-07-29 03:08:59,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-07-29 03:08:59,319 INFO L87 Difference]: Start difference. First operand 1225 states and 1616 transitions. cyclomatic complexity: 397 Second operand 3 states. [2020-07-29 03:08:59,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:08:59,763 INFO L93 Difference]: Finished difference Result 1951 states and 2556 transitions. [2020-07-29 03:08:59,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-07-29 03:08:59,763 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2020-07-29 03:08:59,821 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 49 edges. 49 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2020-07-29 03:08:59,822 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1951 states and 2556 transitions. [2020-07-29 03:08:59,934 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1881 [2020-07-29 03:09:00,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1951 states to 1951 states and 2556 transitions. [2020-07-29 03:09:00,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1951 [2020-07-29 03:09:00,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1951 [2020-07-29 03:09:00,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1951 states and 2556 transitions. [2020-07-29 03:09:00,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-07-29 03:09:00,053 INFO L688 BuchiCegarLoop]: Abstraction has 1951 states and 2556 transitions. [2020-07-29 03:09:00,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1951 states and 2556 transitions. [2020-07-29 03:09:00,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1951 to 1915. [2020-07-29 03:09:00,074 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2020-07-29 03:09:00,074 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1951 states and 2556 transitions. Second operand 1915 states. [2020-07-29 03:09:00,074 INFO L74 IsIncluded]: Start isIncluded. First operand 1951 states and 2556 transitions. Second operand 1915 states. [2020-07-29 03:09:00,074 INFO L87 Difference]: Start difference. First operand 1951 states and 2556 transitions. Second operand 1915 states. [2020-07-29 03:09:00,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:09:00,211 INFO L93 Difference]: Finished difference Result 1951 states and 2556 transitions. [2020-07-29 03:09:00,211 INFO L276 IsEmpty]: Start isEmpty. Operand 1951 states and 2556 transitions. [2020-07-29 03:09:00,213 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:09:00,213 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:09:00,214 INFO L74 IsIncluded]: Start isIncluded. First operand 1915 states. Second operand 1951 states and 2556 transitions. [2020-07-29 03:09:00,214 INFO L87 Difference]: Start difference. First operand 1915 states. Second operand 1951 states and 2556 transitions. [2020-07-29 03:09:00,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-29 03:09:00,320 INFO L93 Difference]: Finished difference Result 1951 states and 2556 transitions. [2020-07-29 03:09:00,320 INFO L276 IsEmpty]: Start isEmpty. Operand 1951 states and 2556 transitions. [2020-07-29 03:09:00,323 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-07-29 03:09:00,323 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2020-07-29 03:09:00,323 INFO L88 GeneralOperation]: Finished isEquivalent. [2020-07-29 03:09:00,323 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2020-07-29 03:09:00,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1915 states. [2020-07-29 03:09:00,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1915 states to 1915 states and 2520 transitions. [2020-07-29 03:09:00,442 INFO L711 BuchiCegarLoop]: Abstraction has 1915 states and 2520 transitions. [2020-07-29 03:09:00,442 INFO L591 BuchiCegarLoop]: Abstraction has 1915 states and 2520 transitions. [2020-07-29 03:09:00,442 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2020-07-29 03:09:00,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1915 states and 2520 transitions. [2020-07-29 03:09:00,447 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1845 [2020-07-29 03:09:00,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-07-29 03:09:00,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-07-29 03:09:00,448 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:09:00,448 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-29 03:09:00,448 INFO L794 eck$LassoCheckResult]: Stem: 47669#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 47599#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 47600#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 47703#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 47716#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47656#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47657#L231-1 assume !(0 == ~M_E~0); 47626#L334-1 assume !(0 == ~T1_E~0); 47627#L339-1 assume !(0 == ~T2_E~0); 47643#L344-1 assume !(0 == ~E_M~0); 47807#L349-1 assume !(0 == ~E_1~0); 47728#L354-1 assume !(0 == ~E_2~0); 47729#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47762#L156 assume !(1 == ~m_pc~0); 47854#L156-2 is_master_triggered_~__retres1~0 := 0; 47855#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47793#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 47794#L415 assume !(0 != activate_threads_~tmp~1); 47840#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 47587#L175 assume !(1 == ~t1_pc~0); 47588#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 47589#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47590#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 47668#L423 assume !(0 != activate_threads_~tmp___0~0); 47717#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 47719#L194 assume !(1 == ~t2_pc~0); 47756#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 47757#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 47847#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 47749#L431 assume !(0 != activate_threads_~tmp___1~0); 47722#L431-2 assume !(1 == ~M_E~0); 47641#L372-1 assume !(1 == ~T1_E~0); 47642#L377-1 assume !(1 == ~T2_E~0); 47806#L382-1 assume !(1 == ~E_M~0); 47723#L387-1 assume !(1 == ~E_1~0); 47724#L392-1 assume !(1 == ~E_2~0); 47759#L543-1 assume !false; 49182#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 49181#L309 [2020-07-29 03:09:00,449 INFO L796 eck$LassoCheckResult]: Loop: 49181#L309 assume !false; 49180#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 49177#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 49176#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 49175#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 49174#L276 assume 0 != eval_~tmp~0; 49172#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 47636#L284 assume !(0 != eval_~tmp_ndt_1~0); 47637#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 49187#L298 assume !(0 != eval_~tmp_ndt_2~0); 49185#L295 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 48707#L312 assume !(0 != eval_~tmp_ndt_3~0); 49181#L309 [2020-07-29 03:09:00,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:09:00,449 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 3 times [2020-07-29 03:09:00,449 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:09:00,449 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720164674] [2020-07-29 03:09:00,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:09:00,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:09:00,461 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:09:00,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:09:00,470 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:09:00,478 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:09:00,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:09:00,479 INFO L82 PathProgramCache]: Analyzing trace with hash 1235481233, now seen corresponding path program 1 times [2020-07-29 03:09:00,479 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:09:00,480 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136381143] [2020-07-29 03:09:00,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:09:00,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:09:00,484 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:09:00,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:09:00,486 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:09:00,488 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:09:00,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-29 03:09:00,489 INFO L82 PathProgramCache]: Analyzing trace with hash 6483030, now seen corresponding path program 1 times [2020-07-29 03:09:00,489 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-29 03:09:00,490 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823292756] [2020-07-29 03:09:00,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-29 03:09:00,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:09:00,498 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:09:00,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-29 03:09:00,505 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-07-29 03:09:00,512 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-29 03:09:00,939 WARN L193 SmtUtils]: Spent 329.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 72 [2020-07-29 03:09:01,102 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 29.07 03:09:01 BoogieIcfgContainer [2020-07-29 03:09:01,102 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-07-29 03:09:01,103 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-07-29 03:09:01,103 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-07-29 03:09:01,103 INFO L275 PluginConnector]: Witness Printer initialized [2020-07-29 03:09:01,104 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.07 03:08:43" (3/4) ... [2020-07-29 03:09:01,108 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-07-29 03:09:01,174 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2020-07-29 03:09:01,174 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-07-29 03:09:01,177 INFO L168 Benchmark]: Toolchain (without parser) took 19399.65 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 377.5 MB). Free memory was 952.2 MB in the beginning and 1.3 GB in the end (delta: -365.9 MB). Peak memory consumption was 11.5 MB. Max. memory is 11.5 GB. [2020-07-29 03:09:01,177 INFO L168 Benchmark]: CDTParser took 1.05 ms. Allocated memory is still 1.0 GB. Free memory is still 981.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2020-07-29 03:09:01,178 INFO L168 Benchmark]: CACSL2BoogieTranslator took 486.91 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 952.2 MB in the beginning and 1.1 GB in the end (delta: -182.3 MB). Peak memory consumption was 27.6 MB. Max. memory is 11.5 GB. [2020-07-29 03:09:01,178 INFO L168 Benchmark]: Boogie Procedure Inliner took 114.09 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2020-07-29 03:09:01,179 INFO L168 Benchmark]: Boogie Preprocessor took 72.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.6 MB). Peak memory consumption was 8.6 MB. Max. memory is 11.5 GB. [2020-07-29 03:09:01,179 INFO L168 Benchmark]: RCFGBuilder took 1205.54 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 93.9 MB). Peak memory consumption was 93.9 MB. Max. memory is 11.5 GB. [2020-07-29 03:09:01,180 INFO L168 Benchmark]: BuchiAutomizer took 17441.38 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 238.6 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -293.1 MB). Peak memory consumption was 458.6 MB. Max. memory is 11.5 GB. [2020-07-29 03:09:01,180 INFO L168 Benchmark]: Witness Printer took 71.67 ms. Allocated memory is still 1.4 GB. Free memory is still 1.3 GB. There was no memory consumed. Max. memory is 11.5 GB. [2020-07-29 03:09:01,182 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.05 ms. Allocated memory is still 1.0 GB. Free memory is still 981.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 486.91 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 952.2 MB in the beginning and 1.1 GB in the end (delta: -182.3 MB). Peak memory consumption was 27.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 114.09 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 72.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.6 MB). Peak memory consumption was 8.6 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1205.54 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 93.9 MB). Peak memory consumption was 93.9 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 17441.38 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 238.6 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -293.1 MB). Peak memory consumption was 458.6 MB. Max. memory is 11.5 GB. * Witness Printer took 71.67 ms. Allocated memory is still 1.4 GB. Free memory is still 1.3 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1915 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 17.3s and 15 iterations. TraceHistogramMax:1. Analysis of lassos took 2.9s. Construction of modules took 0.5s. Büchi inclusion checks took 9.4s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 2.3s AutomataMinimizationTime, 14 MinimizatonAttempts, 2004 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 1.7s Buchi closure took 0.0s. Biggest automaton had 1915 states and ocurred in iteration 14. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 4419 SDtfs, 4671 SDslu, 4581 SDs, 0 SdLazy, 316 SolverSat, 133 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.5s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, token=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@114d7027=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7c9abb1c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@77766e38=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@144d88c4=0, T2_E=2, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@74630841=0, __retres1=0, tmp___0=0, t2_st=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@310dfc23=0, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@45648e0c=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3d069a9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@639eb9cb=0, t1_st=0, \result=0, t2_pc=0, local=0, m_st=0, tmp___1=0, E_M=2, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int m_st ; [L18] int t1_st ; [L19] int t2_st ; [L20] int m_i ; [L21] int t1_i ; [L22] int t2_i ; [L23] int M_E = 2; [L24] int T1_E = 2; [L25] int T2_E = 2; [L26] int E_M = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L33] int token ; [L35] int local ; [L588] int __retres1 ; [L502] m_i = 1 [L503] t1_i = 1 [L504] t2_i = 1 [L529] int kernel_st ; [L530] int tmp ; [L531] int tmp___0 ; [L535] kernel_st = 0 [L221] COND TRUE m_i == 1 [L222] m_st = 0 [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 [L334] COND FALSE !(M_E == 0) [L339] COND FALSE !(T1_E == 0) [L344] COND FALSE !(T2_E == 0) [L349] COND FALSE !(E_M == 0) [L354] COND FALSE !(E_1 == 0) [L359] COND FALSE !(E_2 == 0) [L407] int tmp ; [L408] int tmp___0 ; [L409] int tmp___1 ; [L153] int __retres1 ; [L156] COND FALSE !(m_pc == 1) [L166] __retres1 = 0 [L168] return (__retres1); [L413] tmp = is_master_triggered() [L415] COND FALSE !(\read(tmp)) [L172] int __retres1 ; [L175] COND FALSE !(t1_pc == 1) [L185] __retres1 = 0 [L187] return (__retres1); [L421] tmp___0 = is_transmit1_triggered() [L423] COND FALSE !(\read(tmp___0)) [L191] int __retres1 ; [L194] COND FALSE !(t2_pc == 1) [L204] __retres1 = 0 [L206] return (__retres1); [L429] tmp___1 = is_transmit2_triggered() [L431] COND FALSE !(\read(tmp___1)) [L372] COND FALSE !(M_E == 1) [L377] COND FALSE !(T1_E == 1) [L382] COND FALSE !(T2_E == 1) [L387] COND FALSE !(E_M == 1) [L392] COND FALSE !(E_1 == 1) [L397] COND FALSE !(E_2 == 1) [L543] COND TRUE 1 [L546] kernel_st = 1 [L267] int tmp ; Loop: [L271] COND TRUE 1 [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...