./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.02.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 54858612 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.02.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a08b839794d511e255b2cbb9b4715d014c32f56d ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-5485861 [2020-10-26 05:46:27,986 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-10-26 05:46:27,989 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-10-26 05:46:28,024 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-10-26 05:46:28,025 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-10-26 05:46:28,026 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-10-26 05:46:28,028 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-10-26 05:46:28,031 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-10-26 05:46:28,033 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-10-26 05:46:28,034 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-10-26 05:46:28,036 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-10-26 05:46:28,037 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-10-26 05:46:28,038 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-10-26 05:46:28,040 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-10-26 05:46:28,041 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-10-26 05:46:28,042 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-10-26 05:46:28,044 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-10-26 05:46:28,045 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-10-26 05:46:28,047 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-10-26 05:46:28,049 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-10-26 05:46:28,051 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-10-26 05:46:28,053 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-10-26 05:46:28,055 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-10-26 05:46:28,056 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-10-26 05:46:28,059 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-10-26 05:46:28,060 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-10-26 05:46:28,060 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-10-26 05:46:28,061 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-10-26 05:46:28,062 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-10-26 05:46:28,063 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-10-26 05:46:28,064 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-10-26 05:46:28,065 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-10-26 05:46:28,066 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-10-26 05:46:28,067 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-10-26 05:46:28,068 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-10-26 05:46:28,069 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-10-26 05:46:28,070 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-10-26 05:46:28,070 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-10-26 05:46:28,071 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-10-26 05:46:28,072 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-10-26 05:46:28,073 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-10-26 05:46:28,074 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-10-26 05:46:28,103 INFO L113 SettingsManager]: Loading preferences was successful [2020-10-26 05:46:28,104 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-10-26 05:46:28,105 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-10-26 05:46:28,106 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-10-26 05:46:28,106 INFO L138 SettingsManager]: * Use SBE=true [2020-10-26 05:46:28,106 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-10-26 05:46:28,107 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-10-26 05:46:28,107 INFO L138 SettingsManager]: * Use old map elimination=false [2020-10-26 05:46:28,107 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-10-26 05:46:28,107 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-10-26 05:46:28,108 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-10-26 05:46:28,108 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-10-26 05:46:28,108 INFO L138 SettingsManager]: * sizeof long=4 [2020-10-26 05:46:28,109 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-10-26 05:46:28,109 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-10-26 05:46:28,109 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-10-26 05:46:28,109 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-10-26 05:46:28,110 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-10-26 05:46:28,110 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-10-26 05:46:28,110 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-10-26 05:46:28,111 INFO L138 SettingsManager]: * sizeof long double=12 [2020-10-26 05:46:28,111 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-10-26 05:46:28,111 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-10-26 05:46:28,111 INFO L138 SettingsManager]: * Use constant arrays=true [2020-10-26 05:46:28,112 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-10-26 05:46:28,112 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-10-26 05:46:28,112 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-10-26 05:46:28,113 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-10-26 05:46:28,113 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-10-26 05:46:28,113 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-10-26 05:46:28,114 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-10-26 05:46:28,114 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-10-26 05:46:28,115 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-10-26 05:46:28,116 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a08b839794d511e255b2cbb9b4715d014c32f56d [2020-10-26 05:46:28,503 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-10-26 05:46:28,533 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-10-26 05:46:28,537 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-10-26 05:46:28,539 INFO L271 PluginConnector]: Initializing CDTParser... [2020-10-26 05:46:28,540 INFO L275 PluginConnector]: CDTParser initialized [2020-10-26 05:46:28,541 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2020-10-26 05:46:28,631 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6c32ce726/64082e6b4ed845bbb5558b89aa4c9b18/FLAGa579bf219 [2020-10-26 05:46:29,305 INFO L306 CDTParser]: Found 1 translation units. [2020-10-26 05:46:29,307 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2020-10-26 05:46:29,327 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6c32ce726/64082e6b4ed845bbb5558b89aa4c9b18/FLAGa579bf219 [2020-10-26 05:46:29,621 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6c32ce726/64082e6b4ed845bbb5558b89aa4c9b18 [2020-10-26 05:46:29,626 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-10-26 05:46:29,633 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-10-26 05:46:29,635 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-10-26 05:46:29,635 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-10-26 05:46:29,643 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-10-26 05:46:29,644 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 05:46:29" (1/1) ... [2020-10-26 05:46:29,648 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@418a64e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:29, skipping insertion in model container [2020-10-26 05:46:29,649 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 05:46:29" (1/1) ... [2020-10-26 05:46:29,659 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-10-26 05:46:29,725 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-10-26 05:46:29,949 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-10-26 05:46:29,964 INFO L203 MainTranslator]: Completed pre-run [2020-10-26 05:46:30,050 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-10-26 05:46:30,076 INFO L208 MainTranslator]: Completed translation [2020-10-26 05:46:30,077 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30 WrapperNode [2020-10-26 05:46:30,078 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-10-26 05:46:30,080 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-10-26 05:46:30,080 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-10-26 05:46:30,080 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-10-26 05:46:30,093 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,120 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,166 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-10-26 05:46:30,168 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-10-26 05:46:30,168 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-10-26 05:46:30,174 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-10-26 05:46:30,184 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,185 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,189 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,190 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,201 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,223 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,232 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... [2020-10-26 05:46:30,248 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-10-26 05:46:30,250 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-10-26 05:46:30,252 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-10-26 05:46:30,252 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-10-26 05:46:30,254 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-10-26 05:46:30,345 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-10-26 05:46:30,346 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-10-26 05:46:30,346 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-10-26 05:46:30,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-10-26 05:46:31,400 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-10-26 05:46:31,402 INFO L298 CfgBuilder]: Removed 109 assume(true) statements. [2020-10-26 05:46:31,406 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:46:31 BoogieIcfgContainer [2020-10-26 05:46:31,407 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-10-26 05:46:31,409 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-10-26 05:46:31,409 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-10-26 05:46:31,413 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-10-26 05:46:31,414 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:46:31,414 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.10 05:46:29" (1/3) ... [2020-10-26 05:46:31,416 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4cf859d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.10 05:46:31, skipping insertion in model container [2020-10-26 05:46:31,417 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:46:31,417 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:30" (2/3) ... [2020-10-26 05:46:31,417 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4cf859d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.10 05:46:31, skipping insertion in model container [2020-10-26 05:46:31,417 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:46:31,417 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:46:31" (3/3) ... [2020-10-26 05:46:31,420 INFO L373 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-2.c [2020-10-26 05:46:31,475 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-10-26 05:46:31,475 INFO L360 BuchiCegarLoop]: Hoare is false [2020-10-26 05:46:31,476 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-10-26 05:46:31,476 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-10-26 05:46:31,476 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-10-26 05:46:31,476 INFO L364 BuchiCegarLoop]: Difference is false [2020-10-26 05:46:31,476 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-10-26 05:46:31,476 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-10-26 05:46:31,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states. [2020-10-26 05:46:31,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2020-10-26 05:46:31,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:31,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:31,551 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:31,551 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:31,551 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-10-26 05:46:31,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states. [2020-10-26 05:46:31,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2020-10-26 05:46:31,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:31,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:31,567 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:31,567 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:31,582 INFO L794 eck$LassoCheckResult]: Stem: 70#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 187#L520true havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 205#L228true assume !(1 == ~m_i~0);~m_st~0 := 2; 28#L235-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 32#L240-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 177#L245-1true assume !(0 == ~M_E~0); 135#L348-1true assume !(0 == ~T1_E~0); 154#L353-1true assume !(0 == ~T2_E~0); 50#L358-1true assume !(0 == ~E_M~0); 95#L363-1true assume !(0 == ~E_1~0); 129#L368-1true assume !(0 == ~E_2~0); 8#L373-1true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117#L170true assume 1 == ~m_pc~0; 46#L171true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 118#L181true is_master_triggered_#res := is_master_triggered_~__retres1~0; 47#L182true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 86#L429true assume !(0 != activate_threads_~tmp~1); 92#L429-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 217#L189true assume 1 == ~t1_pc~0; 175#L190true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 218#L200true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 176#L201true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 220#L437true assume !(0 != activate_threads_~tmp___0~0); 198#L437-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4#L208true assume !(1 == ~t2_pc~0); 20#L208-2true is_transmit2_triggered_~__retres1~2 := 0; 5#L219true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 61#L220true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 120#L445true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 126#L445-2true assume !(1 == ~M_E~0); 150#L386-1true assume !(1 == ~T1_E~0); 49#L391-1true assume !(1 == ~T2_E~0); 93#L396-1true assume !(1 == ~E_M~0); 127#L401-1true assume 1 == ~E_1~0;~E_1~0 := 2; 23#L406-1true assume !(1 == ~E_2~0); 137#L557-1true [2020-10-26 05:46:31,586 INFO L796 eck$LassoCheckResult]: Loop: 137#L557-1true assume !false; 209#L558true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 25#L323true assume false; 199#L338true start_simulation_~kernel_st~0 := 2; 202#L228-1true start_simulation_~kernel_st~0 := 3; 136#L348-2true assume 0 == ~M_E~0;~M_E~0 := 1; 133#L348-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 141#L353-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 41#L358-3true assume 0 == ~E_M~0;~E_M~0 := 1; 71#L363-3true assume !(0 == ~E_1~0); 111#L368-3true assume 0 == ~E_2~0;~E_2~0 := 1; 14#L373-3true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67#L170-12true assume 1 == ~m_pc~0; 148#L171-4true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 87#L181-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 151#L182-4true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 63#L429-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 68#L429-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 193#L189-12true assume 1 == ~t1_pc~0; 162#L190-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 227#L200-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 163#L201-4true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 185#L437-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 188#L437-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 130#L208-12true assume 1 == ~t2_pc~0; 76#L209-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16#L219-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 77#L220-4true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 104#L445-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 107#L445-14true assume 1 == ~M_E~0;~M_E~0 := 2; 159#L386-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 40#L391-3true assume !(1 == ~T2_E~0); 69#L396-3true assume 1 == ~E_M~0;~E_M~0 := 2; 109#L401-3true assume 1 == ~E_1~0;~E_1~0 := 2; 10#L406-3true assume 1 == ~E_2~0;~E_2~0 := 2; 27#L411-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 122#L258-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 64#L275-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 139#L276-1true start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 36#L576true assume !(0 == start_simulation_~tmp~3); 37#L576-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 119#L258-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 60#L275-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 138#L276-2true stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 186#L531true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 24#L538true stop_simulation_#res := stop_simulation_~__retres2~0; 105#L539true start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 57#L589true assume !(0 != start_simulation_~tmp___0~1); 137#L557-1true [2020-10-26 05:46:31,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:31,606 INFO L82 PathProgramCache]: Analyzing trace with hash -1720133594, now seen corresponding path program 1 times [2020-10-26 05:46:31,623 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:31,624 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485840272] [2020-10-26 05:46:31,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:31,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:31,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:31,908 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485840272] [2020-10-26 05:46:31,909 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:31,909 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:31,910 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277477798] [2020-10-26 05:46:31,915 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:31,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:31,916 INFO L82 PathProgramCache]: Analyzing trace with hash -1308335761, now seen corresponding path program 1 times [2020-10-26 05:46:31,916 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:31,917 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872961951] [2020-10-26 05:46:31,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:31,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:31,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:31,950 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872961951] [2020-10-26 05:46:31,950 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:31,951 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:31,951 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725726631] [2020-10-26 05:46:31,953 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:31,954 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:31,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:31,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:31,974 INFO L87 Difference]: Start difference. First operand 225 states. Second operand 3 states. [2020-10-26 05:46:32,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:32,025 INFO L93 Difference]: Finished difference Result 223 states and 337 transitions. [2020-10-26 05:46:32,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:32,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 337 transitions. [2020-10-26 05:46:32,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2020-10-26 05:46:32,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 217 states and 331 transitions. [2020-10-26 05:46:32,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2020-10-26 05:46:32,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2020-10-26 05:46:32,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217 states and 331 transitions. [2020-10-26 05:46:32,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:32,053 INFO L691 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2020-10-26 05:46:32,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states and 331 transitions. [2020-10-26 05:46:32,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2020-10-26 05:46:32,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2020-10-26 05:46:32,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 331 transitions. [2020-10-26 05:46:32,105 INFO L714 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2020-10-26 05:46:32,105 INFO L594 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2020-10-26 05:46:32,105 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-10-26 05:46:32,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states and 331 transitions. [2020-10-26 05:46:32,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2020-10-26 05:46:32,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:32,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:32,113 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:32,113 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:32,114 INFO L794 eck$LassoCheckResult]: Stem: 572#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 464#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 465#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 668#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 503#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 504#L240-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 511#L245-1 assume !(0 == ~M_E~0); 624#L348-1 assume !(0 == ~T1_E~0); 625#L353-1 assume !(0 == ~T2_E~0); 549#L358-1 assume !(0 == ~E_M~0); 550#L363-1 assume !(0 == ~E_1~0); 600#L368-1 assume !(0 == ~E_2~0); 466#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 467#L170 assume 1 == ~m_pc~0; 541#L171 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 542#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 544#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 545#L429 assume !(0 != activate_threads_~tmp~1); 591#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 596#L189 assume 1 == ~t1_pc~0; 656#L190 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 657#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 659#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 660#L437 assume !(0 != activate_threads_~tmp___0~0); 671#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 459#L208 assume !(1 == ~t2_pc~0); 460#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 462#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 463#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 561#L445 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 614#L445-2 assume !(1 == ~M_E~0); 616#L386-1 assume !(1 == ~T1_E~0); 547#L391-1 assume !(1 == ~T2_E~0); 548#L396-1 assume !(1 == ~E_M~0); 597#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 494#L406-1 assume !(1 == ~E_2~0); 495#L557-1 [2020-10-26 05:46:32,115 INFO L796 eck$LassoCheckResult]: Loop: 495#L557-1 assume !false; 627#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 498#L323 assume !false; 499#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 568#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 516#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 567#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 509#L290 assume !(0 != eval_~tmp~0); 510#L338 start_simulation_~kernel_st~0 := 2; 672#L228-1 start_simulation_~kernel_st~0 := 3; 626#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 620#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 621#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 530#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 531#L363-3 assume !(0 == ~E_1~0); 573#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 478#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 479#L170-12 assume !(1 == ~m_pc~0); 562#L170-14 is_master_triggered_~__retres1~0 := 0; 563#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 592#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 564#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 565#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 570#L189-12 assume 1 == ~t1_pc~0; 632#L190-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 633#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 635#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 636#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 667#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 617#L208-12 assume 1 == ~t2_pc~0; 581#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 482#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 483#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 583#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 607#L445-14 assume 1 == ~M_E~0;~M_E~0 := 2; 610#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 528#L391-3 assume !(1 == ~T2_E~0); 529#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 571#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 471#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 472#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 502#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 513#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 566#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 518#L576 assume !(0 == start_simulation_~tmp~3); 519#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 521#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 526#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 560#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 628#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 496#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 497#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 558#L589 assume !(0 != start_simulation_~tmp___0~1); 495#L557-1 [2020-10-26 05:46:32,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:32,119 INFO L82 PathProgramCache]: Analyzing trace with hash -1647747036, now seen corresponding path program 1 times [2020-10-26 05:46:32,119 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:32,120 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969200539] [2020-10-26 05:46:32,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:32,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:32,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:32,207 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969200539] [2020-10-26 05:46:32,207 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:32,208 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:32,208 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547261428] [2020-10-26 05:46:32,209 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:32,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:32,210 INFO L82 PathProgramCache]: Analyzing trace with hash -2023675283, now seen corresponding path program 1 times [2020-10-26 05:46:32,210 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:32,210 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328884510] [2020-10-26 05:46:32,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:32,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:32,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:32,271 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328884510] [2020-10-26 05:46:32,272 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:32,272 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:32,272 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447720067] [2020-10-26 05:46:32,273 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:32,273 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:32,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:32,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:32,275 INFO L87 Difference]: Start difference. First operand 217 states and 331 transitions. cyclomatic complexity: 115 Second operand 3 states. [2020-10-26 05:46:32,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:32,294 INFO L93 Difference]: Finished difference Result 217 states and 330 transitions. [2020-10-26 05:46:32,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:32,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 330 transitions. [2020-10-26 05:46:32,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2020-10-26 05:46:32,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 217 states and 330 transitions. [2020-10-26 05:46:32,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2020-10-26 05:46:32,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2020-10-26 05:46:32,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217 states and 330 transitions. [2020-10-26 05:46:32,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:32,306 INFO L691 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2020-10-26 05:46:32,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states and 330 transitions. [2020-10-26 05:46:32,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2020-10-26 05:46:32,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2020-10-26 05:46:32,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 330 transitions. [2020-10-26 05:46:32,319 INFO L714 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2020-10-26 05:46:32,319 INFO L594 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2020-10-26 05:46:32,320 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-10-26 05:46:32,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states and 330 transitions. [2020-10-26 05:46:32,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2020-10-26 05:46:32,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:32,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:32,325 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:32,325 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:32,325 INFO L794 eck$LassoCheckResult]: Stem: 1013#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 905#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 906#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1109#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 944#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 945#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 952#L245-1 assume !(0 == ~M_E~0); 1065#L348-1 assume !(0 == ~T1_E~0); 1066#L353-1 assume !(0 == ~T2_E~0); 990#L358-1 assume !(0 == ~E_M~0); 991#L363-1 assume !(0 == ~E_1~0); 1041#L368-1 assume !(0 == ~E_2~0); 907#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 908#L170 assume 1 == ~m_pc~0; 982#L171 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 983#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 985#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 986#L429 assume !(0 != activate_threads_~tmp~1); 1032#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1037#L189 assume 1 == ~t1_pc~0; 1097#L190 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1098#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1100#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1101#L437 assume !(0 != activate_threads_~tmp___0~0); 1112#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 900#L208 assume !(1 == ~t2_pc~0); 901#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 903#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 904#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1002#L445 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1055#L445-2 assume !(1 == ~M_E~0); 1057#L386-1 assume !(1 == ~T1_E~0); 988#L391-1 assume !(1 == ~T2_E~0); 989#L396-1 assume !(1 == ~E_M~0); 1038#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 935#L406-1 assume !(1 == ~E_2~0); 936#L557-1 [2020-10-26 05:46:32,326 INFO L796 eck$LassoCheckResult]: Loop: 936#L557-1 assume !false; 1068#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 939#L323 assume !false; 940#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1009#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 957#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1008#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 950#L290 assume !(0 != eval_~tmp~0); 951#L338 start_simulation_~kernel_st~0 := 2; 1113#L228-1 start_simulation_~kernel_st~0 := 3; 1067#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1061#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1062#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 971#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 972#L363-3 assume !(0 == ~E_1~0); 1014#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 919#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 920#L170-12 assume 1 == ~m_pc~0; 1010#L171-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1004#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1033#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1005#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1006#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1011#L189-12 assume 1 == ~t1_pc~0; 1073#L190-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1074#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1076#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1077#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1108#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1058#L208-12 assume 1 == ~t2_pc~0; 1022#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 923#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 924#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1024#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1048#L445-14 assume 1 == ~M_E~0;~M_E~0 := 2; 1051#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 969#L391-3 assume !(1 == ~T2_E~0); 970#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1012#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 912#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 913#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 943#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 954#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1007#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 959#L576 assume !(0 == start_simulation_~tmp~3); 960#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 962#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 967#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1001#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1069#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 937#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 938#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 999#L589 assume !(0 != start_simulation_~tmp___0~1); 936#L557-1 [2020-10-26 05:46:32,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:32,327 INFO L82 PathProgramCache]: Analyzing trace with hash 1945620386, now seen corresponding path program 1 times [2020-10-26 05:46:32,327 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:32,327 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668975129] [2020-10-26 05:46:32,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:32,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:32,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:32,399 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668975129] [2020-10-26 05:46:32,400 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:32,400 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:32,403 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055956075] [2020-10-26 05:46:32,404 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:32,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:32,405 INFO L82 PathProgramCache]: Analyzing trace with hash -258858674, now seen corresponding path program 1 times [2020-10-26 05:46:32,405 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:32,405 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962625323] [2020-10-26 05:46:32,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:32,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:32,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:32,512 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962625323] [2020-10-26 05:46:32,512 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:32,512 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:32,512 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879337223] [2020-10-26 05:46:32,513 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:32,514 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:32,515 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:32,515 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:32,515 INFO L87 Difference]: Start difference. First operand 217 states and 330 transitions. cyclomatic complexity: 114 Second operand 3 states. [2020-10-26 05:46:32,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:32,596 INFO L93 Difference]: Finished difference Result 382 states and 568 transitions. [2020-10-26 05:46:32,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:32,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 382 states and 568 transitions. [2020-10-26 05:46:32,601 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 343 [2020-10-26 05:46:32,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 382 states to 382 states and 568 transitions. [2020-10-26 05:46:32,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 382 [2020-10-26 05:46:32,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 382 [2020-10-26 05:46:32,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 382 states and 568 transitions. [2020-10-26 05:46:32,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:32,610 INFO L691 BuchiCegarLoop]: Abstraction has 382 states and 568 transitions. [2020-10-26 05:46:32,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 382 states and 568 transitions. [2020-10-26 05:46:32,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 382 to 363. [2020-10-26 05:46:32,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 363 states. [2020-10-26 05:46:32,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 363 states to 363 states and 542 transitions. [2020-10-26 05:46:32,626 INFO L714 BuchiCegarLoop]: Abstraction has 363 states and 542 transitions. [2020-10-26 05:46:32,626 INFO L594 BuchiCegarLoop]: Abstraction has 363 states and 542 transitions. [2020-10-26 05:46:32,626 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-10-26 05:46:32,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 363 states and 542 transitions. [2020-10-26 05:46:32,629 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 324 [2020-10-26 05:46:32,630 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:32,630 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:32,632 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:32,632 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:32,632 INFO L794 eck$LassoCheckResult]: Stem: 1613#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1511#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1512#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1724#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 1550#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1551#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1558#L245-1 assume !(0 == ~M_E~0); 1666#L348-1 assume !(0 == ~T1_E~0); 1667#L353-1 assume !(0 == ~T2_E~0); 1592#L358-1 assume !(0 == ~E_M~0); 1593#L363-1 assume !(0 == ~E_1~0); 1643#L368-1 assume !(0 == ~E_2~0); 1513#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1514#L170 assume !(1 == ~m_pc~0); 1637#L170-2 is_master_triggered_~__retres1~0 := 0; 1638#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1587#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1588#L429 assume !(0 != activate_threads_~tmp~1); 1632#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1639#L189 assume 1 == ~t1_pc~0; 1712#L190 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1713#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1715#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1716#L437 assume !(0 != activate_threads_~tmp___0~0); 1727#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1506#L208 assume !(1 == ~t2_pc~0); 1507#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 1509#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1510#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1603#L445 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1656#L445-2 assume !(1 == ~M_E~0); 1658#L386-1 assume !(1 == ~T1_E~0); 1590#L391-1 assume !(1 == ~T2_E~0); 1591#L396-1 assume !(1 == ~E_M~0); 1640#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1541#L406-1 assume !(1 == ~E_2~0); 1542#L557-1 [2020-10-26 05:46:32,633 INFO L796 eck$LassoCheckResult]: Loop: 1542#L557-1 assume !false; 1669#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1545#L323 assume !false; 1546#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1610#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1563#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1609#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1556#L290 assume !(0 != eval_~tmp~0); 1557#L338 start_simulation_~kernel_st~0 := 2; 1728#L228-1 start_simulation_~kernel_st~0 := 3; 1668#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1662#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1663#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1576#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1577#L363-3 assume !(0 == ~E_1~0); 1614#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1525#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1526#L170-12 assume !(1 == ~m_pc~0); 1604#L170-14 is_master_triggered_~__retres1~0 := 0; 1605#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1633#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1606#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1607#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1611#L189-12 assume 1 == ~t1_pc~0; 1688#L190-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1689#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1691#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1692#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1723#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1659#L208-12 assume 1 == ~t2_pc~0; 1622#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1529#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1530#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1624#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1649#L445-14 assume 1 == ~M_E~0;~M_E~0 := 2; 1651#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L391-3 assume !(1 == ~T2_E~0); 1575#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1612#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1518#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1519#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1549#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1560#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1608#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1565#L576 assume !(0 == start_simulation_~tmp~3); 1566#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1568#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1572#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1602#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1670#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1543#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 1544#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1600#L589 assume !(0 != start_simulation_~tmp___0~1); 1542#L557-1 [2020-10-26 05:46:32,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:32,634 INFO L82 PathProgramCache]: Analyzing trace with hash -1569365981, now seen corresponding path program 1 times [2020-10-26 05:46:32,634 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:32,634 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145229453] [2020-10-26 05:46:32,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:32,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:32,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:32,693 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145229453] [2020-10-26 05:46:32,693 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:32,693 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:32,694 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374146377] [2020-10-26 05:46:32,694 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:32,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:32,696 INFO L82 PathProgramCache]: Analyzing trace with hash -2023675283, now seen corresponding path program 2 times [2020-10-26 05:46:32,696 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:32,697 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546628075] [2020-10-26 05:46:32,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:32,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:32,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:32,798 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546628075] [2020-10-26 05:46:32,798 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:32,798 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:32,799 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665002797] [2020-10-26 05:46:32,800 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:32,800 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:32,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:32,802 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:32,803 INFO L87 Difference]: Start difference. First operand 363 states and 542 transitions. cyclomatic complexity: 181 Second operand 4 states. [2020-10-26 05:46:32,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:32,963 INFO L93 Difference]: Finished difference Result 802 states and 1173 transitions. [2020-10-26 05:46:32,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:32,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 802 states and 1173 transitions. [2020-10-26 05:46:32,972 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 737 [2020-10-26 05:46:32,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 802 states to 802 states and 1173 transitions. [2020-10-26 05:46:32,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 802 [2020-10-26 05:46:32,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 802 [2020-10-26 05:46:32,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 802 states and 1173 transitions. [2020-10-26 05:46:32,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:32,984 INFO L691 BuchiCegarLoop]: Abstraction has 802 states and 1173 transitions. [2020-10-26 05:46:32,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 802 states and 1173 transitions. [2020-10-26 05:46:33,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 802 to 633. [2020-10-26 05:46:33,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 633 states. [2020-10-26 05:46:33,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 937 transitions. [2020-10-26 05:46:33,015 INFO L714 BuchiCegarLoop]: Abstraction has 633 states and 937 transitions. [2020-10-26 05:46:33,019 INFO L594 BuchiCegarLoop]: Abstraction has 633 states and 937 transitions. [2020-10-26 05:46:33,020 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-10-26 05:46:33,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 937 transitions. [2020-10-26 05:46:33,024 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 594 [2020-10-26 05:46:33,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:33,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:33,031 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:33,031 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:33,033 INFO L794 eck$LassoCheckResult]: Stem: 2789#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2686#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2687#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2898#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 2725#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2726#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2733#L245-1 assume !(0 == ~M_E~0); 2844#L348-1 assume !(0 == ~T1_E~0); 2845#L353-1 assume !(0 == ~T2_E~0); 2767#L358-1 assume !(0 == ~E_M~0); 2768#L363-1 assume !(0 == ~E_1~0); 2822#L368-1 assume !(0 == ~E_2~0); 2688#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2689#L170 assume !(1 == ~m_pc~0); 2814#L170-2 is_master_triggered_~__retres1~0 := 0; 2815#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2762#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2763#L429 assume !(0 != activate_threads_~tmp~1); 2809#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2816#L189 assume !(1 == ~t1_pc~0); 2911#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 2912#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2889#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2890#L437 assume !(0 != activate_threads_~tmp___0~0); 2905#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2681#L208 assume !(1 == ~t2_pc~0); 2682#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 2684#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2685#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2781#L445 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2834#L445-2 assume !(1 == ~M_E~0); 2836#L386-1 assume !(1 == ~T1_E~0); 2765#L391-1 assume !(1 == ~T2_E~0); 2766#L396-1 assume !(1 == ~E_M~0); 2817#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2716#L406-1 assume !(1 == ~E_2~0); 2717#L557-1 [2020-10-26 05:46:33,034 INFO L796 eck$LassoCheckResult]: Loop: 2717#L557-1 assume !false; 2847#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2720#L323 assume !false; 2721#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2786#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2738#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2785#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2731#L290 assume !(0 != eval_~tmp~0); 2732#L338 start_simulation_~kernel_st~0 := 2; 2907#L228-1 start_simulation_~kernel_st~0 := 3; 2846#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2840#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2841#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2751#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2752#L363-3 assume !(0 == ~E_1~0); 2792#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2700#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2701#L170-12 assume !(1 == ~m_pc~0); 2779#L170-14 is_master_triggered_~__retres1~0 := 0; 2780#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2810#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2782#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2783#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2787#L189-12 assume !(1 == ~t1_pc~0); 2901#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 3286#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3285#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3284#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3283#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2837#L208-12 assume 1 == ~t2_pc~0; 2798#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2704#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2705#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2800#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2825#L445-14 assume 1 == ~M_E~0;~M_E~0 := 2; 2827#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2749#L391-3 assume !(1 == ~T2_E~0); 2750#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2788#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2693#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2694#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2724#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2735#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2784#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2740#L576 assume !(0 == start_simulation_~tmp~3); 2741#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2743#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2747#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2778#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 2848#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2718#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 2719#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2776#L589 assume !(0 != start_simulation_~tmp___0~1); 2717#L557-1 [2020-10-26 05:46:33,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:33,036 INFO L82 PathProgramCache]: Analyzing trace with hash 545629540, now seen corresponding path program 1 times [2020-10-26 05:46:33,042 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:33,043 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912064] [2020-10-26 05:46:33,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:33,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:33,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:33,125 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1912064] [2020-10-26 05:46:33,125 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:33,125 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:46:33,126 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690379554] [2020-10-26 05:46:33,126 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:33,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:33,127 INFO L82 PathProgramCache]: Analyzing trace with hash -2080819508, now seen corresponding path program 1 times [2020-10-26 05:46:33,127 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:33,128 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068071702] [2020-10-26 05:46:33,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:33,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:33,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:33,193 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068071702] [2020-10-26 05:46:33,194 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:33,194 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:33,194 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363927640] [2020-10-26 05:46:33,195 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:33,195 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:33,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:46:33,196 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:46:33,196 INFO L87 Difference]: Start difference. First operand 633 states and 937 transitions. cyclomatic complexity: 306 Second operand 5 states. [2020-10-26 05:46:33,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:33,349 INFO L93 Difference]: Finished difference Result 1484 states and 2208 transitions. [2020-10-26 05:46:33,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-10-26 05:46:33,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1484 states and 2208 transitions. [2020-10-26 05:46:33,377 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1426 [2020-10-26 05:46:33,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1484 states to 1484 states and 2208 transitions. [2020-10-26 05:46:33,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1484 [2020-10-26 05:46:33,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1484 [2020-10-26 05:46:33,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1484 states and 2208 transitions. [2020-10-26 05:46:33,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:33,398 INFO L691 BuchiCegarLoop]: Abstraction has 1484 states and 2208 transitions. [2020-10-26 05:46:33,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1484 states and 2208 transitions. [2020-10-26 05:46:33,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1484 to 684. [2020-10-26 05:46:33,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 684 states. [2020-10-26 05:46:33,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 684 states to 684 states and 988 transitions. [2020-10-26 05:46:33,421 INFO L714 BuchiCegarLoop]: Abstraction has 684 states and 988 transitions. [2020-10-26 05:46:33,422 INFO L594 BuchiCegarLoop]: Abstraction has 684 states and 988 transitions. [2020-10-26 05:46:33,422 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-10-26 05:46:33,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 684 states and 988 transitions. [2020-10-26 05:46:33,428 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2020-10-26 05:46:33,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:33,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:33,430 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:33,430 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:33,430 INFO L794 eck$LassoCheckResult]: Stem: 4928#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4816#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4817#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5064#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 4856#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4857#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4864#L245-1 assume !(0 == ~M_E~0); 5006#L348-1 assume !(0 == ~T1_E~0); 5007#L353-1 assume !(0 == ~T2_E~0); 4898#L358-1 assume !(0 == ~E_M~0); 4899#L363-1 assume !(0 == ~E_1~0); 4966#L368-1 assume !(0 == ~E_2~0); 4818#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4819#L170 assume !(1 == ~m_pc~0); 4960#L170-2 is_master_triggered_~__retres1~0 := 0; 4961#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4893#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4894#L429 assume !(0 != activate_threads_~tmp~1); 4954#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4962#L189 assume !(1 == ~t1_pc~0); 5084#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 5085#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5054#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5055#L437 assume !(0 != activate_threads_~tmp___0~0); 5076#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4811#L208 assume !(1 == ~t2_pc~0); 4812#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 4814#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4815#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4990#L445 assume !(0 != activate_threads_~tmp___1~0); 4991#L445-2 assume !(1 == ~M_E~0); 4995#L386-1 assume !(1 == ~T1_E~0); 4896#L391-1 assume !(1 == ~T2_E~0); 4897#L396-1 assume !(1 == ~E_M~0); 4963#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4847#L406-1 assume !(1 == ~E_2~0); 4848#L557-1 [2020-10-26 05:46:33,431 INFO L796 eck$LassoCheckResult]: Loop: 4848#L557-1 assume !false; 5082#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4851#L323 assume !false; 4852#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4925#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4869#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4924#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4862#L290 assume !(0 != eval_~tmp~0); 4863#L338 start_simulation_~kernel_st~0 := 2; 5077#L228-1 start_simulation_~kernel_st~0 := 3; 5008#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5002#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5003#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4882#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4883#L363-3 assume !(0 == ~E_1~0); 4929#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4830#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4831#L170-12 assume !(1 == ~m_pc~0); 4917#L170-14 is_master_triggered_~__retres1~0 := 0; 4918#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4955#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4921#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4922#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4926#L189-12 assume !(1 == ~t1_pc~0); 5066#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 5067#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5033#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5034#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5063#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4997#L208-12 assume !(1 == ~t2_pc~0); 4998#L208-14 is_transmit2_triggered_~__retres1~2 := 0; 5488#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5486#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5484#L445-12 assume !(0 != activate_threads_~tmp___1~0); 5482#L445-14 assume 1 == ~M_E~0;~M_E~0 := 2; 5481#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4880#L391-3 assume !(1 == ~T2_E~0); 4881#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4927#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5479#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5462#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5458#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5454#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5443#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 4871#L576 assume !(0 == start_simulation_~tmp~3); 4872#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4874#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5456#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5453#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 5445#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5442#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 5441#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 5440#L589 assume !(0 != start_simulation_~tmp___0~1); 4848#L557-1 [2020-10-26 05:46:33,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:33,432 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330394, now seen corresponding path program 1 times [2020-10-26 05:46:33,432 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:33,432 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251254216] [2020-10-26 05:46:33,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:33,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:33,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:33,475 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251254216] [2020-10-26 05:46:33,475 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:33,476 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:33,476 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791601083] [2020-10-26 05:46:33,476 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:33,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:33,477 INFO L82 PathProgramCache]: Analyzing trace with hash -193895639, now seen corresponding path program 1 times [2020-10-26 05:46:33,478 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:33,478 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730617671] [2020-10-26 05:46:33,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:33,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:33,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:33,508 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1730617671] [2020-10-26 05:46:33,508 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:33,508 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:33,508 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770713856] [2020-10-26 05:46:33,509 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:33,509 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:33,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:33,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:33,510 INFO L87 Difference]: Start difference. First operand 684 states and 988 transitions. cyclomatic complexity: 306 Second operand 4 states. [2020-10-26 05:46:33,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:33,637 INFO L93 Difference]: Finished difference Result 1103 states and 1562 transitions. [2020-10-26 05:46:33,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:33,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1103 states and 1562 transitions. [2020-10-26 05:46:33,648 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 994 [2020-10-26 05:46:33,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1103 states to 1103 states and 1562 transitions. [2020-10-26 05:46:33,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1103 [2020-10-26 05:46:33,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1103 [2020-10-26 05:46:33,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1103 states and 1562 transitions. [2020-10-26 05:46:33,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:33,663 INFO L691 BuchiCegarLoop]: Abstraction has 1103 states and 1562 transitions. [2020-10-26 05:46:33,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1103 states and 1562 transitions. [2020-10-26 05:46:33,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1103 to 1083. [2020-10-26 05:46:33,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1083 states. [2020-10-26 05:46:33,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1083 states to 1083 states and 1538 transitions. [2020-10-26 05:46:33,686 INFO L714 BuchiCegarLoop]: Abstraction has 1083 states and 1538 transitions. [2020-10-26 05:46:33,686 INFO L594 BuchiCegarLoop]: Abstraction has 1083 states and 1538 transitions. [2020-10-26 05:46:33,686 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-10-26 05:46:33,687 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1083 states and 1538 transitions. [2020-10-26 05:46:33,693 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 980 [2020-10-26 05:46:33,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:33,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:33,697 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:33,698 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:33,698 INFO L794 eck$LassoCheckResult]: Stem: 6721#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 6613#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6614#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6851#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 6653#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6654#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6661#L245-1 assume 0 == ~M_E~0;~M_E~0 := 1; 6791#L348-1 assume !(0 == ~T1_E~0); 6792#L353-1 assume !(0 == ~T2_E~0); 7259#L358-1 assume !(0 == ~E_M~0); 7258#L363-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6760#L368-1 assume !(0 == ~E_2~0); 7233#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7232#L170 assume !(1 == ~m_pc~0); 7231#L170-2 is_master_triggered_~__retres1~0 := 0; 7230#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7229#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7228#L429 assume !(0 != activate_threads_~tmp~1); 7227#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7226#L189 assume !(1 == ~t1_pc~0); 7225#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 7224#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7223#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7222#L437 assume !(0 != activate_threads_~tmp___0~0); 7221#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7220#L208 assume !(1 == ~t2_pc~0); 7219#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 7235#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7234#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7214#L445 assume !(0 != activate_threads_~tmp___1~0); 7213#L445-2 assume !(1 == ~M_E~0); 7212#L386-1 assume !(1 == ~T1_E~0); 7211#L391-1 assume !(1 == ~T2_E~0); 7210#L396-1 assume !(1 == ~E_M~0); 7209#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6644#L406-1 assume !(1 == ~E_2~0); 6645#L557-1 [2020-10-26 05:46:33,698 INFO L796 eck$LassoCheckResult]: Loop: 6645#L557-1 assume !false; 6795#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6790#L323 assume !false; 6717#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6718#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6666#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6716#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 6659#L290 assume !(0 != eval_~tmp~0); 6660#L338 start_simulation_~kernel_st~0 := 2; 7678#L228-1 start_simulation_~kernel_st~0 := 3; 7677#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6794#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7674#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7671#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7670#L363-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6723#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7427#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7397#L170-12 assume !(1 == ~m_pc~0); 7390#L170-14 is_master_triggered_~__retres1~0 := 0; 7385#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7381#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7380#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7379#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7377#L189-12 assume !(1 == ~t1_pc~0); 7376#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 7375#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7374#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7373#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7372#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7371#L208-12 assume 1 == ~t2_pc~0; 7369#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7367#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7365#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7363#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7362#L445-14 assume 1 == ~M_E~0;~M_E~0 := 2; 7361#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7360#L391-3 assume !(1 == ~T2_E~0); 7359#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7358#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6620#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6621#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6652#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6663#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6715#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 6668#L576 assume !(0 == start_simulation_~tmp~3); 6669#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6671#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6675#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6708#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 6796#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6646#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 6647#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6706#L589 assume !(0 != start_simulation_~tmp___0~1); 6645#L557-1 [2020-10-26 05:46:33,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:33,699 INFO L82 PathProgramCache]: Analyzing trace with hash -2059002262, now seen corresponding path program 1 times [2020-10-26 05:46:33,700 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:33,704 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722666382] [2020-10-26 05:46:33,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:33,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:33,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:33,746 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722666382] [2020-10-26 05:46:33,746 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:33,746 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:33,746 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887917633] [2020-10-26 05:46:33,747 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:33,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:33,750 INFO L82 PathProgramCache]: Analyzing trace with hash -235452342, now seen corresponding path program 1 times [2020-10-26 05:46:33,751 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:33,751 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853470345] [2020-10-26 05:46:33,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:33,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:33,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:33,797 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853470345] [2020-10-26 05:46:33,797 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:33,797 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:33,798 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19924932] [2020-10-26 05:46:33,798 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:33,798 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:33,799 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:33,799 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:33,799 INFO L87 Difference]: Start difference. First operand 1083 states and 1538 transitions. cyclomatic complexity: 458 Second operand 3 states. [2020-10-26 05:46:33,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:33,831 INFO L93 Difference]: Finished difference Result 1713 states and 2430 transitions. [2020-10-26 05:46:33,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:33,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1713 states and 2430 transitions. [2020-10-26 05:46:33,847 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1640 [2020-10-26 05:46:33,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1713 states to 1713 states and 2430 transitions. [2020-10-26 05:46:33,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1713 [2020-10-26 05:46:33,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1713 [2020-10-26 05:46:33,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1713 states and 2430 transitions. [2020-10-26 05:46:33,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:33,866 INFO L691 BuchiCegarLoop]: Abstraction has 1713 states and 2430 transitions. [2020-10-26 05:46:33,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1713 states and 2430 transitions. [2020-10-26 05:46:33,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1713 to 1488. [2020-10-26 05:46:33,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1488 states. [2020-10-26 05:46:33,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 2115 transitions. [2020-10-26 05:46:33,919 INFO L714 BuchiCegarLoop]: Abstraction has 1488 states and 2115 transitions. [2020-10-26 05:46:33,919 INFO L594 BuchiCegarLoop]: Abstraction has 1488 states and 2115 transitions. [2020-10-26 05:46:33,919 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-10-26 05:46:33,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1488 states and 2115 transitions. [2020-10-26 05:46:33,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1416 [2020-10-26 05:46:33,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:33,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:33,932 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:33,933 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:33,933 INFO L794 eck$LassoCheckResult]: Stem: 9526#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 9416#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9417#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9660#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 9457#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9458#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9466#L245-1 assume !(0 == ~M_E~0); 9600#L348-1 assume !(0 == ~T1_E~0); 9601#L353-1 assume !(0 == ~T2_E~0); 9501#L358-1 assume !(0 == ~E_M~0); 9502#L363-1 assume 0 == ~E_1~0;~E_1~0 := 1; 9567#L368-1 assume !(0 == ~E_2~0); 9418#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9419#L170 assume !(1 == ~m_pc~0); 9583#L170-2 is_master_triggered_~__retres1~0 := 0; 9757#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9496#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9497#L429 assume !(0 != activate_threads_~tmp~1); 9560#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9561#L189 assume !(1 == ~t1_pc~0); 9684#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 9685#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9688#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9706#L437 assume !(0 != activate_threads_~tmp___0~0); 9704#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9411#L208 assume !(1 == ~t2_pc~0); 9412#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 9414#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9415#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9518#L445 assume !(0 != activate_threads_~tmp___1~0); 9586#L445-2 assume !(1 == ~M_E~0); 9590#L386-1 assume !(1 == ~T1_E~0); 9696#L391-1 assume !(1 == ~T2_E~0); 9695#L396-1 assume !(1 == ~E_M~0); 9694#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9447#L406-1 assume !(1 == ~E_2~0); 9448#L557-1 [2020-10-26 05:46:33,933 INFO L796 eck$LassoCheckResult]: Loop: 9448#L557-1 assume !false; 9683#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9451#L323 assume !false; 9452#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9523#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9471#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9522#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 9464#L290 assume !(0 != eval_~tmp~0); 9465#L338 start_simulation_~kernel_st~0 := 2; 10880#L228-1 start_simulation_~kernel_st~0 := 3; 10879#L348-2 assume !(0 == ~M_E~0); 10877#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10875#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10874#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10873#L363-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10769#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10770#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10765#L170-12 assume !(1 == ~m_pc~0); 10766#L170-14 is_master_triggered_~__retres1~0 := 0; 10754#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10755#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10746#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10747#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10739#L189-12 assume !(1 == ~t1_pc~0); 10738#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 10736#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10735#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10734#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10733#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10731#L208-12 assume !(1 == ~t2_pc~0); 10727#L208-14 is_transmit2_triggered_~__retres1~2 := 0; 10725#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10723#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10721#L445-12 assume !(0 != activate_threads_~tmp___1~0); 10718#L445-14 assume !(1 == ~M_E~0); 10382#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10716#L391-3 assume !(1 == ~T2_E~0); 10715#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10683#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10681#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10680#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10659#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10656#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10624#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9792#L576 assume !(0 == start_simulation_~tmp~3); 9793#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10801#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10798#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10797#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 10796#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10795#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 10793#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10791#L589 assume !(0 != start_simulation_~tmp___0~1); 9448#L557-1 [2020-10-26 05:46:33,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:33,934 INFO L82 PathProgramCache]: Analyzing trace with hash -2036370008, now seen corresponding path program 1 times [2020-10-26 05:46:33,934 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:33,934 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075943749] [2020-10-26 05:46:33,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:33,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:33,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:33,977 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075943749] [2020-10-26 05:46:33,977 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:33,977 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:33,977 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463882274] [2020-10-26 05:46:33,978 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:33,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:33,978 INFO L82 PathProgramCache]: Analyzing trace with hash -934865493, now seen corresponding path program 1 times [2020-10-26 05:46:33,978 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:33,978 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784414631] [2020-10-26 05:46:33,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:33,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:34,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:34,006 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784414631] [2020-10-26 05:46:34,007 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:34,007 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:34,007 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280253618] [2020-10-26 05:46:34,007 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:34,008 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:34,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:34,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:34,009 INFO L87 Difference]: Start difference. First operand 1488 states and 2115 transitions. cyclomatic complexity: 629 Second operand 4 states. [2020-10-26 05:46:34,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:34,077 INFO L93 Difference]: Finished difference Result 1462 states and 2057 transitions. [2020-10-26 05:46:34,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:34,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1462 states and 2057 transitions. [2020-10-26 05:46:34,089 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1412 [2020-10-26 05:46:34,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1462 states to 1462 states and 2057 transitions. [2020-10-26 05:46:34,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1462 [2020-10-26 05:46:34,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1462 [2020-10-26 05:46:34,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1462 states and 2057 transitions. [2020-10-26 05:46:34,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:34,104 INFO L691 BuchiCegarLoop]: Abstraction has 1462 states and 2057 transitions. [2020-10-26 05:46:34,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1462 states and 2057 transitions. [2020-10-26 05:46:34,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1462 to 1232. [2020-10-26 05:46:34,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1232 states. [2020-10-26 05:46:34,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1232 states to 1232 states and 1740 transitions. [2020-10-26 05:46:34,126 INFO L714 BuchiCegarLoop]: Abstraction has 1232 states and 1740 transitions. [2020-10-26 05:46:34,127 INFO L594 BuchiCegarLoop]: Abstraction has 1232 states and 1740 transitions. [2020-10-26 05:46:34,127 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-10-26 05:46:34,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1232 states and 1740 transitions. [2020-10-26 05:46:34,145 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1188 [2020-10-26 05:46:34,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:34,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:34,146 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,146 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,147 INFO L794 eck$LassoCheckResult]: Stem: 12487#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12376#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12377#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12603#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 12416#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12417#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12425#L245-1 assume !(0 == ~M_E~0); 12549#L348-1 assume !(0 == ~T1_E~0); 12550#L353-1 assume !(0 == ~T2_E~0); 12461#L358-1 assume !(0 == ~E_M~0); 12462#L363-1 assume !(0 == ~E_1~0); 12523#L368-1 assume !(0 == ~E_2~0); 12378#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12379#L170 assume !(1 == ~m_pc~0); 12517#L170-2 is_master_triggered_~__retres1~0 := 0; 12518#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12455#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12456#L429 assume !(0 != activate_threads_~tmp~1); 12510#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12519#L189 assume !(1 == ~t1_pc~0); 12618#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 12619#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12595#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12596#L437 assume !(0 != activate_threads_~tmp___0~0); 12610#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12371#L208 assume !(1 == ~t2_pc~0); 12372#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 12374#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12375#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12477#L445 assume !(0 != activate_threads_~tmp___1~0); 12538#L445-2 assume !(1 == ~M_E~0); 12541#L386-1 assume !(1 == ~T1_E~0); 12459#L391-1 assume !(1 == ~T2_E~0); 12460#L396-1 assume !(1 == ~E_M~0); 12520#L401-1 assume !(1 == ~E_1~0); 12407#L406-1 assume !(1 == ~E_2~0); 12408#L557-1 [2020-10-26 05:46:34,147 INFO L796 eck$LassoCheckResult]: Loop: 12408#L557-1 assume !false; 13530#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13528#L323 assume !false; 13526#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13520#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13518#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13517#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 13488#L290 assume !(0 != eval_~tmp~0); 12611#L338 start_simulation_~kernel_st~0 := 2; 12612#L228-1 start_simulation_~kernel_st~0 := 3; 12551#L348-2 assume !(0 == ~M_E~0); 12545#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12546#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12444#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12445#L363-3 assume !(0 == ~E_1~0); 12488#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12390#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12391#L170-12 assume !(1 == ~m_pc~0); 12478#L170-14 is_master_triggered_~__retres1~0 := 0; 12479#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12511#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12480#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12481#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12485#L189-12 assume !(1 == ~t1_pc~0); 12606#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 13544#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13543#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13542#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13539#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13537#L208-12 assume !(1 == ~t2_pc~0); 13534#L208-14 is_transmit2_triggered_~__retres1~2 := 0; 13529#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13527#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13525#L445-12 assume !(0 != activate_threads_~tmp___1~0); 13523#L445-14 assume !(1 == ~M_E~0); 13315#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13519#L391-3 assume !(1 == ~T2_E~0); 13489#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13350#L401-3 assume !(1 == ~E_1~0); 13349#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13348#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13344#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13342#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13292#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12663#L576 assume !(0 == start_simulation_~tmp~3); 12664#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13567#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13564#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13563#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 13562#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13561#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 13559#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 13558#L589 assume !(0 != start_simulation_~tmp___0~1); 12408#L557-1 [2020-10-26 05:46:34,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 1 times [2020-10-26 05:46:34,147 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,148 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866345596] [2020-10-26 05:46:34,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:34,158 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:34,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:34,166 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:34,198 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:34,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,199 INFO L82 PathProgramCache]: Analyzing trace with hash 234870959, now seen corresponding path program 1 times [2020-10-26 05:46:34,199 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,199 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537409401] [2020-10-26 05:46:34,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:34,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:34,225 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537409401] [2020-10-26 05:46:34,225 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:34,225 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:34,225 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873091163] [2020-10-26 05:46:34,226 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:34,226 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:34,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:34,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:34,227 INFO L87 Difference]: Start difference. First operand 1232 states and 1740 transitions. cyclomatic complexity: 510 Second operand 3 states. [2020-10-26 05:46:34,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:34,254 INFO L93 Difference]: Finished difference Result 1492 states and 2088 transitions. [2020-10-26 05:46:34,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:34,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1492 states and 2088 transitions. [2020-10-26 05:46:34,266 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1420 [2020-10-26 05:46:34,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1492 states to 1492 states and 2088 transitions. [2020-10-26 05:46:34,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1492 [2020-10-26 05:46:34,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1492 [2020-10-26 05:46:34,279 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1492 states and 2088 transitions. [2020-10-26 05:46:34,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:34,281 INFO L691 BuchiCegarLoop]: Abstraction has 1492 states and 2088 transitions. [2020-10-26 05:46:34,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1492 states and 2088 transitions. [2020-10-26 05:46:34,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1492 to 1492. [2020-10-26 05:46:34,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1492 states. [2020-10-26 05:46:34,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1492 states to 1492 states and 2088 transitions. [2020-10-26 05:46:34,309 INFO L714 BuchiCegarLoop]: Abstraction has 1492 states and 2088 transitions. [2020-10-26 05:46:34,310 INFO L594 BuchiCegarLoop]: Abstraction has 1492 states and 2088 transitions. [2020-10-26 05:46:34,310 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-10-26 05:46:34,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1492 states and 2088 transitions. [2020-10-26 05:46:34,318 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1420 [2020-10-26 05:46:34,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:34,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:34,320 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,320 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,320 INFO L794 eck$LassoCheckResult]: Stem: 15215#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 15106#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 15107#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15342#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 15146#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15147#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15154#L245-1 assume !(0 == ~M_E~0); 15286#L348-1 assume !(0 == ~T1_E~0); 15287#L353-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15303#L358-1 assume !(0 == ~E_M~0); 15254#L363-1 assume !(0 == ~E_1~0); 15255#L368-1 assume !(0 == ~E_2~0); 15279#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15402#L170 assume !(1 == ~m_pc~0); 15244#L170-2 is_master_triggered_~__retres1~0 := 0; 15245#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15271#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15237#L429 assume !(0 != activate_threads_~tmp~1); 15238#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15370#L189 assume !(1 == ~t1_pc~0); 15371#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 15372#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15373#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15400#L437 assume !(0 != activate_threads_~tmp___0~0); 15355#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15356#L208 assume !(1 == ~t2_pc~0); 15132#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 15104#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15105#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15206#L445 assume !(0 != activate_threads_~tmp___1~0); 15272#L445-2 assume !(1 == ~M_E~0); 15276#L386-1 assume !(1 == ~T1_E~0); 15187#L391-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15188#L396-1 assume !(1 == ~E_M~0); 15248#L401-1 assume !(1 == ~E_1~0); 15137#L406-1 assume !(1 == ~E_2~0); 15138#L557-1 [2020-10-26 05:46:34,320 INFO L796 eck$LassoCheckResult]: Loop: 15138#L557-1 assume !false; 15289#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 15141#L323 assume !false; 15142#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15212#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15159#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15211#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 15152#L290 assume !(0 != eval_~tmp~0); 15153#L338 start_simulation_~kernel_st~0 := 2; 16589#L228-1 start_simulation_~kernel_st~0 := 3; 16588#L348-2 assume !(0 == ~M_E~0); 16587#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16585#L353-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16584#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16582#L363-3 assume !(0 == ~E_1~0); 16580#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16578#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16576#L170-12 assume !(1 == ~m_pc~0); 16574#L170-14 is_master_triggered_~__retres1~0 := 0; 16572#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16570#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16568#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16566#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16508#L189-12 assume !(1 == ~t1_pc~0); 16506#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 16502#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16498#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16494#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16490#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16462#L208-12 assume !(1 == ~t2_pc~0); 16458#L208-14 is_transmit2_triggered_~__retres1~2 := 0; 16455#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16453#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16451#L445-12 assume !(0 != activate_threads_~tmp___1~0); 16443#L445-14 assume !(1 == ~M_E~0); 16438#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16436#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16434#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16432#L401-3 assume !(1 == ~E_1~0); 15113#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15114#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15143#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15672#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15673#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 15668#L576 assume !(0 == start_simulation_~tmp~3); 15164#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15165#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15169#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15200#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 15290#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15139#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 15140#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 15199#L589 assume !(0 != start_simulation_~tmp___0~1); 15138#L557-1 [2020-10-26 05:46:34,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,321 INFO L82 PathProgramCache]: Analyzing trace with hash -1464916824, now seen corresponding path program 1 times [2020-10-26 05:46:34,321 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,321 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131664130] [2020-10-26 05:46:34,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:34,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:34,344 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131664130] [2020-10-26 05:46:34,345 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:34,345 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:34,345 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051306416] [2020-10-26 05:46:34,346 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:34,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1823218861, now seen corresponding path program 1 times [2020-10-26 05:46:34,346 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,346 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022974171] [2020-10-26 05:46:34,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:34,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:34,394 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022974171] [2020-10-26 05:46:34,395 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:34,395 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:46:34,395 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8835762] [2020-10-26 05:46:34,396 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:34,396 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:34,396 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:34,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:34,397 INFO L87 Difference]: Start difference. First operand 1492 states and 2088 transitions. cyclomatic complexity: 598 Second operand 4 states. [2020-10-26 05:46:34,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:34,466 INFO L93 Difference]: Finished difference Result 1763 states and 2472 transitions. [2020-10-26 05:46:34,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:34,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1763 states and 2472 transitions. [2020-10-26 05:46:34,482 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1714 [2020-10-26 05:46:34,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1763 states to 1763 states and 2472 transitions. [2020-10-26 05:46:34,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1763 [2020-10-26 05:46:34,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1763 [2020-10-26 05:46:34,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1763 states and 2472 transitions. [2020-10-26 05:46:34,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:34,502 INFO L691 BuchiCegarLoop]: Abstraction has 1763 states and 2472 transitions. [2020-10-26 05:46:34,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1763 states and 2472 transitions. [2020-10-26 05:46:34,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1763 to 1232. [2020-10-26 05:46:34,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1232 states. [2020-10-26 05:46:34,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1232 states to 1232 states and 1731 transitions. [2020-10-26 05:46:34,531 INFO L714 BuchiCegarLoop]: Abstraction has 1232 states and 1731 transitions. [2020-10-26 05:46:34,531 INFO L594 BuchiCegarLoop]: Abstraction has 1232 states and 1731 transitions. [2020-10-26 05:46:34,531 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-10-26 05:46:34,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1232 states and 1731 transitions. [2020-10-26 05:46:34,538 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1188 [2020-10-26 05:46:34,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:34,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:34,539 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,539 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,540 INFO L794 eck$LassoCheckResult]: Stem: 18483#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 18373#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 18374#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18604#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 18412#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18413#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18421#L245-1 assume !(0 == ~M_E~0); 18555#L348-1 assume !(0 == ~T1_E~0); 18556#L353-1 assume !(0 == ~T2_E~0); 18457#L358-1 assume !(0 == ~E_M~0); 18458#L363-1 assume !(0 == ~E_1~0); 18524#L368-1 assume !(0 == ~E_2~0); 18375#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18376#L170 assume !(1 == ~m_pc~0); 18518#L170-2 is_master_triggered_~__retres1~0 := 0; 18519#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18451#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18452#L429 assume !(0 != activate_threads_~tmp~1); 18511#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18520#L189 assume !(1 == ~t1_pc~0); 18624#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 18625#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18595#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18596#L437 assume !(0 != activate_threads_~tmp___0~0); 18615#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18368#L208 assume !(1 == ~t2_pc~0); 18369#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 18371#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18372#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 18472#L445 assume !(0 != activate_threads_~tmp___1~0); 18541#L445-2 assume !(1 == ~M_E~0); 18547#L386-1 assume !(1 == ~T1_E~0); 18455#L391-1 assume !(1 == ~T2_E~0); 18456#L396-1 assume !(1 == ~E_M~0); 18521#L401-1 assume !(1 == ~E_1~0); 18403#L406-1 assume !(1 == ~E_2~0); 18404#L557-1 [2020-10-26 05:46:34,540 INFO L796 eck$LassoCheckResult]: Loop: 18404#L557-1 assume !false; 18914#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 18912#L323 assume !false; 18909#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 18905#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 18903#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18901#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 18898#L290 assume !(0 != eval_~tmp~0); 18899#L338 start_simulation_~kernel_st~0 := 2; 19205#L228-1 start_simulation_~kernel_st~0 := 3; 19204#L348-2 assume !(0 == ~M_E~0); 19203#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19202#L353-3 assume !(0 == ~T2_E~0); 19201#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19200#L363-3 assume !(0 == ~E_1~0); 19199#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19198#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19197#L170-12 assume !(1 == ~m_pc~0); 19196#L170-14 is_master_triggered_~__retres1~0 := 0; 19195#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19194#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 19193#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19192#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19190#L189-12 assume !(1 == ~t1_pc~0); 18829#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 19187#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19185#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19183#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19181#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19180#L208-12 assume 1 == ~t2_pc~0; 19178#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 19176#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19174#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19172#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 19133#L445-14 assume !(1 == ~M_E~0); 19055#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19009#L391-3 assume !(1 == ~T2_E~0); 19008#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19007#L401-3 assume !(1 == ~E_1~0); 19003#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18999#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 18995#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 18981#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18974#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 18969#L576 assume !(0 == start_simulation_~tmp~3); 18966#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 18964#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 18960#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18959#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 18958#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18957#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 18955#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 18953#L589 assume !(0 != start_simulation_~tmp___0~1); 18404#L557-1 [2020-10-26 05:46:34,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,540 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 2 times [2020-10-26 05:46:34,541 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,541 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168567022] [2020-10-26 05:46:34,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:34,551 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:34,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:34,559 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:34,569 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:34,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,570 INFO L82 PathProgramCache]: Analyzing trace with hash -1228406188, now seen corresponding path program 1 times [2020-10-26 05:46:34,570 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,570 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959454177] [2020-10-26 05:46:34,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:34,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:34,600 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959454177] [2020-10-26 05:46:34,600 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:34,600 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:46:34,600 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475478158] [2020-10-26 05:46:34,601 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:34,601 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:34,601 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:46:34,601 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:46:34,601 INFO L87 Difference]: Start difference. First operand 1232 states and 1731 transitions. cyclomatic complexity: 501 Second operand 5 states. [2020-10-26 05:46:34,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:34,723 INFO L93 Difference]: Finished difference Result 2120 states and 2933 transitions. [2020-10-26 05:46:34,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-10-26 05:46:34,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2120 states and 2933 transitions. [2020-10-26 05:46:34,737 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2072 [2020-10-26 05:46:34,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2120 states to 2120 states and 2933 transitions. [2020-10-26 05:46:34,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2120 [2020-10-26 05:46:34,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2120 [2020-10-26 05:46:34,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2120 states and 2933 transitions. [2020-10-26 05:46:34,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:34,760 INFO L691 BuchiCegarLoop]: Abstraction has 2120 states and 2933 transitions. [2020-10-26 05:46:34,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2120 states and 2933 transitions. [2020-10-26 05:46:34,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2120 to 1256. [2020-10-26 05:46:34,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1256 states. [2020-10-26 05:46:34,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1256 states to 1256 states and 1755 transitions. [2020-10-26 05:46:34,796 INFO L714 BuchiCegarLoop]: Abstraction has 1256 states and 1755 transitions. [2020-10-26 05:46:34,796 INFO L594 BuchiCegarLoop]: Abstraction has 1256 states and 1755 transitions. [2020-10-26 05:46:34,796 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-10-26 05:46:34,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1256 states and 1755 transitions. [2020-10-26 05:46:34,801 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1212 [2020-10-26 05:46:34,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:34,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:34,802 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,802 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,802 INFO L794 eck$LassoCheckResult]: Stem: 21854#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21741#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21742#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21987#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 21781#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21782#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21788#L245-1 assume !(0 == ~M_E~0); 21928#L348-1 assume !(0 == ~T1_E~0); 21929#L353-1 assume !(0 == ~T2_E~0); 21824#L358-1 assume !(0 == ~E_M~0); 21825#L363-1 assume !(0 == ~E_1~0); 21894#L368-1 assume !(0 == ~E_2~0); 21743#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21744#L170 assume !(1 == ~m_pc~0); 21886#L170-2 is_master_triggered_~__retres1~0 := 0; 21887#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21818#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21819#L429 assume !(0 != activate_threads_~tmp~1); 21878#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21888#L189 assume !(1 == ~t1_pc~0); 22005#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 22006#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21979#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21980#L437 assume !(0 != activate_threads_~tmp___0~0); 21996#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21736#L208 assume !(1 == ~t2_pc~0); 21737#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 21739#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21740#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21841#L445 assume !(0 != activate_threads_~tmp___1~0); 21913#L445-2 assume !(1 == ~M_E~0); 21916#L386-1 assume !(1 == ~T1_E~0); 21822#L391-1 assume !(1 == ~T2_E~0); 21823#L396-1 assume !(1 == ~E_M~0); 21889#L401-1 assume !(1 == ~E_1~0); 21771#L406-1 assume !(1 == ~E_2~0); 21772#L557-1 [2020-10-26 05:46:34,802 INFO L796 eck$LassoCheckResult]: Loop: 21772#L557-1 assume !false; 22962#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 21927#L323 assume !false; 21847#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 21848#L258 assume !(0 == ~m_st~0); 21792#L262 assume !(0 == ~t1_st~0); 21794#L266 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 21922#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22721#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 22722#L290 assume !(0 != eval_~tmp~0); 21997#L338 start_simulation_~kernel_st~0 := 2; 21998#L228-1 start_simulation_~kernel_st~0 := 3; 21930#L348-2 assume !(0 == ~M_E~0); 21931#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22896#L353-3 assume !(0 == ~T2_E~0); 22895#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22894#L363-3 assume !(0 == ~E_1~0); 22893#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22892#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21849#L170-12 assume !(1 == ~m_pc~0); 21839#L170-14 is_master_triggered_~__retres1~0 := 0; 21840#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21879#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22889#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21850#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21851#L189-12 assume !(1 == ~t1_pc~0); 21992#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 22009#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22010#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22887#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22886#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22885#L208-12 assume 1 == ~t2_pc~0; 21864#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 21866#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21867#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21868#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21900#L445-14 assume !(1 == ~M_E~0); 21902#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21957#L391-3 assume !(1 == ~T2_E~0); 21852#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21853#L401-3 assume !(1 == ~E_1~0); 21748#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21749#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 21914#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 21790#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 21934#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 21935#L576 assume !(0 == start_simulation_~tmp~3); 21798#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 21799#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22975#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22973#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 22972#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22971#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 22969#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 22967#L589 assume !(0 != start_simulation_~tmp___0~1); 21772#L557-1 [2020-10-26 05:46:34,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,803 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 3 times [2020-10-26 05:46:34,803 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,803 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225615805] [2020-10-26 05:46:34,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:34,814 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:34,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:34,827 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:34,846 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:34,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,847 INFO L82 PathProgramCache]: Analyzing trace with hash -1071572517, now seen corresponding path program 1 times [2020-10-26 05:46:34,847 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,847 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466500214] [2020-10-26 05:46:34,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:34,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:34,919 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466500214] [2020-10-26 05:46:34,919 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:34,919 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:46:34,919 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457077713] [2020-10-26 05:46:34,919 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:34,920 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:34,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:46:34,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:46:34,920 INFO L87 Difference]: Start difference. First operand 1256 states and 1755 transitions. cyclomatic complexity: 501 Second operand 5 states. [2020-10-26 05:46:35,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:35,083 INFO L93 Difference]: Finished difference Result 2474 states and 3430 transitions. [2020-10-26 05:46:35,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-10-26 05:46:35,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2474 states and 3430 transitions. [2020-10-26 05:46:35,099 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2430 [2020-10-26 05:46:35,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2474 states to 2474 states and 3430 transitions. [2020-10-26 05:46:35,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2474 [2020-10-26 05:46:35,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2474 [2020-10-26 05:46:35,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2474 states and 3430 transitions. [2020-10-26 05:46:35,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:35,138 INFO L691 BuchiCegarLoop]: Abstraction has 2474 states and 3430 transitions. [2020-10-26 05:46:35,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2474 states and 3430 transitions. [2020-10-26 05:46:35,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2474 to 1304. [2020-10-26 05:46:35,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1304 states. [2020-10-26 05:46:35,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1304 states to 1304 states and 1790 transitions. [2020-10-26 05:46:35,170 INFO L714 BuchiCegarLoop]: Abstraction has 1304 states and 1790 transitions. [2020-10-26 05:46:35,170 INFO L594 BuchiCegarLoop]: Abstraction has 1304 states and 1790 transitions. [2020-10-26 05:46:35,170 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-10-26 05:46:35,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1304 states and 1790 transitions. [2020-10-26 05:46:35,174 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1260 [2020-10-26 05:46:35,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:35,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:35,175 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,175 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,176 INFO L794 eck$LassoCheckResult]: Stem: 25594#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 25484#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 25485#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25734#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 25525#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25526#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25533#L245-1 assume !(0 == ~M_E~0); 25671#L348-1 assume !(0 == ~T1_E~0); 25672#L353-1 assume !(0 == ~T2_E~0); 25568#L358-1 assume !(0 == ~E_M~0); 25569#L363-1 assume !(0 == ~E_1~0); 25639#L368-1 assume !(0 == ~E_2~0); 25486#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25487#L170 assume !(1 == ~m_pc~0); 25629#L170-2 is_master_triggered_~__retres1~0 := 0; 25630#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25563#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25564#L429 assume !(0 != activate_threads_~tmp~1); 25620#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25631#L189 assume !(1 == ~t1_pc~0); 25748#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 25749#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25725#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25726#L437 assume !(0 != activate_threads_~tmp___0~0); 25741#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25479#L208 assume !(1 == ~t2_pc~0); 25480#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 25482#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25483#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25584#L445 assume !(0 != activate_threads_~tmp___1~0); 25656#L445-2 assume !(1 == ~M_E~0); 25659#L386-1 assume !(1 == ~T1_E~0); 25566#L391-1 assume !(1 == ~T2_E~0); 25567#L396-1 assume !(1 == ~E_M~0); 25632#L401-1 assume !(1 == ~E_1~0); 25515#L406-1 assume !(1 == ~E_2~0); 25516#L557-1 [2020-10-26 05:46:35,176 INFO L796 eck$LassoCheckResult]: Loop: 25516#L557-1 assume !false; 26195#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 26193#L323 assume !false; 26191#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 26186#L258 assume !(0 == ~m_st~0); 26187#L262 assume !(0 == ~t1_st~0); 26183#L266 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 26179#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 26092#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 26093#L290 assume !(0 != eval_~tmp~0); 26175#L338 start_simulation_~kernel_st~0 := 2; 26173#L228-1 start_simulation_~kernel_st~0 := 3; 26171#L348-2 assume !(0 == ~M_E~0); 26169#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26167#L353-3 assume !(0 == ~T2_E~0); 26165#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26163#L363-3 assume !(0 == ~E_1~0); 26161#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25499#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25500#L170-12 assume !(1 == ~m_pc~0); 25589#L170-14 is_master_triggered_~__retres1~0 := 0; 26157#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26155#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26153#L429-12 assume !(0 != activate_threads_~tmp~1); 26151#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26149#L189-12 assume !(1 == ~t1_pc~0); 25871#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 26145#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26142#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26139#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26135#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26132#L208-12 assume 1 == ~t2_pc~0; 26128#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 26123#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26118#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26103#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 26096#L445-14 assume !(1 == ~M_E~0); 25833#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25834#L391-3 assume !(1 == ~T2_E~0); 25827#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25828#L401-3 assume !(1 == ~E_1~0); 25820#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25821#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 25809#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 25808#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 25794#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 25795#L576 assume !(0 == start_simulation_~tmp~3); 26246#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 26232#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 26224#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 26218#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 26217#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 26214#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 26207#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 26203#L589 assume !(0 != start_simulation_~tmp___0~1); 25516#L557-1 [2020-10-26 05:46:35,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,176 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 4 times [2020-10-26 05:46:35,177 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,177 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974544216] [2020-10-26 05:46:35,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:35,186 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:35,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:35,193 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:35,201 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:35,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,202 INFO L82 PathProgramCache]: Analyzing trace with hash -796812903, now seen corresponding path program 1 times [2020-10-26 05:46:35,202 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,202 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596151246] [2020-10-26 05:46:35,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,229 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596151246] [2020-10-26 05:46:35,229 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,229 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,229 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49174851] [2020-10-26 05:46:35,230 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:35,230 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:35,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:35,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:35,231 INFO L87 Difference]: Start difference. First operand 1304 states and 1790 transitions. cyclomatic complexity: 488 Second operand 3 states. [2020-10-26 05:46:35,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:35,279 INFO L93 Difference]: Finished difference Result 1942 states and 2616 transitions. [2020-10-26 05:46:35,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:35,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1942 states and 2616 transitions. [2020-10-26 05:46:35,290 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1898 [2020-10-26 05:46:35,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1942 states to 1942 states and 2616 transitions. [2020-10-26 05:46:35,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1942 [2020-10-26 05:46:35,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1942 [2020-10-26 05:46:35,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1942 states and 2616 transitions. [2020-10-26 05:46:35,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:35,307 INFO L691 BuchiCegarLoop]: Abstraction has 1942 states and 2616 transitions. [2020-10-26 05:46:35,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1942 states and 2616 transitions. [2020-10-26 05:46:35,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1942 to 1872. [2020-10-26 05:46:35,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1872 states. [2020-10-26 05:46:35,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1872 states to 1872 states and 2526 transitions. [2020-10-26 05:46:35,340 INFO L714 BuchiCegarLoop]: Abstraction has 1872 states and 2526 transitions. [2020-10-26 05:46:35,340 INFO L594 BuchiCegarLoop]: Abstraction has 1872 states and 2526 transitions. [2020-10-26 05:46:35,340 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-10-26 05:46:35,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1872 states and 2526 transitions. [2020-10-26 05:46:35,347 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1828 [2020-10-26 05:46:35,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:35,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:35,348 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,348 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,348 INFO L794 eck$LassoCheckResult]: Stem: 28847#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 28736#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28737#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28983#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 28776#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28777#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28783#L245-1 assume !(0 == ~M_E~0); 28924#L348-1 assume !(0 == ~T1_E~0); 28925#L353-1 assume !(0 == ~T2_E~0); 28819#L358-1 assume !(0 == ~E_M~0); 28820#L363-1 assume !(0 == ~E_1~0); 28886#L368-1 assume !(0 == ~E_2~0); 28738#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28739#L170 assume !(1 == ~m_pc~0); 28880#L170-2 is_master_triggered_~__retres1~0 := 0; 28881#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28814#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 28815#L429 assume !(0 != activate_threads_~tmp~1); 28874#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28882#L189 assume !(1 == ~t1_pc~0); 29003#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 29004#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28974#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 28975#L437 assume !(0 != activate_threads_~tmp___0~0); 28991#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28731#L208 assume !(1 == ~t2_pc~0); 28732#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 28734#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28735#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 28834#L445 assume !(0 != activate_threads_~tmp___1~0); 28907#L445-2 assume !(1 == ~M_E~0); 28913#L386-1 assume !(1 == ~T1_E~0); 28817#L391-1 assume !(1 == ~T2_E~0); 28818#L396-1 assume !(1 == ~E_M~0); 28883#L401-1 assume !(1 == ~E_1~0); 28766#L406-1 assume !(1 == ~E_2~0); 28767#L557-1 assume !false; 29463#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 29456#L323 [2020-10-26 05:46:35,348 INFO L796 eck$LassoCheckResult]: Loop: 29456#L323 assume !false; 29453#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 29450#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 29448#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 29440#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 29441#L290 assume 0 != eval_~tmp~0; 29405#L290-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 29402#L298 assume !(0 != eval_~tmp_ndt_1~0); 29403#L295 assume !(0 == ~t1_st~0); 29467#L309 assume !(0 == ~t2_st~0); 29456#L323 [2020-10-26 05:46:35,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,349 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 1 times [2020-10-26 05:46:35,349 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,349 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854119968] [2020-10-26 05:46:35,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:35,358 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:35,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:35,365 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:35,372 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:35,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,373 INFO L82 PathProgramCache]: Analyzing trace with hash -1924930091, now seen corresponding path program 1 times [2020-10-26 05:46:35,373 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,374 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532649383] [2020-10-26 05:46:35,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:35,396 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:35,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:35,399 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:35,403 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:35,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,404 INFO L82 PathProgramCache]: Analyzing trace with hash -460288806, now seen corresponding path program 1 times [2020-10-26 05:46:35,405 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,408 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53917314] [2020-10-26 05:46:35,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,445 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53917314] [2020-10-26 05:46:35,445 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,445 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,446 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074825859] [2020-10-26 05:46:35,512 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:35,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:35,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:35,513 INFO L87 Difference]: Start difference. First operand 1872 states and 2526 transitions. cyclomatic complexity: 657 Second operand 3 states. [2020-10-26 05:46:35,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:35,574 INFO L93 Difference]: Finished difference Result 3336 states and 4454 transitions. [2020-10-26 05:46:35,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:35,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3336 states and 4454 transitions. [2020-10-26 05:46:35,594 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3253 [2020-10-26 05:46:35,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3336 states to 3336 states and 4454 transitions. [2020-10-26 05:46:35,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3336 [2020-10-26 05:46:35,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3336 [2020-10-26 05:46:35,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3336 states and 4454 transitions. [2020-10-26 05:46:35,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:35,628 INFO L691 BuchiCegarLoop]: Abstraction has 3336 states and 4454 transitions. [2020-10-26 05:46:35,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3336 states and 4454 transitions. [2020-10-26 05:46:35,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3336 to 3245. [2020-10-26 05:46:35,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3245 states. [2020-10-26 05:46:35,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3245 states to 3245 states and 4342 transitions. [2020-10-26 05:46:35,710 INFO L714 BuchiCegarLoop]: Abstraction has 3245 states and 4342 transitions. [2020-10-26 05:46:35,710 INFO L594 BuchiCegarLoop]: Abstraction has 3245 states and 4342 transitions. [2020-10-26 05:46:35,710 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-10-26 05:46:35,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3245 states and 4342 transitions. [2020-10-26 05:46:35,750 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3162 [2020-10-26 05:46:35,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:35,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:35,752 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,752 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,752 INFO L794 eck$LassoCheckResult]: Stem: 34061#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 33952#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 33953#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34199#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 33993#L235-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 33994#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35206#L245-1 assume !(0 == ~M_E~0); 35205#L348-1 assume !(0 == ~T1_E~0); 35204#L353-1 assume !(0 == ~T2_E~0); 35203#L358-1 assume !(0 == ~E_M~0); 35202#L363-1 assume !(0 == ~E_1~0); 35201#L368-1 assume !(0 == ~E_2~0); 35200#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35199#L170 assume !(1 == ~m_pc~0); 35198#L170-2 is_master_triggered_~__retres1~0 := 0; 35197#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35196#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35195#L429 assume !(0 != activate_threads_~tmp~1); 35194#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35193#L189 assume !(1 == ~t1_pc~0); 35192#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 35191#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35190#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35189#L437 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 34207#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34208#L208 assume !(1 == ~t2_pc~0); 35186#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 35185#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35184#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 34121#L445 assume !(0 != activate_threads_~tmp___1~0); 34122#L445-2 assume !(1 == ~M_E~0); 34125#L386-1 assume !(1 == ~T1_E~0); 34154#L391-1 assume !(1 == ~T2_E~0); 34098#L396-1 assume !(1 == ~E_M~0); 34099#L401-1 assume !(1 == ~E_1~0); 33983#L406-1 assume !(1 == ~E_2~0); 33984#L557-1 assume !false; 35243#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 35242#L323 [2020-10-26 05:46:35,753 INFO L796 eck$LassoCheckResult]: Loop: 35242#L323 assume !false; 35183#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 35174#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 35170#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 35163#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 35159#L290 assume 0 != eval_~tmp~0; 35147#L290-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 35142#L298 assume !(0 != eval_~tmp_ndt_1~0); 35134#L295 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 35132#L312 assume !(0 != eval_~tmp_ndt_2~0); 35133#L309 assume !(0 == ~t2_st~0); 35242#L323 [2020-10-26 05:46:35,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,754 INFO L82 PathProgramCache]: Analyzing trace with hash 79981826, now seen corresponding path program 1 times [2020-10-26 05:46:35,754 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,757 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869435195] [2020-10-26 05:46:35,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,782 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869435195] [2020-10-26 05:46:35,782 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,783 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,783 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159899106] [2020-10-26 05:46:35,784 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:35,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,784 INFO L82 PathProgramCache]: Analyzing trace with hash 456604542, now seen corresponding path program 1 times [2020-10-26 05:46:35,787 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,787 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678223981] [2020-10-26 05:46:35,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:35,794 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:35,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:35,797 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:35,799 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:35,906 WARN L193 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 24 [2020-10-26 05:46:35,948 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:35,949 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:35,949 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:35,949 INFO L87 Difference]: Start difference. First operand 3245 states and 4342 transitions. cyclomatic complexity: 1100 Second operand 3 states. [2020-10-26 05:46:35,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:35,973 INFO L93 Difference]: Finished difference Result 3208 states and 4293 transitions. [2020-10-26 05:46:35,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:35,973 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3208 states and 4293 transitions. [2020-10-26 05:46:35,994 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3162 [2020-10-26 05:46:36,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3208 states to 3208 states and 4293 transitions. [2020-10-26 05:46:36,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3208 [2020-10-26 05:46:36,026 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3208 [2020-10-26 05:46:36,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3208 states and 4293 transitions. [2020-10-26 05:46:36,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:36,033 INFO L691 BuchiCegarLoop]: Abstraction has 3208 states and 4293 transitions. [2020-10-26 05:46:36,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3208 states and 4293 transitions. [2020-10-26 05:46:36,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3208 to 3208. [2020-10-26 05:46:36,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3208 states. [2020-10-26 05:46:36,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3208 states to 3208 states and 4293 transitions. [2020-10-26 05:46:36,099 INFO L714 BuchiCegarLoop]: Abstraction has 3208 states and 4293 transitions. [2020-10-26 05:46:36,099 INFO L594 BuchiCegarLoop]: Abstraction has 3208 states and 4293 transitions. [2020-10-26 05:46:36,100 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-10-26 05:46:36,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3208 states and 4293 transitions. [2020-10-26 05:46:36,113 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3162 [2020-10-26 05:46:36,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:36,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:36,114 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,114 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,115 INFO L794 eck$LassoCheckResult]: Stem: 40517#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 40411#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 40412#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 40655#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 40451#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40452#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40457#L245-1 assume !(0 == ~M_E~0); 40595#L348-1 assume !(0 == ~T1_E~0); 40596#L353-1 assume !(0 == ~T2_E~0); 40489#L358-1 assume !(0 == ~E_M~0); 40490#L363-1 assume !(0 == ~E_1~0); 40559#L368-1 assume !(0 == ~E_2~0); 40413#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40414#L170 assume !(1 == ~m_pc~0); 40553#L170-2 is_master_triggered_~__retres1~0 := 0; 40554#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40484#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 40485#L429 assume !(0 != activate_threads_~tmp~1); 40546#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40555#L189 assume !(1 == ~t1_pc~0); 40674#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 40675#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40645#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 40646#L437 assume !(0 != activate_threads_~tmp___0~0); 40664#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40406#L208 assume !(1 == ~t2_pc~0); 40407#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 40409#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40410#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40505#L445 assume !(0 != activate_threads_~tmp___1~0); 40579#L445-2 assume !(1 == ~M_E~0); 40583#L386-1 assume !(1 == ~T1_E~0); 40487#L391-1 assume !(1 == ~T2_E~0); 40488#L396-1 assume !(1 == ~E_M~0); 40556#L401-1 assume !(1 == ~E_1~0); 40442#L406-1 assume !(1 == ~E_2~0); 40443#L557-1 assume !false; 41651#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 41647#L323 [2020-10-26 05:46:36,115 INFO L796 eck$LassoCheckResult]: Loop: 41647#L323 assume !false; 41645#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 41643#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 41641#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 41639#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 41606#L290 assume 0 != eval_~tmp~0; 41607#L290-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 41634#L298 assume !(0 != eval_~tmp_ndt_1~0); 41526#L295 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 41523#L312 assume !(0 != eval_~tmp_ndt_2~0); 41524#L309 assume !(0 == ~t2_st~0); 41647#L323 [2020-10-26 05:46:36,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,115 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 2 times [2020-10-26 05:46:36,115 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,116 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778400180] [2020-10-26 05:46:36,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,127 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,135 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,142 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:36,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,143 INFO L82 PathProgramCache]: Analyzing trace with hash 456604542, now seen corresponding path program 2 times [2020-10-26 05:46:36,143 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,143 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535048662] [2020-10-26 05:46:36,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,148 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,150 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,153 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:36,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,154 INFO L82 PathProgramCache]: Analyzing trace with hash -1384155879, now seen corresponding path program 1 times [2020-10-26 05:46:36,154 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,155 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311781287] [2020-10-26 05:46:36,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:36,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:36,189 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311781287] [2020-10-26 05:46:36,189 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:36,189 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:36,190 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906141023] [2020-10-26 05:46:36,279 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:36,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:36,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:36,280 INFO L87 Difference]: Start difference. First operand 3208 states and 4293 transitions. cyclomatic complexity: 1088 Second operand 3 states. [2020-10-26 05:46:36,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:36,370 INFO L93 Difference]: Finished difference Result 5102 states and 6813 transitions. [2020-10-26 05:46:36,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:36,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5102 states and 6813 transitions. [2020-10-26 05:46:36,398 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5052 [2020-10-26 05:46:36,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5102 states to 5102 states and 6813 transitions. [2020-10-26 05:46:36,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5102 [2020-10-26 05:46:36,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5102 [2020-10-26 05:46:36,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5102 states and 6813 transitions. [2020-10-26 05:46:36,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:36,445 INFO L691 BuchiCegarLoop]: Abstraction has 5102 states and 6813 transitions. [2020-10-26 05:46:36,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5102 states and 6813 transitions. [2020-10-26 05:46:36,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5102 to 5018. [2020-10-26 05:46:36,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5018 states. [2020-10-26 05:46:36,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5018 states to 5018 states and 6729 transitions. [2020-10-26 05:46:36,544 INFO L714 BuchiCegarLoop]: Abstraction has 5018 states and 6729 transitions. [2020-10-26 05:46:36,544 INFO L594 BuchiCegarLoop]: Abstraction has 5018 states and 6729 transitions. [2020-10-26 05:46:36,544 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-10-26 05:46:36,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5018 states and 6729 transitions. [2020-10-26 05:46:36,564 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4968 [2020-10-26 05:46:36,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:36,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:36,565 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,565 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,565 INFO L794 eck$LassoCheckResult]: Stem: 48841#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 48729#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 48730#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 48983#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 48770#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48771#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48777#L245-1 assume !(0 == ~M_E~0); 48918#L348-1 assume !(0 == ~T1_E~0); 48919#L353-1 assume !(0 == ~T2_E~0); 48809#L358-1 assume !(0 == ~E_M~0); 48810#L363-1 assume !(0 == ~E_1~0); 48880#L368-1 assume !(0 == ~E_2~0); 48731#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48732#L170 assume !(1 == ~m_pc~0); 48874#L170-2 is_master_triggered_~__retres1~0 := 0; 48875#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48804#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 48805#L429 assume !(0 != activate_threads_~tmp~1); 48868#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48876#L189 assume !(1 == ~t1_pc~0); 49009#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 49010#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48972#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 48973#L437 assume !(0 != activate_threads_~tmp___0~0); 48997#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48724#L208 assume !(1 == ~t2_pc~0); 48725#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 48727#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48728#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48828#L445 assume !(0 != activate_threads_~tmp___1~0); 48902#L445-2 assume !(1 == ~M_E~0); 48907#L386-1 assume !(1 == ~T1_E~0); 48807#L391-1 assume !(1 == ~T2_E~0); 48808#L396-1 assume !(1 == ~E_M~0); 48877#L401-1 assume !(1 == ~E_1~0); 48761#L406-1 assume !(1 == ~E_2~0); 48762#L557-1 assume !false; 50510#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 50506#L323 [2020-10-26 05:46:36,565 INFO L796 eck$LassoCheckResult]: Loop: 50506#L323 assume !false; 50503#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 50481#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 50454#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 50444#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 50438#L290 assume 0 != eval_~tmp~0; 50439#L290-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 50479#L298 assume !(0 != eval_~tmp_ndt_1~0); 50443#L295 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 50116#L312 assume !(0 != eval_~tmp_ndt_2~0); 50517#L309 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 50392#L326 assume !(0 != eval_~tmp_ndt_3~0); 50506#L323 [2020-10-26 05:46:36,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,566 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 3 times [2020-10-26 05:46:36,566 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,566 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435184743] [2020-10-26 05:46:36,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,589 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,604 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,616 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:36,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,617 INFO L82 PathProgramCache]: Analyzing trace with hash 1269836213, now seen corresponding path program 1 times [2020-10-26 05:46:36,618 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,618 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034727454] [2020-10-26 05:46:36,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,621 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,624 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,626 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:36,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,627 INFO L82 PathProgramCache]: Analyzing trace with hash 40838010, now seen corresponding path program 1 times [2020-10-26 05:46:36,627 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,627 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458484126] [2020-10-26 05:46:36,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,637 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:36,646 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:36,657 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:37,559 WARN L193 SmtUtils]: Spent 799.00 ms on a formula simplification. DAG size of input: 158 DAG size of output: 119 [2020-10-26 05:46:37,832 WARN L193 SmtUtils]: Spent 243.00 ms on a formula simplification that was a NOOP. DAG size: 105 [2020-10-26 05:46:37,901 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.10 05:46:37 BoogieIcfgContainer [2020-10-26 05:46:37,901 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-10-26 05:46:37,902 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-10-26 05:46:37,902 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-10-26 05:46:37,902 INFO L275 PluginConnector]: Witness Printer initialized [2020-10-26 05:46:37,903 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:46:31" (3/4) ... [2020-10-26 05:46:37,906 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-10-26 05:46:37,961 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2020-10-26 05:46:37,961 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-10-26 05:46:37,962 INFO L168 Benchmark]: Toolchain (without parser) took 8334.39 ms. Allocated memory was 52.4 MB in the beginning and 161.5 MB in the end (delta: 109.1 MB). Free memory was 29.5 MB in the beginning and 67.2 MB in the end (delta: -37.7 MB). Peak memory consumption was 73.8 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:37,963 INFO L168 Benchmark]: CDTParser took 0.39 ms. Allocated memory is still 52.4 MB. Free memory was 30.2 MB in the beginning and 30.2 MB in the end (delta: 34.3 kB). There was no memory consumed. Max. memory is 16.1 GB. [2020-10-26 05:46:37,963 INFO L168 Benchmark]: CACSL2BoogieTranslator took 443.91 ms. Allocated memory is still 52.4 MB. Free memory was 28.8 MB in the beginning and 26.2 MB in the end (delta: 2.6 MB). Peak memory consumption was 5.6 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:37,964 INFO L168 Benchmark]: Boogie Procedure Inliner took 87.23 ms. Allocated memory is still 52.4 MB. Free memory was 26.2 MB in the beginning and 23.3 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:37,964 INFO L168 Benchmark]: Boogie Preprocessor took 81.29 ms. Allocated memory was 52.4 MB in the beginning and 65.0 MB in the end (delta: 12.6 MB). Free memory was 23.3 MB in the beginning and 46.8 MB in the end (delta: -23.5 MB). Peak memory consumption was 5.4 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:37,964 INFO L168 Benchmark]: RCFGBuilder took 1157.67 ms. Allocated memory is still 65.0 MB. Free memory was 46.8 MB in the beginning and 29.1 MB in the end (delta: 17.7 MB). Peak memory consumption was 19.3 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:37,965 INFO L168 Benchmark]: BuchiAutomizer took 6492.61 ms. Allocated memory was 65.0 MB in the beginning and 161.5 MB in the end (delta: 96.5 MB). Free memory was 28.8 MB in the beginning and 70.3 MB in the end (delta: -41.6 MB). Peak memory consumption was 98.1 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:37,965 INFO L168 Benchmark]: Witness Printer took 59.12 ms. Allocated memory is still 161.5 MB. Free memory was 70.3 MB in the beginning and 67.2 MB in the end (delta: 3.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:37,968 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.39 ms. Allocated memory is still 52.4 MB. Free memory was 30.2 MB in the beginning and 30.2 MB in the end (delta: 34.3 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 443.91 ms. Allocated memory is still 52.4 MB. Free memory was 28.8 MB in the beginning and 26.2 MB in the end (delta: 2.6 MB). Peak memory consumption was 5.6 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 87.23 ms. Allocated memory is still 52.4 MB. Free memory was 26.2 MB in the beginning and 23.3 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 81.29 ms. Allocated memory was 52.4 MB in the beginning and 65.0 MB in the end (delta: 12.6 MB). Free memory was 23.3 MB in the beginning and 46.8 MB in the end (delta: -23.5 MB). Peak memory consumption was 5.4 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1157.67 ms. Allocated memory is still 65.0 MB. Free memory was 46.8 MB in the beginning and 29.1 MB in the end (delta: 17.7 MB). Peak memory consumption was 19.3 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 6492.61 ms. Allocated memory was 65.0 MB in the beginning and 161.5 MB in the end (delta: 96.5 MB). Free memory was 28.8 MB in the beginning and 70.3 MB in the end (delta: -41.6 MB). Peak memory consumption was 98.1 MB. Max. memory is 16.1 GB. * Witness Printer took 59.12 ms. Allocated memory is still 161.5 MB. Free memory was 70.3 MB in the beginning and 67.2 MB in the end (delta: 3.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 5018 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.3s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 3.5s. Construction of modules took 0.6s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 16 MinimizatonAttempts, 4273 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had 5018 states and ocurred in iteration 16. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 5654 SDtfs, 6827 SDslu, 6182 SDs, 0 SdLazy, 478 SolverSat, 162 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=26388} State at position 1 is {NULL=0, token=0, NULL=26388, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@43e19dd0=0, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6cc5e0ad=0, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31a12396=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4eb920=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50b53a15=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7210c601=0, NULL=26391, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3efadf49=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=26390, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=26389, t2_i=1, m_i=1, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7ed716cd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@461bde2d=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int M_E = 2; [L26] int T1_E = 2; [L27] int T2_E = 2; [L28] int E_M = 2; [L29] int E_1 = 2; [L30] int E_2 = 2; [L35] int token ; [L37] int local ; [L602] int __retres1 ; [L516] m_i = 1 [L517] t1_i = 1 [L518] t2_i = 1 [L543] int kernel_st ; [L544] int tmp ; [L545] int tmp___0 ; [L549] kernel_st = 0 [L235] COND TRUE m_i == 1 [L236] m_st = 0 [L240] COND TRUE t1_i == 1 [L241] t1_st = 0 [L245] COND TRUE t2_i == 1 [L246] t2_st = 0 [L348] COND FALSE !(M_E == 0) [L353] COND FALSE !(T1_E == 0) [L358] COND FALSE !(T2_E == 0) [L363] COND FALSE !(E_M == 0) [L368] COND FALSE !(E_1 == 0) [L373] COND FALSE !(E_2 == 0) [L421] int tmp ; [L422] int tmp___0 ; [L423] int tmp___1 ; [L167] int __retres1 ; [L170] COND FALSE !(m_pc == 1) [L180] __retres1 = 0 [L182] return (__retres1); [L427] tmp = is_master_triggered() [L429] COND FALSE !(\read(tmp)) [L186] int __retres1 ; [L189] COND FALSE !(t1_pc == 1) [L199] __retres1 = 0 [L201] return (__retres1); [L435] tmp___0 = is_transmit1_triggered() [L437] COND FALSE !(\read(tmp___0)) [L205] int __retres1 ; [L208] COND FALSE !(t2_pc == 1) [L218] __retres1 = 0 [L220] return (__retres1); [L443] tmp___1 = is_transmit2_triggered() [L445] COND FALSE !(\read(tmp___1)) [L386] COND FALSE !(M_E == 1) [L391] COND FALSE !(T1_E == 1) [L396] COND FALSE !(T2_E == 1) [L401] COND FALSE !(E_M == 1) [L406] COND FALSE !(E_1 == 1) [L411] COND FALSE !(E_2 == 1) [L557] COND TRUE 1 [L560] kernel_st = 1 [L281] int tmp ; Loop: [L285] COND TRUE 1 [L255] int __retres1 ; [L258] COND TRUE m_st == 0 [L259] __retres1 = 1 [L276] return (__retres1); [L288] tmp = exists_runnable_thread() [L290] COND TRUE \read(tmp) [L295] COND TRUE m_st == 0 [L296] int tmp_ndt_1; [L297] tmp_ndt_1 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_1)) [L309] COND TRUE t1_st == 0 [L310] int tmp_ndt_2; [L311] tmp_ndt_2 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_2)) [L323] COND TRUE t2_st == 0 [L324] int tmp_ndt_3; [L325] tmp_ndt_3 = __VERIFIER_nondet_int() [L326] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...