./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 54858612 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e9caf902342f4155ad93c17f48e1d073622ba685 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-5485861 [2020-10-26 05:46:30,715 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-10-26 05:46:30,718 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-10-26 05:46:30,763 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-10-26 05:46:30,763 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-10-26 05:46:30,765 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-10-26 05:46:30,766 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-10-26 05:46:30,769 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-10-26 05:46:30,771 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-10-26 05:46:30,772 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-10-26 05:46:30,773 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-10-26 05:46:30,774 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-10-26 05:46:30,775 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-10-26 05:46:30,776 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-10-26 05:46:30,777 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-10-26 05:46:30,779 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-10-26 05:46:30,780 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-10-26 05:46:30,781 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-10-26 05:46:30,783 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-10-26 05:46:30,785 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-10-26 05:46:30,787 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-10-26 05:46:30,788 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-10-26 05:46:30,790 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-10-26 05:46:30,791 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-10-26 05:46:30,794 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-10-26 05:46:30,794 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-10-26 05:46:30,795 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-10-26 05:46:30,796 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-10-26 05:46:30,797 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-10-26 05:46:30,798 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-10-26 05:46:30,798 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-10-26 05:46:30,799 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-10-26 05:46:30,800 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-10-26 05:46:30,801 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-10-26 05:46:30,802 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-10-26 05:46:30,802 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-10-26 05:46:30,803 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-10-26 05:46:30,803 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-10-26 05:46:30,804 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-10-26 05:46:30,805 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-10-26 05:46:30,806 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-10-26 05:46:30,807 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-10-26 05:46:30,840 INFO L113 SettingsManager]: Loading preferences was successful [2020-10-26 05:46:30,841 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-10-26 05:46:30,842 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-10-26 05:46:30,842 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-10-26 05:46:30,843 INFO L138 SettingsManager]: * Use SBE=true [2020-10-26 05:46:30,843 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-10-26 05:46:30,843 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-10-26 05:46:30,844 INFO L138 SettingsManager]: * Use old map elimination=false [2020-10-26 05:46:30,844 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-10-26 05:46:30,844 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-10-26 05:46:30,844 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-10-26 05:46:30,845 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-10-26 05:46:30,845 INFO L138 SettingsManager]: * sizeof long=4 [2020-10-26 05:46:30,845 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-10-26 05:46:30,846 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-10-26 05:46:30,846 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-10-26 05:46:30,846 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-10-26 05:46:30,846 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-10-26 05:46:30,847 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-10-26 05:46:30,847 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-10-26 05:46:30,847 INFO L138 SettingsManager]: * sizeof long double=12 [2020-10-26 05:46:30,847 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-10-26 05:46:30,848 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-10-26 05:46:30,848 INFO L138 SettingsManager]: * Use constant arrays=true [2020-10-26 05:46:30,848 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-10-26 05:46:30,848 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-10-26 05:46:30,849 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-10-26 05:46:30,849 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-10-26 05:46:30,849 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-10-26 05:46:30,849 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-10-26 05:46:30,850 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-10-26 05:46:30,850 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-10-26 05:46:30,851 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-10-26 05:46:30,851 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e9caf902342f4155ad93c17f48e1d073622ba685 [2020-10-26 05:46:31,216 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-10-26 05:46:31,254 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-10-26 05:46:31,260 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-10-26 05:46:31,262 INFO L271 PluginConnector]: Initializing CDTParser... [2020-10-26 05:46:31,262 INFO L275 PluginConnector]: CDTParser initialized [2020-10-26 05:46:31,263 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2020-10-26 05:46:31,359 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/22fc8c7ee/0144bc7f7a884268ab198a402569cd30/FLAG07ed803af [2020-10-26 05:46:31,901 INFO L306 CDTParser]: Found 1 translation units. [2020-10-26 05:46:31,902 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2020-10-26 05:46:31,918 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/22fc8c7ee/0144bc7f7a884268ab198a402569cd30/FLAG07ed803af [2020-10-26 05:46:32,238 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/22fc8c7ee/0144bc7f7a884268ab198a402569cd30 [2020-10-26 05:46:32,241 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-10-26 05:46:32,248 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-10-26 05:46:32,250 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-10-26 05:46:32,250 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-10-26 05:46:32,255 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-10-26 05:46:32,256 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,260 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5f4df93e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32, skipping insertion in model container [2020-10-26 05:46:32,260 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,269 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-10-26 05:46:32,310 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-10-26 05:46:32,614 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-10-26 05:46:32,626 INFO L203 MainTranslator]: Completed pre-run [2020-10-26 05:46:32,691 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-10-26 05:46:32,720 INFO L208 MainTranslator]: Completed translation [2020-10-26 05:46:32,721 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32 WrapperNode [2020-10-26 05:46:32,721 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-10-26 05:46:32,723 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-10-26 05:46:32,723 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-10-26 05:46:32,723 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-10-26 05:46:32,732 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,745 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,800 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-10-26 05:46:32,805 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-10-26 05:46:32,805 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-10-26 05:46:32,806 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-10-26 05:46:32,823 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,823 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,836 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,836 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,855 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,871 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,877 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... [2020-10-26 05:46:32,887 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-10-26 05:46:32,888 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-10-26 05:46:32,892 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-10-26 05:46:32,892 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-10-26 05:46:32,893 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-10-26 05:46:33,007 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-10-26 05:46:33,007 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-10-26 05:46:33,007 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-10-26 05:46:33,007 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-10-26 05:46:34,246 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-10-26 05:46:34,246 INFO L298 CfgBuilder]: Removed 163 assume(true) statements. [2020-10-26 05:46:34,249 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:46:34 BoogieIcfgContainer [2020-10-26 05:46:34,249 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-10-26 05:46:34,250 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-10-26 05:46:34,250 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-10-26 05:46:34,254 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-10-26 05:46:34,254 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:46:34,255 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.10 05:46:32" (1/3) ... [2020-10-26 05:46:34,256 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@798d5c5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.10 05:46:34, skipping insertion in model container [2020-10-26 05:46:34,256 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:46:34,256 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:46:32" (2/3) ... [2020-10-26 05:46:34,256 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@798d5c5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.10 05:46:34, skipping insertion in model container [2020-10-26 05:46:34,257 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:46:34,257 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:46:34" (3/3) ... [2020-10-26 05:46:34,258 INFO L373 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2020-10-26 05:46:34,306 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-10-26 05:46:34,307 INFO L360 BuchiCegarLoop]: Hoare is false [2020-10-26 05:46:34,307 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-10-26 05:46:34,307 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-10-26 05:46:34,307 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-10-26 05:46:34,307 INFO L364 BuchiCegarLoop]: Difference is false [2020-10-26 05:46:34,307 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-10-26 05:46:34,307 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-10-26 05:46:34,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 414 states. [2020-10-26 05:46:34,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 347 [2020-10-26 05:46:34,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:34,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:34,411 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,411 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,412 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-10-26 05:46:34,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 414 states. [2020-10-26 05:46:34,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 347 [2020-10-26 05:46:34,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:34,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:34,441 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,441 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:34,451 INFO L794 eck$LassoCheckResult]: Stem: 301#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 219#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 252#L758true havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 398#L338true assume !(1 == ~m_i~0);~m_st~0 := 2; 14#L345-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 267#L350-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 162#L355-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 399#L360-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 86#L365-1true assume !(0 == ~M_E~0); 319#L506-1true assume !(0 == ~T1_E~0); 70#L511-1true assume !(0 == ~T2_E~0); 237#L516-1true assume !(0 == ~T3_E~0); 20#L521-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 370#L526-1true assume !(0 == ~E_M~0); 170#L531-1true assume !(0 == ~E_1~0); 411#L536-1true assume !(0 == ~E_2~0); 95#L541-1true assume !(0 == ~E_3~0); 357#L546-1true assume !(0 == ~E_4~0); 143#L551-1true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 296#L242true assume 1 == ~m_pc~0; 117#L243true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 297#L253true is_master_triggered_#res := is_master_triggered_~__retres1~0; 119#L254true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 102#L629true assume !(0 != activate_threads_~tmp~1); 91#L629-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 390#L261true assume !(1 == ~t1_pc~0); 407#L261-2true is_transmit1_triggered_~__retres1~1 := 0; 391#L272true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 258#L273true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 247#L637true assume !(0 != activate_threads_~tmp___0~0); 248#L637-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 80#L280true assume 1 == ~t2_pc~0; 42#L281true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 81#L291true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43#L292true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 363#L645true assume !(0 != activate_threads_~tmp___1~0); 354#L645-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 92#L299true assume !(1 == ~t3_pc~0); 194#L299-2true is_transmit3_triggered_~__retres1~3 := 0; 88#L310true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 163#L311true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27#L653true assume !(0 != activate_threads_~tmp___2~0); 28#L653-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 223#L318true assume 1 == ~t4_pc~0; 323#L319true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 222#L329true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 322#L330true activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 278#L661true assume !(0 != activate_threads_~tmp___3~0); 140#L661-2true assume !(1 == ~M_E~0); 168#L564-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 410#L569-1true assume !(1 == ~T2_E~0); 93#L574-1true assume !(1 == ~T3_E~0); 355#L579-1true assume !(1 == ~T4_E~0); 142#L584-1true assume !(1 == ~E_M~0); 45#L589-1true assume !(1 == ~E_1~0); 326#L594-1true assume !(1 == ~E_2~0); 4#L599-1true assume !(1 == ~E_3~0); 249#L604-1true assume 1 == ~E_4~0;~E_4~0 := 2; 181#L795-1true [2020-10-26 05:46:34,461 INFO L796 eck$LassoCheckResult]: Loop: 181#L795-1true assume !false; 30#L796true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 412#L481true assume !true; 144#L496true start_simulation_~kernel_st~0 := 2; 402#L338-1true start_simulation_~kernel_st~0 := 3; 320#L506-2true assume 0 == ~M_E~0;~M_E~0 := 1; 321#L506-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 77#L511-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 242#L516-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 23#L521-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 372#L526-3true assume 0 == ~E_M~0;~E_M~0 := 1; 173#L531-3true assume !(0 == ~E_1~0); 415#L536-3true assume 0 == ~E_2~0;~E_2~0 := 1; 100#L541-3true assume 0 == ~E_3~0;~E_3~0 := 1; 360#L546-3true assume 0 == ~E_4~0;~E_4~0 := 1; 130#L551-3true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 281#L242-18true assume !(1 == ~m_pc~0); 138#L242-20true is_master_triggered_~__retres1~0 := 0; 307#L253-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 127#L254-6true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 188#L629-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 191#L629-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 374#L261-18true assume !(1 == ~t1_pc~0); 371#L261-20true is_transmit1_triggered_~__retres1~1 := 0; 393#L272-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 265#L273-6true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 217#L637-18true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 334#L637-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44#L280-18true assume !(1 == ~t2_pc~0); 53#L280-20true is_transmit2_triggered_~__retres1~2 := 0; 58#L291-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 367#L292-6true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 344#L645-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 345#L645-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 182#L299-18true assume !(1 == ~t3_pc~0); 180#L299-20true is_transmit3_triggered_~__retres1~3 := 0; 206#L310-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 159#L311-6true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11#L653-18true assume !(0 != activate_threads_~tmp___2~0); 6#L653-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 331#L318-18true assume 1 == ~t4_pc~0; 289#L319-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 212#L329-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 287#L330-6true activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 109#L661-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 115#L661-20true assume 1 == ~M_E~0;~M_E~0 := 2; 172#L564-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 414#L569-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 96#L574-3true assume !(1 == ~T3_E~0); 359#L579-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 146#L584-3true assume 1 == ~E_M~0;~E_M~0 := 2; 48#L589-3true assume 1 == ~E_1~0;~E_1~0 := 2; 327#L594-3true assume 1 == ~E_2~0;~E_2~0 := 2; 68#L599-3true assume 1 == ~E_3~0;~E_3~0 := 2; 236#L604-3true assume 1 == ~E_4~0;~E_4~0 := 2; 19#L609-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 13#L378-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 259#L405-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 245#L406-1true start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 328#L814true assume !(0 == start_simulation_~tmp~3); 330#L814-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15#L378-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 264#L405-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 221#L406-2true stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 251#L769true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 49#L776true stop_simulation_#res := stop_simulation_~__retres2~0; 362#L777true start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 104#L827true assume !(0 != start_simulation_~tmp___0~1); 181#L795-1true [2020-10-26 05:46:34,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,475 INFO L82 PathProgramCache]: Analyzing trace with hash -2002818045, now seen corresponding path program 1 times [2020-10-26 05:46:34,484 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,485 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396468181] [2020-10-26 05:46:34,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:34,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:34,727 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396468181] [2020-10-26 05:46:34,727 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:34,728 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:34,729 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420093164] [2020-10-26 05:46:34,738 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:34,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:34,742 INFO L82 PathProgramCache]: Analyzing trace with hash 6491466, now seen corresponding path program 1 times [2020-10-26 05:46:34,743 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:34,743 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869070557] [2020-10-26 05:46:34,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:34,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:34,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:34,830 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869070557] [2020-10-26 05:46:34,830 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:34,830 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:34,831 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36319756] [2020-10-26 05:46:34,834 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:34,835 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:34,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:34,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:34,862 INFO L87 Difference]: Start difference. First operand 414 states. Second operand 3 states. [2020-10-26 05:46:34,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:34,951 INFO L93 Difference]: Finished difference Result 413 states and 625 transitions. [2020-10-26 05:46:34,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:34,954 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 625 transitions. [2020-10-26 05:46:34,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:34,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 408 states and 620 transitions. [2020-10-26 05:46:34,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2020-10-26 05:46:34,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2020-10-26 05:46:34,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 620 transitions. [2020-10-26 05:46:34,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:34,992 INFO L691 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2020-10-26 05:46:35,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 620 transitions. [2020-10-26 05:46:35,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2020-10-26 05:46:35,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2020-10-26 05:46:35,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 620 transitions. [2020-10-26 05:46:35,083 INFO L714 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2020-10-26 05:46:35,083 INFO L594 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2020-10-26 05:46:35,083 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-10-26 05:46:35,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 620 transitions. [2020-10-26 05:46:35,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:35,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:35,099 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,099 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,100 INFO L794 eck$LassoCheckResult]: Stem: 1223#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1149#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1150#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1179#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 856#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 857#L350-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1098#L355-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1099#L360-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 972#L365-1 assume !(0 == ~M_E~0); 973#L506-1 assume !(0 == ~T1_E~0); 951#L511-1 assume !(0 == ~T2_E~0); 952#L516-1 assume !(0 == ~T3_E~0); 866#L521-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 867#L526-1 assume !(0 == ~E_M~0); 1107#L531-1 assume !(0 == ~E_1~0); 1108#L536-1 assume !(0 == ~E_2~0); 990#L541-1 assume !(0 == ~E_3~0); 991#L546-1 assume !(0 == ~E_4~0); 1068#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1069#L242 assume 1 == ~m_pc~0; 1031#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1032#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1035#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1002#L629 assume !(0 != activate_threads_~tmp~1); 981#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 982#L261 assume !(1 == ~t1_pc~0); 1187#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 1188#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1189#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1176#L637 assume !(0 != activate_threads_~tmp___0~0); 1177#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 962#L280 assume 1 == ~t2_pc~0; 912#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 913#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 915#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 916#L645 assume !(0 != activate_threads_~tmp___1~0); 1241#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 983#L299 assume !(1 == ~t3_pc~0); 984#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 976#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 977#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 880#L653 assume !(0 != activate_threads_~tmp___2~0); 881#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 882#L318 assume 1 == ~t4_pc~0; 1157#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1155#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1156#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1216#L661 assume !(0 != activate_threads_~tmp___3~0); 1063#L661-2 assume !(1 == ~M_E~0); 1064#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1104#L569-1 assume !(1 == ~T2_E~0); 986#L574-1 assume !(1 == ~T3_E~0); 987#L579-1 assume !(1 == ~T4_E~0); 1067#L584-1 assume !(1 == ~E_M~0); 920#L589-1 assume !(1 == ~E_1~0); 921#L594-1 assume !(1 == ~E_2~0); 838#L599-1 assume !(1 == ~E_3~0); 839#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1006#L795-1 [2020-10-26 05:46:35,101 INFO L796 eck$LassoCheckResult]: Loop: 1006#L795-1 assume !false; 884#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 885#L481 assume !false; 1243#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 875#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 876#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1173#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 965#L420 assume !(0 != eval_~tmp~0); 967#L496 start_simulation_~kernel_st~0 := 2; 1070#L338-1 start_simulation_~kernel_st~0 := 3; 1229#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1230#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 958#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 959#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 872#L521-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 873#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1110#L531-3 assume !(0 == ~E_1~0); 1111#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 999#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1000#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1054#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1055#L242-18 assume 1 == ~m_pc~0; 1043#L243-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1044#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1047#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1048#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1124#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1125#L261-18 assume 1 == ~t1_pc~0; 1195#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1196#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1198#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1145#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1146#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 917#L280-18 assume 1 == ~t2_pc~0; 918#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 936#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 940#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1235#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1236#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1118#L299-18 assume 1 == ~t3_pc~0; 1080#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1081#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1096#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 850#L653-18 assume !(0 != activate_threads_~tmp___2~0); 842#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 843#L318-18 assume 1 == ~t4_pc~0; 1218#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1138#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1139#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1017#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1018#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1029#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1109#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 992#L574-3 assume !(1 == ~T3_E~0); 993#L579-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1071#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 926#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 927#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 947#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 948#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 865#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 853#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 854#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1174#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1175#L814 assume !(0 == start_simulation_~tmp~3); 1231#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 858#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 859#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1153#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1154#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 928#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 929#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1005#L827 assume !(0 != start_simulation_~tmp___0~1); 1006#L795-1 [2020-10-26 05:46:35,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,104 INFO L82 PathProgramCache]: Analyzing trace with hash 905363841, now seen corresponding path program 1 times [2020-10-26 05:46:35,104 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,105 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202287877] [2020-10-26 05:46:35,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,222 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202287877] [2020-10-26 05:46:35,222 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,222 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,222 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561195458] [2020-10-26 05:46:35,223 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:35,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,225 INFO L82 PathProgramCache]: Analyzing trace with hash 1575616108, now seen corresponding path program 1 times [2020-10-26 05:46:35,226 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,226 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213809786] [2020-10-26 05:46:35,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,352 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213809786] [2020-10-26 05:46:35,352 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,352 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,353 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975744862] [2020-10-26 05:46:35,353 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:35,353 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:35,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:35,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:35,354 INFO L87 Difference]: Start difference. First operand 408 states and 620 transitions. cyclomatic complexity: 213 Second operand 3 states. [2020-10-26 05:46:35,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:35,387 INFO L93 Difference]: Finished difference Result 408 states and 619 transitions. [2020-10-26 05:46:35,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:35,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 619 transitions. [2020-10-26 05:46:35,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 619 transitions. [2020-10-26 05:46:35,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2020-10-26 05:46:35,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2020-10-26 05:46:35,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 619 transitions. [2020-10-26 05:46:35,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:35,398 INFO L691 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2020-10-26 05:46:35,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 619 transitions. [2020-10-26 05:46:35,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2020-10-26 05:46:35,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2020-10-26 05:46:35,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 619 transitions. [2020-10-26 05:46:35,411 INFO L714 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2020-10-26 05:46:35,411 INFO L594 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2020-10-26 05:46:35,411 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-10-26 05:46:35,411 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 619 transitions. [2020-10-26 05:46:35,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:35,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:35,417 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,417 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,417 INFO L794 eck$LassoCheckResult]: Stem: 2046#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1972#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1973#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2002#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 1679#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1680#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1921#L355-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1922#L360-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1795#L365-1 assume !(0 == ~M_E~0); 1796#L506-1 assume !(0 == ~T1_E~0); 1774#L511-1 assume !(0 == ~T2_E~0); 1775#L516-1 assume !(0 == ~T3_E~0); 1689#L521-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1690#L526-1 assume !(0 == ~E_M~0); 1930#L531-1 assume !(0 == ~E_1~0); 1931#L536-1 assume !(0 == ~E_2~0); 1813#L541-1 assume !(0 == ~E_3~0); 1814#L546-1 assume !(0 == ~E_4~0); 1891#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1892#L242 assume 1 == ~m_pc~0; 1854#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1855#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1858#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1825#L629 assume !(0 != activate_threads_~tmp~1); 1804#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1805#L261 assume !(1 == ~t1_pc~0); 2010#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 2011#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2012#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1999#L637 assume !(0 != activate_threads_~tmp___0~0); 2000#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1785#L280 assume 1 == ~t2_pc~0; 1735#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1736#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1738#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1739#L645 assume !(0 != activate_threads_~tmp___1~0); 2064#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1806#L299 assume !(1 == ~t3_pc~0); 1807#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 1799#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1800#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1703#L653 assume !(0 != activate_threads_~tmp___2~0); 1704#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1705#L318 assume 1 == ~t4_pc~0; 1980#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1978#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1979#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2039#L661 assume !(0 != activate_threads_~tmp___3~0); 1886#L661-2 assume !(1 == ~M_E~0); 1887#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1927#L569-1 assume !(1 == ~T2_E~0); 1809#L574-1 assume !(1 == ~T3_E~0); 1810#L579-1 assume !(1 == ~T4_E~0); 1890#L584-1 assume !(1 == ~E_M~0); 1743#L589-1 assume !(1 == ~E_1~0); 1744#L594-1 assume !(1 == ~E_2~0); 1661#L599-1 assume !(1 == ~E_3~0); 1662#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1829#L795-1 [2020-10-26 05:46:35,418 INFO L796 eck$LassoCheckResult]: Loop: 1829#L795-1 assume !false; 1707#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1708#L481 assume !false; 2066#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1698#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1699#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1996#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1788#L420 assume !(0 != eval_~tmp~0); 1790#L496 start_simulation_~kernel_st~0 := 2; 1893#L338-1 start_simulation_~kernel_st~0 := 3; 2052#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2053#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1781#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1782#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1695#L521-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1696#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1933#L531-3 assume !(0 == ~E_1~0); 1934#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1822#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1823#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1877#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1878#L242-18 assume 1 == ~m_pc~0; 1866#L243-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1867#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1870#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1871#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1947#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1948#L261-18 assume 1 == ~t1_pc~0; 2018#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2019#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2021#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1968#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1969#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1740#L280-18 assume 1 == ~t2_pc~0; 1741#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1759#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1763#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2058#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2059#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1941#L299-18 assume !(1 == ~t3_pc~0); 1905#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 1904#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1919#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1673#L653-18 assume !(0 != activate_threads_~tmp___2~0); 1665#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1666#L318-18 assume 1 == ~t4_pc~0; 2041#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1961#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1962#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1840#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1841#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1852#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1932#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1815#L574-3 assume !(1 == ~T3_E~0); 1816#L579-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1894#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1749#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1750#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1770#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1771#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1688#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1676#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1677#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1997#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1998#L814 assume !(0 == start_simulation_~tmp~3); 2054#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1681#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1682#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1976#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1977#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1751#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 1752#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1828#L827 assume !(0 != start_simulation_~tmp___0~1); 1829#L795-1 [2020-10-26 05:46:35,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,419 INFO L82 PathProgramCache]: Analyzing trace with hash 461463167, now seen corresponding path program 1 times [2020-10-26 05:46:35,419 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,419 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080741328] [2020-10-26 05:46:35,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,466 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080741328] [2020-10-26 05:46:35,466 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,466 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,466 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649769638] [2020-10-26 05:46:35,467 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:35,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,468 INFO L82 PathProgramCache]: Analyzing trace with hash -53034165, now seen corresponding path program 1 times [2020-10-26 05:46:35,468 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,468 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351506069] [2020-10-26 05:46:35,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,519 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351506069] [2020-10-26 05:46:35,520 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,520 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,520 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193707160] [2020-10-26 05:46:35,521 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:35,521 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:35,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:35,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:35,522 INFO L87 Difference]: Start difference. First operand 408 states and 619 transitions. cyclomatic complexity: 212 Second operand 3 states. [2020-10-26 05:46:35,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:35,542 INFO L93 Difference]: Finished difference Result 408 states and 618 transitions. [2020-10-26 05:46:35,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:35,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 618 transitions. [2020-10-26 05:46:35,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 618 transitions. [2020-10-26 05:46:35,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2020-10-26 05:46:35,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2020-10-26 05:46:35,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 618 transitions. [2020-10-26 05:46:35,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:35,553 INFO L691 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2020-10-26 05:46:35,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 618 transitions. [2020-10-26 05:46:35,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2020-10-26 05:46:35,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2020-10-26 05:46:35,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 618 transitions. [2020-10-26 05:46:35,562 INFO L714 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2020-10-26 05:46:35,562 INFO L594 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2020-10-26 05:46:35,562 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-10-26 05:46:35,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 618 transitions. [2020-10-26 05:46:35,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:35,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:35,567 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,567 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,567 INFO L794 eck$LassoCheckResult]: Stem: 2869#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2795#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2796#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2825#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 2502#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2503#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2744#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2745#L360-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2618#L365-1 assume !(0 == ~M_E~0); 2619#L506-1 assume !(0 == ~T1_E~0); 2597#L511-1 assume !(0 == ~T2_E~0); 2598#L516-1 assume !(0 == ~T3_E~0); 2512#L521-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2513#L526-1 assume !(0 == ~E_M~0); 2753#L531-1 assume !(0 == ~E_1~0); 2754#L536-1 assume !(0 == ~E_2~0); 2636#L541-1 assume !(0 == ~E_3~0); 2637#L546-1 assume !(0 == ~E_4~0); 2714#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2715#L242 assume 1 == ~m_pc~0; 2677#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2678#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2681#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2648#L629 assume !(0 != activate_threads_~tmp~1); 2627#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2628#L261 assume !(1 == ~t1_pc~0); 2833#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 2834#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2835#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2822#L637 assume !(0 != activate_threads_~tmp___0~0); 2823#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2608#L280 assume 1 == ~t2_pc~0; 2558#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2559#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2561#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2562#L645 assume !(0 != activate_threads_~tmp___1~0); 2887#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2629#L299 assume !(1 == ~t3_pc~0); 2630#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 2622#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2623#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2526#L653 assume !(0 != activate_threads_~tmp___2~0); 2527#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2528#L318 assume 1 == ~t4_pc~0; 2803#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2801#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2802#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2862#L661 assume !(0 != activate_threads_~tmp___3~0); 2709#L661-2 assume !(1 == ~M_E~0); 2710#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2750#L569-1 assume !(1 == ~T2_E~0); 2632#L574-1 assume !(1 == ~T3_E~0); 2633#L579-1 assume !(1 == ~T4_E~0); 2713#L584-1 assume !(1 == ~E_M~0); 2566#L589-1 assume !(1 == ~E_1~0); 2567#L594-1 assume !(1 == ~E_2~0); 2484#L599-1 assume !(1 == ~E_3~0); 2485#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2652#L795-1 [2020-10-26 05:46:35,568 INFO L796 eck$LassoCheckResult]: Loop: 2652#L795-1 assume !false; 2530#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2531#L481 assume !false; 2889#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2521#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2522#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2819#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2611#L420 assume !(0 != eval_~tmp~0); 2613#L496 start_simulation_~kernel_st~0 := 2; 2716#L338-1 start_simulation_~kernel_st~0 := 3; 2875#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2876#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2604#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2605#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2518#L521-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2519#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2756#L531-3 assume !(0 == ~E_1~0); 2757#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2645#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2646#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2700#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2701#L242-18 assume 1 == ~m_pc~0; 2689#L243-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2690#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2693#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2694#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2770#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2771#L261-18 assume 1 == ~t1_pc~0; 2841#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2842#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2844#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2791#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2792#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2563#L280-18 assume 1 == ~t2_pc~0; 2564#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2582#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2586#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2881#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2882#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2764#L299-18 assume 1 == ~t3_pc~0; 2726#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2727#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2742#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2496#L653-18 assume !(0 != activate_threads_~tmp___2~0); 2488#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2489#L318-18 assume 1 == ~t4_pc~0; 2864#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2784#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2785#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2663#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2664#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2675#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2755#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2638#L574-3 assume !(1 == ~T3_E~0); 2639#L579-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2717#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2572#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2573#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2593#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2594#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2511#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2499#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2500#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2820#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2821#L814 assume !(0 == start_simulation_~tmp~3); 2877#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2504#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2505#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2799#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2800#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2574#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 2575#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2651#L827 assume !(0 != start_simulation_~tmp___0~1); 2652#L795-1 [2020-10-26 05:46:35,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,568 INFO L82 PathProgramCache]: Analyzing trace with hash -1076876863, now seen corresponding path program 1 times [2020-10-26 05:46:35,568 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,569 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242870266] [2020-10-26 05:46:35,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,606 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242870266] [2020-10-26 05:46:35,606 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,606 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,606 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [587224182] [2020-10-26 05:46:35,607 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:35,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1575616108, now seen corresponding path program 2 times [2020-10-26 05:46:35,607 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,608 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128278764] [2020-10-26 05:46:35,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,689 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128278764] [2020-10-26 05:46:35,689 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,689 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,689 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653289910] [2020-10-26 05:46:35,690 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:35,690 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:35,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:35,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:35,691 INFO L87 Difference]: Start difference. First operand 408 states and 618 transitions. cyclomatic complexity: 211 Second operand 3 states. [2020-10-26 05:46:35,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:35,708 INFO L93 Difference]: Finished difference Result 408 states and 617 transitions. [2020-10-26 05:46:35,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:35,709 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 617 transitions. [2020-10-26 05:46:35,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 617 transitions. [2020-10-26 05:46:35,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2020-10-26 05:46:35,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2020-10-26 05:46:35,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 617 transitions. [2020-10-26 05:46:35,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:35,719 INFO L691 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2020-10-26 05:46:35,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 617 transitions. [2020-10-26 05:46:35,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2020-10-26 05:46:35,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2020-10-26 05:46:35,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 617 transitions. [2020-10-26 05:46:35,727 INFO L714 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2020-10-26 05:46:35,731 INFO L594 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2020-10-26 05:46:35,731 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-10-26 05:46:35,731 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 617 transitions. [2020-10-26 05:46:35,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:35,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:35,735 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,736 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,736 INFO L794 eck$LassoCheckResult]: Stem: 3692#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3622#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3623#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3648#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 3328#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3329#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3567#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3568#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3441#L365-1 assume !(0 == ~M_E~0); 3442#L506-1 assume !(0 == ~T1_E~0); 3421#L511-1 assume !(0 == ~T2_E~0); 3422#L516-1 assume !(0 == ~T3_E~0); 3337#L521-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3338#L526-1 assume !(0 == ~E_M~0); 3576#L531-1 assume !(0 == ~E_1~0); 3577#L536-1 assume !(0 == ~E_2~0); 3459#L541-1 assume !(0 == ~E_3~0); 3460#L546-1 assume !(0 == ~E_4~0); 3537#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3538#L242 assume 1 == ~m_pc~0; 3501#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3502#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3504#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3471#L629 assume !(0 != activate_threads_~tmp~1); 3450#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3451#L261 assume !(1 == ~t1_pc~0); 3656#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 3657#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3658#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3645#L637 assume !(0 != activate_threads_~tmp___0~0); 3646#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3431#L280 assume 1 == ~t2_pc~0; 3381#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3382#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3384#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3385#L645 assume !(0 != activate_threads_~tmp___1~0); 3710#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3452#L299 assume !(1 == ~t3_pc~0); 3453#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 3445#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3446#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3349#L653 assume !(0 != activate_threads_~tmp___2~0); 3350#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3351#L318 assume 1 == ~t4_pc~0; 3626#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3624#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3625#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3685#L661 assume !(0 != activate_threads_~tmp___3~0); 3532#L661-2 assume !(1 == ~M_E~0); 3533#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3573#L569-1 assume !(1 == ~T2_E~0); 3455#L574-1 assume !(1 == ~T3_E~0); 3456#L579-1 assume !(1 == ~T4_E~0); 3536#L584-1 assume !(1 == ~E_M~0); 3391#L589-1 assume !(1 == ~E_1~0); 3392#L594-1 assume !(1 == ~E_2~0); 3307#L599-1 assume !(1 == ~E_3~0); 3308#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3475#L795-1 [2020-10-26 05:46:35,736 INFO L796 eck$LassoCheckResult]: Loop: 3475#L795-1 assume !false; 3353#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3354#L481 assume !false; 3712#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3344#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3345#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3642#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3434#L420 assume !(0 != eval_~tmp~0); 3436#L496 start_simulation_~kernel_st~0 := 2; 3539#L338-1 start_simulation_~kernel_st~0 := 3; 3698#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3699#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3427#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3428#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3341#L521-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3342#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3579#L531-3 assume !(0 == ~E_1~0); 3580#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3468#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3469#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3523#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3524#L242-18 assume 1 == ~m_pc~0; 3513#L243-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3514#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3516#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3517#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3593#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3594#L261-18 assume 1 == ~t1_pc~0; 3664#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3665#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3667#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3614#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3615#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3386#L280-18 assume 1 == ~t2_pc~0; 3387#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3405#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3409#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3704#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3705#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3587#L299-18 assume 1 == ~t3_pc~0; 3547#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3548#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3565#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3319#L653-18 assume !(0 != activate_threads_~tmp___2~0); 3311#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3312#L318-18 assume 1 == ~t4_pc~0; 3687#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3607#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3608#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3483#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3484#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 3493#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3578#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3461#L574-3 assume !(1 == ~T3_E~0); 3462#L579-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3540#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3395#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3396#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3416#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3417#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3334#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3322#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3323#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3643#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3644#L814 assume !(0 == start_simulation_~tmp~3); 3700#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3325#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3326#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3620#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 3621#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3397#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 3398#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 3474#L827 assume !(0 != start_simulation_~tmp___0~1); 3475#L795-1 [2020-10-26 05:46:35,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,737 INFO L82 PathProgramCache]: Analyzing trace with hash 951709247, now seen corresponding path program 1 times [2020-10-26 05:46:35,740 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,740 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862820698] [2020-10-26 05:46:35,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,801 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862820698] [2020-10-26 05:46:35,801 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,802 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:35,802 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779318096] [2020-10-26 05:46:35,802 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:35,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,803 INFO L82 PathProgramCache]: Analyzing trace with hash 1575616108, now seen corresponding path program 3 times [2020-10-26 05:46:35,803 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,803 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822446326] [2020-10-26 05:46:35,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,856 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822446326] [2020-10-26 05:46:35,857 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,857 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,858 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348692546] [2020-10-26 05:46:35,858 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:35,859 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:35,859 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:35,859 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:35,860 INFO L87 Difference]: Start difference. First operand 408 states and 617 transitions. cyclomatic complexity: 210 Second operand 3 states. [2020-10-26 05:46:35,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:35,892 INFO L93 Difference]: Finished difference Result 408 states and 612 transitions. [2020-10-26 05:46:35,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:35,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 612 transitions. [2020-10-26 05:46:35,897 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 612 transitions. [2020-10-26 05:46:35,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2020-10-26 05:46:35,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2020-10-26 05:46:35,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 612 transitions. [2020-10-26 05:46:35,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:35,902 INFO L691 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2020-10-26 05:46:35,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 612 transitions. [2020-10-26 05:46:35,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2020-10-26 05:46:35,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2020-10-26 05:46:35,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 612 transitions. [2020-10-26 05:46:35,910 INFO L714 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2020-10-26 05:46:35,910 INFO L594 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2020-10-26 05:46:35,910 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-10-26 05:46:35,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 612 transitions. [2020-10-26 05:46:35,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2020-10-26 05:46:35,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:35,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:35,914 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,914 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:35,915 INFO L794 eck$LassoCheckResult]: Stem: 4515#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4441#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4442#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4471#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 4148#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4149#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4390#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4391#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4264#L365-1 assume !(0 == ~M_E~0); 4265#L506-1 assume !(0 == ~T1_E~0); 4243#L511-1 assume !(0 == ~T2_E~0); 4244#L516-1 assume !(0 == ~T3_E~0); 4158#L521-1 assume !(0 == ~T4_E~0); 4159#L526-1 assume !(0 == ~E_M~0); 4399#L531-1 assume !(0 == ~E_1~0); 4400#L536-1 assume !(0 == ~E_2~0); 4282#L541-1 assume !(0 == ~E_3~0); 4283#L546-1 assume !(0 == ~E_4~0); 4360#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4361#L242 assume 1 == ~m_pc~0; 4324#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4325#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4327#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4294#L629 assume !(0 != activate_threads_~tmp~1); 4273#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4274#L261 assume !(1 == ~t1_pc~0); 4479#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 4480#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4481#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4468#L637 assume !(0 != activate_threads_~tmp___0~0); 4469#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4254#L280 assume 1 == ~t2_pc~0; 4204#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4205#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4207#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4208#L645 assume !(0 != activate_threads_~tmp___1~0); 4533#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4275#L299 assume !(1 == ~t3_pc~0); 4276#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 4268#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4269#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4172#L653 assume !(0 != activate_threads_~tmp___2~0); 4173#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4174#L318 assume 1 == ~t4_pc~0; 4449#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4447#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4448#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4508#L661 assume !(0 != activate_threads_~tmp___3~0); 4355#L661-2 assume !(1 == ~M_E~0); 4356#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4396#L569-1 assume !(1 == ~T2_E~0); 4278#L574-1 assume !(1 == ~T3_E~0); 4279#L579-1 assume !(1 == ~T4_E~0); 4359#L584-1 assume !(1 == ~E_M~0); 4212#L589-1 assume !(1 == ~E_1~0); 4213#L594-1 assume !(1 == ~E_2~0); 4130#L599-1 assume !(1 == ~E_3~0); 4131#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4298#L795-1 [2020-10-26 05:46:35,915 INFO L796 eck$LassoCheckResult]: Loop: 4298#L795-1 assume !false; 4176#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4177#L481 assume !false; 4535#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4167#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4168#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4465#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4257#L420 assume !(0 != eval_~tmp~0); 4259#L496 start_simulation_~kernel_st~0 := 2; 4362#L338-1 start_simulation_~kernel_st~0 := 3; 4521#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4522#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4250#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4251#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4164#L521-3 assume !(0 == ~T4_E~0); 4165#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4402#L531-3 assume !(0 == ~E_1~0); 4403#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4291#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4292#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4346#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4347#L242-18 assume !(1 == ~m_pc~0); 4337#L242-20 is_master_triggered_~__retres1~0 := 0; 4336#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4339#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4340#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4416#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4417#L261-18 assume 1 == ~t1_pc~0; 4487#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4488#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4490#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4437#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4438#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4209#L280-18 assume 1 == ~t2_pc~0; 4210#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4228#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4232#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4527#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4528#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4410#L299-18 assume 1 == ~t3_pc~0; 4372#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4373#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4388#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4142#L653-18 assume !(0 != activate_threads_~tmp___2~0); 4134#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4135#L318-18 assume 1 == ~t4_pc~0; 4510#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4430#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4431#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4309#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4310#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 4321#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4401#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4284#L574-3 assume !(1 == ~T3_E~0); 4285#L579-3 assume !(1 == ~T4_E~0); 4363#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4218#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4219#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4239#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4240#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4157#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4145#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4146#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4466#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 4467#L814 assume !(0 == start_simulation_~tmp~3); 4523#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4150#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4151#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4445#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 4446#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4220#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 4221#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 4297#L827 assume !(0 != start_simulation_~tmp___0~1); 4298#L795-1 [2020-10-26 05:46:35,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,915 INFO L82 PathProgramCache]: Analyzing trace with hash -1414985347, now seen corresponding path program 1 times [2020-10-26 05:46:35,916 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,916 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936682658] [2020-10-26 05:46:35,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,947 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936682658] [2020-10-26 05:46:35,947 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,947 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:35,947 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966332211] [2020-10-26 05:46:35,948 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:35,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:35,948 INFO L82 PathProgramCache]: Analyzing trace with hash -254196081, now seen corresponding path program 1 times [2020-10-26 05:46:35,948 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:35,949 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823537593] [2020-10-26 05:46:35,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:35,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:35,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:35,981 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [823537593] [2020-10-26 05:46:35,981 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:35,981 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:35,981 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731709599] [2020-10-26 05:46:35,982 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:35,982 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:35,982 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:35,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:35,983 INFO L87 Difference]: Start difference. First operand 408 states and 612 transitions. cyclomatic complexity: 205 Second operand 3 states. [2020-10-26 05:46:36,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:36,056 INFO L93 Difference]: Finished difference Result 743 states and 1099 transitions. [2020-10-26 05:46:36,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:36,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 743 states and 1099 transitions. [2020-10-26 05:46:36,065 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 680 [2020-10-26 05:46:36,071 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 743 states to 743 states and 1099 transitions. [2020-10-26 05:46:36,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 743 [2020-10-26 05:46:36,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 743 [2020-10-26 05:46:36,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 743 states and 1099 transitions. [2020-10-26 05:46:36,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:36,074 INFO L691 BuchiCegarLoop]: Abstraction has 743 states and 1099 transitions. [2020-10-26 05:46:36,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 743 states and 1099 transitions. [2020-10-26 05:46:36,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 743 to 710. [2020-10-26 05:46:36,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 710 states. [2020-10-26 05:46:36,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 710 states to 710 states and 1053 transitions. [2020-10-26 05:46:36,092 INFO L714 BuchiCegarLoop]: Abstraction has 710 states and 1053 transitions. [2020-10-26 05:46:36,092 INFO L594 BuchiCegarLoop]: Abstraction has 710 states and 1053 transitions. [2020-10-26 05:46:36,092 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-10-26 05:46:36,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 710 states and 1053 transitions. [2020-10-26 05:46:36,097 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 647 [2020-10-26 05:46:36,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:36,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:36,099 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,099 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,099 INFO L794 eck$LassoCheckResult]: Stem: 5686#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5601#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5602#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5632#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 5309#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5310#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5547#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5548#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5422#L365-1 assume !(0 == ~M_E~0); 5423#L506-1 assume !(0 == ~T1_E~0); 5401#L511-1 assume !(0 == ~T2_E~0); 5402#L516-1 assume !(0 == ~T3_E~0); 5318#L521-1 assume !(0 == ~T4_E~0); 5319#L526-1 assume !(0 == ~E_M~0); 5556#L531-1 assume !(0 == ~E_1~0); 5557#L536-1 assume !(0 == ~E_2~0); 5440#L541-1 assume !(0 == ~E_3~0); 5441#L546-1 assume !(0 == ~E_4~0); 5516#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5517#L242 assume !(1 == ~m_pc~0); 5680#L242-2 is_master_triggered_~__retres1~0 := 0; 5681#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5482#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5452#L629 assume !(0 != activate_threads_~tmp~1); 5431#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5432#L261 assume !(1 == ~t1_pc~0); 5640#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 5641#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5642#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5628#L637 assume !(0 != activate_threads_~tmp___0~0); 5629#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5412#L280 assume 1 == ~t2_pc~0; 5362#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5363#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5365#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5366#L645 assume !(0 != activate_threads_~tmp___1~0); 5716#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5433#L299 assume !(1 == ~t3_pc~0); 5434#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 5426#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5427#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5330#L653 assume !(0 != activate_threads_~tmp___2~0); 5331#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5332#L318 assume 1 == ~t4_pc~0; 5607#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5605#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5606#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5673#L661 assume !(0 != activate_threads_~tmp___3~0); 5511#L661-2 assume !(1 == ~M_E~0); 5512#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5553#L569-1 assume !(1 == ~T2_E~0); 5436#L574-1 assume !(1 == ~T3_E~0); 5437#L579-1 assume !(1 == ~T4_E~0); 5515#L584-1 assume !(1 == ~E_M~0); 5370#L589-1 assume !(1 == ~E_1~0); 5371#L594-1 assume !(1 == ~E_2~0); 5288#L599-1 assume !(1 == ~E_3~0); 5289#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5630#L795-1 [2020-10-26 05:46:36,100 INFO L796 eck$LassoCheckResult]: Loop: 5630#L795-1 assume !false; 5804#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5799#L481 assume !false; 5796#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5754#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5721#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5625#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5415#L420 assume !(0 != eval_~tmp~0); 5417#L496 start_simulation_~kernel_st~0 := 2; 5519#L338-1 start_simulation_~kernel_st~0 := 3; 5699#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5700#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5408#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5409#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5322#L521-3 assume !(0 == ~T4_E~0); 5323#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5559#L531-3 assume !(0 == ~E_1~0); 5560#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5449#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5450#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5501#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5502#L242-18 assume !(1 == ~m_pc~0); 5675#L242-20 is_master_triggered_~__retres1~0 := 0; 5897#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5896#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5895#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5894#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5893#L261-18 assume 1 == ~t1_pc~0; 5891#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5890#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5889#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5888#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5887#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5886#L280-18 assume !(1 == ~t2_pc~0); 5884#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 5883#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5882#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5880#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5878#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5876#L299-18 assume 1 == ~t3_pc~0; 5873#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5871#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5868#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5866#L653-18 assume !(0 != activate_threads_~tmp___2~0); 5864#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5862#L318-18 assume 1 == ~t4_pc~0; 5859#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5857#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5794#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5793#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5792#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 5791#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5790#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5789#L574-3 assume !(1 == ~T3_E~0); 5787#L579-3 assume !(1 == ~T4_E~0); 5785#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5783#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5781#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5779#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5777#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5775#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5771#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5766#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5765#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5701#L814 assume !(0 == start_simulation_~tmp~3); 5702#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5827#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5825#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5823#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 5821#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5819#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 5816#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 5814#L827 assume !(0 != start_simulation_~tmp___0~1); 5630#L795-1 [2020-10-26 05:46:36,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,100 INFO L82 PathProgramCache]: Analyzing trace with hash 1923053566, now seen corresponding path program 1 times [2020-10-26 05:46:36,100 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,101 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019348963] [2020-10-26 05:46:36,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:36,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:36,135 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019348963] [2020-10-26 05:46:36,135 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:36,135 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:36,135 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814376279] [2020-10-26 05:46:36,135 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:36,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,136 INFO L82 PathProgramCache]: Analyzing trace with hash 145795118, now seen corresponding path program 1 times [2020-10-26 05:46:36,136 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,136 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652153277] [2020-10-26 05:46:36,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:36,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:36,165 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652153277] [2020-10-26 05:46:36,166 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:36,166 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:36,166 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777510008] [2020-10-26 05:46:36,166 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:36,166 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:36,167 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:36,167 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:36,167 INFO L87 Difference]: Start difference. First operand 710 states and 1053 transitions. cyclomatic complexity: 345 Second operand 4 states. [2020-10-26 05:46:36,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:36,348 INFO L93 Difference]: Finished difference Result 1608 states and 2350 transitions. [2020-10-26 05:46:36,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:36,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1608 states and 2350 transitions. [2020-10-26 05:46:36,365 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1505 [2020-10-26 05:46:36,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1608 states to 1608 states and 2350 transitions. [2020-10-26 05:46:36,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1608 [2020-10-26 05:46:36,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1608 [2020-10-26 05:46:36,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1608 states and 2350 transitions. [2020-10-26 05:46:36,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:36,381 INFO L691 BuchiCegarLoop]: Abstraction has 1608 states and 2350 transitions. [2020-10-26 05:46:36,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1608 states and 2350 transitions. [2020-10-26 05:46:36,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1608 to 1271. [2020-10-26 05:46:36,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1271 states. [2020-10-26 05:46:36,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1271 states to 1271 states and 1871 transitions. [2020-10-26 05:46:36,406 INFO L714 BuchiCegarLoop]: Abstraction has 1271 states and 1871 transitions. [2020-10-26 05:46:36,406 INFO L594 BuchiCegarLoop]: Abstraction has 1271 states and 1871 transitions. [2020-10-26 05:46:36,406 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-10-26 05:46:36,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1271 states and 1871 transitions. [2020-10-26 05:46:36,415 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1208 [2020-10-26 05:46:36,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:36,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:36,416 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,417 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,417 INFO L794 eck$LassoCheckResult]: Stem: 8024#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7938#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7939#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7970#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 7634#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7635#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7885#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7886#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7756#L365-1 assume !(0 == ~M_E~0); 7757#L506-1 assume !(0 == ~T1_E~0); 7733#L511-1 assume !(0 == ~T2_E~0); 7734#L516-1 assume !(0 == ~T3_E~0); 7644#L521-1 assume !(0 == ~T4_E~0); 7645#L526-1 assume !(0 == ~E_M~0); 7894#L531-1 assume !(0 == ~E_1~0); 7895#L536-1 assume !(0 == ~E_2~0); 7774#L541-1 assume !(0 == ~E_3~0); 7775#L546-1 assume !(0 == ~E_4~0); 7853#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7854#L242 assume !(1 == ~m_pc~0); 8017#L242-2 is_master_triggered_~__retres1~0 := 0; 8018#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7816#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7786#L629 assume !(0 != activate_threads_~tmp~1); 7765#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7766#L261 assume !(1 == ~t1_pc~0); 7978#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 7979#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7980#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7967#L637 assume !(0 != activate_threads_~tmp___0~0); 7968#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7746#L280 assume !(1 == ~t2_pc~0); 7740#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 7741#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7690#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7691#L645 assume !(0 != activate_threads_~tmp___1~0); 8046#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7767#L299 assume !(1 == ~t3_pc~0); 7768#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 7760#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7761#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7658#L653 assume !(0 != activate_threads_~tmp___2~0); 7659#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7660#L318 assume 1 == ~t4_pc~0; 7946#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7944#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7945#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8008#L661 assume !(0 != activate_threads_~tmp___3~0); 7848#L661-2 assume !(1 == ~M_E~0); 7849#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7891#L569-1 assume !(1 == ~T2_E~0); 7770#L574-1 assume !(1 == ~T3_E~0); 7771#L579-1 assume !(1 == ~T4_E~0); 7852#L584-1 assume !(1 == ~E_M~0); 7694#L589-1 assume !(1 == ~E_1~0); 7695#L594-1 assume !(1 == ~E_2~0); 7616#L599-1 assume !(1 == ~E_3~0); 7617#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7790#L795-1 [2020-10-26 05:46:36,417 INFO L796 eck$LassoCheckResult]: Loop: 7790#L795-1 assume !false; 7662#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7663#L481 assume !false; 8053#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7653#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7654#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7964#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7749#L420 assume !(0 != eval_~tmp~0); 7751#L496 start_simulation_~kernel_st~0 := 2; 7855#L338-1 start_simulation_~kernel_st~0 := 3; 8032#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8033#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7742#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7743#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7650#L521-3 assume !(0 == ~T4_E~0); 7651#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7897#L531-3 assume !(0 == ~E_1~0); 7898#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7783#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7784#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7835#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7836#L242-18 assume !(1 == ~m_pc~0); 7846#L242-20 is_master_triggered_~__retres1~0 := 0; 7847#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7828#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7829#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7913#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7914#L261-18 assume 1 == ~t1_pc~0; 7986#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7987#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7989#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7934#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7935#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7692#L280-18 assume !(1 == ~t2_pc~0); 7693#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 8765#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8763#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8761#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8759#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8757#L299-18 assume 1 == ~t3_pc~0; 8754#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8751#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8749#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8747#L653-18 assume !(0 != activate_threads_~tmp___2~0); 8745#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8743#L318-18 assume 1 == ~t4_pc~0; 8740#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8737#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8735#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8733#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8731#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 8729#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8727#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8725#L574-3 assume !(1 == ~T3_E~0); 8723#L579-3 assume !(1 == ~T4_E~0); 8721#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8719#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8718#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8717#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8716#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8715#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 8712#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 8707#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 8705#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 8704#L814 assume !(0 == start_simulation_~tmp~3); 8036#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7636#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7637#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7942#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 7943#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7701#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 7702#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 7789#L827 assume !(0 != start_simulation_~tmp___0~1); 7790#L795-1 [2020-10-26 05:46:36,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,418 INFO L82 PathProgramCache]: Analyzing trace with hash 250535935, now seen corresponding path program 1 times [2020-10-26 05:46:36,418 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,418 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384524104] [2020-10-26 05:46:36,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:36,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:36,453 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384524104] [2020-10-26 05:46:36,453 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:36,453 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:36,454 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [155641370] [2020-10-26 05:46:36,454 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:36,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,454 INFO L82 PathProgramCache]: Analyzing trace with hash 145795118, now seen corresponding path program 2 times [2020-10-26 05:46:36,455 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,455 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829603698] [2020-10-26 05:46:36,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:36,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:36,491 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829603698] [2020-10-26 05:46:36,491 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:36,492 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:36,492 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1935617483] [2020-10-26 05:46:36,492 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:36,492 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:36,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:36,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:36,493 INFO L87 Difference]: Start difference. First operand 1271 states and 1871 transitions. cyclomatic complexity: 602 Second operand 4 states. [2020-10-26 05:46:36,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:36,657 INFO L93 Difference]: Finished difference Result 2889 states and 4199 transitions. [2020-10-26 05:46:36,658 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:36,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2889 states and 4199 transitions. [2020-10-26 05:46:36,685 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2746 [2020-10-26 05:46:36,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2889 states to 2889 states and 4199 transitions. [2020-10-26 05:46:36,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2889 [2020-10-26 05:46:36,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2889 [2020-10-26 05:46:36,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2889 states and 4199 transitions. [2020-10-26 05:46:36,714 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:36,714 INFO L691 BuchiCegarLoop]: Abstraction has 2889 states and 4199 transitions. [2020-10-26 05:46:36,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2889 states and 4199 transitions. [2020-10-26 05:46:36,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2889 to 2312. [2020-10-26 05:46:36,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2312 states. [2020-10-26 05:46:36,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2312 states to 2312 states and 3384 transitions. [2020-10-26 05:46:36,776 INFO L714 BuchiCegarLoop]: Abstraction has 2312 states and 3384 transitions. [2020-10-26 05:46:36,776 INFO L594 BuchiCegarLoop]: Abstraction has 2312 states and 3384 transitions. [2020-10-26 05:46:36,776 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-10-26 05:46:36,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2312 states and 3384 transitions. [2020-10-26 05:46:36,791 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2248 [2020-10-26 05:46:36,791 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:36,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:36,793 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,793 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:36,793 INFO L794 eck$LassoCheckResult]: Stem: 12201#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12111#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12112#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12140#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 11805#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11806#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12054#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12055#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11924#L365-1 assume !(0 == ~M_E~0); 11925#L506-1 assume !(0 == ~T1_E~0); 11900#L511-1 assume !(0 == ~T2_E~0); 11901#L516-1 assume !(0 == ~T3_E~0); 11815#L521-1 assume !(0 == ~T4_E~0); 11816#L526-1 assume !(0 == ~E_M~0); 12064#L531-1 assume !(0 == ~E_1~0); 12065#L536-1 assume !(0 == ~E_2~0); 11942#L541-1 assume !(0 == ~E_3~0); 11943#L546-1 assume !(0 == ~E_4~0); 12021#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12022#L242 assume !(1 == ~m_pc~0); 12190#L242-2 is_master_triggered_~__retres1~0 := 0; 12191#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11984#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11954#L629 assume !(0 != activate_threads_~tmp~1); 11933#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11934#L261 assume !(1 == ~t1_pc~0); 12149#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 12150#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12151#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12137#L637 assume !(0 != activate_threads_~tmp___0~0); 12138#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11914#L280 assume !(1 == ~t2_pc~0); 11908#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 11909#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11861#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11862#L645 assume !(0 != activate_threads_~tmp___1~0); 12233#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11935#L299 assume !(1 == ~t3_pc~0); 11936#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 11928#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11929#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11829#L653 assume !(0 != activate_threads_~tmp___2~0); 11830#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11831#L318 assume !(1 == ~t4_pc~0); 12119#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 12117#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12118#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12182#L661 assume !(0 != activate_threads_~tmp___3~0); 12016#L661-2 assume !(1 == ~M_E~0); 12017#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12060#L569-1 assume !(1 == ~T2_E~0); 11938#L574-1 assume !(1 == ~T3_E~0); 11939#L579-1 assume !(1 == ~T4_E~0); 12020#L584-1 assume !(1 == ~E_M~0); 11865#L589-1 assume !(1 == ~E_1~0); 11866#L594-1 assume !(1 == ~E_2~0); 11786#L599-1 assume !(1 == ~E_3~0); 11787#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11958#L795-1 [2020-10-26 05:46:36,793 INFO L796 eck$LassoCheckResult]: Loop: 11958#L795-1 assume !false; 11833#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11834#L481 assume !false; 12241#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11824#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11825#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12134#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 11917#L420 assume !(0 != eval_~tmp~0); 11919#L496 start_simulation_~kernel_st~0 := 2; 12023#L338-1 start_simulation_~kernel_st~0 := 3; 12214#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12215#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11910#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11911#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11821#L521-3 assume !(0 == ~T4_E~0); 11822#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12067#L531-3 assume !(0 == ~E_1~0); 12068#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11951#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11952#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12003#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12004#L242-18 assume !(1 == ~m_pc~0); 12014#L242-20 is_master_triggered_~__retres1~0 := 0; 12015#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11996#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11997#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12084#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12085#L261-18 assume 1 == ~t1_pc~0; 12157#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12158#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12160#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12108#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12109#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11863#L280-18 assume !(1 == ~t2_pc~0); 11864#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 11881#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11887#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12226#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12227#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12077#L299-18 assume 1 == ~t3_pc~0; 12034#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12035#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12052#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11799#L653-18 assume !(0 != activate_threads_~tmp___2~0); 11790#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11791#L318-18 assume !(1 == ~t4_pc~0); 12218#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 12101#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12102#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11966#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11967#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 11978#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12066#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11944#L574-3 assume !(1 == ~T3_E~0); 11945#L579-3 assume !(1 == ~T4_E~0); 12025#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11871#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11872#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11896#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11897#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11814#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11802#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11803#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12135#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 12136#L814 assume !(0 == start_simulation_~tmp~3); 12217#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11807#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11808#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12115#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 12116#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11873#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 11874#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 11957#L827 assume !(0 != start_simulation_~tmp___0~1); 11958#L795-1 [2020-10-26 05:46:36,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,794 INFO L82 PathProgramCache]: Analyzing trace with hash -819887744, now seen corresponding path program 1 times [2020-10-26 05:46:36,794 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,794 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644839784] [2020-10-26 05:46:36,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:36,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:36,828 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644839784] [2020-10-26 05:46:36,828 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:36,828 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:36,829 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780883728] [2020-10-26 05:46:36,829 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:36,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:36,829 INFO L82 PathProgramCache]: Analyzing trace with hash -162643891, now seen corresponding path program 1 times [2020-10-26 05:46:36,830 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:36,830 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053505369] [2020-10-26 05:46:36,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:36,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:36,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:36,879 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053505369] [2020-10-26 05:46:36,879 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:36,879 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:36,880 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388819047] [2020-10-26 05:46:36,880 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:36,880 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:36,881 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:36,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:36,881 INFO L87 Difference]: Start difference. First operand 2312 states and 3384 transitions. cyclomatic complexity: 1074 Second operand 4 states. [2020-10-26 05:46:37,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:37,008 INFO L93 Difference]: Finished difference Result 4657 states and 6782 transitions. [2020-10-26 05:46:37,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:37,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4657 states and 6782 transitions. [2020-10-26 05:46:37,055 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4496 [2020-10-26 05:46:37,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4657 states to 4657 states and 6782 transitions. [2020-10-26 05:46:37,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4657 [2020-10-26 05:46:37,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4657 [2020-10-26 05:46:37,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4657 states and 6782 transitions. [2020-10-26 05:46:37,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:37,107 INFO L691 BuchiCegarLoop]: Abstraction has 4657 states and 6782 transitions. [2020-10-26 05:46:37,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4657 states and 6782 transitions. [2020-10-26 05:46:37,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4657 to 4657. [2020-10-26 05:46:37,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4657 states. [2020-10-26 05:46:37,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4657 states to 4657 states and 6782 transitions. [2020-10-26 05:46:37,211 INFO L714 BuchiCegarLoop]: Abstraction has 4657 states and 6782 transitions. [2020-10-26 05:46:37,211 INFO L594 BuchiCegarLoop]: Abstraction has 4657 states and 6782 transitions. [2020-10-26 05:46:37,211 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-10-26 05:46:37,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4657 states and 6782 transitions. [2020-10-26 05:46:37,233 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4496 [2020-10-26 05:46:37,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:37,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:37,235 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:37,235 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:37,236 INFO L794 eck$LassoCheckResult]: Stem: 19201#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 19105#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 19106#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19136#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 18786#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18787#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19038#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19039#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18907#L365-1 assume 0 == ~M_E~0;~M_E~0 := 1; 18908#L506-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19216#L511-1 assume !(0 == ~T2_E~0); 19315#L516-1 assume !(0 == ~T3_E~0); 19314#L521-1 assume !(0 == ~T4_E~0); 19313#L526-1 assume !(0 == ~E_M~0); 19312#L531-1 assume !(0 == ~E_1~0); 19311#L536-1 assume !(0 == ~E_2~0); 19310#L541-1 assume !(0 == ~E_3~0); 19309#L546-1 assume !(0 == ~E_4~0); 19308#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19307#L242 assume !(1 == ~m_pc~0); 19306#L242-2 is_master_triggered_~__retres1~0 := 0; 19305#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19304#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19303#L629 assume !(0 != activate_threads_~tmp~1); 19302#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19301#L261 assume !(1 == ~t1_pc~0); 19299#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 19298#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19297#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19296#L637 assume !(0 != activate_threads_~tmp___0~0); 19295#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19294#L280 assume !(1 == ~t2_pc~0); 19293#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 19292#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19291#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 19290#L645 assume !(0 != activate_threads_~tmp___1~0); 19289#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19288#L299 assume !(1 == ~t3_pc~0); 19286#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 19285#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19284#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 19283#L653 assume !(0 != activate_threads_~tmp___2~0); 19282#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19281#L318 assume !(1 == ~t4_pc~0); 19280#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 19279#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19278#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 19277#L661 assume !(0 != activate_threads_~tmp___3~0); 19276#L661-2 assume !(1 == ~M_E~0); 19274#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19275#L569-1 assume !(1 == ~T2_E~0); 22269#L574-1 assume !(1 == ~T3_E~0); 22267#L579-1 assume !(1 == ~T4_E~0); 22265#L584-1 assume !(1 == ~E_M~0); 22263#L589-1 assume !(1 == ~E_1~0); 22260#L594-1 assume !(1 == ~E_2~0); 22258#L599-1 assume !(1 == ~E_3~0); 19132#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19133#L795-1 [2020-10-26 05:46:37,236 INFO L796 eck$LassoCheckResult]: Loop: 19133#L795-1 assume !false; 21749#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 21677#L481 assume !false; 21746#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21745#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21739#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21737#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 21735#L420 assume !(0 != eval_~tmp~0); 19007#L496 start_simulation_~kernel_st~0 := 2; 19008#L338-1 start_simulation_~kernel_st~0 := 3; 19218#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 19219#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23015#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23013#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23011#L521-3 assume !(0 == ~T4_E~0); 23008#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23006#L531-3 assume !(0 == ~E_1~0); 23004#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23002#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23000#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22998#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22997#L242-18 assume !(1 == ~m_pc~0); 22994#L242-20 is_master_triggered_~__retres1~0 := 0; 22992#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22990#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22988#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22987#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22985#L261-18 assume 1 == ~t1_pc~0; 22981#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22979#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22977#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22976#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22975#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22702#L280-18 assume !(1 == ~t2_pc~0); 22703#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 22697#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22698#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22691#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22692#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22688#L299-18 assume 1 == ~t3_pc~0; 22686#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22683#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22684#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22676#L653-18 assume !(0 != activate_threads_~tmp___2~0); 22677#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21834#L318-18 assume !(1 == ~t4_pc~0); 21832#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 21828#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21826#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21824#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21822#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 21804#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21803#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21801#L574-3 assume !(1 == ~T3_E~0); 21799#L579-3 assume !(1 == ~T4_E~0); 21797#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21795#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21793#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21791#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21789#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21787#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21783#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21778#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21776#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 21775#L814 assume !(0 == start_simulation_~tmp~3); 21773#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21765#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21763#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21761#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 21759#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21757#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 21754#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 21752#L827 assume !(0 != start_simulation_~tmp___0~1); 19133#L795-1 [2020-10-26 05:46:37,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:37,236 INFO L82 PathProgramCache]: Analyzing trace with hash -323288768, now seen corresponding path program 1 times [2020-10-26 05:46:37,237 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:37,237 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090800583] [2020-10-26 05:46:37,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:37,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:37,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:37,257 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090800583] [2020-10-26 05:46:37,258 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:37,258 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:37,258 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233709689] [2020-10-26 05:46:37,258 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:37,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:37,259 INFO L82 PathProgramCache]: Analyzing trace with hash -162643891, now seen corresponding path program 2 times [2020-10-26 05:46:37,259 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:37,259 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872664758] [2020-10-26 05:46:37,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:37,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:37,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:37,286 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872664758] [2020-10-26 05:46:37,286 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:37,287 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:37,287 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424692332] [2020-10-26 05:46:37,287 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:37,287 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:37,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:37,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:37,288 INFO L87 Difference]: Start difference. First operand 4657 states and 6782 transitions. cyclomatic complexity: 2129 Second operand 3 states. [2020-10-26 05:46:37,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:37,384 INFO L93 Difference]: Finished difference Result 6938 states and 10103 transitions. [2020-10-26 05:46:37,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:37,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6938 states and 10103 transitions. [2020-10-26 05:46:37,437 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6816 [2020-10-26 05:46:37,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6938 states to 6938 states and 10103 transitions. [2020-10-26 05:46:37,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6938 [2020-10-26 05:46:37,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6938 [2020-10-26 05:46:37,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6938 states and 10103 transitions. [2020-10-26 05:46:37,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:37,511 INFO L691 BuchiCegarLoop]: Abstraction has 6938 states and 10103 transitions. [2020-10-26 05:46:37,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6938 states and 10103 transitions. [2020-10-26 05:46:37,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6938 to 5026. [2020-10-26 05:46:37,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5026 states. [2020-10-26 05:46:37,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5026 states to 5026 states and 7332 transitions. [2020-10-26 05:46:37,677 INFO L714 BuchiCegarLoop]: Abstraction has 5026 states and 7332 transitions. [2020-10-26 05:46:37,677 INFO L594 BuchiCegarLoop]: Abstraction has 5026 states and 7332 transitions. [2020-10-26 05:46:37,677 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-10-26 05:46:37,677 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5026 states and 7332 transitions. [2020-10-26 05:46:37,735 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4916 [2020-10-26 05:46:37,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:37,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:37,741 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:37,741 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:37,741 INFO L794 eck$LassoCheckResult]: Stem: 30798#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 30702#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 30703#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30737#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 30386#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30387#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30642#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30643#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30507#L365-1 assume !(0 == ~M_E~0); 30508#L506-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30481#L511-1 assume !(0 == ~T2_E~0); 30482#L516-1 assume !(0 == ~T3_E~0); 30723#L521-1 assume !(0 == ~T4_E~0); 30858#L526-1 assume !(0 == ~E_M~0); 30859#L531-1 assume !(0 == ~E_1~0); 30869#L536-1 assume !(0 == ~E_2~0); 30870#L541-1 assume !(0 == ~E_3~0); 30842#L546-1 assume !(0 == ~E_4~0); 30843#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30794#L242 assume !(1 == ~m_pc~0); 30795#L242-2 is_master_triggered_~__retres1~0 := 0; 30796#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30571#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30572#L629 assume !(0 != activate_threads_~tmp~1); 30516#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30517#L261 assume !(1 == ~t1_pc~0); 30745#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 30746#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30878#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30877#L637 assume !(0 != activate_threads_~tmp___0~0); 30876#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30494#L280 assume !(1 == ~t2_pc~0); 30495#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 30496#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30497#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30845#L645 assume !(0 != activate_threads_~tmp___1~0); 30846#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30518#L299 assume !(1 == ~t3_pc~0); 30519#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 30511#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30512#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30875#L653 assume !(0 != activate_threads_~tmp___2~0); 30874#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30873#L318 assume !(1 == ~t4_pc~0); 30872#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 30871#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30814#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30815#L661 assume !(0 != activate_threads_~tmp___3~0); 30605#L661-2 assume !(1 == ~M_E~0); 30606#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30650#L569-1 assume !(1 == ~T2_E~0); 30521#L574-1 assume !(1 == ~T3_E~0); 30522#L579-1 assume !(1 == ~T4_E~0); 30609#L584-1 assume !(1 == ~E_M~0); 30446#L589-1 assume !(1 == ~E_1~0); 30447#L594-1 assume !(1 == ~E_2~0); 30367#L599-1 assume !(1 == ~E_3~0); 30368#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30735#L795-1 [2020-10-26 05:46:37,742 INFO L796 eck$LassoCheckResult]: Loop: 30735#L795-1 assume !false; 34730#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 34687#L481 assume !false; 34720#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34715#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34707#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34706#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 34704#L420 assume !(0 != eval_~tmp~0); 34705#L496 start_simulation_~kernel_st~0 := 2; 35326#L338-1 start_simulation_~kernel_st~0 := 3; 35292#L506-2 assume !(0 == ~M_E~0); 35287#L506-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35284#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35058#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35059#L521-3 assume !(0 == ~T4_E~0); 35018#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35019#L531-3 assume !(0 == ~E_1~0); 35014#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35015#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35010#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35011#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34002#L242-18 assume !(1 == ~m_pc~0); 34003#L242-20 is_master_triggered_~__retres1~0 := 0; 33998#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33999#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 33994#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 33995#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33988#L261-18 assume 1 == ~t1_pc~0; 33989#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 33983#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33984#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 33978#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 33979#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33975#L280-18 assume !(1 == ~t2_pc~0); 33974#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 33972#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33970#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 33968#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 33966#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33964#L299-18 assume 1 == ~t3_pc~0; 33961#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 33958#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33956#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 33954#L653-18 assume !(0 != activate_threads_~tmp___2~0); 33952#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33950#L318-18 assume !(1 == ~t4_pc~0); 33538#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 33948#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33946#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 33944#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 33942#L661-20 assume !(1 == ~M_E~0); 33148#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33940#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33939#L574-3 assume !(1 == ~T3_E~0); 33938#L579-3 assume !(1 == ~T4_E~0); 33937#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33936#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33934#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33932#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33930#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33928#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 33924#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 33919#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33916#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 32908#L814 assume !(0 == start_simulation_~tmp~3); 32909#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34755#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34753#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34751#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 34749#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34747#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 34745#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 34740#L827 assume !(0 != start_simulation_~tmp___0~1); 30735#L795-1 [2020-10-26 05:46:37,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:37,745 INFO L82 PathProgramCache]: Analyzing trace with hash -804369026, now seen corresponding path program 1 times [2020-10-26 05:46:37,745 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:37,746 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713075394] [2020-10-26 05:46:37,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:37,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:37,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:37,886 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713075394] [2020-10-26 05:46:37,886 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:37,886 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:37,886 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72131450] [2020-10-26 05:46:37,887 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:37,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:37,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1909488465, now seen corresponding path program 1 times [2020-10-26 05:46:37,888 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:37,888 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118788189] [2020-10-26 05:46:37,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:37,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:37,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:37,922 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118788189] [2020-10-26 05:46:37,922 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:37,922 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:37,922 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760848240] [2020-10-26 05:46:37,923 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:37,923 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:37,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:37,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:37,924 INFO L87 Difference]: Start difference. First operand 5026 states and 7332 transitions. cyclomatic complexity: 2308 Second operand 4 states. [2020-10-26 05:46:38,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:38,008 INFO L93 Difference]: Finished difference Result 6192 states and 8980 transitions. [2020-10-26 05:46:38,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:38,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6192 states and 8980 transitions. [2020-10-26 05:46:38,056 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6120 [2020-10-26 05:46:38,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6192 states to 6192 states and 8980 transitions. [2020-10-26 05:46:38,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6192 [2020-10-26 05:46:38,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6192 [2020-10-26 05:46:38,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6192 states and 8980 transitions. [2020-10-26 05:46:38,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:38,121 INFO L691 BuchiCegarLoop]: Abstraction has 6192 states and 8980 transitions. [2020-10-26 05:46:38,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6192 states and 8980 transitions. [2020-10-26 05:46:38,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6192 to 4288. [2020-10-26 05:46:38,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4288 states. [2020-10-26 05:46:38,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4288 states to 4288 states and 6232 transitions. [2020-10-26 05:46:38,354 INFO L714 BuchiCegarLoop]: Abstraction has 4288 states and 6232 transitions. [2020-10-26 05:46:38,354 INFO L594 BuchiCegarLoop]: Abstraction has 4288 states and 6232 transitions. [2020-10-26 05:46:38,354 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-10-26 05:46:38,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4288 states and 6232 transitions. [2020-10-26 05:46:38,369 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4220 [2020-10-26 05:46:38,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:38,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:38,371 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:38,371 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:38,371 INFO L794 eck$LassoCheckResult]: Stem: 42022#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 41928#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 41929#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41961#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 41614#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41615#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41870#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41871#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41738#L365-1 assume !(0 == ~M_E~0); 41739#L506-1 assume !(0 == ~T1_E~0); 41713#L511-1 assume !(0 == ~T2_E~0); 41714#L516-1 assume !(0 == ~T3_E~0); 41625#L521-1 assume !(0 == ~T4_E~0); 41626#L526-1 assume !(0 == ~E_M~0); 41879#L531-1 assume !(0 == ~E_1~0); 41880#L536-1 assume !(0 == ~E_2~0); 41756#L541-1 assume !(0 == ~E_3~0); 41757#L546-1 assume !(0 == ~E_4~0); 41837#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41838#L242 assume !(1 == ~m_pc~0); 42012#L242-2 is_master_triggered_~__retres1~0 := 0; 42013#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41799#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 41768#L629 assume !(0 != activate_threads_~tmp~1); 41747#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41748#L261 assume !(1 == ~t1_pc~0); 41970#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 41971#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41972#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41957#L637 assume !(0 != activate_threads_~tmp___0~0); 41958#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41728#L280 assume !(1 == ~t2_pc~0); 41722#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 41723#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41672#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 41673#L645 assume !(0 != activate_threads_~tmp___1~0); 42059#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41749#L299 assume !(1 == ~t3_pc~0); 41750#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 41742#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41743#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 41640#L653 assume !(0 != activate_threads_~tmp___2~0); 41641#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41642#L318 assume !(1 == ~t4_pc~0); 41936#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 41934#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41935#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 42004#L661 assume !(0 != activate_threads_~tmp___3~0); 41832#L661-2 assume !(1 == ~M_E~0); 41833#L564-1 assume !(1 == ~T1_E~0); 41876#L569-1 assume !(1 == ~T2_E~0); 41752#L574-1 assume !(1 == ~T3_E~0); 41753#L579-1 assume !(1 == ~T4_E~0); 41836#L584-1 assume !(1 == ~E_M~0); 41676#L589-1 assume !(1 == ~E_1~0); 41677#L594-1 assume !(1 == ~E_2~0); 41595#L599-1 assume !(1 == ~E_3~0); 41596#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 41959#L795-1 [2020-10-26 05:46:38,371 INFO L796 eck$LassoCheckResult]: Loop: 41959#L795-1 assume !false; 45450#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 41716#L481 assume !false; 45449#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 41635#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 41636#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 41952#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 41731#L420 assume !(0 != eval_~tmp~0); 41733#L496 start_simulation_~kernel_st~0 := 2; 41839#L338-1 start_simulation_~kernel_st~0 := 3; 42036#L506-2 assume !(0 == ~M_E~0); 42037#L506-4 assume !(0 == ~T1_E~0); 41724#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41725#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45876#L521-3 assume !(0 == ~T4_E~0); 42071#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41882#L531-3 assume !(0 == ~E_1~0); 41883#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41765#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41766#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42061#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45865#L242-18 assume !(1 == ~m_pc~0); 45863#L242-20 is_master_triggered_~__retres1~0 := 0; 42026#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41811#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 41812#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 41902#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41903#L261-18 assume 1 == ~t1_pc~0; 41979#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 41980#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41982#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41983#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 45809#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41674#L280-18 assume !(1 == ~t2_pc~0); 41675#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 45757#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45755#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 45753#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 45751#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45749#L299-18 assume 1 == ~t3_pc~0; 45744#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 45742#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45740#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 45738#L653-18 assume !(0 != activate_threads_~tmp___2~0); 45736#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 45734#L318-18 assume !(1 == ~t4_pc~0); 44937#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 45731#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45728#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 45726#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 45724#L661-20 assume !(1 == ~M_E~0); 44376#L564-3 assume !(1 == ~T1_E~0); 45721#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45719#L574-3 assume !(1 == ~T3_E~0); 45716#L579-3 assume !(1 == ~T4_E~0); 45714#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45712#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45710#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45708#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45706#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45696#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 45578#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 45478#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 45477#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 42040#L814 assume !(0 == start_simulation_~tmp~3); 42042#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 45459#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 45458#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 45457#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 45456#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 45455#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 45454#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 45453#L827 assume !(0 != start_simulation_~tmp___0~1); 41959#L795-1 [2020-10-26 05:46:38,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:38,372 INFO L82 PathProgramCache]: Analyzing trace with hash -139829374, now seen corresponding path program 1 times [2020-10-26 05:46:38,372 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:38,372 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950271816] [2020-10-26 05:46:38,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:38,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:38,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:38,427 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950271816] [2020-10-26 05:46:38,427 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:38,427 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:38,427 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [576710463] [2020-10-26 05:46:38,428 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:38,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:38,429 INFO L82 PathProgramCache]: Analyzing trace with hash -1487351859, now seen corresponding path program 1 times [2020-10-26 05:46:38,429 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:38,429 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661049748] [2020-10-26 05:46:38,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:38,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:38,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:38,465 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661049748] [2020-10-26 05:46:38,465 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:38,465 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:38,466 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59936076] [2020-10-26 05:46:38,466 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:38,466 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:38,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:38,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:38,467 INFO L87 Difference]: Start difference. First operand 4288 states and 6232 transitions. cyclomatic complexity: 1946 Second operand 4 states. [2020-10-26 05:46:38,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:38,625 INFO L93 Difference]: Finished difference Result 6686 states and 9621 transitions. [2020-10-26 05:46:38,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:38,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6686 states and 9621 transitions. [2020-10-26 05:46:38,662 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6564 [2020-10-26 05:46:38,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6686 states to 6686 states and 9621 transitions. [2020-10-26 05:46:38,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6686 [2020-10-26 05:46:38,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6686 [2020-10-26 05:46:38,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6686 states and 9621 transitions. [2020-10-26 05:46:38,797 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:38,797 INFO L691 BuchiCegarLoop]: Abstraction has 6686 states and 9621 transitions. [2020-10-26 05:46:38,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6686 states and 9621 transitions. [2020-10-26 05:46:38,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6686 to 5018. [2020-10-26 05:46:38,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5018 states. [2020-10-26 05:46:38,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5018 states to 5018 states and 7221 transitions. [2020-10-26 05:46:38,892 INFO L714 BuchiCegarLoop]: Abstraction has 5018 states and 7221 transitions. [2020-10-26 05:46:38,893 INFO L594 BuchiCegarLoop]: Abstraction has 5018 states and 7221 transitions. [2020-10-26 05:46:38,893 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-10-26 05:46:38,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5018 states and 7221 transitions. [2020-10-26 05:46:38,910 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4908 [2020-10-26 05:46:38,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:38,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:38,912 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:38,913 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:38,913 INFO L794 eck$LassoCheckResult]: Stem: 53008#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 52918#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 52919#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 52948#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 52601#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52602#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52852#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52853#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52723#L365-1 assume !(0 == ~M_E~0); 52724#L506-1 assume !(0 == ~T1_E~0); 52698#L511-1 assume !(0 == ~T2_E~0); 52699#L516-1 assume !(0 == ~T3_E~0); 52611#L521-1 assume !(0 == ~T4_E~0); 52612#L526-1 assume !(0 == ~E_M~0); 52861#L531-1 assume !(0 == ~E_1~0); 52862#L536-1 assume !(0 == ~E_2~0); 52739#L541-1 assume !(0 == ~E_3~0); 52740#L546-1 assume 0 == ~E_4~0;~E_4~0 := 1; 52818#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52819#L242 assume !(1 == ~m_pc~0); 52999#L242-2 is_master_triggered_~__retres1~0 := 0; 53000#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52782#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 52751#L629 assume !(0 != activate_threads_~tmp~1); 52730#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52731#L261 assume !(1 == ~t1_pc~0); 52956#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 52957#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52958#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 52943#L637 assume !(0 != activate_threads_~tmp___0~0); 52944#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52710#L280 assume !(1 == ~t2_pc~0); 52704#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 52705#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52655#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 52656#L645 assume !(0 != activate_threads_~tmp___1~0); 53041#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53042#L299 assume !(1 == ~t3_pc~0); 52864#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 52725#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52726#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 52623#L653 assume !(0 != activate_threads_~tmp___2~0); 52624#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 52625#L318 assume !(1 == ~t4_pc~0); 52922#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 52920#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52921#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 52991#L661 assume !(0 != activate_threads_~tmp___3~0); 52813#L661-2 assume !(1 == ~M_E~0); 52814#L564-1 assume !(1 == ~T1_E~0); 52858#L569-1 assume !(1 == ~T2_E~0); 52735#L574-1 assume !(1 == ~T3_E~0); 52736#L579-1 assume !(1 == ~T4_E~0); 52817#L584-1 assume !(1 == ~E_M~0); 52661#L589-1 assume !(1 == ~E_1~0); 52662#L594-1 assume !(1 == ~E_2~0); 52579#L599-1 assume !(1 == ~E_3~0); 52580#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 52946#L795-1 [2020-10-26 05:46:38,913 INFO L796 eck$LassoCheckResult]: Loop: 52946#L795-1 assume !false; 56244#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 56241#L481 assume !false; 56240#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 56239#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 56234#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 56233#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 56231#L420 assume !(0 != eval_~tmp~0); 56232#L496 start_simulation_~kernel_st~0 := 2; 57518#L338-1 start_simulation_~kernel_st~0 := 3; 57516#L506-2 assume !(0 == ~M_E~0); 57514#L506-4 assume !(0 == ~T1_E~0); 57512#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57510#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57507#L521-3 assume !(0 == ~T4_E~0); 57505#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57503#L531-3 assume !(0 == ~E_1~0); 57501#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57499#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56874#L546-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56875#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56865#L242-18 assume !(1 == ~m_pc~0); 56866#L242-20 is_master_triggered_~__retres1~0 := 0; 56861#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56862#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 56856#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 56857#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56848#L261-18 assume 1 == ~t1_pc~0; 56849#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 57227#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57226#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 57225#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 57224#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 57223#L280-18 assume !(1 == ~t2_pc~0); 56061#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 57222#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57221#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 57220#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 57219#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57218#L299-18 assume 1 == ~t3_pc~0; 57216#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 57215#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57214#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 57213#L653-18 assume !(0 != activate_threads_~tmp___2~0); 57212#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56034#L318-18 assume !(1 == ~t4_pc~0); 56031#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 56029#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56026#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56024#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 56021#L661-20 assume !(1 == ~M_E~0); 55120#L564-3 assume !(1 == ~T1_E~0); 56017#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56014#L574-3 assume !(1 == ~T3_E~0); 56011#L579-3 assume !(1 == ~T4_E~0); 56005#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56000#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55995#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55990#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55601#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55600#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 53234#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 53205#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 53199#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 53192#L814 assume !(0 == start_simulation_~tmp~3); 53193#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 56578#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 56576#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 56574#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 56289#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 56287#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 56285#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 56249#L827 assume !(0 != start_simulation_~tmp___0~1); 52946#L795-1 [2020-10-26 05:46:38,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:38,914 INFO L82 PathProgramCache]: Analyzing trace with hash -563476096, now seen corresponding path program 1 times [2020-10-26 05:46:38,914 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:38,914 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897814637] [2020-10-26 05:46:38,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:38,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:38,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:38,949 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897814637] [2020-10-26 05:46:38,949 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:38,949 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:38,950 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459950614] [2020-10-26 05:46:38,950 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:38,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:38,951 INFO L82 PathProgramCache]: Analyzing trace with hash -1487351859, now seen corresponding path program 2 times [2020-10-26 05:46:38,951 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:38,951 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254339403] [2020-10-26 05:46:38,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:38,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:38,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:38,978 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254339403] [2020-10-26 05:46:38,979 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:38,979 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:38,979 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984535022] [2020-10-26 05:46:38,980 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:38,980 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:38,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:46:38,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:46:38,981 INFO L87 Difference]: Start difference. First operand 5018 states and 7221 transitions. cyclomatic complexity: 2205 Second operand 4 states. [2020-10-26 05:46:39,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:39,075 INFO L93 Difference]: Finished difference Result 5924 states and 8498 transitions. [2020-10-26 05:46:39,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:46:39,076 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5924 states and 8498 transitions. [2020-10-26 05:46:39,158 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5844 [2020-10-26 05:46:39,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5924 states to 5924 states and 8498 transitions. [2020-10-26 05:46:39,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5924 [2020-10-26 05:46:39,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5924 [2020-10-26 05:46:39,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5924 states and 8498 transitions. [2020-10-26 05:46:39,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:39,201 INFO L691 BuchiCegarLoop]: Abstraction has 5924 states and 8498 transitions. [2020-10-26 05:46:39,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5924 states and 8498 transitions. [2020-10-26 05:46:39,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5924 to 4288. [2020-10-26 05:46:39,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4288 states. [2020-10-26 05:46:39,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4288 states to 4288 states and 6146 transitions. [2020-10-26 05:46:39,286 INFO L714 BuchiCegarLoop]: Abstraction has 4288 states and 6146 transitions. [2020-10-26 05:46:39,286 INFO L594 BuchiCegarLoop]: Abstraction has 4288 states and 6146 transitions. [2020-10-26 05:46:39,286 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-10-26 05:46:39,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4288 states and 6146 transitions. [2020-10-26 05:46:39,300 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4220 [2020-10-26 05:46:39,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:39,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:39,302 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:39,302 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:39,302 INFO L794 eck$LassoCheckResult]: Stem: 63954#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 63867#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 63868#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 63899#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 63549#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63550#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63807#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63808#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63673#L365-1 assume !(0 == ~M_E~0); 63674#L506-1 assume !(0 == ~T1_E~0); 63649#L511-1 assume !(0 == ~T2_E~0); 63650#L516-1 assume !(0 == ~T3_E~0); 63560#L521-1 assume !(0 == ~T4_E~0); 63561#L526-1 assume !(0 == ~E_M~0); 63816#L531-1 assume !(0 == ~E_1~0); 63817#L536-1 assume !(0 == ~E_2~0); 63691#L541-1 assume !(0 == ~E_3~0); 63692#L546-1 assume !(0 == ~E_4~0); 63771#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 63772#L242 assume !(1 == ~m_pc~0); 63945#L242-2 is_master_triggered_~__retres1~0 := 0; 63946#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 63735#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 63704#L629 assume !(0 != activate_threads_~tmp~1); 63682#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 63683#L261 assume !(1 == ~t1_pc~0); 63908#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 63909#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 63910#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 63895#L637 assume !(0 != activate_threads_~tmp___0~0); 63896#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 63663#L280 assume !(1 == ~t2_pc~0); 63657#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 63658#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 63607#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 63608#L645 assume !(0 != activate_threads_~tmp___1~0); 63989#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 63684#L299 assume !(1 == ~t3_pc~0); 63685#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 63677#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 63678#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 63575#L653 assume !(0 != activate_threads_~tmp___2~0); 63576#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 63577#L318 assume !(1 == ~t4_pc~0); 63875#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 63873#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 63874#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 63939#L661 assume !(0 != activate_threads_~tmp___3~0); 63766#L661-2 assume !(1 == ~M_E~0); 63767#L564-1 assume !(1 == ~T1_E~0); 63813#L569-1 assume !(1 == ~T2_E~0); 63687#L574-1 assume !(1 == ~T3_E~0); 63688#L579-1 assume !(1 == ~T4_E~0); 63770#L584-1 assume !(1 == ~E_M~0); 63611#L589-1 assume !(1 == ~E_1~0); 63612#L594-1 assume !(1 == ~E_2~0); 63531#L599-1 assume !(1 == ~E_3~0); 63532#L604-1 assume !(1 == ~E_4~0); 63897#L795-1 [2020-10-26 05:46:39,303 INFO L796 eck$LassoCheckResult]: Loop: 63897#L795-1 assume !false; 67733#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 67610#L481 assume !false; 67732#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 63570#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 63571#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 63892#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 63666#L420 assume !(0 != eval_~tmp~0); 63668#L496 start_simulation_~kernel_st~0 := 2; 67683#L338-1 start_simulation_~kernel_st~0 := 3; 67681#L506-2 assume !(0 == ~M_E~0); 67680#L506-4 assume !(0 == ~T1_E~0); 67679#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67678#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67677#L521-3 assume !(0 == ~T4_E~0); 67676#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67670#L531-3 assume !(0 == ~E_1~0); 67668#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67666#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67664#L546-3 assume !(0 == ~E_4~0); 67662#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67660#L242-18 assume !(1 == ~m_pc~0); 67658#L242-20 is_master_triggered_~__retres1~0 := 0; 67656#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 67608#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 63838#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 63839#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 63840#L261-18 assume 1 == ~t1_pc~0; 63916#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 63917#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 63919#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 63864#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 63865#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 63973#L280-18 assume !(1 == ~t2_pc~0); 66260#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 66258#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66256#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 66254#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 66252#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66250#L299-18 assume 1 == ~t3_pc~0; 66247#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 66245#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66243#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 66241#L653-18 assume !(0 != activate_threads_~tmp___2~0); 66239#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 66237#L318-18 assume !(1 == ~t4_pc~0); 66124#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 66233#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 66231#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 66229#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 66227#L661-20 assume !(1 == ~M_E~0); 65992#L564-3 assume !(1 == ~T1_E~0); 66224#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66221#L574-3 assume !(1 == ~T3_E~0); 66219#L579-3 assume !(1 == ~T4_E~0); 66217#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66215#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66213#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66211#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66208#L604-3 assume !(1 == ~E_4~0); 66206#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 66095#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 66086#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 66084#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 66081#L814 assume !(0 == start_simulation_~tmp~3); 66082#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 67740#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 67739#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 67738#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 67737#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 67736#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 67735#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 67734#L827 assume !(0 != start_simulation_~tmp___0~1); 63897#L795-1 [2020-10-26 05:46:39,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:39,303 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 1 times [2020-10-26 05:46:39,303 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:39,304 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164116071] [2020-10-26 05:46:39,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:39,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:39,318 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:39,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:39,327 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:39,366 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:39,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:39,366 INFO L82 PathProgramCache]: Analyzing trace with hash -1622450103, now seen corresponding path program 1 times [2020-10-26 05:46:39,367 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:39,367 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612494467] [2020-10-26 05:46:39,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:39,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:39,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:39,402 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612494467] [2020-10-26 05:46:39,402 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:39,402 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:39,402 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1166796242] [2020-10-26 05:46:39,403 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:39,403 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:39,403 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:39,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:39,404 INFO L87 Difference]: Start difference. First operand 4288 states and 6146 transitions. cyclomatic complexity: 1860 Second operand 3 states. [2020-10-26 05:46:39,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:39,448 INFO L93 Difference]: Finished difference Result 5026 states and 7170 transitions. [2020-10-26 05:46:39,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:39,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5026 states and 7170 transitions. [2020-10-26 05:46:39,474 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4916 [2020-10-26 05:46:39,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5026 states to 5026 states and 7170 transitions. [2020-10-26 05:46:39,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5026 [2020-10-26 05:46:39,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5026 [2020-10-26 05:46:39,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5026 states and 7170 transitions. [2020-10-26 05:46:39,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:39,508 INFO L691 BuchiCegarLoop]: Abstraction has 5026 states and 7170 transitions. [2020-10-26 05:46:39,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5026 states and 7170 transitions. [2020-10-26 05:46:39,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5026 to 5026. [2020-10-26 05:46:39,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5026 states. [2020-10-26 05:46:39,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5026 states to 5026 states and 7170 transitions. [2020-10-26 05:46:39,608 INFO L714 BuchiCegarLoop]: Abstraction has 5026 states and 7170 transitions. [2020-10-26 05:46:39,608 INFO L594 BuchiCegarLoop]: Abstraction has 5026 states and 7170 transitions. [2020-10-26 05:46:39,609 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-10-26 05:46:39,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5026 states and 7170 transitions. [2020-10-26 05:46:39,625 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4916 [2020-10-26 05:46:39,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:39,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:39,628 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:39,628 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:39,629 INFO L794 eck$LassoCheckResult]: Stem: 73298#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 73198#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 73199#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 73236#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 72869#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72870#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73130#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73131#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72996#L365-1 assume !(0 == ~M_E~0); 72997#L506-1 assume !(0 == ~T1_E~0); 72968#L511-1 assume !(0 == ~T2_E~0); 72969#L516-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 73221#L521-1 assume !(0 == ~T4_E~0); 73365#L526-1 assume !(0 == ~E_M~0); 73366#L531-1 assume !(0 == ~E_1~0); 73383#L536-1 assume !(0 == ~E_2~0); 73384#L541-1 assume !(0 == ~E_3~0); 73352#L546-1 assume !(0 == ~E_4~0); 73353#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 73293#L242 assume !(1 == ~m_pc~0); 73294#L242-2 is_master_triggered_~__retres1~0 := 0; 73295#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 73059#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 73060#L629 assume !(0 != activate_threads_~tmp~1); 73005#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 73006#L261 assume !(1 == ~t1_pc~0); 73245#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 73246#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 73394#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 73393#L637 assume !(0 != activate_threads_~tmp___0~0); 73392#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 72983#L280 assume !(1 == ~t2_pc~0); 72984#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 72985#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 72986#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 73356#L645 assume !(0 != activate_threads_~tmp___1~0); 73357#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 73007#L299 assume !(1 == ~t3_pc~0); 73008#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 73000#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 73001#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 73391#L653 assume !(0 != activate_threads_~tmp___2~0); 73390#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 73389#L318 assume !(1 == ~t4_pc~0); 73388#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 73387#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 73320#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 73321#L661 assume !(0 != activate_threads_~tmp___3~0); 73091#L661-2 assume !(1 == ~M_E~0); 73092#L564-1 assume !(1 == ~T1_E~0); 73382#L569-1 assume !(1 == ~T2_E~0); 73010#L574-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73011#L579-1 assume !(1 == ~T4_E~0); 73095#L584-1 assume !(1 == ~E_M~0); 72930#L589-1 assume !(1 == ~E_1~0); 72931#L594-1 assume !(1 == ~E_2~0); 72851#L599-1 assume !(1 == ~E_3~0); 72852#L604-1 assume !(1 == ~E_4~0); 73234#L795-1 [2020-10-26 05:46:39,629 INFO L796 eck$LassoCheckResult]: Loop: 73234#L795-1 assume !false; 75781#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 75778#L481 assume !false; 75777#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 75776#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 75771#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 75769#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 75766#L420 assume !(0 != eval_~tmp~0); 75767#L496 start_simulation_~kernel_st~0 := 2; 76638#L338-1 start_simulation_~kernel_st~0 := 3; 76636#L506-2 assume !(0 == ~M_E~0); 76634#L506-4 assume !(0 == ~T1_E~0); 76632#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76629#L516-3 assume !(0 == ~T3_E~0); 76627#L521-3 assume !(0 == ~T4_E~0); 76624#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 76622#L531-3 assume !(0 == ~E_1~0); 76620#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76618#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76616#L546-3 assume !(0 == ~E_4~0); 76614#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76609#L242-18 assume !(1 == ~m_pc~0); 76607#L242-20 is_master_triggered_~__retres1~0 := 0; 76605#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76603#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 76600#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 76601#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 77464#L261-18 assume !(1 == ~t1_pc~0); 77463#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 77461#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76586#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 76583#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 76582#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 75967#L280-18 assume !(1 == ~t2_pc~0); 75964#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 75962#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 75960#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 75958#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 75956#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 75954#L299-18 assume !(1 == ~t3_pc~0); 75953#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 75950#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 75948#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 75946#L653-18 assume !(0 != activate_threads_~tmp___2~0); 75945#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 75944#L318-18 assume !(1 == ~t4_pc~0); 75417#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 75942#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 75941#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 75939#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 75936#L661-20 assume !(1 == ~M_E~0); 75932#L564-3 assume !(1 == ~T1_E~0); 75930#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75837#L574-3 assume !(1 == ~T3_E~0); 75835#L579-3 assume !(1 == ~T4_E~0); 75834#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 75833#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 75832#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75831#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75829#L604-3 assume !(1 == ~E_4~0); 75827#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 75823#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 75818#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 75816#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 75813#L814 assume !(0 == start_simulation_~tmp~3); 75809#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 75799#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 75798#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 75796#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 75794#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 75792#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 75788#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 75786#L827 assume !(0 != start_simulation_~tmp___0~1); 73234#L795-1 [2020-10-26 05:46:39,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:39,630 INFO L82 PathProgramCache]: Analyzing trace with hash -1561748352, now seen corresponding path program 1 times [2020-10-26 05:46:39,630 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:39,631 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895937041] [2020-10-26 05:46:39,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:39,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:39,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:39,657 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895937041] [2020-10-26 05:46:39,658 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:39,658 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:39,658 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411341700] [2020-10-26 05:46:39,658 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:39,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:39,659 INFO L82 PathProgramCache]: Analyzing trace with hash -62313915, now seen corresponding path program 1 times [2020-10-26 05:46:39,659 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:39,660 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475920653] [2020-10-26 05:46:39,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:39,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:39,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:39,739 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475920653] [2020-10-26 05:46:39,740 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:39,740 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:46:39,740 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607663824] [2020-10-26 05:46:39,740 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:39,740 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:39,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:39,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:39,741 INFO L87 Difference]: Start difference. First operand 5026 states and 7170 transitions. cyclomatic complexity: 2146 Second operand 3 states. [2020-10-26 05:46:39,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:39,774 INFO L93 Difference]: Finished difference Result 4288 states and 6096 transitions. [2020-10-26 05:46:39,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:39,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4288 states and 6096 transitions. [2020-10-26 05:46:39,794 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4220 [2020-10-26 05:46:39,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4288 states to 4288 states and 6096 transitions. [2020-10-26 05:46:39,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4288 [2020-10-26 05:46:39,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4288 [2020-10-26 05:46:39,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4288 states and 6096 transitions. [2020-10-26 05:46:39,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:39,818 INFO L691 BuchiCegarLoop]: Abstraction has 4288 states and 6096 transitions. [2020-10-26 05:46:39,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4288 states and 6096 transitions. [2020-10-26 05:46:39,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4288 to 4288. [2020-10-26 05:46:39,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4288 states. [2020-10-26 05:46:39,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4288 states to 4288 states and 6096 transitions. [2020-10-26 05:46:39,885 INFO L714 BuchiCegarLoop]: Abstraction has 4288 states and 6096 transitions. [2020-10-26 05:46:39,885 INFO L594 BuchiCegarLoop]: Abstraction has 4288 states and 6096 transitions. [2020-10-26 05:46:39,885 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-10-26 05:46:39,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4288 states and 6096 transitions. [2020-10-26 05:46:39,898 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4220 [2020-10-26 05:46:39,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:39,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:39,900 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:39,901 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:39,901 INFO L794 eck$LassoCheckResult]: Stem: 82592#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 82505#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 82506#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 82537#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 82192#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82193#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82442#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82443#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82313#L365-1 assume !(0 == ~M_E~0); 82314#L506-1 assume !(0 == ~T1_E~0); 82288#L511-1 assume !(0 == ~T2_E~0); 82289#L516-1 assume !(0 == ~T3_E~0); 82202#L521-1 assume !(0 == ~T4_E~0); 82203#L526-1 assume !(0 == ~E_M~0); 82452#L531-1 assume !(0 == ~E_1~0); 82453#L536-1 assume !(0 == ~E_2~0); 82331#L541-1 assume !(0 == ~E_3~0); 82332#L546-1 assume !(0 == ~E_4~0); 82409#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 82410#L242 assume !(1 == ~m_pc~0); 82584#L242-2 is_master_triggered_~__retres1~0 := 0; 82585#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 82375#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 82344#L629 assume !(0 != activate_threads_~tmp~1); 82322#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 82323#L261 assume !(1 == ~t1_pc~0); 82545#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 82546#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 82547#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 82533#L637 assume !(0 != activate_threads_~tmp___0~0); 82534#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 82303#L280 assume !(1 == ~t2_pc~0); 82297#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 82298#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 82248#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 82249#L645 assume !(0 != activate_threads_~tmp___1~0); 82629#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 82324#L299 assume !(1 == ~t3_pc~0); 82325#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 82317#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 82318#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 82216#L653 assume !(0 != activate_threads_~tmp___2~0); 82217#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 82218#L318 assume !(1 == ~t4_pc~0); 82513#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 82511#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 82512#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 82577#L661 assume !(0 != activate_threads_~tmp___3~0); 82404#L661-2 assume !(1 == ~M_E~0); 82405#L564-1 assume !(1 == ~T1_E~0); 82449#L569-1 assume !(1 == ~T2_E~0); 82327#L574-1 assume !(1 == ~T3_E~0); 82328#L579-1 assume !(1 == ~T4_E~0); 82408#L584-1 assume !(1 == ~E_M~0); 82252#L589-1 assume !(1 == ~E_1~0); 82253#L594-1 assume !(1 == ~E_2~0); 82174#L599-1 assume !(1 == ~E_3~0); 82175#L604-1 assume !(1 == ~E_4~0); 82535#L795-1 [2020-10-26 05:46:39,902 INFO L796 eck$LassoCheckResult]: Loop: 82535#L795-1 assume !false; 85646#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 83916#L481 assume !false; 85645#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 85644#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 82640#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 82529#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 82306#L420 assume !(0 != eval_~tmp~0); 82308#L496 start_simulation_~kernel_st~0 := 2; 86338#L338-1 start_simulation_~kernel_st~0 := 3; 86336#L506-2 assume !(0 == ~M_E~0); 86334#L506-4 assume !(0 == ~T1_E~0); 86332#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86330#L516-3 assume !(0 == ~T3_E~0); 86328#L521-3 assume !(0 == ~T4_E~0); 86325#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 86323#L531-3 assume !(0 == ~E_1~0); 86322#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86319#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86317#L546-3 assume !(0 == ~E_4~0); 86315#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86313#L242-18 assume !(1 == ~m_pc~0); 86312#L242-20 is_master_triggered_~__retres1~0 := 0; 86223#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86222#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 86221#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 86220#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86219#L261-18 assume !(1 == ~t1_pc~0); 86217#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 86214#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86212#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 86210#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 86209#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 85260#L280-18 assume !(1 == ~t2_pc~0); 85259#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 85257#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 85255#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 85253#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 85251#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 85246#L299-18 assume 1 == ~t3_pc~0; 85239#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 85232#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 85226#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 85220#L653-18 assume !(0 != activate_threads_~tmp___2~0); 85215#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 84778#L318-18 assume !(1 == ~t4_pc~0); 84776#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 84774#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 84772#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 84770#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 84768#L661-20 assume !(1 == ~M_E~0); 84697#L564-3 assume !(1 == ~T1_E~0); 84764#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84762#L574-3 assume !(1 == ~T3_E~0); 84760#L579-3 assume !(1 == ~T4_E~0); 84758#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84756#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 84755#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 84753#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84751#L604-3 assume !(1 == ~E_4~0); 84749#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 84744#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 84739#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 84737#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 84734#L814 assume !(0 == start_simulation_~tmp~3); 84735#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 85662#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 85661#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 85658#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 85655#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 85652#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 85649#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 85647#L827 assume !(0 != start_simulation_~tmp___0~1); 82535#L795-1 [2020-10-26 05:46:39,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:39,903 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 2 times [2020-10-26 05:46:39,903 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:39,903 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139694314] [2020-10-26 05:46:39,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:39,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:39,913 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:39,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:39,921 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:39,939 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:39,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:39,940 INFO L82 PathProgramCache]: Analyzing trace with hash 1566336358, now seen corresponding path program 1 times [2020-10-26 05:46:39,940 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:39,941 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680915246] [2020-10-26 05:46:39,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:39,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:39,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:39,975 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680915246] [2020-10-26 05:46:39,976 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:39,976 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:46:39,976 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86875867] [2020-10-26 05:46:39,976 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:39,977 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:39,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:46:39,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:46:39,978 INFO L87 Difference]: Start difference. First operand 4288 states and 6096 transitions. cyclomatic complexity: 1810 Second operand 5 states. [2020-10-26 05:46:40,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:40,122 INFO L93 Difference]: Finished difference Result 7548 states and 10608 transitions. [2020-10-26 05:46:40,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-10-26 05:46:40,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7548 states and 10608 transitions. [2020-10-26 05:46:40,162 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7472 [2020-10-26 05:46:40,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7548 states to 7548 states and 10608 transitions. [2020-10-26 05:46:40,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7548 [2020-10-26 05:46:40,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7548 [2020-10-26 05:46:40,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7548 states and 10608 transitions. [2020-10-26 05:46:40,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:40,211 INFO L691 BuchiCegarLoop]: Abstraction has 7548 states and 10608 transitions. [2020-10-26 05:46:40,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7548 states and 10608 transitions. [2020-10-26 05:46:40,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7548 to 4336. [2020-10-26 05:46:40,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4336 states. [2020-10-26 05:46:40,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4336 states to 4336 states and 6144 transitions. [2020-10-26 05:46:40,300 INFO L714 BuchiCegarLoop]: Abstraction has 4336 states and 6144 transitions. [2020-10-26 05:46:40,300 INFO L594 BuchiCegarLoop]: Abstraction has 4336 states and 6144 transitions. [2020-10-26 05:46:40,300 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-10-26 05:46:40,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4336 states and 6144 transitions. [2020-10-26 05:46:40,315 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4268 [2020-10-26 05:46:40,315 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:40,315 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:40,318 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:40,318 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:40,319 INFO L794 eck$LassoCheckResult]: Stem: 94451#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 94358#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 94359#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 94393#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 94045#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94046#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94301#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94302#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94165#L365-1 assume !(0 == ~M_E~0); 94166#L506-1 assume !(0 == ~T1_E~0); 94143#L511-1 assume !(0 == ~T2_E~0); 94144#L516-1 assume !(0 == ~T3_E~0); 94057#L521-1 assume !(0 == ~T4_E~0); 94058#L526-1 assume !(0 == ~E_M~0); 94310#L531-1 assume !(0 == ~E_1~0); 94311#L536-1 assume !(0 == ~E_2~0); 94183#L541-1 assume !(0 == ~E_3~0); 94184#L546-1 assume !(0 == ~E_4~0); 94266#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 94267#L242 assume !(1 == ~m_pc~0); 94443#L242-2 is_master_triggered_~__retres1~0 := 0; 94444#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 94230#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 94196#L629 assume !(0 != activate_threads_~tmp~1); 94174#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94175#L261 assume !(1 == ~t1_pc~0); 94402#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 94403#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 94404#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 94388#L637 assume !(0 != activate_threads_~tmp___0~0); 94389#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 94156#L280 assume !(1 == ~t2_pc~0); 94150#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 94151#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 94103#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 94104#L645 assume !(0 != activate_threads_~tmp___1~0); 94490#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 94176#L299 assume !(1 == ~t3_pc~0); 94177#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 94169#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 94170#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 94071#L653 assume !(0 != activate_threads_~tmp___2~0); 94072#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 94073#L318 assume !(1 == ~t4_pc~0); 94366#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 94364#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 94365#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 94436#L661 assume !(0 != activate_threads_~tmp___3~0); 94261#L661-2 assume !(1 == ~M_E~0); 94262#L564-1 assume !(1 == ~T1_E~0); 94307#L569-1 assume !(1 == ~T2_E~0); 94179#L574-1 assume !(1 == ~T3_E~0); 94180#L579-1 assume !(1 == ~T4_E~0); 94265#L584-1 assume !(1 == ~E_M~0); 94107#L589-1 assume !(1 == ~E_1~0); 94108#L594-1 assume !(1 == ~E_2~0); 94026#L599-1 assume !(1 == ~E_3~0); 94027#L604-1 assume !(1 == ~E_4~0); 94390#L795-1 [2020-10-26 05:46:40,319 INFO L796 eck$LassoCheckResult]: Loop: 94390#L795-1 assume !false; 98343#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 97338#L481 assume !false; 97862#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 97858#L378 assume !(0 == ~m_st~0); 97854#L382 assume !(0 == ~t1_st~0); 97855#L386 assume !(0 == ~t2_st~0); 97856#L390 assume !(0 == ~t3_st~0); 97857#L394 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 97859#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 96378#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 96379#L420 assume !(0 != eval_~tmp~0); 97850#L496 start_simulation_~kernel_st~0 := 2; 94517#L338-1 start_simulation_~kernel_st~0 := 3; 94518#L506-2 assume !(0 == ~M_E~0); 98141#L506-4 assume !(0 == ~T1_E~0); 98140#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98139#L516-3 assume !(0 == ~T3_E~0); 98138#L521-3 assume !(0 == ~T4_E~0); 98137#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 98136#L531-3 assume !(0 == ~E_1~0); 98135#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 98134#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98133#L546-3 assume !(0 == ~E_4~0); 98132#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98131#L242-18 assume !(1 == ~m_pc~0); 98130#L242-20 is_master_triggered_~__retres1~0 := 0; 98129#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98128#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 98127#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 98126#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98125#L261-18 assume 1 == ~t1_pc~0; 98123#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 98122#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98121#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 98120#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 98119#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98118#L280-18 assume !(1 == ~t2_pc~0); 95523#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 98117#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98116#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 98115#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 98114#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98113#L299-18 assume !(1 == ~t3_pc~0); 98112#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 98110#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98109#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 98108#L653-18 assume !(0 != activate_threads_~tmp___2~0); 98107#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98106#L318-18 assume !(1 == ~t4_pc~0); 97247#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 98105#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 98104#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 98103#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 98102#L661-20 assume !(1 == ~M_E~0); 97999#L564-3 assume !(1 == ~T1_E~0); 98101#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98100#L574-3 assume !(1 == ~T3_E~0); 98099#L579-3 assume !(1 == ~T4_E~0); 98098#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98097#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98096#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98095#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98094#L604-3 assume !(1 == ~E_4~0); 98093#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 98091#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 98085#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 98083#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 98082#L814 assume !(0 == start_simulation_~tmp~3); 94471#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 94472#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 98347#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 98346#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 98345#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 94114#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 94115#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 98344#L827 assume !(0 != start_simulation_~tmp___0~1); 94390#L795-1 [2020-10-26 05:46:40,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:40,320 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 3 times [2020-10-26 05:46:40,320 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:40,320 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190478425] [2020-10-26 05:46:40,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:40,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:40,332 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:40,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:40,341 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:40,358 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:40,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:40,360 INFO L82 PathProgramCache]: Analyzing trace with hash -1594854798, now seen corresponding path program 1 times [2020-10-26 05:46:40,360 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:40,360 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114504865] [2020-10-26 05:46:40,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:40,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:40,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:40,459 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114504865] [2020-10-26 05:46:40,460 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:40,460 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:46:40,460 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568038813] [2020-10-26 05:46:40,461 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:40,461 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:40,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:46:40,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:46:40,462 INFO L87 Difference]: Start difference. First operand 4336 states and 6144 transitions. cyclomatic complexity: 1810 Second operand 5 states. [2020-10-26 05:46:40,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:40,768 INFO L93 Difference]: Finished difference Result 8564 states and 12047 transitions. [2020-10-26 05:46:40,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-10-26 05:46:40,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8564 states and 12047 transitions. [2020-10-26 05:46:40,804 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8496 [2020-10-26 05:46:40,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8564 states to 8564 states and 12047 transitions. [2020-10-26 05:46:40,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8564 [2020-10-26 05:46:40,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8564 [2020-10-26 05:46:40,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8564 states and 12047 transitions. [2020-10-26 05:46:40,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:40,851 INFO L691 BuchiCegarLoop]: Abstraction has 8564 states and 12047 transitions. [2020-10-26 05:46:40,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8564 states and 12047 transitions. [2020-10-26 05:46:40,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8564 to 4468. [2020-10-26 05:46:40,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4468 states. [2020-10-26 05:46:40,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4468 states to 4468 states and 6239 transitions. [2020-10-26 05:46:40,933 INFO L714 BuchiCegarLoop]: Abstraction has 4468 states and 6239 transitions. [2020-10-26 05:46:40,933 INFO L594 BuchiCegarLoop]: Abstraction has 4468 states and 6239 transitions. [2020-10-26 05:46:40,933 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-10-26 05:46:40,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4468 states and 6239 transitions. [2020-10-26 05:46:40,944 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4400 [2020-10-26 05:46:40,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:40,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:40,946 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:40,946 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:40,947 INFO L794 eck$LassoCheckResult]: Stem: 107384#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 107279#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 107280#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 107313#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 106958#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106959#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 107216#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 107217#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 107082#L365-1 assume !(0 == ~M_E~0); 107083#L506-1 assume !(0 == ~T1_E~0); 107058#L511-1 assume !(0 == ~T2_E~0); 107059#L516-1 assume !(0 == ~T3_E~0); 106969#L521-1 assume !(0 == ~T4_E~0); 106970#L526-1 assume !(0 == ~E_M~0); 107225#L531-1 assume !(0 == ~E_1~0); 107226#L536-1 assume !(0 == ~E_2~0); 107101#L541-1 assume !(0 == ~E_3~0); 107102#L546-1 assume !(0 == ~E_4~0); 107184#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 107185#L242 assume !(1 == ~m_pc~0); 107372#L242-2 is_master_triggered_~__retres1~0 := 0; 107373#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 107147#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 107114#L629 assume !(0 != activate_threads_~tmp~1); 107092#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 107093#L261 assume !(1 == ~t1_pc~0); 107322#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 107323#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 107324#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 107309#L637 assume !(0 != activate_threads_~tmp___0~0); 107310#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 107072#L280 assume !(1 == ~t2_pc~0); 107066#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 107067#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 107016#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 107017#L645 assume !(0 != activate_threads_~tmp___1~0); 107419#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 107094#L299 assume !(1 == ~t3_pc~0); 107095#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 107086#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 107087#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 106984#L653 assume !(0 != activate_threads_~tmp___2~0); 106985#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 106986#L318 assume !(1 == ~t4_pc~0); 107287#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 107285#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 107286#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 107357#L661 assume !(0 != activate_threads_~tmp___3~0); 107179#L661-2 assume !(1 == ~M_E~0); 107180#L564-1 assume !(1 == ~T1_E~0); 107222#L569-1 assume !(1 == ~T2_E~0); 107097#L574-1 assume !(1 == ~T3_E~0); 107098#L579-1 assume !(1 == ~T4_E~0); 107183#L584-1 assume !(1 == ~E_M~0); 107020#L589-1 assume !(1 == ~E_1~0); 107021#L594-1 assume !(1 == ~E_2~0); 106939#L599-1 assume !(1 == ~E_3~0); 106940#L604-1 assume !(1 == ~E_4~0); 107311#L795-1 [2020-10-26 05:46:40,947 INFO L796 eck$LassoCheckResult]: Loop: 107311#L795-1 assume !false; 107929#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 108134#L481 assume !false; 108129#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 107875#L378 assume !(0 == ~m_st~0); 107871#L382 assume !(0 == ~t1_st~0); 107866#L386 assume !(0 == ~t2_st~0); 107859#L390 assume !(0 == ~t3_st~0); 107850#L394 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 107851#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 108105#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 107828#L420 assume !(0 != eval_~tmp~0); 107830#L496 start_simulation_~kernel_st~0 := 2; 107811#L338-1 start_simulation_~kernel_st~0 := 3; 107812#L506-2 assume !(0 == ~M_E~0); 107797#L506-4 assume !(0 == ~T1_E~0); 107798#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107783#L516-3 assume !(0 == ~T3_E~0); 107784#L521-3 assume !(0 == ~T4_E~0); 107769#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 107770#L531-3 assume !(0 == ~E_1~0); 107755#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 107756#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107741#L546-3 assume !(0 == ~E_4~0); 107742#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 107727#L242-18 assume !(1 == ~m_pc~0); 107728#L242-20 is_master_triggered_~__retres1~0 := 0; 107713#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 107714#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 107699#L629-18 assume !(0 != activate_threads_~tmp~1); 107700#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 107683#L261-18 assume !(1 == ~t1_pc~0); 107685#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 107662#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 107663#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 107648#L637-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 107649#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 107634#L280-18 assume !(1 == ~t2_pc~0); 107632#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 107628#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 107624#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 107620#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 107616#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 107612#L299-18 assume !(1 == ~t3_pc~0); 107607#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 107602#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 107596#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 107592#L653-18 assume !(0 != activate_threads_~tmp___2~0); 107588#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 107582#L318-18 assume !(1 == ~t4_pc~0); 107575#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 107572#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 107568#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 107569#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 107561#L661-20 assume !(1 == ~M_E~0); 107560#L564-3 assume !(1 == ~T1_E~0); 108832#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108830#L574-3 assume !(1 == ~T3_E~0); 108828#L579-3 assume !(1 == ~T4_E~0); 108826#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 108823#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 108821#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 108819#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108817#L604-3 assume !(1 == ~E_4~0); 108815#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 108811#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 108806#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 108804#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 108803#L814 assume !(0 == start_simulation_~tmp~3); 108801#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 108745#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 108743#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 108741#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 108739#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 108738#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 108735#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 108733#L827 assume !(0 != start_simulation_~tmp___0~1); 107311#L795-1 [2020-10-26 05:46:40,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:40,947 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 4 times [2020-10-26 05:46:40,947 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:40,948 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333748660] [2020-10-26 05:46:40,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:40,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:40,957 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:40,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:40,965 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:40,979 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:40,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:40,980 INFO L82 PathProgramCache]: Analyzing trace with hash -963697521, now seen corresponding path program 1 times [2020-10-26 05:46:40,980 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:40,981 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166394546] [2020-10-26 05:46:40,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:40,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:41,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:41,012 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166394546] [2020-10-26 05:46:41,012 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:41,012 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:41,012 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229165283] [2020-10-26 05:46:41,013 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:46:41,013 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:41,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:41,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:41,013 INFO L87 Difference]: Start difference. First operand 4468 states and 6239 transitions. cyclomatic complexity: 1773 Second operand 3 states. [2020-10-26 05:46:41,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:41,081 INFO L93 Difference]: Finished difference Result 7000 states and 9658 transitions. [2020-10-26 05:46:41,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:41,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7000 states and 9658 transitions. [2020-10-26 05:46:41,111 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6934 [2020-10-26 05:46:41,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7000 states to 7000 states and 9658 transitions. [2020-10-26 05:46:41,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7000 [2020-10-26 05:46:41,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7000 [2020-10-26 05:46:41,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7000 states and 9658 transitions. [2020-10-26 05:46:41,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:41,147 INFO L691 BuchiCegarLoop]: Abstraction has 7000 states and 9658 transitions. [2020-10-26 05:46:41,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7000 states and 9658 transitions. [2020-10-26 05:46:41,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7000 to 6776. [2020-10-26 05:46:41,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6776 states. [2020-10-26 05:46:41,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6776 states to 6776 states and 9358 transitions. [2020-10-26 05:46:41,242 INFO L714 BuchiCegarLoop]: Abstraction has 6776 states and 9358 transitions. [2020-10-26 05:46:41,242 INFO L594 BuchiCegarLoop]: Abstraction has 6776 states and 9358 transitions. [2020-10-26 05:46:41,242 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2020-10-26 05:46:41,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6776 states and 9358 transitions. [2020-10-26 05:46:41,260 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6710 [2020-10-26 05:46:41,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:41,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:41,261 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:41,261 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:41,261 INFO L794 eck$LassoCheckResult]: Stem: 118849#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 118748#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 118749#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 118781#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 118432#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118433#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118687#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118688#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118557#L365-1 assume !(0 == ~M_E~0); 118558#L506-1 assume !(0 == ~T1_E~0); 118530#L511-1 assume !(0 == ~T2_E~0); 118531#L516-1 assume !(0 == ~T3_E~0); 118442#L521-1 assume !(0 == ~T4_E~0); 118443#L526-1 assume !(0 == ~E_M~0); 118696#L531-1 assume !(0 == ~E_1~0); 118697#L536-1 assume !(0 == ~E_2~0); 118573#L541-1 assume !(0 == ~E_3~0); 118574#L546-1 assume !(0 == ~E_4~0); 118655#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 118656#L242 assume !(1 == ~m_pc~0); 118836#L242-2 is_master_triggered_~__retres1~0 := 0; 118837#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 118620#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 118586#L629 assume !(0 != activate_threads_~tmp~1); 118564#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 118565#L261 assume !(1 == ~t1_pc~0); 118790#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 118791#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 118792#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 118775#L637 assume !(0 != activate_threads_~tmp___0~0); 118776#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 118545#L280 assume !(1 == ~t2_pc~0); 118537#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 118538#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 118485#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 118486#L645 assume !(0 != activate_threads_~tmp___1~0); 118885#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 118566#L299 assume !(1 == ~t3_pc~0); 118567#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 118559#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 118560#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 118453#L653 assume !(0 != activate_threads_~tmp___2~0); 118454#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 118455#L318 assume !(1 == ~t4_pc~0); 118752#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 118750#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 118751#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 118826#L661 assume !(0 != activate_threads_~tmp___3~0); 118650#L661-2 assume !(1 == ~M_E~0); 118651#L564-1 assume !(1 == ~T1_E~0); 118693#L569-1 assume !(1 == ~T2_E~0); 118569#L574-1 assume !(1 == ~T3_E~0); 118570#L579-1 assume !(1 == ~T4_E~0); 118654#L584-1 assume !(1 == ~E_M~0); 118491#L589-1 assume !(1 == ~E_1~0); 118492#L594-1 assume !(1 == ~E_2~0); 118413#L599-1 assume !(1 == ~E_3~0); 118414#L604-1 assume !(1 == ~E_4~0); 118777#L795-1 assume !false; 120435#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 120433#L481 [2020-10-26 05:46:41,262 INFO L796 eck$LassoCheckResult]: Loop: 120433#L481 assume !false; 120376#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 120377#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 120546#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 120545#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 120541#L420 assume 0 != eval_~tmp~0; 120538#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 120534#L428 assume !(0 != eval_~tmp_ndt_1~0); 120535#L425 assume !(0 == ~t1_st~0); 120500#L439 assume !(0 == ~t2_st~0); 120499#L453 assume !(0 == ~t3_st~0); 120432#L467 assume !(0 == ~t4_st~0); 120433#L481 [2020-10-26 05:46:41,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:41,262 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 1 times [2020-10-26 05:46:41,262 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:41,262 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421649935] [2020-10-26 05:46:41,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:41,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:41,273 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:41,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:41,281 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:41,295 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:41,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:41,295 INFO L82 PathProgramCache]: Analyzing trace with hash 1329153973, now seen corresponding path program 1 times [2020-10-26 05:46:41,296 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:41,296 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173062228] [2020-10-26 05:46:41,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:41,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:41,299 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:41,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:41,301 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:41,303 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:41,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:41,304 INFO L82 PathProgramCache]: Analyzing trace with hash -1602401766, now seen corresponding path program 1 times [2020-10-26 05:46:41,304 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:41,304 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991678519] [2020-10-26 05:46:41,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:41,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:41,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:41,336 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991678519] [2020-10-26 05:46:41,336 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:41,336 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:41,337 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765793181] [2020-10-26 05:46:41,422 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:41,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:41,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:41,422 INFO L87 Difference]: Start difference. First operand 6776 states and 9358 transitions. cyclomatic complexity: 2585 Second operand 3 states. [2020-10-26 05:46:41,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:41,523 INFO L93 Difference]: Finished difference Result 12355 states and 16882 transitions. [2020-10-26 05:46:41,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:41,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12355 states and 16882 transitions. [2020-10-26 05:46:41,595 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 12228 [2020-10-26 05:46:41,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12355 states to 12355 states and 16882 transitions. [2020-10-26 05:46:41,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12355 [2020-10-26 05:46:41,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12355 [2020-10-26 05:46:41,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12355 states and 16882 transitions. [2020-10-26 05:46:41,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:41,676 INFO L691 BuchiCegarLoop]: Abstraction has 12355 states and 16882 transitions. [2020-10-26 05:46:41,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12355 states and 16882 transitions. [2020-10-26 05:46:41,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12355 to 11711. [2020-10-26 05:46:41,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11711 states. [2020-10-26 05:46:41,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11711 states to 11711 states and 16056 transitions. [2020-10-26 05:46:41,866 INFO L714 BuchiCegarLoop]: Abstraction has 11711 states and 16056 transitions. [2020-10-26 05:46:41,866 INFO L594 BuchiCegarLoop]: Abstraction has 11711 states and 16056 transitions. [2020-10-26 05:46:41,866 INFO L427 BuchiCegarLoop]: ======== Iteration 20============ [2020-10-26 05:46:41,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11711 states and 16056 transitions. [2020-10-26 05:46:41,912 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11584 [2020-10-26 05:46:41,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:41,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:41,913 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:41,913 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:41,914 INFO L794 eck$LassoCheckResult]: Stem: 137984#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 137885#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 137886#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 137921#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 137571#L345-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 137572#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 141585#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 141584#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 141583#L365-1 assume !(0 == ~M_E~0); 141582#L506-1 assume !(0 == ~T1_E~0); 141581#L511-1 assume !(0 == ~T2_E~0); 141580#L516-1 assume !(0 == ~T3_E~0); 141579#L521-1 assume !(0 == ~T4_E~0); 141578#L526-1 assume !(0 == ~E_M~0); 141577#L531-1 assume !(0 == ~E_1~0); 141576#L536-1 assume !(0 == ~E_2~0); 141575#L541-1 assume !(0 == ~E_3~0); 141574#L546-1 assume !(0 == ~E_4~0); 141573#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 141572#L242 assume !(1 == ~m_pc~0); 141571#L242-2 is_master_triggered_~__retres1~0 := 0; 141570#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 141569#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 141568#L629 assume !(0 != activate_threads_~tmp~1); 141567#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 141566#L261 assume !(1 == ~t1_pc~0); 141564#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 141563#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 141562#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 141561#L637 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 137918#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 137682#L280 assume !(1 == ~t2_pc~0); 137675#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 137676#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 137625#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 137626#L645 assume !(0 != activate_threads_~tmp___1~0); 138026#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 141473#L299 assume !(1 == ~t3_pc~0); 141471#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 141470#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141469#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 141468#L653 assume !(0 != activate_threads_~tmp___2~0); 141467#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 141466#L318 assume !(1 == ~t4_pc~0); 141465#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 141464#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 141463#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 137966#L661 assume !(0 != activate_threads_~tmp___3~0); 137785#L661-2 assume !(1 == ~M_E~0); 137786#L564-1 assume !(1 == ~T1_E~0); 137831#L569-1 assume !(1 == ~T2_E~0); 141451#L574-1 assume !(1 == ~T3_E~0); 141449#L579-1 assume !(1 == ~T4_E~0); 141447#L584-1 assume !(1 == ~E_M~0); 137631#L589-1 assume !(1 == ~E_1~0); 137632#L594-1 assume !(1 == ~E_2~0); 137552#L599-1 assume !(1 == ~E_3~0); 137553#L604-1 assume !(1 == ~E_4~0); 137919#L795-1 assume !false; 143612#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 143546#L481 [2020-10-26 05:46:41,914 INFO L796 eck$LassoCheckResult]: Loop: 143546#L481 assume !false; 143611#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 143609#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 143608#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 143607#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 143606#L420 assume 0 != eval_~tmp~0; 143604#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 143603#L428 assume !(0 != eval_~tmp_ndt_1~0); 143602#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 141086#L442 assume !(0 != eval_~tmp_ndt_2~0); 143598#L439 assume !(0 == ~t2_st~0); 143553#L453 assume !(0 == ~t3_st~0); 143549#L467 assume !(0 == ~t4_st~0); 143546#L481 [2020-10-26 05:46:41,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:41,914 INFO L82 PathProgramCache]: Analyzing trace with hash -1892956382, now seen corresponding path program 1 times [2020-10-26 05:46:41,915 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:41,915 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061532563] [2020-10-26 05:46:41,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:41,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:41,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:41,937 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061532563] [2020-10-26 05:46:41,938 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:41,938 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:41,938 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622130233] [2020-10-26 05:46:41,938 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:46:41,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:41,939 INFO L82 PathProgramCache]: Analyzing trace with hash -1891165390, now seen corresponding path program 1 times [2020-10-26 05:46:41,939 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:41,939 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808095773] [2020-10-26 05:46:41,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:41,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:41,944 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:41,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:41,946 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:41,948 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:42,044 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:42,045 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:42,045 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:42,045 INFO L87 Difference]: Start difference. First operand 11711 states and 16056 transitions. cyclomatic complexity: 4348 Second operand 3 states. [2020-10-26 05:46:42,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:42,100 INFO L93 Difference]: Finished difference Result 11654 states and 15980 transitions. [2020-10-26 05:46:42,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:42,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11654 states and 15980 transitions. [2020-10-26 05:46:42,228 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11584 [2020-10-26 05:46:42,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11654 states to 11654 states and 15980 transitions. [2020-10-26 05:46:42,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11654 [2020-10-26 05:46:42,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11654 [2020-10-26 05:46:42,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11654 states and 15980 transitions. [2020-10-26 05:46:42,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:42,284 INFO L691 BuchiCegarLoop]: Abstraction has 11654 states and 15980 transitions. [2020-10-26 05:46:42,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11654 states and 15980 transitions. [2020-10-26 05:46:42,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11654 to 11654. [2020-10-26 05:46:42,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11654 states. [2020-10-26 05:46:42,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11654 states to 11654 states and 15980 transitions. [2020-10-26 05:46:42,416 INFO L714 BuchiCegarLoop]: Abstraction has 11654 states and 15980 transitions. [2020-10-26 05:46:42,416 INFO L594 BuchiCegarLoop]: Abstraction has 11654 states and 15980 transitions. [2020-10-26 05:46:42,416 INFO L427 BuchiCegarLoop]: ======== Iteration 21============ [2020-10-26 05:46:42,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11654 states and 15980 transitions. [2020-10-26 05:46:42,450 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11584 [2020-10-26 05:46:42,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:42,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:42,451 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:42,451 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:42,452 INFO L794 eck$LassoCheckResult]: Stem: 161350#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 161251#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 161252#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 161289#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 160940#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160941#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 161190#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 161191#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 161060#L365-1 assume !(0 == ~M_E~0); 161061#L506-1 assume !(0 == ~T1_E~0); 161035#L511-1 assume !(0 == ~T2_E~0); 161036#L516-1 assume !(0 == ~T3_E~0); 160949#L521-1 assume !(0 == ~T4_E~0); 160950#L526-1 assume !(0 == ~E_M~0); 161200#L531-1 assume !(0 == ~E_1~0); 161201#L536-1 assume !(0 == ~E_2~0); 161078#L541-1 assume !(0 == ~E_3~0); 161079#L546-1 assume !(0 == ~E_4~0); 161158#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 161159#L242 assume !(1 == ~m_pc~0); 161340#L242-2 is_master_triggered_~__retres1~0 := 0; 161341#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 161121#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 161090#L629 assume !(0 != activate_threads_~tmp~1); 161069#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 161070#L261 assume !(1 == ~t1_pc~0); 161297#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 161298#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 161299#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 161284#L637 assume !(0 != activate_threads_~tmp___0~0); 161285#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 161050#L280 assume !(1 == ~t2_pc~0); 161043#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 161044#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 160994#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 160995#L645 assume !(0 != activate_threads_~tmp___1~0); 161386#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 161071#L299 assume !(1 == ~t3_pc~0); 161072#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 161064#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 161065#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 160962#L653 assume !(0 != activate_threads_~tmp___2~0); 160963#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 160964#L318 assume !(1 == ~t4_pc~0); 161259#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 161257#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 161258#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 161332#L661 assume !(0 != activate_threads_~tmp___3~0); 161153#L661-2 assume !(1 == ~M_E~0); 161154#L564-1 assume !(1 == ~T1_E~0); 161197#L569-1 assume !(1 == ~T2_E~0); 161074#L574-1 assume !(1 == ~T3_E~0); 161075#L579-1 assume !(1 == ~T4_E~0); 161157#L584-1 assume !(1 == ~E_M~0); 160998#L589-1 assume !(1 == ~E_1~0); 160999#L594-1 assume !(1 == ~E_2~0); 160923#L599-1 assume !(1 == ~E_3~0); 160924#L604-1 assume !(1 == ~E_4~0); 161286#L795-1 assume !false; 168539#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 168535#L481 [2020-10-26 05:46:42,452 INFO L796 eck$LassoCheckResult]: Loop: 168535#L481 assume !false; 168533#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 168531#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 168528#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 168526#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 168524#L420 assume 0 != eval_~tmp~0; 168521#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 168518#L428 assume !(0 != eval_~tmp_ndt_1~0); 168516#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 168501#L442 assume !(0 != eval_~tmp_ndt_2~0); 168513#L439 assume !(0 == ~t2_st~0); 168548#L453 assume !(0 == ~t3_st~0); 168537#L467 assume !(0 == ~t4_st~0); 168535#L481 [2020-10-26 05:46:42,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:42,453 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 2 times [2020-10-26 05:46:42,453 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:42,453 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834255561] [2020-10-26 05:46:42,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:42,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:42,463 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:42,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:42,471 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:42,483 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:42,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:42,484 INFO L82 PathProgramCache]: Analyzing trace with hash -1891165390, now seen corresponding path program 2 times [2020-10-26 05:46:42,484 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:42,484 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318610312] [2020-10-26 05:46:42,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:42,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:42,488 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:42,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:42,490 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:42,492 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:42,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:42,493 INFO L82 PathProgramCache]: Analyzing trace with hash 1719887213, now seen corresponding path program 1 times [2020-10-26 05:46:42,493 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:42,493 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275651454] [2020-10-26 05:46:42,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:42,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:42,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:42,526 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275651454] [2020-10-26 05:46:42,527 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:42,527 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:42,527 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067899105] [2020-10-26 05:46:42,620 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:42,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:42,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:42,621 INFO L87 Difference]: Start difference. First operand 11654 states and 15980 transitions. cyclomatic complexity: 4329 Second operand 3 states. [2020-10-26 05:46:42,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:42,741 INFO L93 Difference]: Finished difference Result 21510 states and 29292 transitions. [2020-10-26 05:46:42,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:42,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21510 states and 29292 transitions. [2020-10-26 05:46:42,830 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 21432 [2020-10-26 05:46:42,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21510 states to 21510 states and 29292 transitions. [2020-10-26 05:46:42,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21510 [2020-10-26 05:46:42,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21510 [2020-10-26 05:46:42,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21510 states and 29292 transitions. [2020-10-26 05:46:42,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:42,945 INFO L691 BuchiCegarLoop]: Abstraction has 21510 states and 29292 transitions. [2020-10-26 05:46:42,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21510 states and 29292 transitions. [2020-10-26 05:46:43,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21510 to 21048. [2020-10-26 05:46:43,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21048 states. [2020-10-26 05:46:43,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21048 states to 21048 states and 28704 transitions. [2020-10-26 05:46:43,194 INFO L714 BuchiCegarLoop]: Abstraction has 21048 states and 28704 transitions. [2020-10-26 05:46:43,194 INFO L594 BuchiCegarLoop]: Abstraction has 21048 states and 28704 transitions. [2020-10-26 05:46:43,194 INFO L427 BuchiCegarLoop]: ======== Iteration 22============ [2020-10-26 05:46:43,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21048 states and 28704 transitions. [2020-10-26 05:46:43,330 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20970 [2020-10-26 05:46:43,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:43,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:43,333 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:43,333 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:43,333 INFO L794 eck$LassoCheckResult]: Stem: 194526#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 194426#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 194427#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 194463#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 194112#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 194113#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 194366#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 194367#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 194230#L365-1 assume !(0 == ~M_E~0); 194231#L506-1 assume !(0 == ~T1_E~0); 194207#L511-1 assume !(0 == ~T2_E~0); 194208#L516-1 assume !(0 == ~T3_E~0); 194121#L521-1 assume !(0 == ~T4_E~0); 194122#L526-1 assume !(0 == ~E_M~0); 194376#L531-1 assume !(0 == ~E_1~0); 194377#L536-1 assume !(0 == ~E_2~0); 194248#L541-1 assume !(0 == ~E_3~0); 194249#L546-1 assume !(0 == ~E_4~0); 194334#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 194335#L242 assume !(1 == ~m_pc~0); 194517#L242-2 is_master_triggered_~__retres1~0 := 0; 194518#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 194293#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 194261#L629 assume !(0 != activate_threads_~tmp~1); 194239#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 194240#L261 assume !(1 == ~t1_pc~0); 194472#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 194473#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 194474#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 194456#L637 assume !(0 != activate_threads_~tmp___0~0); 194457#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 194221#L280 assume !(1 == ~t2_pc~0); 194214#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 194215#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 194166#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 194167#L645 assume !(0 != activate_threads_~tmp___1~0); 194570#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 194241#L299 assume !(1 == ~t3_pc~0); 194242#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 194234#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 194235#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 194134#L653 assume !(0 != activate_threads_~tmp___2~0); 194135#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 194136#L318 assume !(1 == ~t4_pc~0); 194434#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 194432#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 194433#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 194505#L661 assume !(0 != activate_threads_~tmp___3~0); 194329#L661-2 assume !(1 == ~M_E~0); 194330#L564-1 assume !(1 == ~T1_E~0); 194373#L569-1 assume !(1 == ~T2_E~0); 194244#L574-1 assume !(1 == ~T3_E~0); 194245#L579-1 assume !(1 == ~T4_E~0); 194333#L584-1 assume !(1 == ~E_M~0); 194170#L589-1 assume !(1 == ~E_1~0); 194171#L594-1 assume !(1 == ~E_2~0); 194095#L599-1 assume !(1 == ~E_3~0); 194096#L604-1 assume !(1 == ~E_4~0); 194458#L795-1 assume !false; 199351#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 199348#L481 [2020-10-26 05:46:43,333 INFO L796 eck$LassoCheckResult]: Loop: 199348#L481 assume !false; 199342#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 199339#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 199337#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 199335#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 199334#L420 assume 0 != eval_~tmp~0; 199330#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 199327#L428 assume !(0 != eval_~tmp_ndt_1~0); 199329#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 200301#L442 assume !(0 != eval_~tmp_ndt_2~0); 199054#L439 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 198662#L456 assume !(0 != eval_~tmp_ndt_3~0); 199052#L453 assume !(0 == ~t3_st~0); 199347#L467 assume !(0 == ~t4_st~0); 199348#L481 [2020-10-26 05:46:43,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:43,334 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 3 times [2020-10-26 05:46:43,335 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:43,340 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501000366] [2020-10-26 05:46:43,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:43,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:43,352 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:43,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:43,363 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:43,381 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:43,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:43,382 INFO L82 PathProgramCache]: Analyzing trace with hash 1498730307, now seen corresponding path program 1 times [2020-10-26 05:46:43,382 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:43,382 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91348174] [2020-10-26 05:46:43,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:43,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:43,389 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:43,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:43,391 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:43,393 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:43,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:43,394 INFO L82 PathProgramCache]: Analyzing trace with hash 1772211304, now seen corresponding path program 1 times [2020-10-26 05:46:43,394 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:43,395 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850272842] [2020-10-26 05:46:43,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:43,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:43,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:43,451 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850272842] [2020-10-26 05:46:43,451 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:43,452 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:46:43,452 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7928266] [2020-10-26 05:46:43,576 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:43,577 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:43,577 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:43,577 INFO L87 Difference]: Start difference. First operand 21048 states and 28704 transitions. cyclomatic complexity: 7659 Second operand 3 states. [2020-10-26 05:46:43,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:43,759 INFO L93 Difference]: Finished difference Result 36906 states and 49984 transitions. [2020-10-26 05:46:43,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:43,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36906 states and 49984 transitions. [2020-10-26 05:46:43,945 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 36812 [2020-10-26 05:46:44,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36906 states to 36906 states and 49984 transitions. [2020-10-26 05:46:44,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36906 [2020-10-26 05:46:44,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36906 [2020-10-26 05:46:44,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36906 states and 49984 transitions. [2020-10-26 05:46:44,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:44,143 INFO L691 BuchiCegarLoop]: Abstraction has 36906 states and 49984 transitions. [2020-10-26 05:46:44,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36906 states and 49984 transitions. [2020-10-26 05:46:44,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36906 to 35842. [2020-10-26 05:46:44,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35842 states. [2020-10-26 05:46:44,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35842 states to 35842 states and 48696 transitions. [2020-10-26 05:46:44,666 INFO L714 BuchiCegarLoop]: Abstraction has 35842 states and 48696 transitions. [2020-10-26 05:46:44,666 INFO L594 BuchiCegarLoop]: Abstraction has 35842 states and 48696 transitions. [2020-10-26 05:46:44,666 INFO L427 BuchiCegarLoop]: ======== Iteration 23============ [2020-10-26 05:46:44,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35842 states and 48696 transitions. [2020-10-26 05:46:44,767 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 35748 [2020-10-26 05:46:44,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:44,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:44,768 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:44,769 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:44,769 INFO L794 eck$LassoCheckResult]: Stem: 252510#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 252396#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 252397#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 252437#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 252077#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 252078#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 252332#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 252333#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 252199#L365-1 assume !(0 == ~M_E~0); 252200#L506-1 assume !(0 == ~T1_E~0); 252175#L511-1 assume !(0 == ~T2_E~0); 252176#L516-1 assume !(0 == ~T3_E~0); 252086#L521-1 assume !(0 == ~T4_E~0); 252087#L526-1 assume !(0 == ~E_M~0); 252343#L531-1 assume !(0 == ~E_1~0); 252344#L536-1 assume !(0 == ~E_2~0); 252217#L541-1 assume !(0 == ~E_3~0); 252218#L546-1 assume !(0 == ~E_4~0); 252299#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 252300#L242 assume !(1 == ~m_pc~0); 252497#L242-2 is_master_triggered_~__retres1~0 := 0; 252498#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 252260#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 252229#L629 assume !(0 != activate_threads_~tmp~1); 252208#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 252209#L261 assume !(1 == ~t1_pc~0); 252445#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 252446#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 252447#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 252433#L637 assume !(0 != activate_threads_~tmp___0~0); 252434#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 252190#L280 assume !(1 == ~t2_pc~0); 252184#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 252185#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 252133#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 252134#L645 assume !(0 != activate_threads_~tmp___1~0); 252553#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 252210#L299 assume !(1 == ~t3_pc~0); 252211#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 252203#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 252204#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 252100#L653 assume !(0 != activate_threads_~tmp___2~0); 252101#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 252102#L318 assume !(1 == ~t4_pc~0); 252404#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 252402#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 252403#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 252487#L661 assume !(0 != activate_threads_~tmp___3~0); 252294#L661-2 assume !(1 == ~M_E~0); 252295#L564-1 assume !(1 == ~T1_E~0); 252339#L569-1 assume !(1 == ~T2_E~0); 252213#L574-1 assume !(1 == ~T3_E~0); 252214#L579-1 assume !(1 == ~T4_E~0); 252298#L584-1 assume !(1 == ~E_M~0); 252137#L589-1 assume !(1 == ~E_1~0); 252138#L594-1 assume !(1 == ~E_2~0); 252057#L599-1 assume !(1 == ~E_3~0); 252058#L604-1 assume !(1 == ~E_4~0); 252435#L795-1 assume !false; 262563#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 262043#L481 [2020-10-26 05:46:44,769 INFO L796 eck$LassoCheckResult]: Loop: 262043#L481 assume !false; 262560#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 262558#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 262554#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 262555#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 262352#L420 assume 0 != eval_~tmp~0; 262353#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 262990#L428 assume !(0 != eval_~tmp_ndt_1~0); 262089#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 262083#L442 assume !(0 != eval_~tmp_ndt_2~0); 262081#L439 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 261541#L456 assume !(0 != eval_~tmp_ndt_3~0); 262070#L453 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 261833#L470 assume !(0 != eval_~tmp_ndt_4~0); 262052#L467 assume !(0 == ~t4_st~0); 262043#L481 [2020-10-26 05:46:44,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:44,770 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 4 times [2020-10-26 05:46:44,770 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:44,770 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680681813] [2020-10-26 05:46:44,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:44,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:44,780 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:44,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:44,789 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:44,802 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:44,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:44,803 INFO L82 PathProgramCache]: Analyzing trace with hash -784150620, now seen corresponding path program 1 times [2020-10-26 05:46:44,803 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:44,803 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567644474] [2020-10-26 05:46:44,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:44,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:44,807 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:44,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:44,809 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:44,812 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:44,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:44,812 INFO L82 PathProgramCache]: Analyzing trace with hash -896174305, now seen corresponding path program 1 times [2020-10-26 05:46:44,813 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:44,813 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732360799] [2020-10-26 05:46:44,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:44,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:46:44,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:46:44,857 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732360799] [2020-10-26 05:46:44,857 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:46:44,857 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:46:44,857 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747446295] [2020-10-26 05:46:44,973 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:46:44,974 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:46:44,974 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:46:44,974 INFO L87 Difference]: Start difference. First operand 35842 states and 48696 transitions. cyclomatic complexity: 12857 Second operand 3 states. [2020-10-26 05:46:45,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:46:45,191 INFO L93 Difference]: Finished difference Result 64126 states and 86800 transitions. [2020-10-26 05:46:45,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:46:45,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64126 states and 86800 transitions. [2020-10-26 05:46:45,449 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 64000 [2020-10-26 05:46:45,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64126 states to 64126 states and 86800 transitions. [2020-10-26 05:46:45,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64126 [2020-10-26 05:46:45,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64126 [2020-10-26 05:46:45,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64126 states and 86800 transitions. [2020-10-26 05:46:45,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:46:45,787 INFO L691 BuchiCegarLoop]: Abstraction has 64126 states and 86800 transitions. [2020-10-26 05:46:45,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64126 states and 86800 transitions. [2020-10-26 05:46:47,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64126 to 63790. [2020-10-26 05:46:47,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63790 states. [2020-10-26 05:46:47,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63790 states to 63790 states and 86464 transitions. [2020-10-26 05:46:47,437 INFO L714 BuchiCegarLoop]: Abstraction has 63790 states and 86464 transitions. [2020-10-26 05:46:47,437 INFO L594 BuchiCegarLoop]: Abstraction has 63790 states and 86464 transitions. [2020-10-26 05:46:47,437 INFO L427 BuchiCegarLoop]: ======== Iteration 24============ [2020-10-26 05:46:47,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63790 states and 86464 transitions. [2020-10-26 05:46:47,615 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 63664 [2020-10-26 05:46:47,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:46:47,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:46:47,616 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:47,617 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:46:47,617 INFO L794 eck$LassoCheckResult]: Stem: 352495#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 352384#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 352385#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 352427#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 352053#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 352054#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 352319#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 352320#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 352176#L365-1 assume !(0 == ~M_E~0); 352177#L506-1 assume !(0 == ~T1_E~0); 352152#L511-1 assume !(0 == ~T2_E~0); 352153#L516-1 assume !(0 == ~T3_E~0); 352064#L521-1 assume !(0 == ~T4_E~0); 352065#L526-1 assume !(0 == ~E_M~0); 352328#L531-1 assume !(0 == ~E_1~0); 352329#L536-1 assume !(0 == ~E_2~0); 352194#L541-1 assume !(0 == ~E_3~0); 352195#L546-1 assume !(0 == ~E_4~0); 352284#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 352285#L242 assume !(1 == ~m_pc~0); 352485#L242-2 is_master_triggered_~__retres1~0 := 0; 352486#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 352241#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 352207#L629 assume !(0 != activate_threads_~tmp~1); 352185#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 352186#L261 assume !(1 == ~t1_pc~0); 352437#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 352438#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 352439#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 352422#L637 assume !(0 != activate_threads_~tmp___0~0); 352423#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 352167#L280 assume !(1 == ~t2_pc~0); 352160#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 352161#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 352111#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 352112#L645 assume !(0 != activate_threads_~tmp___1~0); 352544#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 352187#L299 assume !(1 == ~t3_pc~0); 352188#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 352180#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 352181#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 352078#L653 assume !(0 != activate_threads_~tmp___2~0); 352079#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 352080#L318 assume !(1 == ~t4_pc~0); 352392#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 352390#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 352391#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 352474#L661 assume !(0 != activate_threads_~tmp___3~0); 352279#L661-2 assume !(1 == ~M_E~0); 352280#L564-1 assume !(1 == ~T1_E~0); 352325#L569-1 assume !(1 == ~T2_E~0); 352190#L574-1 assume !(1 == ~T3_E~0); 352191#L579-1 assume !(1 == ~T4_E~0); 352283#L584-1 assume !(1 == ~E_M~0); 352115#L589-1 assume !(1 == ~E_1~0); 352116#L594-1 assume !(1 == ~E_2~0); 352033#L599-1 assume !(1 == ~E_3~0); 352034#L604-1 assume !(1 == ~E_4~0); 352424#L795-1 assume !false; 370718#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 367118#L481 [2020-10-26 05:46:47,617 INFO L796 eck$LassoCheckResult]: Loop: 367118#L481 assume !false; 370715#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 370713#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 370712#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 370710#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 370706#L420 assume 0 != eval_~tmp~0; 370702#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 370698#L428 assume !(0 != eval_~tmp_ndt_1~0); 366511#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 366445#L442 assume !(0 != eval_~tmp_ndt_2~0); 366385#L439 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 366380#L456 assume !(0 != eval_~tmp_ndt_3~0); 366381#L453 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 367243#L470 assume !(0 != eval_~tmp_ndt_4~0); 367242#L467 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 365499#L484 assume !(0 != eval_~tmp_ndt_5~0); 367118#L481 [2020-10-26 05:46:47,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:47,618 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 5 times [2020-10-26 05:46:47,618 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:47,618 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850275395] [2020-10-26 05:46:47,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:47,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:47,628 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:47,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:47,636 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:47,650 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:47,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:47,651 INFO L82 PathProgramCache]: Analyzing trace with hash 1461130961, now seen corresponding path program 1 times [2020-10-26 05:46:47,651 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:47,651 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49319463] [2020-10-26 05:46:47,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:47,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:47,655 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:47,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:47,658 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:47,660 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:47,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:46:47,661 INFO L82 PathProgramCache]: Analyzing trace with hash -2011603274, now seen corresponding path program 1 times [2020-10-26 05:46:47,661 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:46:47,661 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083988849] [2020-10-26 05:46:47,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:46:47,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:47,671 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:47,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:46:47,680 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:46:47,699 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:46:49,150 WARN L193 SmtUtils]: Spent 1.31 s on a formula simplification. DAG size of input: 220 DAG size of output: 159 [2020-10-26 05:46:49,645 WARN L193 SmtUtils]: Spent 462.00 ms on a formula simplification that was a NOOP. DAG size: 137 [2020-10-26 05:46:49,725 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.10 05:46:49 BoogieIcfgContainer [2020-10-26 05:46:49,725 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-10-26 05:46:49,726 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-10-26 05:46:49,728 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-10-26 05:46:49,728 INFO L275 PluginConnector]: Witness Printer initialized [2020-10-26 05:46:49,729 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:46:34" (3/4) ... [2020-10-26 05:46:49,735 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-10-26 05:46:49,826 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2020-10-26 05:46:49,826 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-10-26 05:46:49,828 INFO L168 Benchmark]: Toolchain (without parser) took 17585.45 ms. Allocated memory was 39.8 MB in the beginning and 3.7 GB in the end (delta: 3.7 GB). Free memory was 19.6 MB in the beginning and 3.3 GB in the end (delta: -3.2 GB). Peak memory consumption was 449.2 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:49,829 INFO L168 Benchmark]: CDTParser took 0.25 ms. Allocated memory is still 39.8 MB. Free memory is still 25.1 MB. There was no memory consumed. Max. memory is 16.1 GB. [2020-10-26 05:46:49,829 INFO L168 Benchmark]: CACSL2BoogieTranslator took 471.87 ms. Allocated memory was 39.8 MB in the beginning and 48.2 MB in the end (delta: 8.4 MB). Free memory was 19.0 MB in the beginning and 30.9 MB in the end (delta: -11.9 MB). Peak memory consumption was 5.9 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:49,830 INFO L168 Benchmark]: Boogie Procedure Inliner took 77.73 ms. Allocated memory is still 48.2 MB. Free memory was 30.7 MB in the beginning and 26.5 MB in the end (delta: 4.1 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:49,830 INFO L168 Benchmark]: Boogie Preprocessor took 82.41 ms. Allocated memory is still 48.2 MB. Free memory was 26.5 MB in the beginning and 22.8 MB in the end (delta: 3.8 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:49,831 INFO L168 Benchmark]: RCFGBuilder took 1360.76 ms. Allocated memory was 48.2 MB in the beginning and 62.9 MB in the end (delta: 14.7 MB). Free memory was 22.8 MB in the beginning and 36.2 MB in the end (delta: -13.5 MB). Peak memory consumption was 19.6 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:49,831 INFO L168 Benchmark]: BuchiAutomizer took 15475.71 ms. Allocated memory was 62.9 MB in the beginning and 3.7 GB in the end (delta: 3.7 GB). Free memory was 36.2 MB in the beginning and 3.3 GB in the end (delta: -3.2 GB). Peak memory consumption was 587.2 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:49,832 INFO L168 Benchmark]: Witness Printer took 100.43 ms. Allocated memory is still 3.7 GB. Free memory was 3.3 GB in the beginning and 3.3 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-10-26 05:46:49,835 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25 ms. Allocated memory is still 39.8 MB. Free memory is still 25.1 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 471.87 ms. Allocated memory was 39.8 MB in the beginning and 48.2 MB in the end (delta: 8.4 MB). Free memory was 19.0 MB in the beginning and 30.9 MB in the end (delta: -11.9 MB). Peak memory consumption was 5.9 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 77.73 ms. Allocated memory is still 48.2 MB. Free memory was 30.7 MB in the beginning and 26.5 MB in the end (delta: 4.1 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 82.41 ms. Allocated memory is still 48.2 MB. Free memory was 26.5 MB in the beginning and 22.8 MB in the end (delta: 3.8 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1360.76 ms. Allocated memory was 48.2 MB in the beginning and 62.9 MB in the end (delta: 14.7 MB). Free memory was 22.8 MB in the beginning and 36.2 MB in the end (delta: -13.5 MB). Peak memory consumption was 19.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 15475.71 ms. Allocated memory was 62.9 MB in the beginning and 3.7 GB in the end (delta: 3.7 GB). Free memory was 36.2 MB in the beginning and 3.3 GB in the end (delta: -3.2 GB). Peak memory consumption was 587.2 MB. Max. memory is 16.1 GB. * Witness Printer took 100.43 ms. Allocated memory is still 3.7 GB. Free memory was 3.3 GB in the beginning and 3.3 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 63790 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 15.3s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 5.1s. Construction of modules took 0.9s. Büchi inclusion checks took 1.5s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 4.0s AutomataMinimizationTime, 23 MinimizatonAttempts, 18105 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 2.1s Buchi closure took 0.1s. Biggest automaton had 63790 states and ocurred in iteration 23. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 14956 SDtfs, 18246 SDslu, 13384 SDs, 0 SdLazy, 611 SolverSat, 247 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 415]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=1, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@727110b5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4fcec4f5=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@59ee3ab8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12665b96=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@46035f79=0, tmp=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2c258ab6=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@21b04644=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5c682f31=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@482abd5d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5264ab6e=0, NULL=4, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@484f632=0, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, NULL=2, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=3, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@18898704=0, t1_st=0, tmp_ndt_5=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@540544e3=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 415]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int T2_E = 2; [L34] int T3_E = 2; [L35] int T4_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L39] int E_3 = 2; [L40] int E_4 = 2; [L47] int token ; [L49] int local ; [L840] int __retres1 ; [L752] m_i = 1 [L753] t1_i = 1 [L754] t2_i = 1 [L755] t3_i = 1 [L756] t4_i = 1 [L781] int kernel_st ; [L782] int tmp ; [L783] int tmp___0 ; [L787] kernel_st = 0 [L345] COND TRUE m_i == 1 [L346] m_st = 0 [L350] COND TRUE t1_i == 1 [L351] t1_st = 0 [L355] COND TRUE t2_i == 1 [L356] t2_st = 0 [L360] COND TRUE t3_i == 1 [L361] t3_st = 0 [L365] COND TRUE t4_i == 1 [L366] t4_st = 0 [L506] COND FALSE !(M_E == 0) [L511] COND FALSE !(T1_E == 0) [L516] COND FALSE !(T2_E == 0) [L521] COND FALSE !(T3_E == 0) [L526] COND FALSE !(T4_E == 0) [L531] COND FALSE !(E_M == 0) [L536] COND FALSE !(E_1 == 0) [L541] COND FALSE !(E_2 == 0) [L546] COND FALSE !(E_3 == 0) [L551] COND FALSE !(E_4 == 0) [L619] int tmp ; [L620] int tmp___0 ; [L621] int tmp___1 ; [L622] int tmp___2 ; [L623] int tmp___3 ; [L239] int __retres1 ; [L242] COND FALSE !(m_pc == 1) [L252] __retres1 = 0 [L254] return (__retres1); [L627] tmp = is_master_triggered() [L629] COND FALSE !(\read(tmp)) [L258] int __retres1 ; [L261] COND FALSE !(t1_pc == 1) [L271] __retres1 = 0 [L273] return (__retres1); [L635] tmp___0 = is_transmit1_triggered() [L637] COND FALSE !(\read(tmp___0)) [L277] int __retres1 ; [L280] COND FALSE !(t2_pc == 1) [L290] __retres1 = 0 [L292] return (__retres1); [L643] tmp___1 = is_transmit2_triggered() [L645] COND FALSE !(\read(tmp___1)) [L296] int __retres1 ; [L299] COND FALSE !(t3_pc == 1) [L309] __retres1 = 0 [L311] return (__retres1); [L651] tmp___2 = is_transmit3_triggered() [L653] COND FALSE !(\read(tmp___2)) [L315] int __retres1 ; [L318] COND FALSE !(t4_pc == 1) [L328] __retres1 = 0 [L330] return (__retres1); [L659] tmp___3 = is_transmit4_triggered() [L661] COND FALSE !(\read(tmp___3)) [L564] COND FALSE !(M_E == 1) [L569] COND FALSE !(T1_E == 1) [L574] COND FALSE !(T2_E == 1) [L579] COND FALSE !(T3_E == 1) [L584] COND FALSE !(T4_E == 1) [L589] COND FALSE !(E_M == 1) [L594] COND FALSE !(E_1 == 1) [L599] COND FALSE !(E_2 == 1) [L604] COND FALSE !(E_3 == 1) [L609] COND FALSE !(E_4 == 1) [L795] COND TRUE 1 [L798] kernel_st = 1 [L411] int tmp ; Loop: [L415] COND TRUE 1 [L375] int __retres1 ; [L378] COND TRUE m_st == 0 [L379] __retres1 = 1 [L406] return (__retres1); [L418] tmp = exists_runnable_thread() [L420] COND TRUE \read(tmp) [L425] COND TRUE m_st == 0 [L426] int tmp_ndt_1; [L427] tmp_ndt_1 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_1)) [L439] COND TRUE t1_st == 0 [L440] int tmp_ndt_2; [L441] tmp_ndt_2 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_2)) [L453] COND TRUE t2_st == 0 [L454] int tmp_ndt_3; [L455] tmp_ndt_3 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_3)) [L467] COND TRUE t3_st == 0 [L468] int tmp_ndt_4; [L469] tmp_ndt_4 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_4)) [L481] COND TRUE t4_st == 0 [L482] int tmp_ndt_5; [L483] tmp_ndt_5 = __VERIFIER_nondet_int() [L484] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...