./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 54858612 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3723db60962369c4b10118802934116c8cea6114 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-5485861 [2020-10-26 05:48:08,006 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-10-26 05:48:08,009 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-10-26 05:48:08,062 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-10-26 05:48:08,064 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-10-26 05:48:08,070 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-10-26 05:48:08,072 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-10-26 05:48:08,079 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-10-26 05:48:08,083 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-10-26 05:48:08,090 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-10-26 05:48:08,091 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-10-26 05:48:08,096 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-10-26 05:48:08,097 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-10-26 05:48:08,101 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-10-26 05:48:08,103 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-10-26 05:48:08,105 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-10-26 05:48:08,106 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-10-26 05:48:08,109 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-10-26 05:48:08,113 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-10-26 05:48:08,122 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-10-26 05:48:08,124 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-10-26 05:48:08,126 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-10-26 05:48:08,127 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-10-26 05:48:08,129 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-10-26 05:48:08,139 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-10-26 05:48:08,143 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-10-26 05:48:08,143 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-10-26 05:48:08,147 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-10-26 05:48:08,148 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-10-26 05:48:08,149 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-10-26 05:48:08,150 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-10-26 05:48:08,151 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-10-26 05:48:08,154 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-10-26 05:48:08,155 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-10-26 05:48:08,157 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-10-26 05:48:08,157 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-10-26 05:48:08,161 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-10-26 05:48:08,162 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-10-26 05:48:08,162 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-10-26 05:48:08,165 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-10-26 05:48:08,166 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-10-26 05:48:08,167 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-10-26 05:48:08,229 INFO L113 SettingsManager]: Loading preferences was successful [2020-10-26 05:48:08,229 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-10-26 05:48:08,232 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-10-26 05:48:08,233 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-10-26 05:48:08,233 INFO L138 SettingsManager]: * Use SBE=true [2020-10-26 05:48:08,233 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-10-26 05:48:08,233 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-10-26 05:48:08,234 INFO L138 SettingsManager]: * Use old map elimination=false [2020-10-26 05:48:08,234 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-10-26 05:48:08,235 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-10-26 05:48:08,236 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-10-26 05:48:08,236 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-10-26 05:48:08,236 INFO L138 SettingsManager]: * sizeof long=4 [2020-10-26 05:48:08,237 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-10-26 05:48:08,237 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-10-26 05:48:08,237 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-10-26 05:48:08,237 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-10-26 05:48:08,238 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-10-26 05:48:08,238 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-10-26 05:48:08,238 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-10-26 05:48:08,238 INFO L138 SettingsManager]: * sizeof long double=12 [2020-10-26 05:48:08,239 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-10-26 05:48:08,239 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-10-26 05:48:08,239 INFO L138 SettingsManager]: * Use constant arrays=true [2020-10-26 05:48:08,239 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-10-26 05:48:08,240 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-10-26 05:48:08,240 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-10-26 05:48:08,240 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-10-26 05:48:08,241 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-10-26 05:48:08,241 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-10-26 05:48:08,241 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-10-26 05:48:08,241 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-10-26 05:48:08,244 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-10-26 05:48:08,244 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3723db60962369c4b10118802934116c8cea6114 [2020-10-26 05:48:08,685 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-10-26 05:48:08,726 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-10-26 05:48:08,732 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-10-26 05:48:08,733 INFO L271 PluginConnector]: Initializing CDTParser... [2020-10-26 05:48:08,734 INFO L275 PluginConnector]: CDTParser initialized [2020-10-26 05:48:08,735 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.04.cil.c [2020-10-26 05:48:08,815 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bae01819d/19f320616dea4436a3a3a10e786f55dc/FLAGffa37f722 [2020-10-26 05:48:09,553 INFO L306 CDTParser]: Found 1 translation units. [2020-10-26 05:48:09,554 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c [2020-10-26 05:48:09,576 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bae01819d/19f320616dea4436a3a3a10e786f55dc/FLAGffa37f722 [2020-10-26 05:48:09,852 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bae01819d/19f320616dea4436a3a3a10e786f55dc [2020-10-26 05:48:09,856 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-10-26 05:48:09,866 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-10-26 05:48:09,881 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-10-26 05:48:09,882 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-10-26 05:48:09,886 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-10-26 05:48:09,891 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 05:48:09" (1/1) ... [2020-10-26 05:48:09,900 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7bdd7ba9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:09, skipping insertion in model container [2020-10-26 05:48:09,900 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 05:48:09" (1/1) ... [2020-10-26 05:48:09,910 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-10-26 05:48:09,988 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-10-26 05:48:10,233 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-10-26 05:48:10,247 INFO L203 MainTranslator]: Completed pre-run [2020-10-26 05:48:10,319 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-10-26 05:48:10,357 INFO L208 MainTranslator]: Completed translation [2020-10-26 05:48:10,358 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10 WrapperNode [2020-10-26 05:48:10,358 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-10-26 05:48:10,359 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-10-26 05:48:10,360 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-10-26 05:48:10,360 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-10-26 05:48:10,369 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,381 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,459 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-10-26 05:48:10,460 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-10-26 05:48:10,460 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-10-26 05:48:10,461 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-10-26 05:48:10,471 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,471 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,478 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,478 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,500 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,535 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,545 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... [2020-10-26 05:48:10,560 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-10-26 05:48:10,564 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-10-26 05:48:10,564 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-10-26 05:48:10,564 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-10-26 05:48:10,568 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-10-26 05:48:10,679 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-10-26 05:48:10,679 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-10-26 05:48:10,680 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-10-26 05:48:10,680 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-10-26 05:48:12,100 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-10-26 05:48:12,101 INFO L298 CfgBuilder]: Removed 150 assume(true) statements. [2020-10-26 05:48:12,103 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:48:12 BoogieIcfgContainer [2020-10-26 05:48:12,104 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-10-26 05:48:12,105 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-10-26 05:48:12,105 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-10-26 05:48:12,109 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-10-26 05:48:12,110 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:48:12,110 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.10 05:48:09" (1/3) ... [2020-10-26 05:48:12,112 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64047af5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.10 05:48:12, skipping insertion in model container [2020-10-26 05:48:12,112 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:48:12,112 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:10" (2/3) ... [2020-10-26 05:48:12,112 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64047af5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.10 05:48:12, skipping insertion in model container [2020-10-26 05:48:12,112 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:48:12,113 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:48:12" (3/3) ... [2020-10-26 05:48:12,114 INFO L373 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2020-10-26 05:48:12,177 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-10-26 05:48:12,178 INFO L360 BuchiCegarLoop]: Hoare is false [2020-10-26 05:48:12,178 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-10-26 05:48:12,178 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-10-26 05:48:12,178 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-10-26 05:48:12,178 INFO L364 BuchiCegarLoop]: Difference is false [2020-10-26 05:48:12,178 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-10-26 05:48:12,178 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-10-26 05:48:12,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 374 states. [2020-10-26 05:48:12,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 309 [2020-10-26 05:48:12,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:12,252 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:12,266 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:12,266 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:12,266 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-10-26 05:48:12,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 374 states. [2020-10-26 05:48:12,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 309 [2020-10-26 05:48:12,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:12,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:12,283 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:12,283 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:12,293 INFO L794 eck$LassoCheckResult]: Stem: 150#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 23#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 39#L731true havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 247#L326true assume !(1 == ~m_i~0);~m_st~0 := 2; 319#L333-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 344#L338-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 199#L343-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 250#L348-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 295#L353-1true assume !(0 == ~M_E~0); 54#L494-1true assume !(0 == ~T1_E~0); 98#L499-1true assume !(0 == ~T2_E~0); 306#L504-1true assume !(0 == ~T3_E~0); 323#L509-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 363#L514-1true assume !(0 == ~E_1~0); 217#L519-1true assume !(0 == ~E_2~0); 269#L524-1true assume !(0 == ~E_3~0); 303#L529-1true assume !(0 == ~E_4~0); 148#L534-1true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15#L230true assume !(1 == ~m_pc~0); 48#L230-2true is_master_triggered_~__retres1~0 := 0; 17#L241true is_master_triggered_#res := is_master_triggered_~__retres1~0; 146#L242true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 231#L607true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 213#L607-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 255#L249true assume 1 == ~t1_pc~0; 325#L250true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 256#L260true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 326#L261true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 75#L615true assume !(0 != activate_threads_~tmp___0~0); 78#L615-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 100#L268true assume !(1 == ~t2_pc~0); 93#L268-2true is_transmit2_triggered_~__retres1~2 := 0; 103#L279true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 192#L280true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 285#L623true assume !(0 != activate_threads_~tmp___1~0); 260#L623-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 298#L287true assume 1 == ~t3_pc~0; 210#L288true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 299#L298true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211#L299true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 114#L631true assume !(0 != activate_threads_~tmp___2~0); 117#L631-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 122#L306true assume !(1 == ~t4_pc~0); 126#L306-2true is_transmit4_triggered_~__retres1~4 := 0; 121#L317true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 24#L318true activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 131#L639true assume !(0 != activate_threads_~tmp___3~0); 300#L639-2true assume !(1 == ~M_E~0); 359#L547-1true assume !(1 == ~T1_E~0); 215#L552-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 265#L557-1true assume !(1 == ~T3_E~0); 302#L562-1true assume !(1 == ~T4_E~0); 147#L567-1true assume !(1 == ~E_1~0); 176#L572-1true assume !(1 == ~E_2~0); 20#L577-1true assume !(1 == ~E_3~0); 79#L582-1true assume !(1 == ~E_4~0); 321#L768-1true [2020-10-26 05:48:12,295 INFO L796 eck$LassoCheckResult]: Loop: 321#L768-1true assume !false; 88#L769true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 272#L469true assume false; 161#L484true start_simulation_~kernel_st~0 := 2; 253#L326-1true start_simulation_~kernel_st~0 := 3; 60#L494-2true assume 0 == ~M_E~0;~M_E~0 := 1; 65#L494-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 107#L499-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 309#L504-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 324#L509-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 372#L514-3true assume !(0 == ~E_1~0); 194#L519-3true assume 0 == ~E_2~0;~E_2~0 := 1; 235#L524-3true assume 0 == ~E_3~0;~E_3~0 := 1; 290#L529-3true assume 0 == ~E_4~0;~E_4~0 := 1; 135#L534-3true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 189#L230-15true assume !(1 == ~m_pc~0); 182#L230-17true is_master_triggered_~__retres1~0 := 0; 33#L241-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 157#L242-5true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 376#L607-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 353#L607-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 207#L249-15true assume 1 == ~t1_pc~0; 333#L250-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 234#L260-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 335#L261-5true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12#L615-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18#L615-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19#L268-15true assume 1 == ~t2_pc~0; 169#L269-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 63#L279-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 170#L280-5true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 229#L623-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 209#L623-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 226#L287-15true assume 1 == ~t3_pc~0; 356#L288-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 258#L298-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 357#L299-5true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 73#L631-15true assume !(0 != activate_threads_~tmp___2~0); 76#L631-17true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 85#L306-15true assume 1 == ~t4_pc~0; 9#L307-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 111#L317-5true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5#L318-5true activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 282#L639-15true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 259#L639-17true assume 1 == ~M_E~0;~M_E~0 := 2; 369#L547-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 221#L552-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 276#L557-3true assume !(1 == ~T3_E~0); 305#L562-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 134#L567-3true assume 1 == ~E_1~0;~E_1~0 := 2; 162#L572-3true assume 1 == ~E_2~0;~E_2~0 := 2; 184#L577-3true assume 1 == ~E_3~0;~E_3~0 := 2; 51#L582-3true assume 1 == ~E_4~0;~E_4~0 := 2; 96#L587-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 318#L366-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 336#L393-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 119#L394-1true start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 151#L787true assume !(0 == start_simulation_~tmp~3); 152#L787-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 320#L366-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 341#L393-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 120#L394-2true stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 38#L742true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 130#L749true stop_simulation_#res := stop_simulation_~__retres2~0; 224#L750true start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 203#L800true assume !(0 != start_simulation_~tmp___0~1); 321#L768-1true [2020-10-26 05:48:12,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:12,303 INFO L82 PathProgramCache]: Analyzing trace with hash 1688618289, now seen corresponding path program 1 times [2020-10-26 05:48:12,313 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:12,314 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537956676] [2020-10-26 05:48:12,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:12,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:12,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:12,532 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537956676] [2020-10-26 05:48:12,533 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:12,533 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:12,534 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926102901] [2020-10-26 05:48:12,540 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:12,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:12,541 INFO L82 PathProgramCache]: Analyzing trace with hash 1315173295, now seen corresponding path program 1 times [2020-10-26 05:48:12,541 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:12,541 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233773602] [2020-10-26 05:48:12,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:12,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:12,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:12,574 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233773602] [2020-10-26 05:48:12,574 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:12,574 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:12,575 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1671842015] [2020-10-26 05:48:12,576 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:12,577 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:12,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:12,596 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:12,598 INFO L87 Difference]: Start difference. First operand 374 states. Second operand 3 states. [2020-10-26 05:48:12,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:12,666 INFO L93 Difference]: Finished difference Result 373 states and 564 transitions. [2020-10-26 05:48:12,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:12,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 373 states and 564 transitions. [2020-10-26 05:48:12,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:12,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 373 states to 368 states and 559 transitions. [2020-10-26 05:48:12,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2020-10-26 05:48:12,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2020-10-26 05:48:12,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 559 transitions. [2020-10-26 05:48:12,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:12,707 INFO L691 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2020-10-26 05:48:12,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 559 transitions. [2020-10-26 05:48:12,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2020-10-26 05:48:12,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2020-10-26 05:48:12,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 559 transitions. [2020-10-26 05:48:12,764 INFO L714 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2020-10-26 05:48:12,764 INFO L594 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2020-10-26 05:48:12,764 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-10-26 05:48:12,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 559 transitions. [2020-10-26 05:48:12,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:12,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:12,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:12,771 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:12,771 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:12,772 INFO L794 eck$LassoCheckResult]: Stem: 967#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 799#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 800#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 838#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 1072#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1115#L338-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1004#L343-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1005#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1073#L353-1 assume !(0 == ~M_E~0); 864#L494-1 assume !(0 == ~T1_E~0); 865#L499-1 assume !(0 == ~T2_E~0); 918#L504-1 assume !(0 == ~T3_E~0); 1110#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1118#L514-1 assume !(0 == ~E_1~0); 1036#L519-1 assume !(0 == ~E_2~0); 1037#L524-1 assume !(0 == ~E_3~0); 1092#L529-1 assume !(0 == ~E_4~0); 964#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 786#L230 assume !(1 == ~m_pc~0); 787#L230-2 is_master_triggered_~__retres1~0 := 0; 789#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 790#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 961#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1029#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1030#L249 assume 1 == ~t1_pc~0; 1077#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1068#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1078#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 891#L615 assume !(0 != activate_threads_~tmp___0~0); 892#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 896#L268 assume !(1 == ~t2_pc~0); 912#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 913#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 921#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 993#L623 assume !(0 != activate_threads_~tmp___1~0); 1084#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1085#L287 assume 1 == ~t3_pc~0; 1022#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1023#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1027#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 933#L631 assume !(0 != activate_threads_~tmp___2~0); 934#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 935#L306 assume !(1 == ~t4_pc~0); 806#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 807#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 803#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 804#L639 assume !(0 != activate_threads_~tmp___3~0); 945#L639-2 assume !(1 == ~M_E~0); 1108#L547-1 assume !(1 == ~T1_E~0); 1031#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1032#L557-1 assume !(1 == ~T3_E~0); 1089#L562-1 assume !(1 == ~T4_E~0); 962#L567-1 assume !(1 == ~E_1~0); 963#L572-1 assume !(1 == ~E_2~0); 793#L577-1 assume !(1 == ~E_3~0); 794#L582-1 assume !(1 == ~E_4~0); 897#L768-1 [2020-10-26 05:48:12,772 INFO L796 eck$LassoCheckResult]: Loop: 897#L768-1 assume !false; 908#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 860#L469 assume !false; 1093#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1114#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 930#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1112#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1105#L408 assume !(0 != eval_~tmp~0); 981#L484 start_simulation_~kernel_st~0 := 2; 982#L326-1 start_simulation_~kernel_st~0 := 3; 874#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 875#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 881#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 927#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1111#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1119#L514-3 assume !(0 == ~E_1~0); 994#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 995#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1057#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 948#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 949#L230-15 assume 1 == ~m_pc~0; 973#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 822#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 823#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 975#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1120#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1016#L249-15 assume 1 == ~t1_pc~0; 1017#L250-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1054#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1055#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 777#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 778#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 791#L268-15 assume 1 == ~t2_pc~0; 792#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 780#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 878#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 986#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1020#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1021#L287-15 assume !(1 == ~t3_pc~0); 1046#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 1076#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1079#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 888#L631-15 assume !(0 != activate_threads_~tmp___2~0); 889#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 893#L306-15 assume !(1 == ~t4_pc~0); 769#L306-17 is_transmit4_triggered_~__retres1~4 := 0; 768#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 760#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 761#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1080#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1081#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1040#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1041#L557-3 assume !(1 == ~T3_E~0); 1094#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 946#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 947#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 983#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 855#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 856#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 915#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 900#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 936#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 937#L787 assume !(0 == start_simulation_~tmp~3); 966#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 968#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 905#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 938#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 832#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 833#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 942#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1007#L800 assume !(0 != start_simulation_~tmp___0~1); 897#L768-1 [2020-10-26 05:48:12,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:12,773 INFO L82 PathProgramCache]: Analyzing trace with hash 1244717615, now seen corresponding path program 1 times [2020-10-26 05:48:12,773 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:12,774 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904586315] [2020-10-26 05:48:12,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:12,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:12,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:12,843 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904586315] [2020-10-26 05:48:12,843 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:12,843 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:12,844 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530469324] [2020-10-26 05:48:12,844 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:12,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:12,845 INFO L82 PathProgramCache]: Analyzing trace with hash 243970403, now seen corresponding path program 1 times [2020-10-26 05:48:12,845 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:12,846 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593574138] [2020-10-26 05:48:12,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:12,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:12,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:12,976 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593574138] [2020-10-26 05:48:12,976 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:12,977 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:12,978 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112257177] [2020-10-26 05:48:12,979 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:12,983 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:12,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:12,985 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:12,985 INFO L87 Difference]: Start difference. First operand 368 states and 559 transitions. cyclomatic complexity: 192 Second operand 3 states. [2020-10-26 05:48:13,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:13,017 INFO L93 Difference]: Finished difference Result 368 states and 558 transitions. [2020-10-26 05:48:13,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:13,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 558 transitions. [2020-10-26 05:48:13,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:13,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 558 transitions. [2020-10-26 05:48:13,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2020-10-26 05:48:13,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2020-10-26 05:48:13,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 558 transitions. [2020-10-26 05:48:13,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:13,040 INFO L691 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2020-10-26 05:48:13,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 558 transitions. [2020-10-26 05:48:13,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2020-10-26 05:48:13,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2020-10-26 05:48:13,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 558 transitions. [2020-10-26 05:48:13,072 INFO L714 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2020-10-26 05:48:13,072 INFO L594 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2020-10-26 05:48:13,073 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-10-26 05:48:13,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 558 transitions. [2020-10-26 05:48:13,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:13,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:13,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:13,078 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:13,078 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:13,079 INFO L794 eck$LassoCheckResult]: Stem: 1709#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1542#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1543#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1577#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 1814#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1858#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1746#L343-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1747#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1816#L353-1 assume !(0 == ~M_E~0); 1604#L494-1 assume !(0 == ~T1_E~0); 1605#L499-1 assume !(0 == ~T2_E~0); 1660#L504-1 assume !(0 == ~T3_E~0); 1853#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1861#L514-1 assume !(0 == ~E_1~0); 1777#L519-1 assume !(0 == ~E_2~0); 1778#L524-1 assume !(0 == ~E_3~0); 1833#L529-1 assume !(0 == ~E_4~0); 1707#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1526#L230 assume !(1 == ~m_pc~0); 1527#L230-2 is_master_triggered_~__retres1~0 := 0; 1532#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1533#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1704#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1771#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1772#L249 assume 1 == ~t1_pc~0; 1820#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1811#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1821#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1634#L615 assume !(0 != activate_threads_~tmp___0~0); 1635#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1638#L268 assume !(1 == ~t2_pc~0); 1655#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 1656#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1664#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1736#L623 assume !(0 != activate_threads_~tmp___1~0); 1825#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1826#L287 assume 1 == ~t3_pc~0; 1765#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1766#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1768#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1676#L631 assume !(0 != activate_threads_~tmp___2~0); 1677#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1678#L306 assume !(1 == ~t4_pc~0); 1549#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 1550#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1544#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1545#L639 assume !(0 != activate_threads_~tmp___3~0); 1686#L639-2 assume !(1 == ~M_E~0); 1851#L547-1 assume !(1 == ~T1_E~0); 1774#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1775#L557-1 assume !(1 == ~T3_E~0); 1830#L562-1 assume !(1 == ~T4_E~0); 1705#L567-1 assume !(1 == ~E_1~0); 1706#L572-1 assume !(1 == ~E_2~0); 1536#L577-1 assume !(1 == ~E_3~0); 1537#L582-1 assume !(1 == ~E_4~0); 1639#L768-1 [2020-10-26 05:48:13,079 INFO L796 eck$LassoCheckResult]: Loop: 1639#L768-1 assume !false; 1651#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1603#L469 assume !false; 1836#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1857#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1673#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1855#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1848#L408 assume !(0 != eval_~tmp~0); 1724#L484 start_simulation_~kernel_st~0 := 2; 1725#L326-1 start_simulation_~kernel_st~0 := 3; 1615#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1616#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1623#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1670#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1854#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1862#L514-3 assume !(0 == ~E_1~0); 1737#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1738#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1800#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1691#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1692#L230-15 assume 1 == ~m_pc~0; 1716#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1565#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1566#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1718#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1863#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1759#L249-15 assume 1 == ~t1_pc~0; 1760#L250-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1798#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1799#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1520#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1521#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1534#L268-15 assume !(1 == ~t2_pc~0); 1522#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 1523#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1621#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1729#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1763#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1764#L287-15 assume !(1 == ~t3_pc~0); 1789#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 1819#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1822#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1631#L631-15 assume !(0 != activate_threads_~tmp___2~0); 1632#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1636#L306-15 assume 1 == ~t4_pc~0; 1513#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1514#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1503#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1504#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1823#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1824#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1783#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1784#L557-3 assume !(1 == ~T3_E~0); 1839#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1689#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1690#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1726#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1598#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1599#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1658#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1643#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1679#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1680#L787 assume !(0 == start_simulation_~tmp~3); 1710#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1711#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1648#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1681#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 1575#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1576#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 1685#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1751#L800 assume !(0 != start_simulation_~tmp___0~1); 1639#L768-1 [2020-10-26 05:48:13,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:13,080 INFO L82 PathProgramCache]: Analyzing trace with hash -1021663571, now seen corresponding path program 1 times [2020-10-26 05:48:13,080 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:13,081 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909121679] [2020-10-26 05:48:13,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:13,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:13,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:13,149 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909121679] [2020-10-26 05:48:13,149 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:13,149 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:13,150 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615651936] [2020-10-26 05:48:13,150 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:13,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:13,151 INFO L82 PathProgramCache]: Analyzing trace with hash 959559651, now seen corresponding path program 1 times [2020-10-26 05:48:13,151 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:13,151 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000713598] [2020-10-26 05:48:13,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:13,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:13,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:13,221 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000713598] [2020-10-26 05:48:13,221 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:13,221 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:13,222 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324691016] [2020-10-26 05:48:13,222 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:13,222 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:13,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:13,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:13,224 INFO L87 Difference]: Start difference. First operand 368 states and 558 transitions. cyclomatic complexity: 191 Second operand 3 states. [2020-10-26 05:48:13,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:13,244 INFO L93 Difference]: Finished difference Result 368 states and 557 transitions. [2020-10-26 05:48:13,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:13,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 557 transitions. [2020-10-26 05:48:13,249 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:13,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 557 transitions. [2020-10-26 05:48:13,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2020-10-26 05:48:13,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2020-10-26 05:48:13,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 557 transitions. [2020-10-26 05:48:13,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:13,256 INFO L691 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2020-10-26 05:48:13,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 557 transitions. [2020-10-26 05:48:13,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2020-10-26 05:48:13,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2020-10-26 05:48:13,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 557 transitions. [2020-10-26 05:48:13,268 INFO L714 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2020-10-26 05:48:13,268 INFO L594 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2020-10-26 05:48:13,268 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-10-26 05:48:13,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 557 transitions. [2020-10-26 05:48:13,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:13,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:13,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:13,279 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:13,279 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:13,280 INFO L794 eck$LassoCheckResult]: Stem: 2453#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2285#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2286#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2324#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 2558#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2601#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2489#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2490#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2559#L353-1 assume !(0 == ~M_E~0); 2350#L494-1 assume !(0 == ~T1_E~0); 2351#L499-1 assume !(0 == ~T2_E~0); 2404#L504-1 assume !(0 == ~T3_E~0); 2596#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2604#L514-1 assume !(0 == ~E_1~0); 2520#L519-1 assume !(0 == ~E_2~0); 2521#L524-1 assume !(0 == ~E_3~0); 2578#L529-1 assume !(0 == ~E_4~0); 2450#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2272#L230 assume !(1 == ~m_pc~0); 2273#L230-2 is_master_triggered_~__retres1~0 := 0; 2275#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2276#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2447#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2515#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2516#L249 assume 1 == ~t1_pc~0; 2563#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2554#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2564#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2377#L615 assume !(0 != activate_threads_~tmp___0~0); 2378#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2382#L268 assume !(1 == ~t2_pc~0); 2398#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 2399#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2407#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2479#L623 assume !(0 != activate_threads_~tmp___1~0); 2570#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2571#L287 assume 1 == ~t3_pc~0; 2508#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2509#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2511#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2419#L631 assume !(0 != activate_threads_~tmp___2~0); 2420#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2421#L306 assume !(1 == ~t4_pc~0); 2292#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 2293#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2289#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2290#L639 assume !(0 != activate_threads_~tmp___3~0); 2431#L639-2 assume !(1 == ~M_E~0); 2594#L547-1 assume !(1 == ~T1_E~0); 2517#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2518#L557-1 assume !(1 == ~T3_E~0); 2575#L562-1 assume !(1 == ~T4_E~0); 2448#L567-1 assume !(1 == ~E_1~0); 2449#L572-1 assume !(1 == ~E_2~0); 2279#L577-1 assume !(1 == ~E_3~0); 2280#L582-1 assume !(1 == ~E_4~0); 2383#L768-1 [2020-10-26 05:48:13,282 INFO L796 eck$LassoCheckResult]: Loop: 2383#L768-1 assume !false; 2394#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2346#L469 assume !false; 2579#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2600#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2416#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2598#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2591#L408 assume !(0 != eval_~tmp~0); 2467#L484 start_simulation_~kernel_st~0 := 2; 2468#L326-1 start_simulation_~kernel_st~0 := 3; 2360#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2361#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2367#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2413#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2597#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2605#L514-3 assume !(0 == ~E_1~0); 2480#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2481#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2544#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2434#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2435#L230-15 assume 1 == ~m_pc~0; 2459#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2308#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2309#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2461#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2606#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2502#L249-15 assume 1 == ~t1_pc~0; 2503#L250-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2540#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2541#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2263#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2264#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2277#L268-15 assume 1 == ~t2_pc~0; 2278#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2266#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2364#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2472#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2506#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2507#L287-15 assume !(1 == ~t3_pc~0); 2532#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 2562#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2565#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2374#L631-15 assume !(0 != activate_threads_~tmp___2~0); 2375#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2379#L306-15 assume 1 == ~t4_pc~0; 2253#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2254#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2246#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2247#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2566#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2567#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2525#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2526#L557-3 assume !(1 == ~T3_E~0); 2580#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2432#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2433#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2469#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2341#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2342#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2401#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2386#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2422#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2423#L787 assume !(0 == start_simulation_~tmp~3); 2452#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2454#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2391#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2424#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 2316#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2317#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 2428#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2492#L800 assume !(0 != start_simulation_~tmp___0~1); 2383#L768-1 [2020-10-26 05:48:13,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:13,283 INFO L82 PathProgramCache]: Analyzing trace with hash -540583313, now seen corresponding path program 1 times [2020-10-26 05:48:13,284 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:13,284 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315146189] [2020-10-26 05:48:13,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:13,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:13,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:13,349 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315146189] [2020-10-26 05:48:13,349 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:13,349 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:13,350 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1630735085] [2020-10-26 05:48:13,350 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:13,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:13,351 INFO L82 PathProgramCache]: Analyzing trace with hash 1916488034, now seen corresponding path program 1 times [2020-10-26 05:48:13,351 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:13,351 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226131529] [2020-10-26 05:48:13,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:13,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:13,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:13,435 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226131529] [2020-10-26 05:48:13,435 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:13,435 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:13,436 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188018661] [2020-10-26 05:48:13,436 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:13,436 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:13,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:13,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:13,438 INFO L87 Difference]: Start difference. First operand 368 states and 557 transitions. cyclomatic complexity: 190 Second operand 3 states. [2020-10-26 05:48:13,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:13,453 INFO L93 Difference]: Finished difference Result 368 states and 556 transitions. [2020-10-26 05:48:13,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:13,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 556 transitions. [2020-10-26 05:48:13,458 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:13,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 556 transitions. [2020-10-26 05:48:13,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2020-10-26 05:48:13,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2020-10-26 05:48:13,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 556 transitions. [2020-10-26 05:48:13,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:13,463 INFO L691 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2020-10-26 05:48:13,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 556 transitions. [2020-10-26 05:48:13,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2020-10-26 05:48:13,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2020-10-26 05:48:13,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 556 transitions. [2020-10-26 05:48:13,472 INFO L714 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2020-10-26 05:48:13,472 INFO L594 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2020-10-26 05:48:13,472 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-10-26 05:48:13,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 556 transitions. [2020-10-26 05:48:13,475 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:13,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:13,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:13,477 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:13,477 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:13,477 INFO L794 eck$LassoCheckResult]: Stem: 3195#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3028#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3029#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3063#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 3300#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3344#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3232#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3233#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3302#L353-1 assume !(0 == ~M_E~0); 3090#L494-1 assume !(0 == ~T1_E~0); 3091#L499-1 assume !(0 == ~T2_E~0); 3146#L504-1 assume !(0 == ~T3_E~0); 3339#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3347#L514-1 assume !(0 == ~E_1~0); 3263#L519-1 assume !(0 == ~E_2~0); 3264#L524-1 assume !(0 == ~E_3~0); 3319#L529-1 assume !(0 == ~E_4~0); 3193#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3012#L230 assume !(1 == ~m_pc~0); 3013#L230-2 is_master_triggered_~__retres1~0 := 0; 3018#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3019#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3190#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3257#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3258#L249 assume 1 == ~t1_pc~0; 3306#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3297#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3307#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3120#L615 assume !(0 != activate_threads_~tmp___0~0); 3121#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3124#L268 assume !(1 == ~t2_pc~0); 3141#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 3142#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3150#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3222#L623 assume !(0 != activate_threads_~tmp___1~0); 3311#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3312#L287 assume 1 == ~t3_pc~0; 3251#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3252#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3254#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3162#L631 assume !(0 != activate_threads_~tmp___2~0); 3163#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3164#L306 assume !(1 == ~t4_pc~0); 3035#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 3036#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3030#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3031#L639 assume !(0 != activate_threads_~tmp___3~0); 3172#L639-2 assume !(1 == ~M_E~0); 3337#L547-1 assume !(1 == ~T1_E~0); 3260#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3261#L557-1 assume !(1 == ~T3_E~0); 3316#L562-1 assume !(1 == ~T4_E~0); 3191#L567-1 assume !(1 == ~E_1~0); 3192#L572-1 assume !(1 == ~E_2~0); 3022#L577-1 assume !(1 == ~E_3~0); 3023#L582-1 assume !(1 == ~E_4~0); 3125#L768-1 [2020-10-26 05:48:13,478 INFO L796 eck$LassoCheckResult]: Loop: 3125#L768-1 assume !false; 3137#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3089#L469 assume !false; 3322#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3343#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3159#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3341#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3334#L408 assume !(0 != eval_~tmp~0); 3210#L484 start_simulation_~kernel_st~0 := 2; 3211#L326-1 start_simulation_~kernel_st~0 := 3; 3101#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3102#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3109#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3156#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3340#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3348#L514-3 assume !(0 == ~E_1~0); 3223#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3224#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3286#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3177#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3178#L230-15 assume 1 == ~m_pc~0; 3202#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3051#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3052#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3204#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3349#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3245#L249-15 assume 1 == ~t1_pc~0; 3246#L250-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3284#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3285#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3006#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3007#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3020#L268-15 assume !(1 == ~t2_pc~0); 3008#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 3009#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3107#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3215#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3249#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3250#L287-15 assume !(1 == ~t3_pc~0); 3275#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 3305#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3308#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3117#L631-15 assume !(0 != activate_threads_~tmp___2~0); 3118#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3122#L306-15 assume 1 == ~t4_pc~0; 2999#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3000#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2989#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2990#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3309#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 3310#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3269#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3270#L557-3 assume !(1 == ~T3_E~0); 3325#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3175#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3176#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3212#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3084#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3085#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3144#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3129#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3165#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3166#L787 assume !(0 == start_simulation_~tmp~3); 3196#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3197#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3134#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3167#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3061#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3062#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 3171#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3237#L800 assume !(0 != start_simulation_~tmp___0~1); 3125#L768-1 [2020-10-26 05:48:13,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:13,479 INFO L82 PathProgramCache]: Analyzing trace with hash -525064595, now seen corresponding path program 1 times [2020-10-26 05:48:13,479 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:13,479 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567507600] [2020-10-26 05:48:13,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:13,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:13,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:13,518 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [567507600] [2020-10-26 05:48:13,519 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:13,519 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:13,519 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [662747134] [2020-10-26 05:48:13,520 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:13,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:13,521 INFO L82 PathProgramCache]: Analyzing trace with hash 959559651, now seen corresponding path program 2 times [2020-10-26 05:48:13,521 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:13,521 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068014817] [2020-10-26 05:48:13,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:13,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:13,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:13,607 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068014817] [2020-10-26 05:48:13,607 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:13,608 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:13,608 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107756520] [2020-10-26 05:48:13,608 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:13,609 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:13,611 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:13,612 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:13,612 INFO L87 Difference]: Start difference. First operand 368 states and 556 transitions. cyclomatic complexity: 189 Second operand 3 states. [2020-10-26 05:48:13,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:13,645 INFO L93 Difference]: Finished difference Result 368 states and 551 transitions. [2020-10-26 05:48:13,646 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:13,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 551 transitions. [2020-10-26 05:48:13,650 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:13,654 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 551 transitions. [2020-10-26 05:48:13,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2020-10-26 05:48:13,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2020-10-26 05:48:13,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 551 transitions. [2020-10-26 05:48:13,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:13,656 INFO L691 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2020-10-26 05:48:13,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 551 transitions. [2020-10-26 05:48:13,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2020-10-26 05:48:13,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2020-10-26 05:48:13,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 551 transitions. [2020-10-26 05:48:13,664 INFO L714 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2020-10-26 05:48:13,664 INFO L594 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2020-10-26 05:48:13,664 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-10-26 05:48:13,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 551 transitions. [2020-10-26 05:48:13,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2020-10-26 05:48:13,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:13,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:13,676 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:13,676 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:13,677 INFO L794 eck$LassoCheckResult]: Stem: 3939#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3771#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3772#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3809#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 4044#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4087#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3975#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3976#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4045#L353-1 assume !(0 == ~M_E~0); 3833#L494-1 assume !(0 == ~T1_E~0); 3834#L499-1 assume !(0 == ~T2_E~0); 3890#L504-1 assume !(0 == ~T3_E~0); 4082#L509-1 assume !(0 == ~T4_E~0); 4090#L514-1 assume !(0 == ~E_1~0); 4006#L519-1 assume !(0 == ~E_2~0); 4007#L524-1 assume !(0 == ~E_3~0); 4064#L529-1 assume !(0 == ~E_4~0); 3936#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3758#L230 assume !(1 == ~m_pc~0); 3759#L230-2 is_master_triggered_~__retres1~0 := 0; 3761#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3762#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3933#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4001#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4002#L249 assume 1 == ~t1_pc~0; 4049#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4040#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4050#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3863#L615 assume !(0 != activate_threads_~tmp___0~0); 3864#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3868#L268 assume !(1 == ~t2_pc~0); 3884#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 3885#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3893#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3965#L623 assume !(0 != activate_threads_~tmp___1~0); 4056#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4057#L287 assume 1 == ~t3_pc~0; 3994#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3995#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3997#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3905#L631 assume !(0 != activate_threads_~tmp___2~0); 3906#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3907#L306 assume !(1 == ~t4_pc~0); 3778#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 3779#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3773#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3774#L639 assume !(0 != activate_threads_~tmp___3~0); 3917#L639-2 assume !(1 == ~M_E~0); 4080#L547-1 assume !(1 == ~T1_E~0); 4003#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4004#L557-1 assume !(1 == ~T3_E~0); 4060#L562-1 assume !(1 == ~T4_E~0); 3934#L567-1 assume !(1 == ~E_1~0); 3935#L572-1 assume !(1 == ~E_2~0); 3765#L577-1 assume !(1 == ~E_3~0); 3766#L582-1 assume !(1 == ~E_4~0); 3869#L768-1 [2020-10-26 05:48:13,678 INFO L796 eck$LassoCheckResult]: Loop: 3869#L768-1 assume !false; 3880#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3832#L469 assume !false; 4065#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4086#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3902#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4084#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4077#L408 assume !(0 != eval_~tmp~0); 3953#L484 start_simulation_~kernel_st~0 := 2; 3954#L326-1 start_simulation_~kernel_st~0 := 3; 3844#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3845#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3852#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3899#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4083#L509-3 assume !(0 == ~T4_E~0); 4091#L514-3 assume !(0 == ~E_1~0); 3966#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3967#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4029#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3920#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3921#L230-15 assume 1 == ~m_pc~0; 3945#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3794#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3795#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3947#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4092#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3989#L249-15 assume 1 == ~t1_pc~0; 3990#L250-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4027#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4028#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3753#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3754#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3763#L268-15 assume 1 == ~t2_pc~0; 3764#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3750#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3848#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3958#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3992#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3993#L287-15 assume !(1 == ~t3_pc~0); 4017#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 4048#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4051#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3860#L631-15 assume !(0 != activate_threads_~tmp___2~0); 3861#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3865#L306-15 assume 1 == ~t4_pc~0; 3739#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3740#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3730#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3731#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4052#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 4053#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4011#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4012#L557-3 assume !(1 == ~T3_E~0); 4066#L562-3 assume !(1 == ~T4_E~0); 3918#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3919#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3955#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3827#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3828#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3887#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3872#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3908#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3909#L787 assume !(0 == start_simulation_~tmp~3); 3938#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3940#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3877#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3910#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3802#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3803#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 3914#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3978#L800 assume !(0 != start_simulation_~tmp___0~1); 3869#L768-1 [2020-10-26 05:48:13,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:13,679 INFO L82 PathProgramCache]: Analyzing trace with hash 1720514859, now seen corresponding path program 1 times [2020-10-26 05:48:13,679 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:13,679 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427804397] [2020-10-26 05:48:13,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:13,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:13,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:13,749 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427804397] [2020-10-26 05:48:13,749 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:13,750 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:48:13,750 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953181043] [2020-10-26 05:48:13,750 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:13,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:13,751 INFO L82 PathProgramCache]: Analyzing trace with hash 1183260578, now seen corresponding path program 1 times [2020-10-26 05:48:13,751 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:13,751 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097977739] [2020-10-26 05:48:13,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:13,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:13,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:13,791 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097977739] [2020-10-26 05:48:13,791 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:13,791 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:13,791 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958967560] [2020-10-26 05:48:13,792 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:13,792 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:13,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:48:13,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:48:13,793 INFO L87 Difference]: Start difference. First operand 368 states and 551 transitions. cyclomatic complexity: 184 Second operand 5 states. [2020-10-26 05:48:13,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:13,984 INFO L93 Difference]: Finished difference Result 1005 states and 1494 transitions. [2020-10-26 05:48:13,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-10-26 05:48:13,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1005 states and 1494 transitions. [2020-10-26 05:48:13,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 867 [2020-10-26 05:48:14,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1005 states to 1005 states and 1494 transitions. [2020-10-26 05:48:14,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1005 [2020-10-26 05:48:14,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1005 [2020-10-26 05:48:14,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1005 states and 1494 transitions. [2020-10-26 05:48:14,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:14,006 INFO L691 BuchiCegarLoop]: Abstraction has 1005 states and 1494 transitions. [2020-10-26 05:48:14,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1005 states and 1494 transitions. [2020-10-26 05:48:14,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1005 to 389. [2020-10-26 05:48:14,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2020-10-26 05:48:14,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 572 transitions. [2020-10-26 05:48:14,019 INFO L714 BuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2020-10-26 05:48:14,019 INFO L594 BuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2020-10-26 05:48:14,019 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-10-26 05:48:14,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 572 transitions. [2020-10-26 05:48:14,021 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 325 [2020-10-26 05:48:14,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:14,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:14,028 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,028 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,028 INFO L794 eck$LassoCheckResult]: Stem: 5331#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5157#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5158#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5192#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 5447#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5491#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5376#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5377#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5449#L353-1 assume !(0 == ~M_E~0); 5219#L494-1 assume !(0 == ~T1_E~0); 5220#L499-1 assume !(0 == ~T2_E~0); 5275#L504-1 assume !(0 == ~T3_E~0); 5486#L509-1 assume !(0 == ~T4_E~0); 5494#L514-1 assume !(0 == ~E_1~0); 5409#L519-1 assume !(0 == ~E_2~0); 5410#L524-1 assume !(0 == ~E_3~0); 5466#L529-1 assume !(0 == ~E_4~0); 5329#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5141#L230 assume !(1 == ~m_pc~0); 5142#L230-2 is_master_triggered_~__retres1~0 := 0; 5147#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5148#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5427#L607 assume !(0 != activate_threads_~tmp~1); 5402#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5403#L249 assume 1 == ~t1_pc~0; 5453#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5444#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5454#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5249#L615 assume !(0 != activate_threads_~tmp___0~0); 5250#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5253#L268 assume !(1 == ~t2_pc~0); 5270#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 5271#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5279#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5365#L623 assume !(0 != activate_threads_~tmp___1~0); 5458#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5459#L287 assume 1 == ~t3_pc~0; 5396#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5397#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5399#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5291#L631 assume !(0 != activate_threads_~tmp___2~0); 5292#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5293#L306 assume !(1 == ~t4_pc~0); 5164#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 5165#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5159#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5160#L639 assume !(0 != activate_threads_~tmp___3~0); 5301#L639-2 assume !(1 == ~M_E~0); 5484#L547-1 assume !(1 == ~T1_E~0); 5405#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5406#L557-1 assume !(1 == ~T3_E~0); 5463#L562-1 assume !(1 == ~T4_E~0); 5327#L567-1 assume !(1 == ~E_1~0); 5328#L572-1 assume !(1 == ~E_2~0); 5151#L577-1 assume !(1 == ~E_3~0); 5152#L582-1 assume !(1 == ~E_4~0); 5254#L768-1 [2020-10-26 05:48:14,029 INFO L796 eck$LassoCheckResult]: Loop: 5254#L768-1 assume !false; 5266#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5218#L469 assume !false; 5469#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5490#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5288#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5488#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 5481#L408 assume !(0 != eval_~tmp~0); 5353#L484 start_simulation_~kernel_st~0 := 2; 5354#L326-1 start_simulation_~kernel_st~0 := 3; 5230#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5231#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5238#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5285#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5487#L509-3 assume !(0 == ~T4_E~0); 5495#L514-3 assume !(0 == ~E_1~0); 5366#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5367#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5433#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5306#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5307#L230-15 assume 1 == ~m_pc~0; 5340#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5341#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5343#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5344#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5496#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5390#L249-15 assume !(1 == ~t1_pc~0); 5392#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 5431#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5432#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5135#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5136#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5149#L268-15 assume !(1 == ~t2_pc~0); 5137#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 5138#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5236#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5358#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5394#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5395#L287-15 assume !(1 == ~t3_pc~0); 5421#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 5452#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5455#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5246#L631-15 assume !(0 != activate_threads_~tmp___2~0); 5247#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5251#L306-15 assume 1 == ~t4_pc~0; 5128#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5129#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5118#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5119#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5456#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 5457#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5415#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5416#L557-3 assume !(1 == ~T3_E~0); 5472#L562-3 assume !(1 == ~T4_E~0); 5304#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5305#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5355#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5213#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5214#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5273#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5258#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5294#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 5295#L787 assume !(0 == start_simulation_~tmp~3); 5332#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5333#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5263#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5296#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 5190#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5191#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 5300#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5382#L800 assume !(0 != start_simulation_~tmp___0~1); 5254#L768-1 [2020-10-26 05:48:14,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:14,029 INFO L82 PathProgramCache]: Analyzing trace with hash -523468439, now seen corresponding path program 1 times [2020-10-26 05:48:14,030 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:14,030 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78644446] [2020-10-26 05:48:14,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:14,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:14,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:14,070 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78644446] [2020-10-26 05:48:14,070 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:14,070 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:14,071 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007798340] [2020-10-26 05:48:14,071 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:14,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:14,072 INFO L82 PathProgramCache]: Analyzing trace with hash -647145500, now seen corresponding path program 1 times [2020-10-26 05:48:14,072 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:14,072 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322513293] [2020-10-26 05:48:14,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:14,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:14,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:14,103 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322513293] [2020-10-26 05:48:14,103 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:14,103 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:14,103 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847367525] [2020-10-26 05:48:14,104 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:14,104 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:14,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:48:14,105 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:48:14,105 INFO L87 Difference]: Start difference. First operand 389 states and 572 transitions. cyclomatic complexity: 184 Second operand 4 states. [2020-10-26 05:48:14,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:14,280 INFO L93 Difference]: Finished difference Result 952 states and 1374 transitions. [2020-10-26 05:48:14,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:48:14,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1374 transitions. [2020-10-26 05:48:14,290 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2020-10-26 05:48:14,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1374 transitions. [2020-10-26 05:48:14,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2020-10-26 05:48:14,299 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2020-10-26 05:48:14,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1374 transitions. [2020-10-26 05:48:14,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:14,316 INFO L691 BuchiCegarLoop]: Abstraction has 952 states and 1374 transitions. [2020-10-26 05:48:14,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1374 transitions. [2020-10-26 05:48:14,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 886. [2020-10-26 05:48:14,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 886 states. [2020-10-26 05:48:14,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 886 states to 886 states and 1287 transitions. [2020-10-26 05:48:14,344 INFO L714 BuchiCegarLoop]: Abstraction has 886 states and 1287 transitions. [2020-10-26 05:48:14,344 INFO L594 BuchiCegarLoop]: Abstraction has 886 states and 1287 transitions. [2020-10-26 05:48:14,344 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-10-26 05:48:14,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 886 states and 1287 transitions. [2020-10-26 05:48:14,352 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 822 [2020-10-26 05:48:14,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:14,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:14,354 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,354 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,355 INFO L794 eck$LassoCheckResult]: Stem: 6678#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 6507#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6508#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6542#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 6793#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6838#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6724#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6725#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6794#L353-1 assume !(0 == ~M_E~0); 6569#L494-1 assume !(0 == ~T1_E~0); 6570#L499-1 assume !(0 == ~T2_E~0); 6624#L504-1 assume !(0 == ~T3_E~0); 6833#L509-1 assume !(0 == ~T4_E~0); 6843#L514-1 assume !(0 == ~E_1~0); 6755#L519-1 assume !(0 == ~E_2~0); 6756#L524-1 assume !(0 == ~E_3~0); 6811#L529-1 assume !(0 == ~E_4~0); 6675#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6495#L230 assume !(1 == ~m_pc~0); 6496#L230-2 is_master_triggered_~__retres1~0 := 0; 6497#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6498#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6672#L607 assume !(0 != activate_threads_~tmp~1); 6749#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6750#L249 assume !(1 == ~t1_pc~0); 6788#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 6789#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6798#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6597#L615 assume !(0 != activate_threads_~tmp___0~0); 6598#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6603#L268 assume !(1 == ~t2_pc~0); 6619#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 6620#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6628#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6714#L623 assume !(0 != activate_threads_~tmp___1~0); 6803#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6804#L287 assume 1 == ~t3_pc~0; 6741#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6742#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6744#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6640#L631 assume !(0 != activate_threads_~tmp___2~0); 6641#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6642#L306 assume !(1 == ~t4_pc~0); 6514#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 6515#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6509#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6510#L639 assume !(0 != activate_threads_~tmp___3~0); 6653#L639-2 assume !(1 == ~M_E~0); 6831#L547-1 assume !(1 == ~T1_E~0); 6751#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6752#L557-1 assume !(1 == ~T3_E~0); 6808#L562-1 assume !(1 == ~T4_E~0); 6673#L567-1 assume !(1 == ~E_1~0); 6674#L572-1 assume !(1 == ~E_2~0); 6501#L577-1 assume !(1 == ~E_3~0); 6502#L582-1 assume !(1 == ~E_4~0); 6604#L768-1 [2020-10-26 05:48:14,355 INFO L796 eck$LassoCheckResult]: Loop: 6604#L768-1 assume !false; 6842#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7161#L469 assume !false; 7160#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7159#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7154#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 6835#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6826#L408 assume !(0 != eval_~tmp~0); 6828#L484 start_simulation_~kernel_st~0 := 2; 7349#L326-1 start_simulation_~kernel_st~0 := 3; 7348#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7347#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7346#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7345#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7344#L509-3 assume !(0 == ~T4_E~0); 7343#L514-3 assume !(0 == ~E_1~0); 7342#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7341#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7340#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7339#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7338#L230-15 assume !(1 == ~m_pc~0); 7337#L230-17 is_master_triggered_~__retres1~0 := 0; 7336#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7335#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7334#L607-15 assume !(0 != activate_threads_~tmp~1); 7333#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7332#L249-15 assume !(1 == ~t1_pc~0); 7331#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 7330#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7329#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7328#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7327#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7326#L268-15 assume !(1 == ~t2_pc~0); 7324#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 7323#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7322#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7321#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7320#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7319#L287-15 assume 1 == ~t3_pc~0; 7317#L288-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7316#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7315#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7314#L631-15 assume !(0 != activate_threads_~tmp___2~0); 7313#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7312#L306-15 assume 1 == ~t4_pc~0; 7310#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7309#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7308#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7307#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7306#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 7305#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7304#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7303#L557-3 assume !(1 == ~T3_E~0); 7302#L562-3 assume !(1 == ~T4_E~0); 7301#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7300#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7299#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7298#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7297#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7254#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7251#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7250#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7248#L787 assume !(0 == start_simulation_~tmp~3); 7246#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7238#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7235#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7234#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 7233#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7232#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 7231#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 6727#L800 assume !(0 != start_simulation_~tmp___0~1); 6604#L768-1 [2020-10-26 05:48:14,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:14,356 INFO L82 PathProgramCache]: Analyzing trace with hash 395506184, now seen corresponding path program 1 times [2020-10-26 05:48:14,356 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:14,357 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [576327562] [2020-10-26 05:48:14,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:14,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:14,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:14,402 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [576327562] [2020-10-26 05:48:14,403 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:14,403 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:14,403 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498569788] [2020-10-26 05:48:14,404 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:14,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:14,404 INFO L82 PathProgramCache]: Analyzing trace with hash -1524517338, now seen corresponding path program 1 times [2020-10-26 05:48:14,405 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:14,405 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651997392] [2020-10-26 05:48:14,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:14,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:14,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:14,453 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651997392] [2020-10-26 05:48:14,456 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:14,457 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:14,457 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1123756935] [2020-10-26 05:48:14,459 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:14,459 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:14,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:48:14,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:48:14,460 INFO L87 Difference]: Start difference. First operand 886 states and 1287 transitions. cyclomatic complexity: 403 Second operand 4 states. [2020-10-26 05:48:14,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:14,657 INFO L93 Difference]: Finished difference Result 2293 states and 3293 transitions. [2020-10-26 05:48:14,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:48:14,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2293 states and 3293 transitions. [2020-10-26 05:48:14,680 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2131 [2020-10-26 05:48:14,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2293 states to 2293 states and 3293 transitions. [2020-10-26 05:48:14,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2293 [2020-10-26 05:48:14,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2293 [2020-10-26 05:48:14,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2293 states and 3293 transitions. [2020-10-26 05:48:14,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:14,706 INFO L691 BuchiCegarLoop]: Abstraction has 2293 states and 3293 transitions. [2020-10-26 05:48:14,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2293 states and 3293 transitions. [2020-10-26 05:48:14,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2293 to 2162. [2020-10-26 05:48:14,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2162 states. [2020-10-26 05:48:14,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3127 transitions. [2020-10-26 05:48:14,754 INFO L714 BuchiCegarLoop]: Abstraction has 2162 states and 3127 transitions. [2020-10-26 05:48:14,754 INFO L594 BuchiCegarLoop]: Abstraction has 2162 states and 3127 transitions. [2020-10-26 05:48:14,754 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-10-26 05:48:14,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3127 transitions. [2020-10-26 05:48:14,769 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2020-10-26 05:48:14,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:14,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:14,771 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,771 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,771 INFO L794 eck$LassoCheckResult]: Stem: 9891#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 9698#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 9699#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9734#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 10027#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10096#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9956#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9957#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10028#L353-1 assume !(0 == ~M_E~0); 9762#L494-1 assume !(0 == ~T1_E~0); 9763#L499-1 assume !(0 == ~T2_E~0); 9827#L504-1 assume !(0 == ~T3_E~0); 10086#L509-1 assume !(0 == ~T4_E~0); 10100#L514-1 assume !(0 == ~E_1~0); 9984#L519-1 assume !(0 == ~E_2~0); 9985#L524-1 assume !(0 == ~E_3~0); 10056#L529-1 assume !(0 == ~E_4~0); 9887#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9684#L230 assume !(1 == ~m_pc~0); 9685#L230-2 is_master_triggered_~__retres1~0 := 0; 9686#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9687#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9884#L607 assume !(0 != activate_threads_~tmp~1); 9978#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9979#L249 assume !(1 == ~t1_pc~0); 10023#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 10024#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10035#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9795#L615 assume !(0 != activate_threads_~tmp___0~0); 9796#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9801#L268 assume !(1 == ~t2_pc~0); 9820#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 9821#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9833#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9945#L623 assume !(0 != activate_threads_~tmp___1~0); 10045#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10046#L287 assume !(1 == ~t3_pc~0); 10052#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 10053#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9974#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9846#L631 assume !(0 != activate_threads_~tmp___2~0); 9847#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9848#L306 assume !(1 == ~t4_pc~0); 9707#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 9708#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9702#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9703#L639 assume !(0 != activate_threads_~tmp___3~0); 9863#L639-2 assume !(1 == ~M_E~0); 10082#L547-1 assume !(1 == ~T1_E~0); 9980#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9981#L557-1 assume !(1 == ~T3_E~0); 10051#L562-1 assume !(1 == ~T4_E~0); 9885#L567-1 assume !(1 == ~E_1~0); 9886#L572-1 assume !(1 == ~E_2~0); 9692#L577-1 assume !(1 == ~E_3~0); 9693#L582-1 assume !(1 == ~E_4~0); 9802#L768-1 [2020-10-26 05:48:14,772 INFO L796 eck$LassoCheckResult]: Loop: 9802#L768-1 assume !false; 9816#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 9758#L469 assume !false; 10057#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 10094#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9840#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11707#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 11705#L408 assume !(0 != eval_~tmp~0); 11706#L484 start_simulation_~kernel_st~0 := 2; 10033#L326-1 start_simulation_~kernel_st~0 := 3; 10034#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9780#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9781#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10088#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10089#L509-3 assume !(0 == ~T4_E~0); 10150#L514-3 assume !(0 == ~E_1~0); 10151#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10012#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10013#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9866#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9867#L230-15 assume !(1 == ~m_pc~0); 9938#L230-17 is_master_triggered_~__retres1~0 := 0; 9939#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9903#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9904#L607-15 assume !(0 != activate_threads_~tmp~1); 10130#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10131#L249-15 assume !(1 == ~t1_pc~0); 10143#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 10144#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10109#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10110#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9688#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9689#L268-15 assume 1 == ~t2_pc~0; 9690#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9774#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9775#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10006#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10007#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9995#L287-15 assume !(1 == ~t3_pc~0); 9996#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 10038#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10039#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9792#L631-15 assume !(0 != activate_threads_~tmp___2~0); 9793#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9809#L306-15 assume 1 == ~t4_pc~0; 9810#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9842#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9843#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10067#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10068#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 10145#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10146#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10061#L557-3 assume !(1 == ~T3_E~0); 10062#L562-3 assume !(1 == ~T4_E~0); 9864#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9865#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9935#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9936#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9823#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9824#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9805#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9849#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 9850#L787 assume !(0 == start_simulation_~tmp~3); 9890#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 10095#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9813#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9851#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 9727#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9728#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 9993#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 9994#L800 assume !(0 != start_simulation_~tmp___0~1); 9802#L768-1 [2020-10-26 05:48:14,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:14,772 INFO L82 PathProgramCache]: Analyzing trace with hash 1056839975, now seen corresponding path program 1 times [2020-10-26 05:48:14,772 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:14,773 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816893426] [2020-10-26 05:48:14,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:14,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:14,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:14,808 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816893426] [2020-10-26 05:48:14,808 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:14,808 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:14,809 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692139736] [2020-10-26 05:48:14,809 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:14,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:14,810 INFO L82 PathProgramCache]: Analyzing trace with hash -2144146714, now seen corresponding path program 1 times [2020-10-26 05:48:14,810 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:14,810 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812391397] [2020-10-26 05:48:14,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:14,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:14,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:14,853 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812391397] [2020-10-26 05:48:14,853 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:14,853 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:14,853 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877241256] [2020-10-26 05:48:14,854 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:14,854 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:14,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:14,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:14,855 INFO L87 Difference]: Start difference. First operand 2162 states and 3127 transitions. cyclomatic complexity: 969 Second operand 3 states. [2020-10-26 05:48:14,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:14,889 INFO L93 Difference]: Finished difference Result 2162 states and 3098 transitions. [2020-10-26 05:48:14,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:14,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3098 transitions. [2020-10-26 05:48:14,912 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2020-10-26 05:48:14,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3098 transitions. [2020-10-26 05:48:14,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2020-10-26 05:48:14,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2020-10-26 05:48:14,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3098 transitions. [2020-10-26 05:48:14,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:14,938 INFO L691 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2020-10-26 05:48:14,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3098 transitions. [2020-10-26 05:48:14,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2162. [2020-10-26 05:48:14,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2162 states. [2020-10-26 05:48:14,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3098 transitions. [2020-10-26 05:48:14,986 INFO L714 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2020-10-26 05:48:14,986 INFO L594 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2020-10-26 05:48:14,986 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-10-26 05:48:14,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3098 transitions. [2020-10-26 05:48:14,999 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2020-10-26 05:48:15,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:15,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:15,001 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,001 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,001 INFO L794 eck$LassoCheckResult]: Stem: 14206#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 14027#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14028#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14064#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 14324#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14381#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14256#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14257#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14325#L353-1 assume !(0 == ~M_E~0); 14092#L494-1 assume !(0 == ~T1_E~0); 14093#L499-1 assume !(0 == ~T2_E~0); 14147#L504-1 assume !(0 == ~T3_E~0); 14374#L509-1 assume !(0 == ~T4_E~0); 14385#L514-1 assume !(0 == ~E_1~0); 14286#L519-1 assume !(0 == ~E_2~0); 14287#L524-1 assume !(0 == ~E_3~0); 14349#L529-1 assume !(0 == ~E_4~0); 14202#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14015#L230 assume !(1 == ~m_pc~0); 14016#L230-2 is_master_triggered_~__retres1~0 := 0; 14017#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14018#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14199#L607 assume !(0 != activate_threads_~tmp~1); 14280#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14281#L249 assume !(1 == ~t1_pc~0); 14318#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 14319#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14330#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14118#L615 assume !(0 != activate_threads_~tmp___0~0); 14119#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14123#L268 assume !(1 == ~t2_pc~0); 14141#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 14142#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14153#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14245#L623 assume !(0 != activate_threads_~tmp___1~0); 14339#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14340#L287 assume !(1 == ~t3_pc~0); 14345#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 14346#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14278#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14163#L631 assume !(0 != activate_threads_~tmp___2~0); 14164#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14165#L306 assume !(1 == ~t4_pc~0); 14036#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 14037#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14031#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14032#L639 assume !(0 != activate_threads_~tmp___3~0); 14178#L639-2 assume !(1 == ~M_E~0); 14372#L547-1 assume !(1 == ~T1_E~0); 14282#L552-1 assume !(1 == ~T2_E~0); 14283#L557-1 assume !(1 == ~T3_E~0); 14344#L562-1 assume !(1 == ~T4_E~0); 14200#L567-1 assume !(1 == ~E_1~0); 14201#L572-1 assume !(1 == ~E_2~0); 14021#L577-1 assume !(1 == ~E_3~0); 14022#L582-1 assume !(1 == ~E_4~0); 14124#L768-1 [2020-10-26 05:48:15,001 INFO L796 eck$LassoCheckResult]: Loop: 14124#L768-1 assume !false; 15590#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 15588#L469 assume !false; 15586#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15584#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15125#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15126#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 15318#L408 assume !(0 != eval_~tmp~0); 15319#L484 start_simulation_~kernel_st~0 := 2; 15736#L326-1 start_simulation_~kernel_st~0 := 3; 15735#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15733#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15731#L499-3 assume !(0 == ~T2_E~0); 15729#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15727#L509-3 assume !(0 == ~T4_E~0); 15725#L514-3 assume !(0 == ~E_1~0); 15723#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15721#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15719#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15717#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15715#L230-15 assume !(1 == ~m_pc~0); 15713#L230-17 is_master_triggered_~__retres1~0 := 0; 15711#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15709#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15707#L607-15 assume !(0 != activate_threads_~tmp~1); 15705#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15703#L249-15 assume !(1 == ~t1_pc~0); 15701#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 15700#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15699#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15698#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15697#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15696#L268-15 assume !(1 == ~t2_pc~0); 15694#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 15692#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15690#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15688#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15686#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15684#L287-15 assume !(1 == ~t3_pc~0); 15682#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 15680#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15678#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15676#L631-15 assume !(0 != activate_threads_~tmp___2~0); 15674#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15672#L306-15 assume 1 == ~t4_pc~0; 15669#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15667#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15665#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15663#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15661#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 15659#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15655#L552-3 assume !(1 == ~T2_E~0); 15653#L557-3 assume !(1 == ~T3_E~0); 15651#L562-3 assume !(1 == ~T4_E~0); 15649#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15647#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15645#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15643#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15640#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15633#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15629#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15627#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 15624#L787 assume !(0 == start_simulation_~tmp~3); 15621#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15612#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15608#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15606#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 15604#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15602#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 15600#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 15598#L800 assume !(0 != start_simulation_~tmp___0~1); 14124#L768-1 [2020-10-26 05:48:15,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,002 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 1 times [2020-10-26 05:48:15,002 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,003 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874747436] [2020-10-26 05:48:15,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:15,013 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:15,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:15,022 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:15,061 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:15,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,062 INFO L82 PathProgramCache]: Analyzing trace with hash 936943527, now seen corresponding path program 1 times [2020-10-26 05:48:15,062 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,063 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063257182] [2020-10-26 05:48:15,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,092 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063257182] [2020-10-26 05:48:15,092 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,092 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,092 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220240529] [2020-10-26 05:48:15,093 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:15,093 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:15,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:15,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:15,094 INFO L87 Difference]: Start difference. First operand 2162 states and 3098 transitions. cyclomatic complexity: 940 Second operand 3 states. [2020-10-26 05:48:15,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:15,145 INFO L93 Difference]: Finished difference Result 2594 states and 3694 transitions. [2020-10-26 05:48:15,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:15,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2594 states and 3694 transitions. [2020-10-26 05:48:15,168 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2480 [2020-10-26 05:48:15,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2594 states to 2594 states and 3694 transitions. [2020-10-26 05:48:15,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2594 [2020-10-26 05:48:15,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2594 [2020-10-26 05:48:15,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2594 states and 3694 transitions. [2020-10-26 05:48:15,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:15,196 INFO L691 BuchiCegarLoop]: Abstraction has 2594 states and 3694 transitions. [2020-10-26 05:48:15,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2594 states and 3694 transitions. [2020-10-26 05:48:15,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2594 to 2594. [2020-10-26 05:48:15,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2594 states. [2020-10-26 05:48:15,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2594 states to 2594 states and 3694 transitions. [2020-10-26 05:48:15,244 INFO L714 BuchiCegarLoop]: Abstraction has 2594 states and 3694 transitions. [2020-10-26 05:48:15,244 INFO L594 BuchiCegarLoop]: Abstraction has 2594 states and 3694 transitions. [2020-10-26 05:48:15,244 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-10-26 05:48:15,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2594 states and 3694 transitions. [2020-10-26 05:48:15,260 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2480 [2020-10-26 05:48:15,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:15,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:15,261 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,261 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,262 INFO L794 eck$LassoCheckResult]: Stem: 18970#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 18791#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 18792#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18828#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 19088#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19148#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19020#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19021#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19089#L353-1 assume !(0 == ~M_E~0); 18855#L494-1 assume !(0 == ~T1_E~0); 18856#L499-1 assume !(0 == ~T2_E~0); 18911#L504-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19139#L509-1 assume !(0 == ~T4_E~0); 19177#L514-1 assume !(0 == ~E_1~0); 19049#L519-1 assume !(0 == ~E_2~0); 19050#L524-1 assume !(0 == ~E_3~0); 20825#L529-1 assume !(0 == ~E_4~0); 20824#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20823#L230 assume !(1 == ~m_pc~0); 20822#L230-2 is_master_triggered_~__retres1~0 := 0; 19679#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18963#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18964#L607 assume !(0 != activate_threads_~tmp~1); 19042#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19043#L249 assume !(1 == ~t1_pc~0); 19083#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 19084#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19093#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18880#L615 assume !(0 != activate_threads_~tmp___0~0); 18881#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18886#L268 assume !(1 == ~t2_pc~0); 18905#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 18906#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18917#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19010#L623 assume !(0 != activate_threads_~tmp___1~0); 19127#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19226#L287 assume !(1 == ~t3_pc~0); 19108#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 19109#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19040#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 18926#L631 assume !(0 != activate_threads_~tmp___2~0); 18927#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18928#L306 assume !(1 == ~t4_pc~0); 18800#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 18801#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18795#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 18796#L639 assume !(0 != activate_threads_~tmp___3~0); 19197#L639-2 assume !(1 == ~M_E~0); 19174#L547-1 assume !(1 == ~T1_E~0); 19044#L552-1 assume !(1 == ~T2_E~0); 19045#L557-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19107#L562-1 assume !(1 == ~T4_E~0); 18965#L567-1 assume !(1 == ~E_1~0); 18966#L572-1 assume !(1 == ~E_2~0); 18785#L577-1 assume !(1 == ~E_3~0); 18786#L582-1 assume !(1 == ~E_4~0); 18887#L768-1 [2020-10-26 05:48:15,262 INFO L796 eck$LassoCheckResult]: Loop: 18887#L768-1 assume !false; 20877#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 20875#L469 assume !false; 20874#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20865#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20858#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20854#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 20852#L408 assume !(0 != eval_~tmp~0); 18990#L484 start_simulation_~kernel_st~0 := 2; 18991#L326-1 start_simulation_~kernel_st~0 := 3; 18861#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 18862#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18870#L499-3 assume !(0 == ~T2_E~0); 18920#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19142#L509-3 assume !(0 == ~T4_E~0); 21316#L514-3 assume !(0 == ~E_1~0); 21313#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21311#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21308#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21306#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21302#L230-15 assume !(1 == ~m_pc~0); 21298#L230-17 is_master_triggered_~__retres1~0 := 0; 21295#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21293#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21290#L607-15 assume !(0 != activate_threads_~tmp~1); 21289#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21288#L249-15 assume !(1 == ~t1_pc~0); 21287#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 21286#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21285#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21284#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21283#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21282#L268-15 assume !(1 == ~t2_pc~0); 21280#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 21279#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21278#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21277#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21276#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21275#L287-15 assume !(1 == ~t3_pc~0); 21274#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 21273#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21272#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21271#L631-15 assume !(0 != activate_threads_~tmp___2~0); 18882#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18883#L306-15 assume 1 == ~t4_pc~0; 18761#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18762#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18751#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 18752#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 19097#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 19098#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19181#L552-3 assume !(1 == ~T2_E~0); 19119#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19120#L562-3 assume !(1 == ~T4_E~0); 18943#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18944#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18992#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18844#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18845#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 18908#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 18890#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 18929#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 18930#L787 assume !(0 == start_simulation_~tmp~3); 18969#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20923#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20912#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20911#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 20909#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20903#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 20892#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 20891#L800 assume !(0 != start_simulation_~tmp___0~1); 18887#L768-1 [2020-10-26 05:48:15,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1881102697, now seen corresponding path program 1 times [2020-10-26 05:48:15,263 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,263 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903494843] [2020-10-26 05:48:15,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,284 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903494843] [2020-10-26 05:48:15,285 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,285 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:15,285 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918789368] [2020-10-26 05:48:15,285 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:15,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,286 INFO L82 PathProgramCache]: Analyzing trace with hash -1669080027, now seen corresponding path program 1 times [2020-10-26 05:48:15,286 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,286 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513121264] [2020-10-26 05:48:15,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,317 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513121264] [2020-10-26 05:48:15,317 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,317 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:48:15,318 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365200012] [2020-10-26 05:48:15,318 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:15,318 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:15,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:15,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:15,319 INFO L87 Difference]: Start difference. First operand 2594 states and 3694 transitions. cyclomatic complexity: 1104 Second operand 3 states. [2020-10-26 05:48:15,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:15,350 INFO L93 Difference]: Finished difference Result 2162 states and 3069 transitions. [2020-10-26 05:48:15,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:15,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3069 transitions. [2020-10-26 05:48:15,366 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2020-10-26 05:48:15,382 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3069 transitions. [2020-10-26 05:48:15,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2020-10-26 05:48:15,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2020-10-26 05:48:15,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3069 transitions. [2020-10-26 05:48:15,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:15,388 INFO L691 BuchiCegarLoop]: Abstraction has 2162 states and 3069 transitions. [2020-10-26 05:48:15,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3069 transitions. [2020-10-26 05:48:15,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2162. [2020-10-26 05:48:15,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2162 states. [2020-10-26 05:48:15,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3069 transitions. [2020-10-26 05:48:15,459 INFO L714 BuchiCegarLoop]: Abstraction has 2162 states and 3069 transitions. [2020-10-26 05:48:15,459 INFO L594 BuchiCegarLoop]: Abstraction has 2162 states and 3069 transitions. [2020-10-26 05:48:15,459 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-10-26 05:48:15,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3069 transitions. [2020-10-26 05:48:15,474 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2020-10-26 05:48:15,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:15,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:15,476 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,476 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,476 INFO L794 eck$LassoCheckResult]: Stem: 23728#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 23554#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23555#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 23588#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 23847#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23907#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23783#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23784#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23848#L353-1 assume !(0 == ~M_E~0); 23615#L494-1 assume !(0 == ~T1_E~0); 23616#L499-1 assume !(0 == ~T2_E~0); 23673#L504-1 assume !(0 == ~T3_E~0); 23899#L509-1 assume !(0 == ~T4_E~0); 23911#L514-1 assume !(0 == ~E_1~0); 23811#L519-1 assume !(0 == ~E_2~0); 23812#L524-1 assume !(0 == ~E_3~0); 23872#L529-1 assume !(0 == ~E_4~0); 23726#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23539#L230 assume !(1 == ~m_pc~0); 23540#L230-2 is_master_triggered_~__retres1~0 := 0; 23544#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23545#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23723#L607 assume !(0 != activate_threads_~tmp~1); 23804#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23805#L249 assume !(1 == ~t1_pc~0); 23843#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 23844#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23853#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23647#L615 assume !(0 != activate_threads_~tmp___0~0); 23648#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23651#L268 assume !(1 == ~t2_pc~0); 23668#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 23669#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23677#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 23773#L623 assume !(0 != activate_threads_~tmp___1~0); 23859#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23860#L287 assume !(1 == ~t3_pc~0); 23870#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 23871#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23801#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23690#L631 assume !(0 != activate_threads_~tmp___2~0); 23691#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23692#L306 assume !(1 == ~t4_pc~0); 23561#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 23562#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23556#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23557#L639 assume !(0 != activate_threads_~tmp___3~0); 23702#L639-2 assume !(1 == ~M_E~0); 23897#L547-1 assume !(1 == ~T1_E~0); 23808#L552-1 assume !(1 == ~T2_E~0); 23809#L557-1 assume !(1 == ~T3_E~0); 23866#L562-1 assume !(1 == ~T4_E~0); 23724#L567-1 assume !(1 == ~E_1~0); 23725#L572-1 assume !(1 == ~E_2~0); 23548#L577-1 assume !(1 == ~E_3~0); 23549#L582-1 assume !(1 == ~E_4~0); 23652#L768-1 [2020-10-26 05:48:15,477 INFO L796 eck$LassoCheckResult]: Loop: 23652#L768-1 assume !false; 23664#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 23614#L469 assume !false; 23875#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23906#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23686#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23903#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 23893#L408 assume !(0 != eval_~tmp~0); 23895#L484 start_simulation_~kernel_st~0 := 2; 25623#L326-1 start_simulation_~kernel_st~0 := 3; 25621#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25619#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25617#L499-3 assume !(0 == ~T2_E~0); 25615#L504-3 assume !(0 == ~T3_E~0); 25613#L509-3 assume !(0 == ~T4_E~0); 23945#L514-3 assume !(0 == ~E_1~0); 23774#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23775#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23834#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23707#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23708#L230-15 assume !(1 == ~m_pc~0); 23768#L230-17 is_master_triggered_~__retres1~0 := 0; 23769#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25638#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23948#L607-15 assume !(0 != activate_threads_~tmp~1); 23949#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25637#L249-15 assume !(1 == ~t1_pc~0); 25636#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 25635#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25634#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25633#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25632#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25631#L268-15 assume !(1 == ~t2_pc~0); 25629#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 25628#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25627#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25626#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23799#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23800#L287-15 assume !(1 == ~t3_pc~0); 23822#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 23852#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23856#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23644#L631-15 assume !(0 != activate_threads_~tmp___2~0); 23645#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23649#L306-15 assume 1 == ~t4_pc~0; 23526#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23527#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23516#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23517#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 23857#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 23858#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23816#L552-3 assume !(1 == ~T2_E~0); 23817#L557-3 assume !(1 == ~T3_E~0); 23880#L562-3 assume !(1 == ~T4_E~0); 23705#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23706#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23752#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23608#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23609#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23671#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23656#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23693#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 23694#L787 assume !(0 == start_simulation_~tmp~3); 23730#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 25360#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 25357#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 25356#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 23586#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23587#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 23701#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 23788#L800 assume !(0 != start_simulation_~tmp___0~1); 23652#L768-1 [2020-10-26 05:48:15,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,477 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 2 times [2020-10-26 05:48:15,477 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,478 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346382774] [2020-10-26 05:48:15,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:15,487 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:15,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:15,497 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:15,521 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:15,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,522 INFO L82 PathProgramCache]: Analyzing trace with hash 1370672613, now seen corresponding path program 1 times [2020-10-26 05:48:15,522 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,522 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1206582097] [2020-10-26 05:48:15,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,559 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1206582097] [2020-10-26 05:48:15,559 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,560 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:48:15,560 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991532937] [2020-10-26 05:48:15,560 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:15,561 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:15,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:48:15,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:48:15,562 INFO L87 Difference]: Start difference. First operand 2162 states and 3069 transitions. cyclomatic complexity: 911 Second operand 5 states. [2020-10-26 05:48:15,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:15,714 INFO L93 Difference]: Finished difference Result 3731 states and 5221 transitions. [2020-10-26 05:48:15,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-10-26 05:48:15,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3731 states and 5221 transitions. [2020-10-26 05:48:15,783 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3643 [2020-10-26 05:48:15,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3731 states to 3731 states and 5221 transitions. [2020-10-26 05:48:15,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3731 [2020-10-26 05:48:15,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3731 [2020-10-26 05:48:15,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3731 states and 5221 transitions. [2020-10-26 05:48:15,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:15,828 INFO L691 BuchiCegarLoop]: Abstraction has 3731 states and 5221 transitions. [2020-10-26 05:48:15,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3731 states and 5221 transitions. [2020-10-26 05:48:15,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3731 to 2189. [2020-10-26 05:48:15,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2189 states. [2020-10-26 05:48:15,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2189 states to 2189 states and 3096 transitions. [2020-10-26 05:48:15,901 INFO L714 BuchiCegarLoop]: Abstraction has 2189 states and 3096 transitions. [2020-10-26 05:48:15,901 INFO L594 BuchiCegarLoop]: Abstraction has 2189 states and 3096 transitions. [2020-10-26 05:48:15,902 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-10-26 05:48:15,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2189 states and 3096 transitions. [2020-10-26 05:48:15,917 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2116 [2020-10-26 05:48:15,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:15,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:15,918 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,918 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,919 INFO L794 eck$LassoCheckResult]: Stem: 29645#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 29466#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 29467#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29499#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 29765#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29822#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29700#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29701#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29766#L353-1 assume !(0 == ~M_E~0); 29525#L494-1 assume !(0 == ~T1_E~0); 29526#L499-1 assume !(0 == ~T2_E~0); 29589#L504-1 assume !(0 == ~T3_E~0); 29814#L509-1 assume !(0 == ~T4_E~0); 29827#L514-1 assume !(0 == ~E_1~0); 29728#L519-1 assume !(0 == ~E_2~0); 29729#L524-1 assume !(0 == ~E_3~0); 29791#L529-1 assume !(0 == ~E_4~0); 29643#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29448#L230 assume !(1 == ~m_pc~0); 29449#L230-2 is_master_triggered_~__retres1~0 := 0; 29453#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29454#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 29640#L607 assume !(0 != activate_threads_~tmp~1); 29722#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29723#L249 assume !(1 == ~t1_pc~0); 29761#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 29762#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29773#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 29558#L615 assume !(0 != activate_threads_~tmp___0~0); 29559#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29563#L268 assume !(1 == ~t2_pc~0); 29583#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 29584#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29593#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 29691#L623 assume !(0 != activate_threads_~tmp___1~0); 29780#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29781#L287 assume !(1 == ~t3_pc~0); 29789#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 29790#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29719#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 29607#L631 assume !(0 != activate_threads_~tmp___2~0); 29608#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29609#L306 assume !(1 == ~t4_pc~0); 29473#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 29474#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29468#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 29469#L639 assume !(0 != activate_threads_~tmp___3~0); 29618#L639-2 assume !(1 == ~M_E~0); 29810#L547-1 assume !(1 == ~T1_E~0); 29725#L552-1 assume !(1 == ~T2_E~0); 29726#L557-1 assume !(1 == ~T3_E~0); 29786#L562-1 assume !(1 == ~T4_E~0); 29641#L567-1 assume !(1 == ~E_1~0); 29642#L572-1 assume !(1 == ~E_2~0); 29460#L577-1 assume !(1 == ~E_3~0); 29461#L582-1 assume !(1 == ~E_4~0); 29564#L768-1 [2020-10-26 05:48:15,919 INFO L796 eck$LassoCheckResult]: Loop: 29564#L768-1 assume !false; 29579#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 29524#L469 assume !false; 29794#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29820#L366 assume !(0 == ~m_st~0); 29758#L370 assume !(0 == ~t1_st~0); 29673#L374 assume !(0 == ~t2_st~0); 29601#L378 assume !(0 == ~t3_st~0); 29602#L382 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 29830#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29831#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 30887#L408 assume !(0 != eval_~tmp~0); 29666#L484 start_simulation_~kernel_st~0 := 2; 29667#L326-1 start_simulation_~kernel_st~0 := 3; 29536#L494-2 assume 0 == ~M_E~0;~M_E~0 := 1; 29537#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29599#L499-3 assume !(0 == ~T2_E~0); 29600#L504-3 assume !(0 == ~T3_E~0); 29828#L509-3 assume !(0 == ~T4_E~0); 29829#L514-3 assume !(0 == ~E_1~0); 29692#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29693#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29804#L529-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29805#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29688#L230-15 assume !(1 == ~m_pc~0); 29689#L230-17 is_master_triggered_~__retres1~0 := 0; 29487#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29488#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 29873#L607-15 assume !(0 != activate_threads_~tmp~1); 29874#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29714#L249-15 assume !(1 == ~t1_pc~0); 29715#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 29749#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29750#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 29442#L615-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 29443#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29457#L268-15 assume 1 == ~t2_pc~0; 29458#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 29540#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29541#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 29744#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 29745#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29738#L287-15 assume !(1 == ~t3_pc~0); 29739#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 29776#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29777#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 29555#L631-15 assume !(0 != activate_threads_~tmp___2~0); 29556#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29572#L306-15 assume 1 == ~t4_pc~0; 29573#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 29605#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29425#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 29426#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 29778#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 29779#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29733#L552-3 assume !(1 == ~T2_E~0); 29734#L557-3 assume !(1 == ~T3_E~0); 29797#L562-3 assume !(1 == ~T4_E~0); 29621#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29622#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31546#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29519#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29520#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29821#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 29568#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29610#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 29611#L787 assume !(0 == start_simulation_~tmp~3); 29646#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29647#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 31522#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31518#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 31516#L742 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 31515#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 31510#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 31506#L800 assume !(0 != start_simulation_~tmp___0~1); 29564#L768-1 [2020-10-26 05:48:15,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,920 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 3 times [2020-10-26 05:48:15,920 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,920 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758833728] [2020-10-26 05:48:15,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:15,930 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:15,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:15,938 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:15,954 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:15,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,955 INFO L82 PathProgramCache]: Analyzing trace with hash -981709840, now seen corresponding path program 1 times [2020-10-26 05:48:15,955 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,955 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099444664] [2020-10-26 05:48:15,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,992 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099444664] [2020-10-26 05:48:15,992 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,992 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,992 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136190288] [2020-10-26 05:48:15,993 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:15,993 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:15,993 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:15,994 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:15,994 INFO L87 Difference]: Start difference. First operand 2189 states and 3096 transitions. cyclomatic complexity: 911 Second operand 3 states. [2020-10-26 05:48:16,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:16,083 INFO L93 Difference]: Finished difference Result 3483 states and 4857 transitions. [2020-10-26 05:48:16,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:16,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3483 states and 4857 transitions. [2020-10-26 05:48:16,112 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3408 [2020-10-26 05:48:16,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3483 states to 3483 states and 4857 transitions. [2020-10-26 05:48:16,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3483 [2020-10-26 05:48:16,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3483 [2020-10-26 05:48:16,142 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3483 states and 4857 transitions. [2020-10-26 05:48:16,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:16,149 INFO L691 BuchiCegarLoop]: Abstraction has 3483 states and 4857 transitions. [2020-10-26 05:48:16,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3483 states and 4857 transitions. [2020-10-26 05:48:16,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3483 to 3363. [2020-10-26 05:48:16,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3363 states. [2020-10-26 05:48:16,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3363 states to 3363 states and 4697 transitions. [2020-10-26 05:48:16,229 INFO L714 BuchiCegarLoop]: Abstraction has 3363 states and 4697 transitions. [2020-10-26 05:48:16,229 INFO L594 BuchiCegarLoop]: Abstraction has 3363 states and 4697 transitions. [2020-10-26 05:48:16,229 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-10-26 05:48:16,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3363 states and 4697 transitions. [2020-10-26 05:48:16,250 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3288 [2020-10-26 05:48:16,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:16,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:16,251 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,251 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,251 INFO L794 eck$LassoCheckResult]: Stem: 35316#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 35142#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 35143#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 35178#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 35432#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35486#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35369#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35370#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35433#L353-1 assume !(0 == ~M_E~0); 35207#L494-1 assume !(0 == ~T1_E~0); 35208#L499-1 assume !(0 == ~T2_E~0); 35259#L504-1 assume !(0 == ~T3_E~0); 35477#L509-1 assume !(0 == ~T4_E~0); 35489#L514-1 assume !(0 == ~E_1~0); 35398#L519-1 assume !(0 == ~E_2~0); 35399#L524-1 assume !(0 == ~E_3~0); 35455#L529-1 assume !(0 == ~E_4~0); 35313#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35129#L230 assume !(1 == ~m_pc~0); 35130#L230-2 is_master_triggered_~__retres1~0 := 0; 35131#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35132#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35310#L607 assume !(0 != activate_threads_~tmp~1); 35391#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35392#L249 assume !(1 == ~t1_pc~0); 35427#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 35428#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35437#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35232#L615 assume !(0 != activate_threads_~tmp___0~0); 35233#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35237#L268 assume !(1 == ~t2_pc~0); 35253#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 35254#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35265#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 35359#L623 assume !(0 != activate_threads_~tmp___1~0); 35444#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35445#L287 assume !(1 == ~t3_pc~0); 35451#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 35452#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35387#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 35274#L631 assume !(0 != activate_threads_~tmp___2~0); 35275#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35276#L306 assume !(1 == ~t4_pc~0); 35151#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 35152#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35146#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 35147#L639 assume !(0 != activate_threads_~tmp___3~0); 35288#L639-2 assume !(1 == ~M_E~0); 35474#L547-1 assume !(1 == ~T1_E~0); 35393#L552-1 assume !(1 == ~T2_E~0); 35394#L557-1 assume !(1 == ~T3_E~0); 35450#L562-1 assume !(1 == ~T4_E~0); 35311#L567-1 assume !(1 == ~E_1~0); 35312#L572-1 assume !(1 == ~E_2~0); 35136#L577-1 assume !(1 == ~E_3~0); 35137#L582-1 assume !(1 == ~E_4~0); 35238#L768-1 assume !false; 37825#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 37819#L469 [2020-10-26 05:48:16,252 INFO L796 eck$LassoCheckResult]: Loop: 37819#L469 assume !false; 37816#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 37813#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 37810#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 37807#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 37802#L408 assume 0 != eval_~tmp~0; 37798#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 35479#L416 assume !(0 != eval_~tmp_ndt_1~0); 35294#L413 assume !(0 == ~t1_st~0); 35295#L427 assume !(0 == ~t2_st~0); 37833#L441 assume !(0 == ~t3_st~0); 36579#L455 assume !(0 == ~t4_st~0); 37819#L469 [2020-10-26 05:48:16,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,252 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 1 times [2020-10-26 05:48:16,253 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,253 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69137818] [2020-10-26 05:48:16,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:16,263 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:16,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:16,272 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:16,287 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:16,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,288 INFO L82 PathProgramCache]: Analyzing trace with hash 590384519, now seen corresponding path program 1 times [2020-10-26 05:48:16,288 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,289 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820861110] [2020-10-26 05:48:16,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:16,292 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:16,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:16,295 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:16,297 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:16,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,298 INFO L82 PathProgramCache]: Analyzing trace with hash 162355665, now seen corresponding path program 1 times [2020-10-26 05:48:16,298 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,298 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143747292] [2020-10-26 05:48:16,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,337 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143747292] [2020-10-26 05:48:16,337 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,337 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:16,338 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319161569] [2020-10-26 05:48:16,424 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:16,424 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:16,425 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:16,425 INFO L87 Difference]: Start difference. First operand 3363 states and 4697 transitions. cyclomatic complexity: 1341 Second operand 3 states. [2020-10-26 05:48:16,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:16,511 INFO L93 Difference]: Finished difference Result 6225 states and 8602 transitions. [2020-10-26 05:48:16,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:16,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6225 states and 8602 transitions. [2020-10-26 05:48:16,561 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5817 [2020-10-26 05:48:16,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6225 states to 6225 states and 8602 transitions. [2020-10-26 05:48:16,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6225 [2020-10-26 05:48:16,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6225 [2020-10-26 05:48:16,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6225 states and 8602 transitions. [2020-10-26 05:48:16,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:16,621 INFO L691 BuchiCegarLoop]: Abstraction has 6225 states and 8602 transitions. [2020-10-26 05:48:16,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6225 states and 8602 transitions. [2020-10-26 05:48:16,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6225 to 6085. [2020-10-26 05:48:16,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6085 states. [2020-10-26 05:48:16,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6085 states to 6085 states and 8416 transitions. [2020-10-26 05:48:16,780 INFO L714 BuchiCegarLoop]: Abstraction has 6085 states and 8416 transitions. [2020-10-26 05:48:16,780 INFO L594 BuchiCegarLoop]: Abstraction has 6085 states and 8416 transitions. [2020-10-26 05:48:16,780 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-10-26 05:48:16,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6085 states and 8416 transitions. [2020-10-26 05:48:16,813 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5677 [2020-10-26 05:48:16,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:16,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:16,814 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,814 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,814 INFO L794 eck$LassoCheckResult]: Stem: 44925#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 44739#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 44740#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 44772#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 45049#L333-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 45119#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44980#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44981#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45050#L353-1 assume !(0 == ~M_E~0); 44801#L494-1 assume !(0 == ~T1_E~0); 44802#L499-1 assume !(0 == ~T2_E~0); 45110#L504-1 assume !(0 == ~T3_E~0); 45111#L509-1 assume !(0 == ~T4_E~0); 45167#L514-1 assume !(0 == ~E_1~0); 45168#L519-1 assume !(0 == ~E_2~0); 45074#L524-1 assume !(0 == ~E_3~0); 45075#L529-1 assume !(0 == ~E_4~0); 44922#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44923#L230 assume !(1 == ~m_pc~0); 44787#L230-2 is_master_triggered_~__retres1~0 := 0; 44788#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44918#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 44919#L607 assume !(0 != activate_threads_~tmp~1); 45004#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45005#L249 assume !(1 == ~t1_pc~0); 45044#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 45045#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45130#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 45131#L615 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 44833#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44863#L268 assume !(1 == ~t2_pc~0); 44864#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 44867#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44868#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 45091#L623 assume !(0 != activate_threads_~tmp___1~0); 45092#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45102#L287 assume !(1 == ~t3_pc~0); 45103#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 45104#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45105#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 44880#L631 assume !(0 != activate_threads_~tmp___2~0); 44881#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44887#L306 assume !(1 == ~t4_pc~0); 44888#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 49418#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49416#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 44896#L639 assume !(0 != activate_threads_~tmp___3~0); 44897#L639-2 assume !(1 == ~M_E~0); 45106#L547-1 assume !(1 == ~T1_E~0); 45007#L552-1 assume !(1 == ~T2_E~0); 45008#L557-1 assume !(1 == ~T3_E~0); 45069#L562-1 assume !(1 == ~T4_E~0); 44920#L567-1 assume !(1 == ~E_1~0); 44921#L572-1 assume !(1 == ~E_2~0); 44958#L577-1 assume !(1 == ~E_3~0); 44838#L582-1 assume !(1 == ~E_4~0); 44839#L768-1 assume !false; 49491#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 49489#L469 [2020-10-26 05:48:16,814 INFO L796 eck$LassoCheckResult]: Loop: 49489#L469 assume !false; 49487#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 49484#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 49481#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 49479#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 49477#L408 assume 0 != eval_~tmp~0; 49474#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 45112#L416 assume !(0 != eval_~tmp_ndt_1~0); 45113#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 47396#L430 assume !(0 != eval_~tmp_ndt_2~0); 47397#L427 assume !(0 == ~t2_st~0); 49497#L441 assume !(0 == ~t3_st~0); 49392#L455 assume !(0 == ~t4_st~0); 49489#L469 [2020-10-26 05:48:16,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,815 INFO L82 PathProgramCache]: Analyzing trace with hash -750579381, now seen corresponding path program 1 times [2020-10-26 05:48:16,815 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,816 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459126605] [2020-10-26 05:48:16,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,841 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459126605] [2020-10-26 05:48:16,841 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,841 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:16,841 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452984778] [2020-10-26 05:48:16,842 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:16,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,842 INFO L82 PathProgramCache]: Analyzing trace with hash 976788693, now seen corresponding path program 1 times [2020-10-26 05:48:16,843 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,843 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109863901] [2020-10-26 05:48:16,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:16,847 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:16,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:16,849 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:16,851 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:16,931 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:16,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:16,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:16,932 INFO L87 Difference]: Start difference. First operand 6085 states and 8416 transitions. cyclomatic complexity: 2342 Second operand 3 states. [2020-10-26 05:48:16,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:16,964 INFO L93 Difference]: Finished difference Result 4976 states and 6896 transitions. [2020-10-26 05:48:16,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:16,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4976 states and 6896 transitions. [2020-10-26 05:48:16,998 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4891 [2020-10-26 05:48:17,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4976 states to 4976 states and 6896 transitions. [2020-10-26 05:48:17,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4976 [2020-10-26 05:48:17,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4976 [2020-10-26 05:48:17,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4976 states and 6896 transitions. [2020-10-26 05:48:17,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:17,037 INFO L691 BuchiCegarLoop]: Abstraction has 4976 states and 6896 transitions. [2020-10-26 05:48:17,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4976 states and 6896 transitions. [2020-10-26 05:48:17,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4976 to 4976. [2020-10-26 05:48:17,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4976 states. [2020-10-26 05:48:17,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4976 states to 4976 states and 6896 transitions. [2020-10-26 05:48:17,269 INFO L714 BuchiCegarLoop]: Abstraction has 4976 states and 6896 transitions. [2020-10-26 05:48:17,269 INFO L594 BuchiCegarLoop]: Abstraction has 4976 states and 6896 transitions. [2020-10-26 05:48:17,269 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-10-26 05:48:17,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4976 states and 6896 transitions. [2020-10-26 05:48:17,295 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4891 [2020-10-26 05:48:17,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:17,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:17,296 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:17,296 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:17,297 INFO L794 eck$LassoCheckResult]: Stem: 55987#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 55807#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 55808#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 55841#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 56108#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56166#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56041#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56042#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56109#L353-1 assume !(0 == ~M_E~0); 55869#L494-1 assume !(0 == ~T1_E~0); 55870#L499-1 assume !(0 == ~T2_E~0); 55929#L504-1 assume !(0 == ~T3_E~0); 56157#L509-1 assume !(0 == ~T4_E~0); 56172#L514-1 assume !(0 == ~E_1~0); 56071#L519-1 assume !(0 == ~E_2~0); 56072#L524-1 assume !(0 == ~E_3~0); 56131#L529-1 assume !(0 == ~E_4~0); 55985#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55790#L230 assume !(1 == ~m_pc~0); 55791#L230-2 is_master_triggered_~__retres1~0 := 0; 55795#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55796#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 55982#L607 assume !(0 != activate_threads_~tmp~1); 56064#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56065#L249 assume !(1 == ~t1_pc~0); 56103#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 56104#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56114#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 55899#L615 assume !(0 != activate_threads_~tmp___0~0); 55900#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55903#L268 assume !(1 == ~t2_pc~0); 55924#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 55925#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55933#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 56031#L623 assume !(0 != activate_threads_~tmp___1~0); 56118#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56119#L287 assume !(1 == ~t3_pc~0); 56129#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 56130#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56061#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 55945#L631 assume !(0 != activate_threads_~tmp___2~0); 55946#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55948#L306 assume !(1 == ~t4_pc~0); 55814#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 55815#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55809#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55810#L639 assume !(0 != activate_threads_~tmp___3~0); 55960#L639-2 assume !(1 == ~M_E~0); 56154#L547-1 assume !(1 == ~T1_E~0); 56068#L552-1 assume !(1 == ~T2_E~0); 56069#L557-1 assume !(1 == ~T3_E~0); 56125#L562-1 assume !(1 == ~T4_E~0); 55983#L567-1 assume !(1 == ~E_1~0); 55984#L572-1 assume !(1 == ~E_2~0); 55801#L577-1 assume !(1 == ~E_3~0); 55802#L582-1 assume !(1 == ~E_4~0); 55904#L768-1 assume !false; 58984#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 58985#L469 [2020-10-26 05:48:17,297 INFO L796 eck$LassoCheckResult]: Loop: 58985#L469 assume !false; 59764#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 59763#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 59762#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 59761#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 59760#L408 assume 0 != eval_~tmp~0; 59759#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 59758#L416 assume !(0 != eval_~tmp_ndt_1~0); 59757#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 57877#L430 assume !(0 != eval_~tmp_ndt_2~0); 57878#L427 assume !(0 == ~t2_st~0); 59184#L441 assume !(0 == ~t3_st~0); 59182#L455 assume !(0 == ~t4_st~0); 58985#L469 [2020-10-26 05:48:17,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:17,298 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 2 times [2020-10-26 05:48:17,298 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:17,298 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920161221] [2020-10-26 05:48:17,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:17,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:17,307 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:17,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:17,315 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:17,327 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:17,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:17,329 INFO L82 PathProgramCache]: Analyzing trace with hash 976788693, now seen corresponding path program 2 times [2020-10-26 05:48:17,329 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:17,329 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088346486] [2020-10-26 05:48:17,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:17,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:17,333 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:17,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:17,336 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:17,338 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:17,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:17,339 INFO L82 PathProgramCache]: Analyzing trace with hash 592796107, now seen corresponding path program 1 times [2020-10-26 05:48:17,339 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:17,340 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883112433] [2020-10-26 05:48:17,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:17,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:17,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:17,375 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883112433] [2020-10-26 05:48:17,375 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:17,375 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:17,375 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677460038] [2020-10-26 05:48:17,474 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:17,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:17,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:17,476 INFO L87 Difference]: Start difference. First operand 4976 states and 6896 transitions. cyclomatic complexity: 1927 Second operand 3 states. [2020-10-26 05:48:17,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:17,573 INFO L93 Difference]: Finished difference Result 8779 states and 12099 transitions. [2020-10-26 05:48:17,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:17,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8779 states and 12099 transitions. [2020-10-26 05:48:17,638 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8669 [2020-10-26 05:48:17,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8779 states to 8779 states and 12099 transitions. [2020-10-26 05:48:17,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8779 [2020-10-26 05:48:17,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8779 [2020-10-26 05:48:17,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8779 states and 12099 transitions. [2020-10-26 05:48:17,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:17,807 INFO L691 BuchiCegarLoop]: Abstraction has 8779 states and 12099 transitions. [2020-10-26 05:48:17,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8779 states and 12099 transitions. [2020-10-26 05:48:17,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8779 to 8289. [2020-10-26 05:48:17,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8289 states. [2020-10-26 05:48:17,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8289 states to 8289 states and 11469 transitions. [2020-10-26 05:48:17,968 INFO L714 BuchiCegarLoop]: Abstraction has 8289 states and 11469 transitions. [2020-10-26 05:48:17,968 INFO L594 BuchiCegarLoop]: Abstraction has 8289 states and 11469 transitions. [2020-10-26 05:48:17,968 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-10-26 05:48:17,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8289 states and 11469 transitions. [2020-10-26 05:48:18,008 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8179 [2020-10-26 05:48:18,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:18,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:18,009 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:18,009 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:18,010 INFO L794 eck$LassoCheckResult]: Stem: 69750#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 69568#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 69569#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 69604#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 69882#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69953#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69808#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69809#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69883#L353-1 assume !(0 == ~M_E~0); 69632#L494-1 assume !(0 == ~T1_E~0); 69633#L499-1 assume !(0 == ~T2_E~0); 69690#L504-1 assume !(0 == ~T3_E~0); 69942#L509-1 assume !(0 == ~T4_E~0); 69957#L514-1 assume !(0 == ~E_1~0); 69837#L519-1 assume !(0 == ~E_2~0); 69838#L524-1 assume !(0 == ~E_3~0); 69908#L529-1 assume !(0 == ~E_4~0); 69745#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69556#L230 assume !(1 == ~m_pc~0); 69557#L230-2 is_master_triggered_~__retres1~0 := 0; 69558#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69559#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 69742#L607 assume !(0 != activate_threads_~tmp~1); 69831#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69832#L249 assume !(1 == ~t1_pc~0); 69875#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 69876#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69891#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69662#L615 assume !(0 != activate_threads_~tmp___0~0); 69663#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69667#L268 assume !(1 == ~t2_pc~0); 69684#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 69685#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69697#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 69797#L623 assume !(0 != activate_threads_~tmp___1~0); 69898#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69899#L287 assume !(1 == ~t3_pc~0); 69906#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 69907#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69826#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 69708#L631 assume !(0 != activate_threads_~tmp___2~0); 69709#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69710#L306 assume !(1 == ~t4_pc~0); 69578#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 69579#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69572#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 69573#L639 assume !(0 != activate_threads_~tmp___3~0); 69723#L639-2 assume !(1 == ~M_E~0); 69940#L547-1 assume !(1 == ~T1_E~0); 69833#L552-1 assume !(1 == ~T2_E~0); 69834#L557-1 assume !(1 == ~T3_E~0); 69903#L562-1 assume !(1 == ~T4_E~0); 69743#L567-1 assume !(1 == ~E_1~0); 69744#L572-1 assume !(1 == ~E_2~0); 69562#L577-1 assume !(1 == ~E_3~0); 69563#L582-1 assume !(1 == ~E_4~0); 69668#L768-1 assume !false; 71397#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 71398#L469 [2020-10-26 05:48:18,010 INFO L796 eck$LassoCheckResult]: Loop: 71398#L469 assume !false; 71385#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 71386#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 71373#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 71374#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 71361#L408 assume 0 != eval_~tmp~0; 71362#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 71247#L416 assume !(0 != eval_~tmp_ndt_1~0); 71226#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 70843#L430 assume !(0 != eval_~tmp_ndt_2~0); 70844#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 71163#L444 assume !(0 != eval_~tmp_ndt_3~0); 71502#L441 assume !(0 == ~t3_st~0); 71401#L455 assume !(0 == ~t4_st~0); 71398#L469 [2020-10-26 05:48:18,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:18,011 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 3 times [2020-10-26 05:48:18,011 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:18,011 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306803263] [2020-10-26 05:48:18,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:18,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:18,021 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:18,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:18,029 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:18,041 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:18,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:18,042 INFO L82 PathProgramCache]: Analyzing trace with hash 210997045, now seen corresponding path program 1 times [2020-10-26 05:48:18,042 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:18,043 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102741177] [2020-10-26 05:48:18,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:18,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:18,047 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:18,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:18,049 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:18,052 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:18,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:18,053 INFO L82 PathProgramCache]: Analyzing trace with hash 1192128767, now seen corresponding path program 1 times [2020-10-26 05:48:18,053 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:18,053 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523368971] [2020-10-26 05:48:18,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:18,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:18,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:18,158 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523368971] [2020-10-26 05:48:18,158 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:18,159 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:18,159 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1296377318] [2020-10-26 05:48:18,279 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:18,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:18,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:18,280 INFO L87 Difference]: Start difference. First operand 8289 states and 11469 transitions. cyclomatic complexity: 3187 Second operand 3 states. [2020-10-26 05:48:18,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:18,391 INFO L93 Difference]: Finished difference Result 12888 states and 17790 transitions. [2020-10-26 05:48:18,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:18,392 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12888 states and 17790 transitions. [2020-10-26 05:48:18,477 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 12758 [2020-10-26 05:48:18,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12888 states to 12888 states and 17790 transitions. [2020-10-26 05:48:18,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12888 [2020-10-26 05:48:18,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12888 [2020-10-26 05:48:18,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12888 states and 17790 transitions. [2020-10-26 05:48:18,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:18,573 INFO L691 BuchiCegarLoop]: Abstraction has 12888 states and 17790 transitions. [2020-10-26 05:48:18,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12888 states and 17790 transitions. [2020-10-26 05:48:18,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12888 to 12688. [2020-10-26 05:48:18,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12688 states. [2020-10-26 05:48:18,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12688 states to 12688 states and 17530 transitions. [2020-10-26 05:48:18,988 INFO L714 BuchiCegarLoop]: Abstraction has 12688 states and 17530 transitions. [2020-10-26 05:48:18,988 INFO L594 BuchiCegarLoop]: Abstraction has 12688 states and 17530 transitions. [2020-10-26 05:48:18,989 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-10-26 05:48:18,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12688 states and 17530 transitions. [2020-10-26 05:48:19,158 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 12558 [2020-10-26 05:48:19,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:19,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:19,161 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:19,161 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:19,161 INFO L794 eck$LassoCheckResult]: Stem: 90934#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 90754#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 90755#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 90789#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 91061#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91124#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90990#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 90991#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91062#L353-1 assume !(0 == ~M_E~0); 90816#L494-1 assume !(0 == ~T1_E~0); 90817#L499-1 assume !(0 == ~T2_E~0); 90877#L504-1 assume !(0 == ~T3_E~0); 91115#L509-1 assume !(0 == ~T4_E~0); 91129#L514-1 assume !(0 == ~E_1~0); 91019#L519-1 assume !(0 == ~E_2~0); 91020#L524-1 assume !(0 == ~E_3~0); 91086#L529-1 assume !(0 == ~E_4~0); 90931#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 90738#L230 assume !(1 == ~m_pc~0); 90739#L230-2 is_master_triggered_~__retres1~0 := 0; 90743#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 90744#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 90928#L607 assume !(0 != activate_threads_~tmp~1); 91013#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91014#L249 assume !(1 == ~t1_pc~0); 91056#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 91057#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 91067#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 90849#L615 assume !(0 != activate_threads_~tmp___0~0); 90850#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 90856#L268 assume !(1 == ~t2_pc~0); 90871#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 90872#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 90881#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 90981#L623 assume !(0 != activate_threads_~tmp___1~0); 91073#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 91074#L287 assume !(1 == ~t3_pc~0); 91084#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 91085#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 91010#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 90894#L631 assume !(0 != activate_threads_~tmp___2~0); 90895#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 90896#L306 assume !(1 == ~t4_pc~0); 90761#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 90762#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 90756#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 90757#L639 assume !(0 != activate_threads_~tmp___3~0); 90905#L639-2 assume !(1 == ~M_E~0); 91112#L547-1 assume !(1 == ~T1_E~0); 91016#L552-1 assume !(1 == ~T2_E~0); 91017#L557-1 assume !(1 == ~T3_E~0); 91080#L562-1 assume !(1 == ~T4_E~0); 90929#L567-1 assume !(1 == ~E_1~0); 90930#L572-1 assume !(1 == ~E_2~0); 90748#L577-1 assume !(1 == ~E_3~0); 90749#L582-1 assume !(1 == ~E_4~0); 90857#L768-1 assume !false; 99758#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 99756#L469 [2020-10-26 05:48:19,161 INFO L796 eck$LassoCheckResult]: Loop: 99756#L469 assume !false; 99755#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 99753#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 99748#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 99747#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 99745#L408 assume 0 != eval_~tmp~0; 99743#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 99740#L416 assume !(0 != eval_~tmp_ndt_1~0); 99676#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 99213#L430 assume !(0 != eval_~tmp_ndt_2~0); 99214#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 99909#L444 assume !(0 != eval_~tmp_ndt_3~0); 99906#L441 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 99902#L458 assume !(0 != eval_~tmp_ndt_4~0); 99761#L455 assume !(0 == ~t4_st~0); 99756#L469 [2020-10-26 05:48:19,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:19,162 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 4 times [2020-10-26 05:48:19,162 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:19,162 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029490875] [2020-10-26 05:48:19,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:19,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:19,174 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:19,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:19,185 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:19,207 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:19,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:19,209 INFO L82 PathProgramCache]: Analyzing trace with hash -2049172697, now seen corresponding path program 1 times [2020-10-26 05:48:19,210 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:19,210 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681844868] [2020-10-26 05:48:19,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:19,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:19,215 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:19,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:19,217 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:19,219 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:19,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:19,219 INFO L82 PathProgramCache]: Analyzing trace with hash -1698860387, now seen corresponding path program 1 times [2020-10-26 05:48:19,220 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:19,220 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780307186] [2020-10-26 05:48:19,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:19,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:19,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:19,261 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1780307186] [2020-10-26 05:48:19,262 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:19,262 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:19,262 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048605741] [2020-10-26 05:48:19,402 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:19,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:19,402 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:19,402 INFO L87 Difference]: Start difference. First operand 12688 states and 17530 transitions. cyclomatic complexity: 4849 Second operand 3 states. [2020-10-26 05:48:19,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:19,535 INFO L93 Difference]: Finished difference Result 23888 states and 32880 transitions. [2020-10-26 05:48:19,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:19,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23888 states and 32880 transitions. [2020-10-26 05:48:19,779 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 23688 [2020-10-26 05:48:19,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23888 states to 23888 states and 32880 transitions. [2020-10-26 05:48:19,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23888 [2020-10-26 05:48:19,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23888 [2020-10-26 05:48:19,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23888 states and 32880 transitions. [2020-10-26 05:48:19,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:19,944 INFO L691 BuchiCegarLoop]: Abstraction has 23888 states and 32880 transitions. [2020-10-26 05:48:19,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23888 states and 32880 transitions. [2020-10-26 05:48:20,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23888 to 23888. [2020-10-26 05:48:20,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23888 states. [2020-10-26 05:48:20,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23888 states to 23888 states and 32880 transitions. [2020-10-26 05:48:20,539 INFO L714 BuchiCegarLoop]: Abstraction has 23888 states and 32880 transitions. [2020-10-26 05:48:20,539 INFO L594 BuchiCegarLoop]: Abstraction has 23888 states and 32880 transitions. [2020-10-26 05:48:20,539 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2020-10-26 05:48:20,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23888 states and 32880 transitions. [2020-10-26 05:48:20,651 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 23688 [2020-10-26 05:48:20,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:20,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:20,652 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:20,652 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:20,652 INFO L794 eck$LassoCheckResult]: Stem: 127523#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 127337#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 127338#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 127372#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 127656#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127727#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 127583#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 127584#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127659#L353-1 assume !(0 == ~M_E~0); 127399#L494-1 assume !(0 == ~T1_E~0); 127400#L499-1 assume !(0 == ~T2_E~0); 127461#L504-1 assume !(0 == ~T3_E~0); 127716#L509-1 assume !(0 == ~T4_E~0); 127732#L514-1 assume !(0 == ~E_1~0); 127613#L519-1 assume !(0 == ~E_2~0); 127614#L524-1 assume !(0 == ~E_3~0); 127683#L529-1 assume !(0 == ~E_4~0); 127520#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 127322#L230 assume !(1 == ~m_pc~0); 127323#L230-2 is_master_triggered_~__retres1~0 := 0; 127327#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 127328#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 127517#L607 assume !(0 != activate_threads_~tmp~1); 127606#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 127607#L249 assume !(1 == ~t1_pc~0); 127651#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 127652#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 127666#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 127432#L615 assume !(0 != activate_threads_~tmp___0~0); 127433#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 127436#L268 assume !(1 == ~t2_pc~0); 127454#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 127455#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 127465#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 127573#L623 assume !(0 != activate_threads_~tmp___1~0); 127670#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 127671#L287 assume !(1 == ~t3_pc~0); 127681#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 127682#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 127603#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 127481#L631 assume !(0 != activate_threads_~tmp___2~0); 127482#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 127483#L306 assume !(1 == ~t4_pc~0); 127344#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 127345#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 127339#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 127340#L639 assume !(0 != activate_threads_~tmp___3~0); 127494#L639-2 assume !(1 == ~M_E~0); 127713#L547-1 assume !(1 == ~T1_E~0); 127610#L552-1 assume !(1 == ~T2_E~0); 127611#L557-1 assume !(1 == ~T3_E~0); 127678#L562-1 assume !(1 == ~T4_E~0); 127518#L567-1 assume !(1 == ~E_1~0); 127519#L572-1 assume !(1 == ~E_2~0); 127331#L577-1 assume !(1 == ~E_3~0); 127332#L582-1 assume !(1 == ~E_4~0); 127437#L768-1 assume !false; 147604#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 145727#L469 [2020-10-26 05:48:20,653 INFO L796 eck$LassoCheckResult]: Loop: 145727#L469 assume !false; 147319#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 147313#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 147311#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 142894#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 142893#L408 assume 0 != eval_~tmp~0; 142889#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 142887#L416 assume !(0 != eval_~tmp_ndt_1~0); 142886#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 142884#L430 assume !(0 != eval_~tmp_ndt_2~0); 142881#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 141439#L444 assume !(0 != eval_~tmp_ndt_3~0); 142760#L441 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 137548#L458 assume !(0 != eval_~tmp_ndt_4~0); 137549#L455 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 145719#L472 assume !(0 != eval_~tmp_ndt_5~0); 145727#L469 [2020-10-26 05:48:20,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:20,654 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 5 times [2020-10-26 05:48:20,654 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:20,654 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119665912] [2020-10-26 05:48:20,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:20,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:20,669 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:20,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:20,679 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:20,693 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:20,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:20,694 INFO L82 PathProgramCache]: Analyzing trace with hash 900155619, now seen corresponding path program 1 times [2020-10-26 05:48:20,694 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:20,694 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799877760] [2020-10-26 05:48:20,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:20,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:20,702 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:20,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:20,706 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:20,708 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:20,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:20,709 INFO L82 PathProgramCache]: Analyzing trace with hash -1125064659, now seen corresponding path program 1 times [2020-10-26 05:48:20,709 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:20,709 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208016174] [2020-10-26 05:48:20,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:20,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:20,876 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:20,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:20,893 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:20,910 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:21,020 WARN L193 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2020-10-26 05:48:22,321 WARN L193 SmtUtils]: Spent 1.24 s on a formula simplification. DAG size of input: 210 DAG size of output: 153 [2020-10-26 05:48:22,693 WARN L193 SmtUtils]: Spent 338.00 ms on a formula simplification that was a NOOP. DAG size: 131 [2020-10-26 05:48:22,747 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.10 05:48:22 BoogieIcfgContainer [2020-10-26 05:48:22,748 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-10-26 05:48:22,748 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-10-26 05:48:22,749 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-10-26 05:48:22,749 INFO L275 PluginConnector]: Witness Printer initialized [2020-10-26 05:48:22,750 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:48:12" (3/4) ... [2020-10-26 05:48:22,753 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-10-26 05:48:22,819 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2020-10-26 05:48:22,819 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-10-26 05:48:22,821 INFO L168 Benchmark]: Toolchain (without parser) took 12961.47 ms. Allocated memory was 44.0 MB in the beginning and 3.4 GB in the end (delta: 3.4 GB). Free memory was 20.7 MB in the beginning and 3.1 GB in the end (delta: -3.1 GB). Peak memory consumption was 320.0 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:22,821 INFO L168 Benchmark]: CDTParser took 0.30 ms. Allocated memory is still 44.0 MB. Free memory was 25.6 MB in the beginning and 25.6 MB in the end (delta: 33.2 kB). There was no memory consumed. Max. memory is 16.1 GB. [2020-10-26 05:48:22,822 INFO L168 Benchmark]: CACSL2BoogieTranslator took 477.14 ms. Allocated memory is still 54.5 MB. Free memory was 39.6 MB in the beginning and 37.9 MB in the end (delta: 1.8 MB). Peak memory consumption was 16.0 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:22,822 INFO L168 Benchmark]: Boogie Procedure Inliner took 100.09 ms. Allocated memory is still 54.5 MB. Free memory was 37.7 MB in the beginning and 33.7 MB in the end (delta: 4.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:22,823 INFO L168 Benchmark]: Boogie Preprocessor took 102.92 ms. Allocated memory is still 54.5 MB. Free memory was 33.7 MB in the beginning and 30.2 MB in the end (delta: 3.5 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:22,823 INFO L168 Benchmark]: RCFGBuilder took 1539.72 ms. Allocated memory was 54.5 MB in the beginning and 67.1 MB in the end (delta: 12.6 MB). Free memory was 30.2 MB in the beginning and 42.7 MB in the end (delta: -12.6 MB). Peak memory consumption was 21.2 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:22,824 INFO L168 Benchmark]: BuchiAutomizer took 10642.79 ms. Allocated memory was 67.1 MB in the beginning and 3.4 GB in the end (delta: 3.4 GB). Free memory was 42.7 MB in the beginning and 3.1 GB in the end (delta: -3.0 GB). Peak memory consumption was 351.7 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:22,824 INFO L168 Benchmark]: Witness Printer took 70.83 ms. Allocated memory is still 3.4 GB. Free memory was 3.1 GB in the beginning and 3.1 GB in the end (delta: 3.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:22,827 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30 ms. Allocated memory is still 44.0 MB. Free memory was 25.6 MB in the beginning and 25.6 MB in the end (delta: 33.2 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 477.14 ms. Allocated memory is still 54.5 MB. Free memory was 39.6 MB in the beginning and 37.9 MB in the end (delta: 1.8 MB). Peak memory consumption was 16.0 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 100.09 ms. Allocated memory is still 54.5 MB. Free memory was 37.7 MB in the beginning and 33.7 MB in the end (delta: 4.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 102.92 ms. Allocated memory is still 54.5 MB. Free memory was 33.7 MB in the beginning and 30.2 MB in the end (delta: 3.5 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1539.72 ms. Allocated memory was 54.5 MB in the beginning and 67.1 MB in the end (delta: 12.6 MB). Free memory was 30.2 MB in the beginning and 42.7 MB in the end (delta: -12.6 MB). Peak memory consumption was 21.2 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 10642.79 ms. Allocated memory was 67.1 MB in the beginning and 3.4 GB in the end (delta: 3.4 GB). Free memory was 42.7 MB in the beginning and 3.1 GB in the end (delta: -3.0 GB). Peak memory consumption was 351.7 MB. Max. memory is 16.1 GB. * Witness Printer took 70.83 ms. Allocated memory is still 3.4 GB. Free memory was 3.1 GB in the beginning and 3.1 GB in the end (delta: 3.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 23888 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.5s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 4.6s. Construction of modules took 0.6s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 18. Minimization of nondet autom 0. Automata minimization 2.0s AutomataMinimizationTime, 18 MinimizatonAttempts, 3305 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 1.2s Buchi closure took 0.0s. Biggest automaton had 23888 states and ocurred in iteration 18. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 10357 SDtfs, 11393 SDslu, 8774 SDs, 0 SdLazy, 397 SolverSat, 199 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 403]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {__retres1=0, NULL=0, t3_st=0, NULL=1, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5cd7a4fe=0, t4_pc=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@178e6082=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@19093e8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@678f49bd=0, NULL=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b3c351c=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@13628f47=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@57d46571=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@362e37a3=0, NULL=4, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d287e29=0, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, NULL=2, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=3, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@667d9d24=0, t1_st=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5ee713d4=0, t2_pc=0, tmp___3=0, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@72b522c3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@99a0f10=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 403]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int t4_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L39] int E_3 = 2; [L40] int E_4 = 2; [L813] int __retres1 ; [L725] m_i = 1 [L726] t1_i = 1 [L727] t2_i = 1 [L728] t3_i = 1 [L729] t4_i = 1 [L754] int kernel_st ; [L755] int tmp ; [L756] int tmp___0 ; [L760] kernel_st = 0 [L333] COND TRUE m_i == 1 [L334] m_st = 0 [L338] COND TRUE t1_i == 1 [L339] t1_st = 0 [L343] COND TRUE t2_i == 1 [L344] t2_st = 0 [L348] COND TRUE t3_i == 1 [L349] t3_st = 0 [L353] COND TRUE t4_i == 1 [L354] t4_st = 0 [L494] COND FALSE !(M_E == 0) [L499] COND FALSE !(T1_E == 0) [L504] COND FALSE !(T2_E == 0) [L509] COND FALSE !(T3_E == 0) [L514] COND FALSE !(T4_E == 0) [L519] COND FALSE !(E_1 == 0) [L524] COND FALSE !(E_2 == 0) [L529] COND FALSE !(E_3 == 0) [L534] COND FALSE !(E_4 == 0) [L597] int tmp ; [L598] int tmp___0 ; [L599] int tmp___1 ; [L600] int tmp___2 ; [L601] int tmp___3 ; [L227] int __retres1 ; [L230] COND FALSE !(m_pc == 1) [L240] __retres1 = 0 [L242] return (__retres1); [L605] tmp = is_master_triggered() [L607] COND FALSE !(\read(tmp)) [L246] int __retres1 ; [L249] COND FALSE !(t1_pc == 1) [L259] __retres1 = 0 [L261] return (__retres1); [L613] tmp___0 = is_transmit1_triggered() [L615] COND FALSE !(\read(tmp___0)) [L265] int __retres1 ; [L268] COND FALSE !(t2_pc == 1) [L278] __retres1 = 0 [L280] return (__retres1); [L621] tmp___1 = is_transmit2_triggered() [L623] COND FALSE !(\read(tmp___1)) [L284] int __retres1 ; [L287] COND FALSE !(t3_pc == 1) [L297] __retres1 = 0 [L299] return (__retres1); [L629] tmp___2 = is_transmit3_triggered() [L631] COND FALSE !(\read(tmp___2)) [L303] int __retres1 ; [L306] COND FALSE !(t4_pc == 1) [L316] __retres1 = 0 [L318] return (__retres1); [L637] tmp___3 = is_transmit4_triggered() [L639] COND FALSE !(\read(tmp___3)) [L547] COND FALSE !(M_E == 1) [L552] COND FALSE !(T1_E == 1) [L557] COND FALSE !(T2_E == 1) [L562] COND FALSE !(T3_E == 1) [L567] COND FALSE !(T4_E == 1) [L572] COND FALSE !(E_1 == 1) [L577] COND FALSE !(E_2 == 1) [L582] COND FALSE !(E_3 == 1) [L587] COND FALSE !(E_4 == 1) [L768] COND TRUE 1 [L771] kernel_st = 1 [L399] int tmp ; Loop: [L403] COND TRUE 1 [L363] int __retres1 ; [L366] COND TRUE m_st == 0 [L367] __retres1 = 1 [L394] return (__retres1); [L406] tmp = exists_runnable_thread() [L408] COND TRUE \read(tmp) [L413] COND TRUE m_st == 0 [L414] int tmp_ndt_1; [L415] tmp_ndt_1 = __VERIFIER_nondet_int() [L416] COND FALSE !(\read(tmp_ndt_1)) [L427] COND TRUE t1_st == 0 [L428] int tmp_ndt_2; [L429] tmp_ndt_2 = __VERIFIER_nondet_int() [L430] COND FALSE !(\read(tmp_ndt_2)) [L441] COND TRUE t2_st == 0 [L442] int tmp_ndt_3; [L443] tmp_ndt_3 = __VERIFIER_nondet_int() [L444] COND FALSE !(\read(tmp_ndt_3)) [L455] COND TRUE t3_st == 0 [L456] int tmp_ndt_4; [L457] tmp_ndt_4 = __VERIFIER_nondet_int() [L458] COND FALSE !(\read(tmp_ndt_4)) [L469] COND TRUE t4_st == 0 [L470] int tmp_ndt_5; [L471] tmp_ndt_5 = __VERIFIER_nondet_int() [L472] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...